Display control method and display device

Abstract

To provide a display control method and a display device with reduced power consumption.SOLUTION: Storing a first value corresponding to a voltage supplied to each of the plurality of data lines 70 of the electro-optical device 10 in a blanking period, calculating a first addition value obtained by adding the first value and a value obtained by integrating a voltage corresponding to frame data supplied to a first data line 70 among the plurality of data lines 70 in an N-th period and an (N + 1) - th period subsequent to the N-th period, and, based on the first addition value, A display control method comprising: generating correction data for correcting frame data supplied to a first data line 70 in an (N + 1) - th period; and outputting the frame data corrected using the correction data.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display control method and a display device. [Background technology]

[0002] A liquid crystal display device that uses liquid crystal elements as display elements forms images by utilizing the dielectric anisotropy of liquid crystal and the optical rotation of light in the liquid crystal layer. In a liquid crystal display device, scanning lines and data lines are arranged in the image display area, and pixels are arranged in a matrix at their intersections. Transistors are provided in the pixels, and images are formed by supplying image signals to each pixel via the transistors.

[0003] When driving a liquid crystal display device, multiple scan lines are selected in sequence, and image signals are written to pixel circuits corresponding to the selected scan lines via data lines. Therefore, the voltage on the data lines changes every horizontal scan period. However, the data lines and liquid crystal elements are capacitively coupled by stray capacitance. Therefore, if the voltage on the data lines fluctuates between the time an image signal is written to a pixel circuit corresponding to a certain scan line and the time the next image signal is written, the voltage of the image signal held by the liquid crystal element fluctuates due to capacitive coupling. This can result in degradation of the quality of the displayed image and the occurrence of a phenomenon known as vertical crosstalk.

[0004] For example, the display control circuit in Patent Document 1 identifies two pixel circuits adjacent to each other in the direction in which the scan lines extend as boundary pixel circuits when a correction difference value representing the difference between two correction data corresponding to those pixel circuits is equal to or greater than a predetermined threshold. It then identifies a predetermined number of pixel circuits including one or both of the two pixel circuits that make up the boundary pixel circuit. It then updates a predetermined number of correction data corresponding to the predetermined number of pixel circuits so that the values ​​are between the two correction data corresponding to the two pixel circuits that make up the boundary pixel circuit. This reduces the probability of a sudden change in display grayscale due to vertical crosstalk correction. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-178362 Summary of the Invention [Problem to be solved by the invention]

[0006] The display control circuit disclosed in Patent Document 1 also discloses a technique for suppressing the occurrence of vertical crosstalk, but does not disclose a technique for suppressing vertical crosstalk caused by voltage during the blanking period. If the voltage integral value is calculated and corrected for the blanking period as in Patent Document 1, the more values ​​are integrated, the greater the power consumption required for processing. [Means for solving the problem]

[0007] The present disclosure relates to a display control method including: storing a first value corresponding to a voltage supplied to each of a plurality of data lines of an electro-optical device during a retrace period; calculating a first sum by adding the first value to a value obtained by integrating a voltage corresponding to an image signal supplied to a first data line of the plurality of data lines during a first period and a second period following the first period; generating first correction data for correcting the image signal supplied to the first data line during the second period based on the first sum; and outputting the image signal corrected using the first correction data.

[0008] The present disclosure relates to a display device including an electro-optical device including a plurality of scanning lines, a first data line, a plurality of pixel circuits respectively corresponding to the plurality of scanning lines and the first data line, and a drive circuit that supplies a voltage of an image signal to the first data line; a memory device that stores a first value corresponding to a voltage supplied to each of the plurality of data lines of the electro-optical device during a retrace period; and a control circuit that performs the following operations: calculating a first sum by adding the first value and a value obtained by integrating a voltage corresponding to an image signal supplied to a first data line of the plurality of data lines during a first period and a second period following the first period; calculating a first sum by adding the first value and a value obtained by integrating a voltage of the image signal supplied to the first data line of the plurality of data lines during the first period; generating first correction data based on the first sum for correcting the image signal supplied to the first data line during the second period following the first period; and outputting the image signal corrected using the first correction data. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration of an electro-optical device. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a pixel circuit. [Figure 3] FIG. 2 is a block diagram showing the configuration of a control circuit. [Figure 4] FIG. 4 is a diagram showing an example of a format of frame data. [Figure 5] FIG. 4 is a diagram showing the correspondence between pixel regions and first and second integration buffers. [Figure 6] FIG. 4 is a diagram for explaining the operation of a counter calculation unit. [Figure 7] FIG. 4 is a diagram for explaining the operation of a counter calculation unit. [Figure 8] 10 is a flowchart showing an operation for generating an H_VFP value or an H_VBP value. [Figure 9] 10 is a flowchart showing the operation of a counter calculation unit of the control circuit. [Figure 10]10 is a flowchart showing the operation of a counter calculation unit of the control circuit. [Figure 11] 10 is a flowchart showing the operation of a counter calculation unit of the control circuit. [Figure 12] 10 is a flowchart showing the operation of a counter calculation unit of the control circuit. [Figure 13] FIG. 1 is a diagram showing the configuration of a projector. DETAILED DESCRIPTION OF THE INVENTION

[0010] [1. Configuration of the electro-optical device] Hereinafter, embodiments will be described with reference to the accompanying drawings. FIG. 1 is a diagram showing the configuration of an electro-optical device 10 included in a display device 1. As shown in FIG. The electro-optical device 10 is, for example, a transmissive liquid crystal panel, each having a plurality of pixel circuits 100. Each of the plurality of pixel circuits 100 includes a liquid crystal element. The liquid crystal elements are driven based on a data signal, which will be described later, and have a transmittance that corresponds to the voltage of the data signal. In the electro-optical device 10, a transmission image is generated by individually controlling the transmittance of the liquid crystal elements.

[0011] 1, the electro-optical device 10 has a configuration in which a scanning line driving circuit 20 and a data line driving circuit 30 are provided on the periphery of a pixel region 50 in which a plurality of pixel circuits 100 are arranged. The scanning line driving circuit 20 and the data line driving circuit 30 correspond to driving circuits.

[0012] A plurality of pixel circuits 100 are arranged in a matrix in the pixel region 50 of the electro-optical device 10. A plurality of scanning lines 60 and data lines 70 are provided in the pixel region 50. Any one of the plurality of data lines 70 corresponds to a "first data line," and the data line 70 adjacent to the first data line 70 corresponds to a "second data line." The scanning lines 60 are provided to extend along an X-axis, which is an axis parallel to the horizontal direction of the pixel region 50, as viewed in the drawing. The data lines 70 are provided to extend along a Y-axis, which is an axis parallel to the vertical direction of the pixel region 50, as viewed in the drawing. The pixel circuits 100 are provided in a matrix at each intersection of the plurality of scanning lines 60 and the plurality of data lines 70. If the number of scanning lines 60 is m and the number of data lines 70 is n, the pixel circuits 100 are arranged in a matrix of m rows and n columns. Both m and n are integers greater than or equal to 2.

[0013] The scanning line driving circuit 20 selects the scanning lines 60 one by one in the order of, for example, the 1st, 2nd, 3rd, ..., mth rows in accordance with the control signal Ctr supplied from the control circuit 200, and sets the scanning signal to the selected scanning line 60 to H level. The scanning line driving circuit 20 sets the scanning signals to the scanning lines 60 other than the selected scanning line 60 to L level. The data line driving circuit 30 latches the corresponding data signals for one row among the data signals supplied from the control circuit 200, and outputs them via the data line 70 to the pixel circuit 100 located on the scanning line 60 during the period when the scanning signal to the scanning line 60 is at H level.

[0014] 2 is a diagram showing an equivalent circuit of four pixel circuits 100A, 100B, 100C, and 100D arranged in two rows and two columns corresponding to the intersections of two adjacent scanning lines 60A and 60B and two adjacent data lines 70A and 70B. The pixel circuits 100A, 100B, 100C, and 100D all have the same circuit configuration. Therefore, focusing on the pixel circuit 100A corresponding to the intersection of the scanning line 60A and the data line 70A, the pixel circuit 100A will be described.

[0015] The pixel circuit 100A includes a liquid crystal element 130, a transistor 110, and a storage capacitor 120. The transistor 110 is, for example, an n-channel thin film transistor. In the pixel circuit 100A, the gate electrode of the transistor 110 is electrically connected to the scan line 60A, the source electrode is electrically connected to the data line 70A, and the drain electrode is electrically connected to a pixel electrode 140 and one end of the storage capacitor 120.

[0016] In the transistor 110, when the direction of current flow is reversed, the source electrode and the drain electrode are swapped, but in this embodiment, the electrode electrically connected to the data line 70A is the source electrode, and the area electrically connected to the pixel electrode 140 is the drain electrode. Furthermore, "electrical connection" or simply "connection" means a direct or indirect connection or coupling between two or more elements, and includes, for example, the connection of different wirings through contact holes even if two or more elements are not directly connected to each other on an element substrate.

[0017] A common electrode 151 is provided in common to all pixels so as to face the pixel electrode 140. A voltage LCcom is applied to the common electrode 151. As described above, the liquid crystal 135 is sandwiched between the pixel electrode 140 and the common electrode 151. Therefore, for each pixel circuit 100, a liquid crystal element 130 is formed in which the liquid crystal 135 is sandwiched between the pixel electrode 140 and the common electrode 151.

[0018] Furthermore, a storage capacitor 120 is provided electrically in parallel with the liquid crystal element 130. One end of the storage capacitor 120 is connected to the pixel electrode 140, and the other end is connected to a capacitance line 153. A time-constant voltage, for example, a voltage LCcom that is the same as the voltage applied to the common electrode 151, is applied to the capacitance line 153.

[0019] 2, the capacitance line 153 is arranged along the X-axis, which is the extension direction of the scanning line 60, but in reality, a plurality of wirings are connected via contact holes and arranged in a mesh shape when viewed in a plan view along the X-axis and Y-axis. Also, in FIG. 2, the two scanning lines 60 are labeled 60A and 60B to distinguish between them, and the two data lines are labeled 70A and 70B to distinguish between them. When the scanning line 60 and the data line 70 are not to be distinguished from each other, they are labeled 60 and 70, as shown in FIG. 1 above.

[0020] When the scanning signal for a scanning line 60 becomes H level, the transistor 110 of the pixel circuit 100 provided corresponding to that scanning line 60 is turned on. When the transistor 110 is turned on, the data line 70 and the pixel electrode 140 are electrically connected, and the data signal supplied to the data line 70 reaches the pixel electrode 140 via the transistor 110 that is turned on. When the scanning line 60 becomes L level, the transistor 110 is turned off, but the voltage of the data signal that reaches the pixel electrode 140 is held by the liquid crystal element 130 and the storage capacitor 120.

[0021] In the liquid crystal element 130, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 140 and the common electrode 151. Therefore, the transmittance of the liquid crystal element 130 corresponds to the effective value of the applied voltage. If the liquid crystal element 130 is in a normally black mode, the transmittance increases as the applied voltage to the liquid crystal element 130 increases.

[0022] The operation of supplying data signals to the pixel electrodes 140 of the liquid crystal elements 130 is executed in the order of the first, second, third, ..., mth rows during one vertical scanning period. As a result, a voltage corresponding to the data signal is held in each of the liquid crystal elements 130 of the pixel circuits 100 arranged in m rows and n columns, each liquid crystal element 130 has the desired transmittance, and a transmission image of the corresponding color is generated by the liquid crystal elements 130 arranged in m rows and n columns. In this way, the generation of a transmission image is executed for each RGB, and a color image obtained by combining the RGB is projected onto the screen.

[0023] [2. Control circuit configuration] FIG. 3 is a block diagram showing the configuration of the control circuit 200. As shown in FIG. Next, the configuration of the control circuit 200 will be described with reference to FIG. The control circuit 200 includes a control unit 210, a LUT value conversion unit 220, an accumulation permission determination unit 230, a storage unit 240, a counter calculation unit 250, a correction coefficient calculation unit 260, a polarity determination unit 270, and a correction calculation unit 280.

[0024] A synchronization signal is input to the control unit 210 from a higher-level device (not shown). Based on the input synchronization signal, the control unit 210 generates a control signal Ctr and a polarity inversion signal P that control the operation of the electro-optical device 10. The polarity inversion signal P is a signal for inverting the polarity of the voltage applied to the pixel circuit 100. In this embodiment, a case will be described in which the polarity inversion signal P is a signal that inverts the polarity of frame data for each frame.

[0025] The control unit 210 supplies the generated control signal Ctr to the scanning line driving circuit 20 and the data line driving circuit 30. The control unit 210 also outputs the generated control signal Ctr to the LUT value conversion unit 220, the accumulation permission determination unit 230, the counter calculation unit 250, the correction coefficient calculation unit 260, the polarity determination unit 270, and the correction calculation unit 280. Signal lines through which the control unit 210 outputs signals to the components within the control circuit 200 are not shown. The control signal Ctr includes, for example, a pulse signal, a clock signal, an enable signal, etc. The control unit 210 outputs the generated polarity inversion signal P to the counter calculation unit 250.

[0026] Frame data is input to the LUT value conversion unit 220. The LUT value conversion unit 220 includes a lookup table (not shown), and converts the pixel values ​​of each pixel included in the input frame data into LUT values, which are values ​​registered in the lookup table.

[0027] Frame data is also input to the accumulation permission determination unit 230. The accumulation permission determination unit 230 also stores a first determination threshold value and a second determination threshold value. The first determination threshold is a threshold used to determine whether or not input frame data contains pixels with high pixel values. The second determination threshold is a threshold used to determine whether or not input frame data includes pixels with low pixel values.

[0028] The accumulation permission determination unit 230 outputs a first determination signal to the counter calculation unit 250 when a pixel whose pixel value is greater than the first determination threshold is detected in the input frame data. Furthermore, the accumulation permission determination unit 230 outputs a second determination signal to the counter calculation unit 250 when a pixel whose pixel value is smaller than the second determination threshold value is detected in the frame data.

[0029] The storage unit 240 stores set values ​​of vertical blanking intervals to be accumulated by the counter calculation unit 250. The set values ​​include four set values: H_VFP value, L_VFP value, H_VBP value, and L_VBP value. The H_VFP value and L_VFP value correspond to the second value, and the H_VBP value and L_VBP value correspond to the third value. The storage unit 240 corresponds to a storage device.

[0030] The H_VFP value and the H_VBP value are set values ​​that are accumulated in the first H counter 252 or the second H counter 256 provided in the counter calculation unit 250. The H_VFP value is a setting value for the front porch period included in the vertical blanking period, and corresponds to the voltage supplied during the front porch period. The H_VBP value is a setting value for the back porch period included in the vertical blanking period, and corresponds to the voltage supplied during the back porch period. The H_VFP and H_VBP values ​​are LUT values ​​corresponding to the voltages supplied during the vertical blanking interval.

[0031] The L_VFP value and the L_VBP value are set values ​​that are accumulated in the first L counter 253 or the second L counter 257 provided in the counter calculation unit 250. The L_VFP value is a setting value for the front porch period included in the vertical blanking period, and corresponds to the voltage supplied during the front porch period. The L_VBP value is a setting value for the back porch period included in the vertical blanking period, and corresponds to the voltage supplied during the back porch period. The L_VFP and L_VBP values ​​are LUT values ​​corresponding to the voltages supplied during the vertical blanking interval.

[0032] Now, the vertical blanking interval, front porch, and back porch will be described with reference to FIG. 4 is a diagram showing an example of a frame data format defined by a vertical synchronization signal VSync and a horizontal synchronization signal HSync. Frame data corresponds to an image signal.

[0033] The vertical synchronization signal VSync is used to define a frame period, which is the period for one frame, and the period from VSync to the next VSync is the frame period. The vertical front porch period immediately before the vertical synchronization signal VSync and the vertical back porch period immediately after the vertical synchronization signal VSync are both defined as vertical blanking periods. Frame data during the vertical blanking periods is treated as invalid data, i.e., data that is not displayed by the electro-optical device 10. The period from the end of the vertical back porch period to the start of the vertical front porch period is the valid period, and an image displayed during this valid period is displayed as a valid image in the display area shown in FIG. 4. Frame data during the vertical front porch period and vertical back porch period is treated as invalid data, i.e., data in the non-display area that is not displayed by the electro-optical device 10.

[0034] The horizontal synchronization signal HSync is used to define one line (row) period, and the period from one HSync signal to the next HSync signal is one line period. The horizontal front porch period immediately before the horizontal synchronization signal HSync and the horizontal back porch period immediately after the horizontal synchronization signal HSync are both defined as horizontal blanking periods. Frame data during the horizontal blanking period is treated as invalid data, i.e., data in a non-display area that is not displayed by the electro-optical device 10. The period from the end of the horizontal back porch period to the start of the horizontal front porch period is the valid period, and an image displayed during this valid period is displayed as a valid image in the display area shown in FIG. 4. Frame data during the horizontal front porch period and horizontal back porch period is treated as invalid data, i.e., data in a non-display area that is not displayed by the electro-optical device 10.

[0035] The frame data is scanned in a horizontal direction starting from the upper left pixel and then arranged in a sequential manner, with pixel data arranged in a horizontal direction to the right, pixel by pixel. Following the first row of data, the second row of pixel data is arranged vertically downward, and this scanning is repeated line by line to form one frame period of frame data. The frame data during the valid period, excluding the blanking period of one frame period and one line period, is the valid image, and is treated as the data actually displayed on the electro-optical device 10.

[0036] Returning to FIG. 3, the configuration of the control circuit 200 will be further described. Counter calculation unit 250 includes first accumulating buffer 251 and second accumulating buffer 255. First accumulating buffer 251 and second accumulating buffer 255 are configured by static random access memory. First accumulating buffer 251 corresponds to an example of a first static random access memory, and second accumulating buffer 255 corresponds to an example of a second static random access memory. The counter calculation unit 250 receives the frame data converted into LUT values ​​from the LUT value conversion unit 220, and receives the first and second determination signals from the accumulation permission determination unit 230. The counter calculation unit 250 also receives the polarity inversion signal P from the control unit 210. The counter calculation unit 250 accumulates the LUT values ​​for two frames of frame data in each of the first accumulation buffer 251 and the second accumulation buffer 255. The LUT values ​​include the LUT values ​​for the vertical blanking interval.

[0037] The first integrating buffer 251 includes a first high counter 252 and a first low counter 253. Hereinafter, the first high counter 252 will be abbreviated to a first H counter 252, and the first low counter 253 will be abbreviated to a first L counter 253. The second integrating buffer 255 includes a second high counter 256 and a second low counter 257. The second high counter 256 is abbreviated to a second H counter 256, and the second low counter 257 is abbreviated to a second L counter 257.

[0038] 5 is a diagram showing the correspondence between the pixel region 50 of the electro-optical device 10 and the storage regions of the first integration buffer 251 and the second integration buffer 255. Note that the horizontal back porch and horizontal front porch are not shown in FIG. The first H counter 252 and the first L counter 253 configured in the first integration buffer 251 each include m storage areas (m is any natural number). The second H counter 256 and the second L counter 257 configured in the second integration buffer 255 also each include m storage areas, where m corresponds to the number of pixels in the row direction of the pixel region 50 of the electro-optical device 10. The m storage areas of the first H counter 252 and the first L counter 253 are each accumulated with LUT values ​​for two frames by the counter calculation unit 250. Similarly, the m storage areas of the second H counter 256 and the second L counter 257 are each accumulated with LUT values ​​for two frames by the counter calculation unit 250.

[0039] 6 and 7 are diagrams showing the signal levels of polarity inversion signals input during four periods from the Nth period to the (N+3)th period, the LUT values ​​of frame data, and the LUT values ​​accumulated in the first accumulation buffer 251 and the second accumulation buffer 255. N is an arbitrary natural number. FIG. 6 shows a case where the pixel value of the frame data is greater than the first determination threshold value, and FIG. 7 shows a case where the pixel value of the frame data is smaller than the second determination threshold value. The operation of the counter calculation unit 250 will be described with reference to FIGS.

[0040] For example, the Nth period corresponds to the “first period,” and the N+1th period corresponds to the “second period.” Furthermore, if the N+1th period corresponds to the “first period,” the N+2th period corresponds to the “second period.”

[0041] 6 and 7, (A) shows the vertical synchronization signal VSYNC, (B) shows the polarity inversion signal P of the frame to be processed, and (C) shows the polarity inversion signal P of the frame following the frame to be processed. (D) in FIG. 6 shows the LUT value of the frame data and the first determination threshold, and (D) in FIG. 7 shows the LUT value of the frame data and the second determination threshold. (E) in FIGS. 6 and 7 shows the change in the integrated value of the first H counter 252 from the Nth period to the N+3th period, and (F) shows the change in the integrated value of the first L counter 253 from the Nth period to the N+3th period. (G) in FIGS. 6 and 7 shows the change in the integrated value of the second H counter 256 from the Nth period to the N+3th period, and (H) shows the change in the integrated value of the second L counter 257 from the Nth period to the N+3th period.

[0042] The frame to be processed in the Nth period shown in FIG. 6 is called frame S, and the frame next to frame S is called frame S+1. First, we will explain the operation of the counter calculation unit 250 when, during the Nth period shown in Figure 6, the polarity inversion signal P of the S frame, which is the frame to be processed, is at a low level and the polarity inversion signal P of the S+1 frame following the S frame is at a high level. When the vertical synchronization signal VSync is input and the Nth period starts, the counter calculation unit 250 first initializes the first integration buffer 251. As a result, the first integration buffer 251 is reset.

[0043] Next, the counter calculation unit 250 accumulates the accumulated value of the vertical blanking interval and the pixel value of the first line, and writes the accumulated value into the first accumulation buffer 251.

[0044] 6 shows a case where the first determination signal is input from the accumulation permission determination unit 230 to the counter calculation unit 250. That is, the frame data of the S frame includes pixels whose pixel values ​​are greater than the first determination threshold value. When the first determination signal is input from the accumulation permission determination unit 230, the counter calculation unit 250 obtains the H_VFP value and the H_VBP value from the storage unit 240 as an accumulation value of the vertical blanking interval. Next, the counter calculation unit 250 determines whether to add or subtract the obtained accumulation value of the vertical blanking interval. If the frame to be processed is the first frame after the first accumulation buffer 251 is initialized, the counter calculation unit 250 determines whether to add or subtract the obtained accumulation value of the vertical blanking interval to or from the first accumulation buffer 251 based on the signal level of the polarity inversion signal P of the next frame (S+1). Because the signal level of the polarity inversion signal P of the S+1 frame is high, the counter calculation unit 250 adds (H_VFP value + H_VBP value) to the first H counter 252 as the accumulation value of the vertical blanking interval.

[0045] Next, the counter calculation unit 250 adds or subtracts the LUT value of each pixel of the S frame to or from the first H counter 252 to which the integrated value of the vertical blanking period has been added. When the signal level of the polarity inversion signal P of the next frame (S+1) is high, the counter calculation unit 250 adds the LUT value of each pixel of the S frame to the first H counter 252 . First, the processing for the first row of the S frame will be described. The counter calculation unit 250 compares the LUT value of the pixel in the first row of the S frame with the first determination threshold value. If the LUT value is greater than the first determination threshold value, the counter calculation unit 250 increments the LUT value of the first row using the first H counter 252. This increases the integrated value of the first H counter 252 for the Nth period shown in FIG. 6(E).

[0046] Next, the counter calculation unit 250 processes the second row of the S frame. The counter calculation unit 250 compares the LUT value of the second row of the S frame with the first determination threshold. If the LUT value is greater than the first determination threshold, the counter calculation unit 250 adds the LUT value of the second row to the first H counter 252. Thereafter, the counter calculation unit 250 repeats the process for the third row, the fourth row, ..., and so on up to the final row of the S frame, thereby further increasing the integrated value of the 1H counter 252 for the Nth period shown in FIG.

[0047] When processing of the S frame to be processed is completed in the Nth period, the counter calculation unit 250 outputs the accumulated value accumulated in the first accumulation buffer 251 or the second accumulation buffer 255 to the polarity determination unit 270. In the above description, the counter calculation unit 250 outputs the accumulated value of the first H counter 252 to the polarity determination unit 270.

[0048] Next, a vertical synchronization signal VSync is input, and the period transitions from the Nth period to the N+1th period. When the N+1th period begins, the frame to be processed changes from the Sth frame to the S+1th frame. Furthermore, while the signal level of the polarity inversion signal P for the Sth frame to be processed was low during the Nth period, the signal level of the polarity inversion signal P for the S+1th frame to be processed becomes high during the N+1th period. In other words, the polarity of the voltage supplied to the data line 70 is inverted between the Nth period and the N+1th period.

[0049] When the frame to be processed is the second frame after the first integration buffer 251 is initialized, the counter calculation unit 250 determines whether to add or subtract the integration value of the vertical blanking interval to the first integration buffer 251 based on the signal level of the polarity inversion signal P between the frame to be processed, frame S+1, and the next frame, frame S+2.

[0050] As shown in the N+1 period in Figure 6, it is assumed that the signal level of the polarity inversion signal P of the S+1 frame to be processed is high, and the signal level of the polarity inversion signal P of the next frame, S+2, is low. In this case, the counter calculation unit 250 determines the integrated value of the vertical blanking interval to be added to the first H counter 252 as -(H_VBP value x 2). -H_VBP value x 2 corresponds to the fourth value.

[0051] The counter calculation unit 250 subtracts the integrated value of the vertical blanking interval when the signal level of the polarity inversion signal P of the S+1 frame, which is the frame to be processed, is high, and also subtracts the integrated value of the vertical blanking interval when the signal level of the polarity inversion signal P of the next frame, S+2, is low. Therefore, by subtracting the integrated value of the vertical blanking interval of the S+1 frame and the integrated value of the vertical blanking interval of the S+2 frame, the integrated value of the vertical blanking interval becomes −(H_VBP value×2). As a result, the integrated value of the first H counter 252 for the N+1th period shown in FIG. 6(E) decreases.

[0052] Although not shown in the N+1 period in Figure 6, it is assumed that the signal level of the polarity inversion signal P of the S+1 frame to be processed is low, and the signal level of the polarity inversion signal P of the next frame, S+2, is high. In this case, the counter calculation unit 250 determines the integrated value of the vertical blanking interval to be added to the first H counter 252 as (H_VBP value x 2). H_VBP value x 2 corresponds to the fourth value.

[0053] Counter calculation unit 250 adds the integrated value of the vertical blanking interval when the signal level of polarity inversion signal P of frame S+1, which is the frame to be processed, is low, and also adds the integrated value of the vertical blanking interval when the signal level of polarity inversion signal P of the next frame, frame S+2, is high. Therefore, by adding the integrated value of the vertical blanking interval of frame S+1 and the integrated value of the vertical blanking interval of frame S+2, the integrated value of the vertical blanking interval becomes (H_VBP value x 2). Therefore, by adding the integrated value of the vertical blanking interval of the S+1 frame and then adding the integrated value of the vertical blanking interval of the S+2 frame, the integrated value of the vertical blanking interval becomes (H_VBP value×2).

[0054] Although not shown in the N+1 period in Figure 6, it is assumed that the signal levels of the polarity inversion signal P for the S+1 frame and the S+2 frame are both low. In this case, the counter calculation unit 250 determines that the integrated value of the vertical blanking interval to be added to the 1st H counter 252 is 0. 6, it is assumed that the signal levels of the polarity inversion signal P for the S+1 frame and the S+2 frame are both high. In this case, the counter calculation unit 250 determines that the integrated value of the vertical blanking interval to be added to the first H counter 252 is 0. Determining that the integrated value of the vertical blanking interval is 0 corresponds to the case where the fourth value is 0.

[0055] In more detail, if the signal level of the polarity inversion signal P of the S+1 frame, which is the frame to be processed, is low, the integrated value of the vertical blanking interval is added, and if the signal level of the polarity inversion signal P of the next frame, S+2 frame, is also low, the integrated value of the vertical blanking interval is subtracted. Therefore, by adding the integrated value of the vertical blanking interval of the S+1 frame and subtracting the integrated value of the vertical blanking interval of the S+2 frame, the integrated value of the vertical blanking interval becomes 0. If the signal levels of the polarity inversion signal P of both the S+1 frame and the S+2 frame are high, the integrated value of the vertical blanking interval of the S+1 frame is subtracted and the integrated value of the vertical blanking interval of the S+2 frame is added, so that the integrated value of the vertical blanking interval becomes 0.

[0056] Next, the counter calculation unit 250 adds or subtracts the integrated value of the vertical blanking period of the second frame, S+1, from the 1H counter 252, and then determines whether to add or subtract the LUT value of the S+1 frame and the LUT value of the previous S frame from the 1H counter 252. If the signal level of the polarity inversion signal P of the S+1 frame to be processed is high, the counter calculation unit 250 determines to subtract the LUT value of the immediately preceding S frame from the first H counter 252. Furthermore, if the signal level of the polarity inversion signal P of the next S+2 frame is low, the counter calculation unit 250 determines to subtract the LUT value of the S+1 frame to be processed from the first H counter 252. Counter calculation unit 250 compares the LUT value of the pixel in the first row of frame S+1 with the first determination threshold, and if the LUT value is greater than the first determination threshold, subtracts the pixel value in the first row of frame S+1 using 1H counter 252, and also subtracts the pixel value in the first row of frame S, which is the previous frame, using 1H counter 252. As a result, the integrated value of 1H counter 252 shown in the N+1 period in FIG. 6(E) decreases. The counter calculation unit 250 performs the same process on the second row, the third row, . . . , and repeats the process up to the final row of the S+1 frame.

[0057] For example, the kth storage area among the m storage areas of the first H counter 252 stores the sum of the vertical blanking interval supplied to one data line 70k of the multiple data lines 70 included in the electro-optical device 10 and the sum of the voltage corresponding to the frame data. This value corresponds to the "first sum." k is a variable that takes a value between 2 and m-1. Furthermore, the k+1th storage area or the k-1th storage area stores the sum of the vertical blanking intervals supplied to the data line 70k+1 or the data line 70k-1 and the voltage corresponding to the frame data. This sum corresponds to the "second sum." The data line 70k+1 or the data line 70k-1 corresponds to the "second data line."

[0058] In the above explanation, the sum of (H_VFP value + H_VBP value) added to the 1st H counter 252 as the integrated value of the vertical retrace period in the Nth period and - (H_VBP value x 2) added to the 1st H counter 252 as the integrated value of the vertical retrace period in the N+1th period corresponds to the "first value." The H_VFP value added to the first H counter 252 as the integrated value of the vertical blanking period during the Nth period corresponds to the "second value." The H_VBP value added to the first H counter 252 as the integrated value of the vertical blanking interval during the Nth period corresponds to the "third value." During the (N+1)th period, −(H_VBP value×2) added to the first H counter 252 as the integrated value of the vertical blanking period corresponds to the “fourth value”. As described above, whether the "first value" is a positive value or a negative value is determined based on the polarity, which is the signal level of the polarity inversion signal P of the S frame, S+1 frame, and S+2 frame.

[0059] Next, a description will be given of the processing of the counter calculation unit 250 on the second accumulation buffer 255. The counter calculation unit 250 also starts processing on the second accumulation buffer 255 when the (N+1)th period starts. First, the counter calculation unit 250 initializes the second accumulation buffer 255. As a result, the second accumulation buffer 255 is reset.

[0060] Next, the counter calculation unit 250 accumulates the accumulated value of the vertical blanking interval and the pixel value of the first line, and writes the accumulated value into the second accumulation buffer 255.

[0061] When the first determination signal is input from the accumulation permission determination section 230, the counter calculation section 250 acquires the H_VFP value and the H_VBP value from the storage section 240. Next, the counter calculation unit 250 determines whether to add or subtract the integrated value of the acquired vertical blanking interval. If the frame to be processed is the first frame after the second integration buffer 255 is initialized, the counter calculation unit 250 determines whether to add or subtract the integrated value of the acquired vertical blanking interval to or from the second integration buffer 255 based on the signal level of the polarity inversion signal P of the next frame, frame S+2. Because the signal level of the polarity inversion signal P of frame S+2 is low, the counter calculation unit 250 adds −(H_VFP value+H_VBP value) to the second H counter 256 as the integrated value of the vertical blanking interval.

[0062] Next, the counter calculation unit 250 adds or subtracts the LUT value of each pixel of the S+1 frame to or from the second H counter 256 to which the integrated value of the vertical blanking period has been added. When the signal level of the polarity inversion signal P of the next frame (S+2 frame) is low, the counter calculation unit 250 causes the second H counter 256 to subtract the pixel value of each pixel of the S+1 frame. First, the processing for the first row of the S+1 frame will be described. The counter calculation unit 250 compares the LUT value of the pixel in the first row of the S+1 frame with the first determination threshold. If the LUT value is greater than the first determination threshold, the counter calculation unit 250 subtracts the LUT value of the first row using the second H counter 256. This decreases the integrated value of the second H counter 256 for the N+1th period shown in FIG. 6(G).

[0063] Next, the counter calculation unit 250 processes the second row of the S+1 frame. The counter calculation unit 250 compares the LUT value of the second row of the S+1 frame with the first determination threshold. If the LUT value is greater than the first determination threshold, the counter calculation unit 250 subtracts the LUT value of the second row using the second H counter 256. This further decreases the integrated value of the second H counter 256 for the N+1th period shown in FIG. 6(G). The counter calculation unit 250 repeats the process for the third row, the fourth row, ..., and so on up to the final row of the S+1 frame, thereby further decreasing the integrated value of the second H counter 256 for the Nth period shown in FIG. 6(G).

[0064] When processing of the S+1 frame to be processed is completed in the N+1th period, the counter calculation unit 250 outputs the integrated value accumulated in the first integration buffer 251 or the second integration buffer 255 to the polarity determination unit 270. In the above-described case, the counter calculation unit 250 outputs the integrated value of the second H counter 256 to the polarity determination unit 270.

[0065] Next, a vertical synchronization signal VSync is input, and the period transitions from the N+1th period to the N+2th period. When the N+2th period begins, the frame to be processed changes from frame S+1 to frame S+2. The N+2th period corresponds to the third period. In the N+1th period, the signal level of the polarity inversion signal P for the S+1th frame to be processed was high, but in the N+2th period, the signal level of the polarity inversion signal P for the S+2th frame to be processed becomes low. In other words, the polarity of the voltage supplied to the data line 70 is inverted between the N+1th period and the N+2th period.

[0066] When the frame to be processed is the second frame after the second integration buffer 255 is initialized, the counter calculation unit 250 determines whether to add or subtract the integration value of the vertical blanking interval to the second integration buffer 255 based on the signal level of the polarity inversion signal P between the frame to be processed, frame S+2, and the next frame, frame S+3.

[0067] As described above, when the signal levels of the polarity inversion signal P for the S+2 frame and the S+3 frame are both low, or when the signal levels of the polarity inversion signal P for the S+2 frame and the S+3 frame are both high, the integrated value of the vertical blanking period to be added to the second H counter 256 becomes 0. Furthermore, if the signal level of the polarity inversion signal P of the S+2 frame to be processed is high and the signal level of the polarity inversion signal P of the next frame, S+3 frame, is low, the integrated value of the vertical blanking period to be added to the second H counter 256 is determined to be -(H_VBP value x 2). Furthermore, if the signal level of the polarity inversion signal P of the S+2 frame to be processed is low and the signal level of the polarity inversion signal P of the next frame, S+3 frame, is high, the integrated value of the vertical blanking period to be added to the second H counter 256 is determined to be (H_VBP value x 2).

[0068] Next, the counter calculation unit 250 determines whether to add or subtract the LUT value of the S+2 frame and the LUT value of the previous S frame to the second H counter 256 based on the signal levels of the polarity inversion signal P of the S+2 frame to be processed and the next S+3 frame. If the signal level of the polarity inversion signal P of the S+2 frame to be processed is low, the counter calculation unit 250 determines to add the LUT value of the immediately preceding S+1 frame to the second H counter 256. Furthermore, if the signal level of the polarity inversion signal P of the next S+3 frame is high, the counter calculation unit 250 determines to add the LUT value of the S+2 frame to be processed to the second H counter 256. The counter calculation unit 250 compares the LUT value of the pixel in the first row of the S+2 frame with the first determination threshold, and if the LUT value is greater than the first determination threshold, adds the pixel value in the first row of the S+2 frame by the second H counter 256, and also adds the pixel value in the first row of the immediately preceding S+1 frame by the second H counter 256. This causes the integrated value of the second H counter 256 for the N+2 period shown in FIG. 6(G) to increase. The counter calculation unit 250 performs the same process on the second row, the third row, ..., and repeats the process up to the final row of the S+2 frame. As a result, the integrated value of the second H counter 256 for the N+2 period shown in Figure 6(G) further increases. The integrated value accumulated by the second H counter 256 in the N+2 period corresponds to the third additional value, and the correction data generated by the correction coefficient calculation unit 260 and the polarity determination unit 270 based on this integrated value corresponds to the third correction data.

[0069] When the vertical synchronization signal VSync is input and the period transitions from the N+1th period to the N+2th period, the counter calculation unit 250 initializes the first integration buffer 251 and performs the same processing as in the Nth period.

[0070] In the above explanation, the sum of -(H_VFP value + H_VBP value) added to the second H counter 256 as the integrated value of the vertical retrace period during the N+1th period and (H_VBP value x 2) added to the second H counter 256 as the integrated value of the vertical retrace period during the N+2th period corresponds to the "first value." The −H_VFP value added to the second H counter 256 as the integrated value of the vertical blanking period during the N+1th period corresponds to the “second value”. The −H_VBP value added to the second H counter 256 as the integrated value of the vertical blanking period during the N+1th period corresponds to the “third value”. The value (H_VBP value×2) added to the first H counter 252 as the integrated value of the vertical blanking period during the (N+1)th period corresponds to the "fourth value." As described above, whether the "first value" is a positive value or a negative value is determined based on the polarity, which is the signal level of the polarity inversion signal P of the S+1 frame, the S+2 frame, and the S+3 frame.

[0071] 7 shows a case where the second determination signal is input from the accumulation permission determination unit 230 to the counter calculation unit 250. The frame data of the S frame includes pixels whose pixel values ​​are smaller than the second determination threshold value. When the signal input from accumulation permission determination unit 230 is the first determination signal, counter calculation unit 250 reads out the H_VFP value and the H_VBP value from storage unit 240. When the signal input from accumulation permission determination unit 230 is the second determination signal, counter calculation unit 250 reads out the L_VFP value and the L_VBP value from storage unit 240. When the frame to be processed is the first frame, S frame, and the signal level of the polarity inversion signal P of the next frame, S+1 frame, is low, the counter calculation unit 250 adds -(L_VFP value + L_VBP value) to the first L counter 253 as the integrated value of the vertical blanking period. Furthermore, when the frame to be processed is the first frame, S frame, and the signal level of the polarity inversion signal P of the next frame, S+1 frame, is high, the counter calculation unit 250 adds (L_VFP value + L_VBP value) to the first L counter 253 as the integrated value of the vertical blanking period.

[0072] Furthermore, when the frame to be processed is the second frame, frame S+1, and the signal levels of the polarity inversion signal P of frame S+1 and the next frame S+2 are both low, the counter calculation unit 250 adds 0 to the first L counter 253 as the integrated value of the vertical blanking period. If the frame to be processed is the second frame, frame S+1, and the signal levels of the polarity inversion signal P of frame S+1 and the next frame S+2 are both high, the counter calculation unit 250 adds 0 to the first L counter 253 as the integrated value of the vertical blanking period.

[0073] The other processing is the same as that described with reference to FIG. When the period transitions from the Nth period to the N+1th period and the frame to be processed changes from frame S to frame S+1, the counter calculation unit 250 determines the integrated value of the vertical blanking period to be added to or subtracted from the 1L counter 253 based on the signal level of the polarity inversion signal P between frame S+1, which is the frame to be processed, and frame S+2, which is the next frame.

[0074] If the signal level of the polarity inversion signal P of the S+1 frame to be processed is high and the signal level of the polarity inversion signal P of the next frame, S+2 frame, is low, the integrated value of the vertical blanking period to be added to the first L counter 253 is determined to be -(L_VBP value x 2).

[0075] If the signal level of the polarity inversion signal P of the S+1 frame to be processed is low and the signal level of the polarity inversion signal P of the next frame, S+2 frame, is high, the integrated value of the vertical blanking period to be added to the first L counter 253 is determined to be (L_VBP value x 2).

[0076] If the signal levels of the polarity inversion signal P for the S+1 frame to be processed and the subsequent S+2 frame are both low, the integrated value of the vertical blanking interval to be added to the 1L counter 253 is determined to be 0. Also, if the signal levels of the polarity inversion signal P for the S+1 frame and the S+2 frame are both high, the integrated value of the vertical blanking interval to be added to the 1L counter 253 is determined to be 0.

[0077] In addition, the counter calculation unit 250 determines whether to add or subtract the LUT value of the S+1 frame and the LUT value of the previous S frame to the first L counter 253 based on the signal levels of the polarity inversion signal P of the S+1 frame to be processed and the next S+2 frame. Similarly, the counter calculation unit 250 determines whether to add or subtract the LUT value of the S+2 frame and the LUT value of the previous S+1 frame to the second L counter 257 based on the signal levels of the polarity inversion signal P of the S+2 frame to be processed and the next S+3 frame.

[0078] When the integrated value of the vertical blanking interval and the LUT values ​​for two frames are integrated in the first integration buffer 251 or the second integration buffer 255, the counter calculation unit 250 reads out the integrated value from the first H counter 252, the first L counter 253, the second H counter 256 or the second L counter 257 and outputs it to the correction coefficient calculation unit 260.

[0079] The correction coefficient calculation unit 260 calculates correction data for correcting the frame data based on the integrated value input from the counter calculation unit 250.

[0080] The polarity determination unit 270 receives the accumulated values ​​of the first frame of the first H counter 252 and the first L counter 253 from the counter calculation unit 250. The polarity determination unit 270 also receives the accumulated values ​​of the first frame of the second H counter 256 and the second L counter 257 from the counter calculation unit 250.

[0081] The polarity determination section 270 calculates a high-side integration calculation result and a low-side integration calculation result. The high-side integration calculation result is calculated using the following formula. High-side integration calculation result=absolute value of the integration value of the first H counter 252 or the second H counter 256 for the first frame×High-side coefficient The first frame refers to the S frame to be processed or the S+1 frame to be processed. The low-side integration calculation result is calculated by the following formula: Low-side integration calculation result = absolute value of the integration value of the first L counter 253 or the integration value of the second L counter 257 for the first frame × Low-side coefficient The high-side coefficient and the low-side coefficient are preset coefficients.

[0082] When the polarity determination unit 270 obtains the high-side integration calculation result and the low-side integration calculation result, it subtracts the low-side integration calculation result from the high-side integration calculation result. If the subtraction result is positive, the polarity determination unit 270 determines that the high-side integration calculation result is larger, and determines the correction coefficient calculated by the correction coefficient calculation unit 260 to be positive correction data. On the other hand, if the subtraction result is negative, the polarity determination unit 270 determines that the low-side integration calculation result is larger, and determines the correction coefficient calculated by the correction coefficient calculation unit 260 to be negative correction data.

[0083] The correction calculation unit 280 corrects the frame data using the positive correction data or negative correction data determined by the correction coefficient calculation unit 260 and the polarity determination unit 270. The positive correction data and negative correction data are calculated for each data line 70. The positive correction data or negative correction data corresponding to any one of the data lines 70 corresponds to "first correction data." The positive correction data or negative correction data corresponding to another one of the data lines 70 corresponds to "second correction data." The positive correction data or negative correction data corresponds to "first correction data" or "second correction data."

[0084] FIG. 8 is a flowchart showing the operation of generating an H_VFP value or an H_VBP value and storing the generated H_VFP value or H_VBP value in the storage unit 240 of the control circuit 200. In this explanation, the subject of the operation will be a processor of a computer provided outside the display device, but the processing may also be executed by a processor provided in the display device.

[0085] First, the processor acquires the setting value of the vertical blanking interval (step T1), and then converts the acquired setting value of the vertical blanking interval into an LUT value (step T2).

[0086] Next, the processor compares the converted LUT value with a first decision threshold (step T3). If the converted LUT value is greater than the first decision threshold (step T3 / YES), the processor multiplies the LUT value by the number of pixels in the front porch portion included in the vertical blanking interval (step T5). Alternatively, the processor multiplies the LUT value by the number of pixels in the back porch portion included in the vertical blanking interval (step T5).

[0087] Next, the processor clips the calculated LUT value x the number of pixels in the front porch section at an upper limit value (step T6) and stores the clipped value as an H_VFP value in storage unit 240. Similarly, the processor clips the calculated LUT value x the number of pixels in the back porch section at an upper limit value (step T6) and stores the clipped value as an H_VBP value in storage unit 240. The H_VFP value and H_VBP value stored in storage unit 240 correspond to the voltage supplied during the vertical blanking interval.

[0088] Furthermore, if the LUT value is equal to or less than the first determination threshold value (step T3 / NO), the processor sets the H_VFP value and H_VBP value to "0" (step T4). The calculated H_VFP value and H_VBP value are stored in the storage unit 240 (step T7).

[0089] The method for generating the L_VFP value and the L_VBP value is the same as the operation shown in the flowchart of FIG. 8, and therefore a detailed description thereof will be omitted.

[0090] [3. Control circuit operation] 9 to 12 are flowcharts showing the operation of counter calculation unit 250 provided in control circuit 200 with respect to first accumulation buffer 251. Note that the operation of counter calculation unit 250 with respect to second accumulation buffer 255 is the same as the operation with respect to first accumulation buffer 251, and therefore detailed description thereof will be omitted.

[0091] The operation of the counter calculation unit 250 will be described with reference to the flowchart shown in FIG. First, the counter calculation unit 250 initializes the first accumulation buffer 251 (step S1). Next, the counter calculation unit 250 determines whether or not the first determination signal has been input from the accumulation permission determination unit 230 (step S2).

[0092] When the first determination signal is input from the accumulation permission determination unit 230 (step S2 / YES), the counter calculation unit 250 reads out the H_VFP value and the H_VBP value from the storage unit 240 (step S3).

[0093] Next, the counter calculation unit 250 determines whether the signal level of the polarity inversion signal P of the S+1 frame, which is the frame next to the S frame to be processed, is high (step S4). If the signal level of the polarity inversion signal P of the S+1 frame is high (step S4 / YES), the counter calculation unit 250 adds the H_VFP value+H_VBP value to the first H counter 252 configured in the initialized first integration buffer 251 (step S5).

[0094] Next, the counter calculation unit 250 adds the LUT value of the m-th row of the S frame to the first H counter 252. The variable m is a variable that counts the number of rows of frame data. First, the counter calculation unit 250 sets the variable m to "1" and starts processing the first row of the S frame. The counter calculation unit 250 determines whether or not there is a pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S7).

[0095] If there is a pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S7 / YES), the counter calculation unit 250 adds the LUT value of the S frame to the storage area of ​​the first H counter 252 corresponding to this pixel (step S8). Next, the counter calculation unit 250 proceeds to the determination of step S9.

[0096] Furthermore, if there is no pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S7 / NO), the counter calculation unit 250 determines whether the value of the variable m indicates the last row of the S frame (step S9). If the value of the variable m does not indicate the last row of the S frame (step S9 / NO), the counter calculation unit 250 increments the value of the variable m by 1 (step S10) and returns to the determination of step S7. If the value of the variable m indicates the last row of the S frame (step S9 / YES), the counter calculation unit 250 determines that processing of the S frame to be processed has ended, and outputs the integrated value accumulated in the first H counter 252 to the polarity determination unit 270. Subsequent operations of the counter calculation unit 250 will be described with reference to the flowchart shown in FIG. 10.

[0097] If the counter calculation unit 250 determines in step S4 that the polarity inversion signal P of the S+1 frame is at a low level (step S4 / NO), it adds −(H_VFP value+H_VBP value) to the first H counter 252 (step S6).

[0098] Next, the counter calculation unit 250 sets the variable m to "1" and starts processing the first row of the S frame. The counter calculation unit 250 determines whether or not there is a pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S11).

[0099] If there is a pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S11 / YES), the counter calculation unit 250 subtracts the LUT value of the S frame from the storage area of ​​the first H counter 252 corresponding to this pixel (step S12). Next, the counter calculation unit 250 proceeds to the determination of step S13.

[0100] Furthermore, if there is no pixel in the first row of the S frame whose LUT value is greater than the first determination threshold value (step S11 / NO), the counter calculation unit 250 determines whether the value of the variable m indicates the last row of the S frame (step S13). If the value of the variable m does not indicate the last row of the S frame (step S13 / NO), the counter calculation unit 250 increments the value of the variable m by 1 (step S14) and returns to the determination of step S11. If the value of the variable m indicates the last row of the S frame (step S13 / YES), the counter calculation unit 250 determines that processing of the S frame to be processed has ended, and outputs the integrated value accumulated in the first H counter 252 to the polarity determination unit 270. Subsequent operations of the counter calculation unit 250 will be described with reference to the flowchart shown in FIG. 10.

[0101] The operation of the counter calculation unit 250 will be further described with reference to the flowchart shown in Fig. 10. Fig. 10 is a flowchart showing the operation of the counter calculation unit 250 when the determination in step S9 or step S13 of the flowchart shown in Fig. 9 is positive. Next, the counter calculation unit 250 changes the frame to be processed from frame S to frame S+1. The counter calculation unit 250 determines whether the polarity inversion signal P of the frame S+1 to be processed is at a low level (step S15).

[0102] If the polarity inversion signal P of the S+1 frame to be processed is at a low level (step S15 / YES), the counter calculation unit 250 determines whether the polarity inversion signal P of the next frame, S+2 frame, is at a low level (step S16).

[0103] If the polarity inversion signal P of the S+1 frame and the S+2 frame is at a low level (step S15 / YES and step S16 / YES), the counter calculation unit 250 sets the integrated value of the vertical blanking period to "0" (step S17) and does not add the integrated value of the vertical blanking period to the 1st H counter 252.

[0104] Furthermore, if the polarity inversion signal P of the S+1 frame is at a low level and the polarity inversion signal P of the S+2 frame is at a high level (step S15 / YES and step S16 / NO), the counter calculation unit 250 sets the H_VBP value×2 as the integrated value of the vertical blanking interval (step S18). The counter calculation unit 250 adds the H_VBP value×2 to the first H counter 252 as the integrated value of the vertical blanking interval.

[0105] Even when the polarity inversion signal P of the S+1 frame and the S+2 frame is at a high level (step S15 / NO and step S19 / NO), the counter calculation unit 250 sets the integrated value of the vertical blanking period to "0" (step S21) and does not add the integrated value of the vertical blanking period to the 1st H counter 252.

[0106] Furthermore, if the polarity inversion signal P of the S+1 frame is at a high level and the polarity inversion signal P of the S+2 frame is at a low level (step S15 / NO and step S19 / YES), the counter calculation unit 250 sets the integrated value of the vertical blanking interval to -H_VBP value×2 (step S20). The counter calculation unit 250 adds -H_VBP value×2 to the first H counter 252 as the integrated value of the vertical blanking interval.

[0107] Next, the counter calculation unit 250 determines whether to add or subtract the LUT values ​​of the S+1 frame and the previous S frame from the first H counter 252 based on the polarity inversion signal P of the S+1 frame to be processed and the next S+2 frame (step S22).

[0108] When the polarity inversion signal P of the S+1 frame to be processed is at a high level, the counter calculation unit 250 determines to subtract the LUT value of the immediately preceding S frame from the first H counter 252. When the polarity inversion signal P of the S+1 frame is at a low level, the counter calculation unit 250 determines to add the LUT value of the immediately preceding S frame to the first H counter 252.

[0109] If the polarity inversion signal P of the next S+2 frame is at a high level, the counter calculation unit 250 determines to add the LUT value of the S+1 frame to be processed to the first H counter 252. Also, if the polarity inversion signal P of the S+2 frame is at a low level, the counter calculation unit 250 determines to subtract the LUT value of the S+1 frame to be processed from the first H counter 252.

[0110] After determining whether to add or subtract the LUT values ​​of the S+1 frame and the S frame from the first H counter 252, the counter calculation unit 250 sets the variable m to "1" and starts processing for the first row of the S+1 frame. The counter calculation unit 250 determines whether or not there is a pixel in the first row of the S+1 frame whose LUT value is greater than the first determination threshold value (step S23).

[0111] If there is a pixel in the mth row of the S+1 frame whose LUT value is greater than the first judgment threshold (step S23 / YES), the counter calculation unit 250 adds or subtracts the LUT values ​​of the S frame and the S+1 frame to or from the first H counter 252 according to the decision made in step S22 (step S24).

[0112] Next, the counter calculation unit 250 determines whether the variable m indicates the last row of the S+1 frame (step S25).

[0113] If the variable m does not indicate the last row of the S+1 frame (step S25 / NO), the counter calculation unit 250 adds 1 to the variable m (step S26) and returns to the determination in step S23.

[0114] Furthermore, if the variable m indicates the last row of the S+1 frame (step S25 / YES), the counter calculation unit 250 outputs the integration result to the subsequent correction coefficient calculation unit 260 and polarity determination unit 270 (step S27).

[0115] FIG. 11 is a flowchart showing the operation when the determination in step S2 of the flowchart shown in FIG. 9 is negative. First, the counter calculation unit 250 determines whether or not a second determination signal has been input (step S28). If the second determination signal has not been input (step S28 / NO), the counter calculation unit 250 determines whether or not the input of frame data has ended (step S29). For example, the counter calculation unit 250 determines that the input of frame data has ended when the input of the vertical synchronization signal output by the control unit 210 has ended. When the input of frame data has ended (step S29 / YES), the counter calculation unit 250 ends this processing flow.

[0116] If the input of frame data has not ended (step S29 / NO), the counter calculation unit 250 returns to the determination in step S2 of the flowchart shown in FIG.

[0117] Furthermore, when the second determination signal is input (step S28 / YES), the counter calculation unit 250 reads out L_VFP and L_VBP from the storage unit 240 (step S30). Next, the counter calculation unit 250 determines whether the polarity inversion signal P of the S+1 frame following the S frame to be processed is at a high level (step S31).

[0118] If the polarity inversion signal P of the S+1 frame is at a high level (step S31 / YES), the counter calculation unit 250 adds L_VFP+L_VBP to the firstL counter 253 (step S32). If the polarity inversion signal P of the S+1 frame is at a low level (step S31 / NO), the counter calculation unit 250 adds −(L_VFP+L_VBP) to the firstL counter 253 (step S33).

[0119] The processing in steps S34 to S41 in the flowchart shown in Fig. 11 is substantially the same as the processing in steps S7 to S14 in the flowchart shown in Fig. 9. That is, in steps S7 to S14 in the flowchart shown in Fig. 9, the LUT value is added or subtracted by the first H counter 252, but in steps S34 to S41 in the flowchart shown in Fig. 11, the LUT value is added or subtracted by the first L counter 253. For this reason, a description of the processing operations in steps S34 to S41 in the flowchart shown in Fig. 11 will be omitted.

[0120] FIG. 12 is a flowchart showing the operation of the counter calculation unit 250 when the determination in step S36 or step S40 in the flowchart shown in FIG. 11 is positive. The flowchart shown in FIG. 12 differs from the flowchart shown in FIG. 10 in that when the polarity inversion signal P of the S+1 frame is at a low level and the polarity inversion signal P of the S+2 frame is at a high level (step S42 / YES and step S43 / NO), the integrated value of the vertical blanking period is set to L_VBP value x 2. Also, if the polarity inversion signal P of the S+1 frame is at a high level and the polarity inversion signal P of the S+2 frame is at a low level (step S42 / NO and step S46 / YES), the integrated value of the vertical blanking period is set to -(L_VBP value x 2). Other operations are the same as those in the flowchart shown in FIG. 10, and therefore detailed explanations will be omitted.

[0121] [4. Display Device Configuration] Fig. 13 is a diagram showing the configuration of a projector 1 corresponding to an example of a display device. The projector 1 is an example of an electronic device that uses an electro-optical device 10. In the projector 1, the electro-optical device 10 is used as a light valve. Hereinafter, the light valve will be referred to as a light valve 10A.

[0122] As shown in FIG. 13 , a lamp unit 502 having a white light source such as a halogen lamp is provided inside the projector 1. Projection light emitted from the lamp unit 502 is separated into three primary colors, R (red), G (green), and B (blue), by three mirrors 507, 611, and 612 and two dichroic mirrors 503 and 507 arranged inside. The separated projection light is guided to light valves 10A corresponding to each primary color. The light valve 10A corresponding to R is referred to as light valve 10A(R), the light valve 10A corresponding to G is referred to as light valve 10A(G), and the light valve 10A corresponding to B is referred to as light valve 10A(B). Since the optical path of B light is longer than that of the other R and G colors, the B light is guided via a relay lens system 600 having an input lens 601, a relay lens 602, and an output lens 603 to prevent loss of the B light.

[0123] The projector 1 is provided with three sets of liquid crystal display devices, each including an electro-optical device 10, corresponding to the R, G, and B colors. The light valves 10A(R), 10A(G), and 10A(B) have the same configuration as the electro-optical device 10. Video signals specifying the gradation levels of the R, G, and B primary color components are supplied from an external host circuit, respectively, to drive the light valves 10A(R), 10A(G), and 10A(B), respectively. Light modulated by the light valves 10A(R), 10A(G), and 10A(B), respectively, enters a dichroic prism 510 from three directions. The dichroic prism 510 then refracts the R and B light at 90 degrees, while the G light travels straight. Therefore, after the images of the primary colors are combined, a color image is projected onto the screen SC by a projection lens group 520.

[0124] Light corresponding to R, G, and B, respectively, enters the light valves 10A(R), 10A(G), and 10A(B) via dichroic mirrors 503 and 507, eliminating the need for color filters. Furthermore, the transmitted images of the light valves 10A(R) and 10A(B) are projected after being reflected by the dichroic prism 510, whereas the transmitted image of the light valve 10A(G) is projected as is. Therefore, the horizontal scanning direction of the light valves 10A(R) and 10A(B) is opposite to the horizontal scanning direction of the light valve 10A(G), resulting in a configuration in which a left-right inverted image is displayed.

[0125] The above-described embodiment is a preferred embodiment of the present invention, but the present invention is not limited to the above-described embodiment and various modifications are possible within the scope of the gist of the present invention. For example, the processing units in the flowcharts shown in Figures 9 to 12 are divided according to the main processing content in order to make it easier to understand the processing of the counter calculation unit 250. The present invention is not limited by the way in which the processing units are divided or the names of the processing units shown in the flowcharts of Figures 9 to 12.

[0126] In the above-described embodiment, the electro-optical device 10 may be a transmissive liquid crystal panel or a reflective liquid crystal panel.

[0127] 5. Summary of this Disclosure A summary of this disclosure is provided below.

[0128] (Appendix 1) A display control method comprising: storing a first value corresponding to a voltage supplied to each of a plurality of data lines of an electro-optical device during a retrace period; calculating a first sum by adding the first value to a value obtained by integrating a voltage corresponding to an image signal supplied to a first data line of the plurality of data lines during a first period and a second period following the first period; generating first correction data for correcting the image signal supplied to the first data line during the second period based on the first sum; and outputting the image signal corrected using the first correction data.

[0129] According to this, by calculating the first sum by adding the first value stored in advance and the voltage corresponding to the image signal, it is possible to reduce the power consumption of the electro-optical device compared to accumulating the values ​​of each pixel during the blanking period.

[0130] (Appendix 2) 2. The display control method of claim 1, further comprising: inverting the polarity of the voltage supplied to the first data line between the first period and the second period; and determining the sign of the first value depending on the polarity of the voltage of the image signal supplied to the first data line during the first period.

[0131] This allows the sign of the first value to be determined depending on the polarity of the voltage of the image signal, so there is no need to store both positive and negative values ​​as the first value, and the capacity of the device for storing the first value can be reduced.

[0132] (Appendix 3) The display control method of claim 1, further comprising: calculating a second sum by adding the first value and a value obtained by integrating the voltage of the image signal supplied to a second data line of the electro-optical device adjacent to the first data line during the first period; and generating second correction data for correcting the image signal supplied to the second data line during the second period based on the second sum.

[0133] According to this, also for the second data line, a second sum is calculated by adding a value obtained by multiplying the voltage of the image signal supplied during the first period to the first value, and second correction data for correcting the image signal supplied to the second data line during the second period is generated based on the calculated second sum. Therefore, there is no need to separately store the first value for correcting the image signal supplied to the second data line, and the capacity of the device for storing the first value can be reduced.

[0134] (Appendix 4) 2. The display control method according to claim 1, wherein the first period and the second period each include a front porch period and a back porch period, and the first value includes a second value corresponding to a voltage supplied during the front porch period of the first period, a third value corresponding to a voltage supplied during the back porch period of the first period, and a fourth value corresponding to a voltage supplied during the back porch period of the second period.

[0135] According to this, the first value includes a second value corresponding to a voltage supplied during a front porch period of the first period, a third value corresponding to a voltage supplied during a back porch period of the first period, and a fourth value corresponding to a voltage supplied during a back porch period of the second period. Therefore, the first correction data for correcting the image signal supplied to the first data line can be generated by accurately reflecting the value corresponding to the voltage supplied during the blanking period.

[0136] (Appendix 5) 5. The display control method according to claim 4, wherein the fourth value is 0 when the polarity of the voltage of the image signal supplied to the first data line during the first period is the same as the polarity of the voltage of the image signal supplied to the first data line during the second period, and the fourth value is twice the third value when the polarity of the voltage of the image signal supplied to the first data line during the first period is different from the polarity of the voltage of the image signal supplied to the first data line during the second period.

[0137] According to this, the fourth value corresponding to the voltage supplied during the back porch period of the second period is changed depending on the polarity of the voltage of the image signal supplied to the first data line during the first period and the polarity of the voltage of the image signal supplied to the first data line during the second period. Therefore, the fourth value according to the polarity of the voltage in the first period and the second period can be added, and the first correction data for correcting the image signal supplied to the first data line can be generated with high accuracy.

[0138] (Appendix 6) a memory device that stores a first value corresponding to a voltage supplied to each of the data lines of the electro-optical device during a blanking period; and a control circuit that performs the following operations: calculating a first sum by adding the first value to a value obtained by integrating voltages corresponding to the image signal supplied to the first data lines during a first period and a second period following the first period; generating first correction data based on the first sum for correcting the image signal supplied to the first data lines during the second period; and outputting the image signal corrected using the first correction data.

[0139] According to this configuration, by calculating the first sum by adding the first value stored in advance in the storage device and the voltage corresponding to the image signal, it is possible to reduce the power consumption of the electro-optical device compared to accumulating the values ​​of each pixel during the blanking period.

[0140] (Appendix 7) 7. The display device of claim 6, wherein the storage device includes a first static random access memory and a second static random access memory, and the control circuit uses the first static random access memory to calculate a first sum by adding the first value and a value obtained by integrating voltages corresponding to image signals supplied to the first data line during the first period and the second period; uses the second static random access memory to calculate a third sum by adding the first value and a value obtained by integrating voltages corresponding to image signals supplied to the first data line during the second period and a third period subsequent to the second period; and generates third correction data for correcting the image signal supplied to the first data line during the third period based on the third sum.

[0141] According to this configuration, the first static random access memory is used to calculate a first sum by adding the first value and a value obtained by integrating the voltages corresponding to the image signals supplied in the first period and the second period, and the second static random access memory is used to calculate a third sum by adding the first value and a value obtained by integrating the voltages corresponding to the image signals supplied in the second period and the third period. When the first and second added values ​​are calculated using the first and second static random access memories, it is necessary to switch between the first and second static random access memories even when calculating a value corresponding to the voltage supplied during the blanking period, which increases power consumption. In contrast to this, according to the invention described in Supplementary Note 7, a value corresponding to the voltage supplied during the blanking period is pre-stored in the storage device as the first value, so there is no need to switch between the first static random access memory and the second static random access memory to calculate the value corresponding to the voltage supplied during the blanking period, thereby reducing power consumption. [Explanation of symbols]

[0142] 1...projector, 10...electro-optical device, 10A...light valve, 20...scanning line driving circuit, 30...data line driving circuit, 50...pixel area, 60...scanning line, 70...data line, 100...pixel circuit, 110...transistor, 120...storage capacitance, 130...liquid crystal element, 135...liquid crystal, 140...pixel electrode, 151...common electrode, 153...capacitance line, 200...control circuit, 210...control unit, 220...LUT value conversion unit, 230...accumulation permission determination unit, 240...storage unit, 250...counter calculation unit, 251...first accumulation buffer, 252...first H counter, 253 ...first L counter, 255...second integrating buffer, 256...second H counter, 257...second L counter, 260...correction coefficient calculation unit, 270...polarity determination unit, 280...correction calculation unit, 502...lamp unit, 503...dichroic mirror, 507...mirror, 510...dichroic prism, 520...projection lens group, 600...relay lens system, 601...entrance lens, 602...relay lens, 603...exit lens, 611...mirror, 612...mirror, Ctr...control signal, HSync...horizontal synchronization signal, LCcom...voltage, P...polarity inversion signal.

Claims

1. storing a first value corresponding to a voltage supplied to each of a plurality of data lines of the electro-optical device during a blanking period; calculating a first sum by adding the first value and a value obtained by integrating a voltage corresponding to an image signal supplied to a first data line among the plurality of data lines during a first period and a second period subsequent to the first period; generating first correction data for correcting the image signal supplied to the first data line during the second period based on the first added value; outputting the image signal corrected using the first correction data; A display control method comprising:

2. Inverting the polarity of a voltage supplied to the first data line between the first period and the second period; determining a sign of the first value according to a polarity of a voltage of the image signal supplied to the first data line during the first period; The display control method of claim 1 , further comprising:

3. calculating a second sum by adding the first value and a value obtained by integrating a voltage of the image signal supplied to a second data line of the electro-optical device adjacent to the first data line during the first period; generating second correction data for correcting the image signal supplied to the second data line during the second period based on the second added value; The display control method of claim 1 , further comprising:

4. the first period and the second period each include a front porch period and a back porch period; 2. The display control method according to claim 1, wherein the first value includes a second value corresponding to a voltage supplied during the front porch period of the first period, a third value corresponding to a voltage supplied during the back porch period of the first period, and a fourth value corresponding to a voltage supplied during the back porch period of the second period.

5. when the polarity of the voltage of the image signal supplied to the first data line in the first period is the same as the polarity of the voltage of the image signal supplied to the first data line in the second period, the fourth value is 0; 5. The display control method according to claim 4, wherein when the polarity of the voltage of the image signal supplied to the first data line during the first period is different from the polarity of the voltage of the image signal supplied to the first data line during the second period, the fourth value is twice the third value.

6. A plurality of scan lines; a plurality of data lines including a first data line; a plurality of pixel circuits respectively corresponding to the plurality of scanning lines and the first data lines; a drive circuit that supplies a voltage of an image signal to the first data line; an electro-optical device including: a storage device that stores a first value corresponding to a voltage supplied to each of a plurality of data lines of the electro-optical device during a blanking period; calculating a first sum by adding the first value and a value obtained by integrating voltages corresponding to the image signal supplied to the first data line during a first period and a second period subsequent to the first period; generating first correction data for correcting the image signal supplied to the first data line during the second period based on the first added value; outputting the image signal corrected using the first correction data; a control circuit for performing the A display device comprising:

7. the storage device comprises a first static random access memory and a second static random access memory; The control circuit calculating, using the first static random access memory, the first sum obtained by adding the first value and a value obtained by integrating voltages corresponding to image signals supplied to the first data line during the first period and the second period; calculating, using the second static random access memory, a third sum obtained by adding the first value and a value obtained by integrating voltages corresponding to image signals supplied to the first data line during the second period and a third period subsequent to the second period; generating third correction data for correcting the image signal supplied to the first data line during the third period based on the third added value; The display device according to claim 6, wherein the display device executes the following.

Images