Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of securing a withstand voltage between narrow-pitch wiring and a via, and to provide a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device according to an embodiment includes a plurality of first wiring layers arranged at a predetermined distance from each other, a plurality of air gap layers arranged between the plurality of first wiring layers so as to protrude from the height positions of the first wiring layers and extend along the first wiring layers, and a plurality of second wiring layers arranged above the plurality of first wiring layers, wherein the plurality of vias are connected to any of the plurality of second wiring layers and extend above the plurality of air gap layers to the plurality of first wiring layers, the semiconductor device includes an upper structure having a first diameter larger than a width of each of the plurality of first wiring layers in a first direction intersecting an extending direction of the plurality of first wiring layers, and a lower structure extending at a height position of the plurality of air gap layers, connected to any of the plurality of first wiring layers, and having a second diameter smaller than the first diameter.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] As semiconductor devices become smaller, the distance and pitch between interconnects are becoming smaller, which increases the capacitance between interconnects and between the interconnects and vias that connect the interconnects, raising concerns about insufficient breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-060918 [Patent Document 2] Japanese Patent Application Publication No. 2020-155490 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-120988 [Non-patent literature]

[0004] [Non-Patent Document 1] K. Motoyama et al., “A novel integration scheme for self-aligned Ru topvia as post-Cu alternative metal interconnects”, 2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC / MAM), Dresden, Germany,IEEE,22-25 May 2023. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor device and a method for manufacturing the semiconductor device that can ensure a withstand voltage between narrow-pitch wiring and vias. [Means for solving the problem]

[0006] a plurality of second wiring layers disposed above the plurality of first wiring layers; and a plurality of vias extending from the plurality of second wiring layers between the plurality of air gap layers to the plurality of first wiring layers and connecting the plurality of first and second wiring layers, wherein the plurality of vias each include an upper structure connected to one of the plurality of second wiring layers and extending above the plurality of air gap layers to the plurality of first wiring layers, the upper structure having a first diameter greater than a width of each of the plurality of first wiring layers in a first direction intersecting with the extension direction of the plurality of first wiring layers; and a lower structure extending at a height position of the plurality of air gap layers and connected to one of the plurality of first wiring layers, the upper structure having a second diameter smaller than the first diameter. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram showing a schematic configuration example of a semiconductor device according to an embodiment; [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 3] 3A and 3B are schematic diagrams showing an example of a layout of various components in a memory region of the semiconductor device according to the embodiment; [Figure 4] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] [Embodiment] Hereinafter, the embodiments will be described in detail with reference to the drawings.

[0010] (Configuration example of semiconductor device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor device 1 according to an embodiment. More specifically, Fig. 1A is a cross-sectional view of the semiconductor device 1 taken along the X direction, and Fig. 1B is a schematic plan view illustrating the layout of the semiconductor device 1.

[0011] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0012] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0013] As shown in FIG. 1(a), the semiconductor device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0014] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from outside to the semiconductor device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL.

[0015] 1(a) and 1(b), a memory region MR is arranged in the center in the X direction of the plurality of word lines WL, etc., and staircase regions SR are arranged at both ends in the X direction of the plurality of word lines WL, etc. These memory region MR and staircase regions SR are divided into a plurality of regions by a plurality of plate-like contacts LI that extend in the X direction and penetrate the plurality of word lines WL, etc.

[0016] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0017] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0018] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction thereof. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0019] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0020] In this specification, the direction in which the terrace surfaces of the word lines WL and select gate lines SGD and SGS face is defined as the upper side of the semiconductor device 1.

[0021] The above-mentioned isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0022] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0023] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0024] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0025] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0026] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0027] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components including the word lines WL.

[0028] The semiconductor substrate SB above the insulating layer 50 covering the above-described configuration is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0029] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0030] Next, a detailed configuration example of the semiconductor device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the embodiment.

[0031] More specifically, Figure 2(a) is a cross-sectional view along the X direction in the memory region MR of the semiconductor device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0032] Fig. 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS. Fig. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL. Fig. 2(d) is an enlarged cross-sectional view along the X direction showing the connection state between the bit line BL and the upper layer wiring M1.

[0033] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be, for example, a conductive polysilicon layer into which impurities are diffused.

[0034] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA within the insulating layer 50 outside the laminated body LM.

[0035] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0036] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0037] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0038] The upper surface of the laminate LM is covered with insulating layers 52 to 55 in this order. Each of the insulating layers 52 to 55 constitutes a part of the insulating layer 50 in FIG.

[0039] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0040] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0041] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0042] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0043] More specifically, the channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is disposed on the side surface of the pillar PL except for the depth of the intermediate source line BSL. The memory layer ME is also disposed on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0044] As a result, the channel layer CN is brought into contact with the intermediate source line BSL at the side surface, and further, is electrically connected to the entire source line SL via the intermediate source line BSL.

[0045] The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. Furthermore, the cap layer CP is connected to a bit line BL disposed further above the insulating layer 52 via a plug CH disposed in the uppermost insulating layer OL of the laminate LM and a plug VY disposed in the insulating layer 52. The bit line BL extends above the laminate LM in the Y direction so as to intersect with the leading-out direction of the word line WL.

[0046] As shown in FIGS. 2(b) and 2(c), the memory layer ME has a stacked structure including, in order from the outer periphery of the pillar PL, a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN.

[0047] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0048] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0049] As shown in Figure 2(b), select gates STD are formed on the side surfaces of the pillars PL facing select gate lines SGD0 and SGD1, respectively, and select gates STS are formed on the side surfaces of the pillars PL facing select gate lines SGS0 and SGS1 located below the word lines WL.

[0050] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0051] As shown in FIG. 2(a), the bit lines BL extend in the Y direction on an insulating layer 52 that covers the laminated body LM, at predetermined distances from one another in the X direction.

[0052] The pillars PL aligned in the X direction are connected to every predetermined number of bit lines BL, which are aligned at predetermined intervals in the X direction, via the plugs CH and VY described above. For example, in the example of FIG. 2(a), the pillars PL are connected to every fifth bit line BL. The other bit lines BL are connected to pillars PL different from the pillars PL shown in FIG. 2(a) at positions different from the cross section shown in FIG. 2(a) via plugs CH and VY (not shown in FIG. 2(a)).

[0053] The plurality of bit lines BL are covered with an insulating layer 53. Air gap layers 56 are disposed between the plurality of bit lines BL. These air gap layers 56 protrude up to the height position of the upper surface of the insulating layer 53, and also divide the insulating layer 53 into a plurality of linear shapes extending in the Y direction.

[0054] The plurality of bit lines BL are connected to upper layer wiring M1 disposed in insulating layer 55 via vias V1 that extend through insulating layers 54 and 53.

[0055] 2(d), the via V1 includes an upper via TPv having a diameter larger than the width of the bit line BL in the X direction, and a lower via BTv having a diameter smaller than the diameter of the upper via TPv. More specifically, the diameter of the lower via BTv is approximately equal to the width of the bit line BL in the X direction.

[0056] The upper via TPv is connected to the upper layer wiring M1 at its upper end and extends downward in the insulating layer 54. The lower via BTv extends downward in the insulating layer 53 from the lower end of the upper via TPv and is connected to the bit line BL at its lower end.

[0057] The upper via TPv and the lower via BTv are connected at a height position between the height position of the upper surface of the insulating layer 53 and the height position of the upper surface of the bit line BL. As a result, the via V1 has a step LVv that protrudes into the air gap layer 56 on both sides in the X direction at the connection portion between the upper via TPv and the lower via BTv.

[0058] Preferably, the upper via TPv and the lower via BTv are connected at a height position that is a predetermined distance above the top surface of the bit line BL. This allows a large distance D to be secured between the most protruding part of the via V1 at the step LVv and the bit line BL to which the via V1 is connected and the bit line BL adjacent to it in the X direction, thereby reducing the capacitance between the via V1 and the adjacent bit line BL.

[0059] In addition, the via V1 and the adjacent bit line BL are separated by an air gap layer 56 having a low dielectric constant. The air gap layer 56 has a dielectric constant of, for example, 1. This further reduces the capacitance between the via V1 and the bit line BL, ensuring a sufficient breakdown voltage.

[0060] It is preferable that the distance D between the protruding portion of the step LVv of the via V1 and the adjacent bit line BL is equal to or greater than the distance between the plurality of bit lines BL, for example.

[0061] Next, a detailed example of the connection between the pillars PL and the bit lines BL will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing an example of the layout of various components in the memory region MR of the semiconductor device 1 according to the embodiment.

[0062] More specifically, Fig. 3(a) is a schematic diagram showing an example of a connection between pillars PL and plugs CH, VY. Figs. 3(b) and 3(c) are enlarged views of a portion of the memory region MR, with Fig. 3(b) omitting the bit lines BL and Fig. 3(c) showing the bit lines BL. Fig. 3(d) is a schematic top view showing a portion of the memory region MR.

[0063] As shown in FIG. 3(d) and as described above, the memory region MR between the plate contacts LI adjacent in the Y direction is separated into a plurality of sections by a plurality of separation layers SHE extending along the X direction.

[0064] That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction of the stacked body LM and the X direction. More specifically, the plate-shaped contacts LI penetrate the stacked body LM and the upper source line DSLb to reach the intermediate source line BSL (see FIG. 2(a)).

[0065] On the other hand, the multiple isolation layers SHE extend in the X direction through the regions between the plate-like contacts LI adjacent in the Y direction, penetrating the upper layer portion of the stacked body LMb. More specifically, these isolation layers SHE penetrate the select gate lines SGD0 and SGD1 (see FIG. 2(a)) and reach the insulating layer OL immediately below the select gate line SGD1.

[0066] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0067] Between the plate contact LI and the separation layer SHE adjacent in the Y direction, and between the separation layers SHE adjacent in the Y direction, the pillars PL are arranged in multiple rows extending in the X direction. In the rows shown in FIG. 3(d), the pillars PL are arranged in five rows R1 to R5. However, one end side in the Y direction of the pillars PL belonging to rows R1 and R5 adjacent to the separation layer SHE overlaps with the separation layer SHE when viewed from the stacking direction of the laminate LM. The separation layer SHE is, for example, an insulating layer, and does not affect the electrical characteristics of the pillars PL even if it comes into contact with the pillars PL.

[0068] In the arrangement of these pillars PL, the pillars PL belonging to adjacent columns R1 and R2, columns R2 and R3, columns R3 and R4, and columns R4 and R5 are arranged with their positions shifted in the Y direction so as not to overlap with each other in the Y direction. On the other hand, the pillars PL belonging to adjacent columns R1, R3, and R5, and columns R2 and R4, which are separated by an adjacent column, are arranged so that their positions in the Y direction are the same.

[0069] As a result, the pillars PL are arranged in a staggered pattern when viewed from the stacking direction of the laminate LM, for example. More preferably, the pillars PL are arranged at substantially equal pitches.

[0070] As described above, by arranging the pillars PL so as to allow interference between some of the pillars PL and the separation layer SHE, it is possible to maintain a periodic arrangement, such as a staggered arrangement, of the pillars PL, which allows for increased processing accuracy when forming the pillars PL at high density.

[0071] To explain the pillar PL overlapping with the isolation layer SHE in more detail, the pillar PL is arranged in the region between the plate-shaped contact LI and the isolation layer SHE, and one end side in the Y direction of the pillar PL belonging to column R1 or column R5 overlaps with the isolation layer SHE at the height of the select gate line SGD, and that portion is missing. Also, the select gate line SGD surrounding the pillar PL of column R1 or column R5 overlaps with the isolation layer SHE, and that portion is missing.

[0072] However, the select transistors STD formed at the intersections of the pillars PL and the select gate lines SGD are adjusted to function as select transistors STD in the pillars PL of column R1 or column R5. Furthermore, because the isolation layers SHE do not reach the height of the word lines WL, no chips are formed in the pillars PL of column R1 or column R5, and there are no chips in the word lines WL either. Therefore, the memory cells MC formed at the intersections of the pillars and word lines WL in column R1 or column R5 function in the same way as memory cells MC belonging to the pillars PL of other columns.

[0073] Similarly, one end of the pillar PL in the Y direction, which is disposed in the region between the two isolation layers SHE and belongs to columns R1 and R5, overlaps with the isolation layer SHE at the height of the select gate line SGD, and that portion is missing. Also, the select gate line SGD surrounding the pillar PL in columns R1 and R5 overlaps with the isolation layer SHE, and that portion is missing.

[0074] However, the select transistors STD formed at the intersections of the pillars PL and the select gate lines SGD are adjusted to function as select transistors STD in the pillars PL of columns R1 and R5 as well. Because the isolation layers SHE do not reach the height of the word lines WL, no chips are formed in the pillars PL of columns R1 and R5, and there are no chips in the word lines WL either. Therefore, the memory cells MC formed at the intersections of the pillars and word lines WL in columns R1 and R5 function in the same way as memory cells MC belonging to the pillars PL of other columns.

[0075] As shown in FIG. 3(a) and as described above, plugs CH and VY are arranged in this order from the pillar PL side at the upper end of the pillar PL, and each pillar PL is connected to the bit line BL above via these plugs CH and VY.

[0076] That is, above these pillars PL, a plurality of bit lines BL are arranged, for example, spaced a predetermined distance from each other in the X direction and extending in the Y direction. More preferably, the plurality of bit lines BL are arranged at substantially equal intervals in the X direction.

[0077] Each pillar PL is electrically connected to one of these bit lines BL. In this case, in order to enable individual driving of the memory cells MC belonging to each pillar PL, the pillar PL arranged between the plate-shaped contact LI and the isolation layer SHE adjacent in the Y direction, and between the isolation layers SHE adjacent in the Y direction, are connected to different bit lines BL. Figure 3(c) shows the configuration of the pillar PL to achieve this connection configuration.

[0078] 3(b), the pillars PL have, for example, a circular shape when viewed from the stacking direction of the laminate LM, but may also have other shapes such as an oval or elliptical shape.

[0079] The plug CH at the upper end of the pillar PL has, for example, a top surface shape similar to that of the pillar PL. In the example of Fig. 3(b), like the circular pillar PL, the plug CH also has a circular shape when viewed from the stacking direction of the laminate LM. However, the plug CH may have another shape, such as an oval shape.

[0080] When viewed from the stacking direction of the laminate LM, the outer shape of the plug CH is smaller than the outer shape of the pillar PL and is disposed so as to fit within the range of the upper surface of the pillar PL. Moreover, when viewed from the stacking direction of the laminate LM, the center point of the plug CH substantially coincides with the center point of the corresponding pillar PL.

[0081] On the other hand, the plug VY disposed on the upper surface of the plug CH has an elliptical shape with the longitudinal direction along, for example, the Y direction. That is, the plug VY extends in the direction in which the bit line BL extends.

[0082] Furthermore, the center point of the plug VY as viewed from the stacking direction of the laminate LM substantially coincides with the center points of the corresponding pillar PL and plug CH in the Y direction, but is offset in the X direction. In this case, the amount of offset between the center point of the plug VY and the center points of the corresponding pillar PL and plug CH differs for each pillar PL so that the pillar PL arranged between the plate contact LI and the isolation layer SHE adjacent in the Y direction and between the isolation layers SHE adjacent in the Y direction are connected to different bit lines BL.

[0083] As shown in Figure 3(c), when the bit line BL is superimposed on Figure 3(b), it can be seen that, due to the above configuration, the pillars PL arranged between the plate-shaped contact LI and the isolation layer SHE adjacent in the Y direction, and between the isolation layers SHE adjacent in the Y direction, are each connected to a different bit line BL.

[0084] More specifically, the position of each plug VY in the X direction is determined according to the position of the bit line BL to be connected among the multiple bit lines BL in the X direction. Therefore, as described above, the amount of deviation in the X direction between the center point of the plug VY and the center points of the corresponding pillar PL and plug CH varies individually, and such displacement of the center points makes it possible to connect the pillar PL arranged between the plate contact LI and the isolation layer SHE and between the isolation layers SHE to different bit lines BL individually.

[0085] That is, in the example shown in FIG. 3( c), between the plate-shaped contact LI and the isolation layer SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL1, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL4, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL2, is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL5, is connected to bit line BL3 via plugs CH and VY.

[0086] In the example shown in FIG. 3(c), between the separation layers SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL5, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL2, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL4, is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL1, is connected to bit line BL3 via plugs CH and VY.

[0087] In this way, the multiple bit lines BL are connected to any of the pillars PL in each of the columns R1 to R5 at intervals of 5. In other words, among the arrangement of the multiple pillars PL, the pillars PL belonging to the same column of the columns R1 to R5 are connected to every fifth bit line BL, the number of which is the same as the number of the pillars PL arranged, among the multiple bit lines BL aligned in the Y direction.

[0088] As described above, in order to connect to each of the plurality of pillars PL arranged in a staggered pattern at high density, the distance between the plurality of bit lines BL in the X direction is also reduced and they are arranged at a narrow pitch.

[0089] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to Fig. 4 to Fig. 16. Fig. 4 to Fig. 16 are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor device 1 according to the embodiment. Fig. 4 to Fig. 16, excluding some drawings of Fig. 9 to Fig. 11, Fig. 14, and Fig. 16, show a cross section along the X direction of a region that will later become the memory region MR.

[0090] As shown in FIG. 4(a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are formed in this order on a support substrate SS.

[0091] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. The insulating layer 60 (see FIG. 2(a)) may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0092] A stacked body LMsa is formed on the upper source line DSLb, in which multiple insulating layers NL and multiple insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become the word lines WL or the select gate lines SGS.

[0093] After that, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsa multiple times.

[0094] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are recessed to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the laminate LMsa is formed with a stepped shape at both ends in the X direction.

[0095] Thereafter, the staircase shape at both ends in the X direction is covered with a part of the insulating layer 50 (see FIG. 1(a)).

[0096] As shown in FIG. 4(b), multiple memory holes MHa are formed in the stack LMsa, extending in the stacking direction. The multiple memory holes MHa penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reach the lower source line DSLa. These memory holes MHa will later become the lower structure of the pillar PL.

[0097] 4(c), these memory holes MHa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer, thereby forming pillars PLc in which the sacrificial layer 26 is filled in the multiple memory holes MHa.

[0098] 5(a), a laminate LMsb is formed by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL, covering the laminate LMsa. The insulating layers NL of the laminate LMsb function as sacrificial layers that will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0099] After this, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the processing performed on the laminate LMsa described above.

[0100] At this time, the uppermost step of the staircase portion already formed in the laminate LMsa and the lowermost step of the staircase portion formed in the laminate LMsb are brought close to each other to form a staircase shape that is continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. As a result, the laminates LMsa and LMsb are formed with staircase regions SR having a staircase shape extending from the laminate LMsa to the laminate LMsb, at both ends in the X direction.

[0101] Thereafter, the staircase shape at both ends in the X direction is further covered with a part of the insulating layer 50 (see FIG. 1(a)).

[0102] As shown in Fig. 5(b), multiple memory holes MHb are formed through the stack LMsb and connected to the multiple pillars PLc already formed in the stack LMsa. The memory holes MHb will later become the upper structure of the pillars PL.

[0103] 6(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, a memory hole MHa is opened at the bottom of each of the memory holes MHb, and a plurality of memory holes MH are formed that penetrate the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0104] In addition, if the sacrificial layer 26 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in forming the memory holes MHb in Figure 5(b) above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed all at once from these pillars PLc.

[0105] As shown in FIG. 6(b), the memory layer MEb, the channel layer CNb, and the core layer CRb are formed in this order in the memory hole MH. As a result, the memory layer MEb and the channel layer CNb are formed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the core layer CRb is filled in the center of the memory hole MH. The memory layer MEb, the channel layer CNb, and the core layer CRb are also formed in this order on the top surface of the stacked body LMsb.

[0106] 7(a), the core layer CRb, the channel layer CNb, and the memory layer MEb formed on the upper surface of the laminate LMsb are etched back to form the core layer CR, the channel layer CN, and the memory layer ME individually separated in the memory hole MH. In addition, a recess DN is formed in the upper end of the core layer CR.

[0107] 7(b), a cap layer CPb is formed in the recess DN at the upper end of the memory hole MH, and also on the upper surface of the stacked body LMsb.

[0108] As shown in FIG. 8(a), the cap layer CPb on the upper surface of the laminated body LMsb is removed by CMP or the like together with a part of the insulating layer OL that is the uppermost layer of the laminated body LMsb, to form the cap layer CP disposed at the upper end of the memory hole MH.

[0109] As shown in Figure 8(b), an insulating layer OL is deposited on the top layer of the laminate LMsb, which has been thinned by CMP or the like. This forms a pillar PL in which the cap layer CP is buried in the top insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and only a portion of the side surface of the channel layer CN is exposed from the memory layer ME.

[0110] 9 to 11 show cross sections along the Y direction as well as cross sections along the X direction of the region that will later become the memory region MR. More specifically, (Aa) and (Ab) in FIGS. 9 to 11 show cross sections along the X direction, and (Ba) and (Bb) show cross sections along the Y direction.

[0111] 9(Ba), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 57 are formed on the side walls of the slit ST that face each other in the Y direction. The slit ST also extends in the X direction within the stacked bodies LMsa, LMsb.

[0112] As shown in Figures 9(Ab) and (Bb), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 57 to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0113] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs. At this time, since the sidewalls of the slits ST are protected by the insulating layer 57, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well.

[0114] 10(Aa)(Ba), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b)(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0115] 10(Ab) and 10(Bb), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 67, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0116] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL. After that, the insulating layer 57 on the side wall of the slit ST is removed.

[0117] 11(Aa) and 11(Ba), the insulating layers NL of the laminates LMsa and LMsb are removed by flowing an insulating layer NL remover, such as hot phosphoric acid, into the interior of the laminates LMsa and LMsb through the slits ST from which the insulating layers 57 have been removed. This forms laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0118] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. The multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layers OL remaining in the laminates LMga and LMgb from bending and prevents the laminates LMga and LMgb from being distorted or broken.

[0119] 11(Ab) and 11(Bb), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST, and the gap layers GP of the laminates LMga, LMgb are filled with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0120] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0121] After this, although not shown, a conductive layer is filled into the slit ST via an insulating liner layer or the like to form a plate-like contact LI. A trench is then formed through one or more conductive layers, including the top conductive layer of the stack LMb, and an insulating layer is filled into the trench to form a separation layer SHE that separates these conductive layers into the pattern of the select gate line SGD. A plurality of contacts CC are also formed from above the staircase region SR, reaching the word lines WL and select gate lines SGD and SGS that constitute each step of the staircase structure in the staircase region SR.

[0122] As shown in FIG. 12(a), a plug CH is formed that penetrates the uppermost insulating layer OL of the laminated body LM and is connected to the cap layer CP at the upper end of the pillar PL.

[0123] As shown in FIG. 12(b), an insulating layer 52 is formed to cover the laminate LM.

[0124] As shown in FIG. 13(a), a plug VY is formed which penetrates the insulating layer 52 and is connected to the plug CH.

[0125] As shown in FIG. 13(b), a metal layer BLb is formed to cover the insulating layer 52 in which the plugs VY are formed. The metal layer BLb is a layer that will later be formed into a pattern spaced apart from each other in the X direction and extending in the Y direction to become the bit lines BL. An insulating layer 53 is also formed to cover the metal layer BLb. At this point, the insulating layer 53 is formed to be thicker than the insulating layer 53 that will ultimately be included in the semiconductor device 1.

[0126] 14 to 16, the laminate LM below the insulating layer 52 and pillars PL formed on the laminate LM are omitted from the illustration.

[0127] 14(a), a metal mask pattern MK such as a tungsten layer is formed on an insulating layer 53. In a memory region MR in which a plurality of pillars PL are arranged, the metal mask pattern MK has a line-and-space pattern that is spaced apart from each other in the X direction and extends in the Y direction.

[0128] 14(b), the metal mask patterns MK are connected to each other in a loop and terminate at a position a predetermined distance away from the memory region MR in the Y direction. Such metal mask patterns MK are formed by, for example, a multi-patterning method.

[0129] In forming a metal mask pattern MK using a multi-patterning method, a core pattern such as an insulating layer is formed in the spaces of the metal mask pattern MK having a line-and-space pattern. The sidewalls of these cores are then covered with a metal layer such as a tungsten layer, and the cores are then removed. As a result, the metal layer formed on the sidewalls of the cores is formed into a metal mask pattern MK having a line-and-space pattern.

[0130] By using the multi-patterning method, it is possible to obtain a metal mask pattern MK having a line and space pattern that is finer and has a narrower pitch than the pattern that serves as the core material.

[0131] As shown in FIG. 14( c ), the insulating layer 53 exposed from the metal mask pattern MK is etched to transfer the line and space pattern of the metal mask pattern MK to the insulating layer 53 .

[0132] 14(d), the metal layer BLb is etched using the patterned insulating layer 53 as a mask, and the line-and-space pattern is further transferred to the metal layer BLb to form a plurality of bit lines BL spaced apart from each other in the X direction and extending in the Y direction. This reduces the thickness of the insulating layer 53 to, for example, the layer thickness that the semiconductor device 1 will ultimately have.

[0133] 15(a), an insulating layer 56s such as a silicon nitride layer is formed in the spaces between the insulating layer 53 having a line-and-space pattern and the bit lines BL. That is, the insulating layer 56s extends in the Y direction between the insulating layer 53 and the multiple lines of the bit lines BL.

[0134] As shown in FIG. 15(b), an insulating layer 54 is formed to cover the entire surfaces of the insulating layers 53 and 56s.

[0135] As shown in FIG. 15(c), via holes VL are formed at positions corresponding to the plugs VY connected to the pillars PL, respectively, so as to penetrate the insulating layers 54 and 53 and reach the bit lines BL.

[0136] The via hole VL is configured so that the diameter of the upper end is larger than the width of the bit line BL in the X direction, and is formed in the insulating layers 53 and 54, which are silicon oxide layers or the like, using etching conditions that have a selectivity with the insulating layer 56s, which is a silicon nitride layer or the like.

[0137] During the formation of the via hole VL, the etching end of the via hole VL penetrates the insulating layer 54 and reaches the upper surfaces of the insulating layers 53 and 56s. At this time, etching conditions are used that provide a selectivity for the insulating layer 53 relative to the insulating layer 56s. Therefore, from this point on, of the insulating layers 53 and 56s, etching of the insulating layer 53 proceeds preferentially, and etching of the insulating layer 56s stagnates.

[0138] As a result, the via hole VL is narrowed to a diameter at a height between the upper surfaces of the insulating layers 53, 56s and the upper surface of the bit line BL, which is approximately equal to the distance between the insulating layers 56s in the X direction, i.e., the width of the bit line BL in the X direction.

[0139] As a result, the via hole VL is formed to include an upper via hole TPh that extends downward in the insulating layer 54 and has a diameter larger than the width of the bit line BL in the X direction, and a lower via hole BTh that has a diameter smaller than that of the upper via hole TPh and extends downward in the insulating layer 53 to reach the bit line BL. The via hole VL also has a step LVh at the connection portion between the upper via hole TPh and the lower via hole BTh.

[0140] At this time, the higher the selectivity with respect to the insulating layer 56s, the closer the step LVh is to the top surfaces of the insulating layers 53 and 56s.

[0141] As shown in Fig. 15(d), a conductive layer is filled into the via hole VL, whereby the upper via hole TPh becomes an upper via TPv, the lower via hole BTh becomes a lower via BTv, and a via V1 having a step LVv (see Fig. 2(d)) is formed.

[0142] As described above, by forming the via hole VL while maintaining the selectivity with the insulating layer 56s, for example, the via V1 having a diameter larger than the width of the bit line BL in the X direction can be connected to the narrow-pitch bit line BL in a self-aligned manner. That is, there is no need to form the via hole VL having a fine diameter that matches the width of the bit line BL throughout, and even if the via hole VL is formed in a position misaligned with the bit line BL, interference between the adjacent bit line BL and the via V1 is suppressed.

[0143] Thereafter, as shown in FIG. 16, a process called loop cut is performed in which the bit lines BL connected to each other in a loop are individually cut off.

[0144] As shown in Figure 16(a), a mask pattern MKp such as a photoresist layer having an opening OP is formed a predetermined distance in the Y direction from the memory region MR, near the area where the above-mentioned metal mask pattern MK is transferred and the bit lines BL are connected to each other in a loop shape.

[0145] In addition, by removing the insulating layer 54, insulating layers 53, 56s, and bit lines BL exposed from the openings OP of the mask pattern MKp and exposing the insulating layer 52 below the bit lines BL, the bit lines BL on the memory region MR side are cut off from the loop-shaped portion and separated into individual bit lines BL.

[0146] As shown in FIG. 16(b), by removing the insulating layers 54, 53, 56s and the bit lines BL, the cut surfaces of these layers are exposed in the openings OP of the mask pattern MKp.

[0147] 16(c), a chemical solution is allowed to penetrate from the cut surfaces of the insulating layers 54, 53, 56s and the bit line BL, and the insulating layer 56s, which is, for example, a silicon nitride layer, is entirely removed by wet etching, etc. As a result, a plurality of air gap layers 56 are formed between and along the bit line BL and insulating layer 53 having a line-and-space pattern, extending in the Y direction.

[0148] As shown in FIG. 16(d), the entire insulating layer 56s is removed by wet etching or the like, thereby forming air gap layers 56 on both sides in the X direction of the via V1, which is disposed in the memory region MR and connected to the pillar PL via the bit line BL or the like.

[0149] Thereafter, an insulating layer 55 is formed on the upper surface of the insulating layer 54, and upper layer wiring M1 connected to each via V1 is formed in the insulating layer 55. Also, electrode pads and the like for electrical conduction with the peripheral circuit CBA are formed on the uppermost surface of the insulating layer 50 including the insulating layers 52 to 55 and the like.

[0150] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0151] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0152] In this manner, the semiconductor device 1 of the embodiment is manufactured.

[0153] (Overview) In order to increase the storage capacity of semiconductor devices such as three-dimensional nonvolatile memories, attempts are being made to increase the layout density of pillars that create memory cells in three dimensions. Accordingly, the density of bit lines connected to the pillars and the wiring above the bit lines is also increasing. As the pitch between the wiring lines is reduced, the capacitance between the wiring lines and the vias connecting these lines increases, making it difficult to ensure sufficient breakdown voltage.

[0154] The semiconductor device 1 of the embodiment includes a plurality of vias V1 that extend from the plurality of upper layer wirings M1 to the plurality of bit lines BL between the plurality of air gap layers 56 and connect the plurality of bit lines BL to the plurality of upper layer wirings M1, respectively. This ensures a breakdown voltage between the narrow-pitch bit lines BL and the vias V1.

[0155] According to the semiconductor device 1 of the embodiment, the multiple vias V1 each include an upper via TPv that is connected to one of the multiple upper layer wirings M1 and extends above the multiple air gap layers 56 to the multiple bit lines BL, and has a diameter larger than the width of each of the multiple bit lines BL in the X direction that intersects with the extension direction of the multiple bit lines BL, and a lower via BTv that extends at a height position of the multiple air gap layers 56 and is connected to one of the multiple bit lines BL, and has a diameter smaller than the diameter of the upper via TPv.

[0156] Such a via V1 structure is obtained by forming the via holes VL while ensuring a selectivity with respect to the insulating layer 56s, which will be removed later and become the air gap layer 56. This allows multiple vias V1 to be connected to narrow-pitch bit lines BL in a self-aligned manner.

[0157] According to the semiconductor device 1 of the embodiment, the steps LVv of the multiple vias V1 protrude into the multiple air gap layers 56. This further ensures the breakdown voltage between the narrow-pitch bit lines BL and the vias V1.

[0158] According to the semiconductor device 1 of the embodiment, the diameter of the lower via BTv is approximately equal to the width of each of the bit lines BL in the X direction, which prevents the via V1 from interfering with the bit line BL adjacent to the bit line BL connected to the via V1 in the X direction.

[0159] The semiconductor device 1 of the embodiment includes a plurality of pillars PL that extend within the laminate LM in the stacking direction of the laminate LM, each having a channel layer CN connected to one of a plurality of bit lines BL, and arranged in a plurality of rows in the Y direction intersecting the X direction. In this way, the narrow-pitch bit lines BL corresponding to the high-density pillars PL and the upper layer wiring M1 can be connected with low capacitance and high breakdown voltage by the vias V1 of the embodiment.

[0160] In the above-described embodiment, the semiconductor device 1 includes a stack LM having a two-tier structure in which two stacks LMa and LMb are stacked one above the other. However, the configuration of the stack is not limited to two tiers, and may be one tier, or three or more tiers.

[0161] In the above-described embodiment, the pillars PL and the like are connected to the source lines SL at the side surfaces of the channel layers CN, but this is not limiting. For example, the pillars may be configured so that the memory layer at the bottom of the pillars is removed and the lower end of the channel layer is connected to the source lines.

[0162] In the above-described embodiment, the peripheral circuits CBA and CUA are arranged above or below the stacked body LM. However, the peripheral circuits may be arranged on the same layer as the stacked body. In this case, the stacked body can be formed at a different position from the peripheral circuits on the semiconductor substrate on which the peripheral circuits are formed.

[0163] In the above-described embodiment, the via V1 formed in a self-aligned manner and the air gap layer 56 disposed around it are used in the connection structure between the bit line BL and the upper layer wiring M1. However, the configuration of the above-described embodiment may be applied to other parts of the semiconductor device 1, such as the connection structure between the contact CC disposed in the staircase region SR and the upper layer wiring.

[0164] Furthermore, in the above-described embodiment, the above configuration is applied to a semiconductor device 1 such as a three-dimensional nonvolatile memory, but other semiconductor devices such as a DRAM (Dynamic Random Access Memory) may also have a narrow-pitch wiring structure, and the configuration of the above-described embodiment can also be applied to these structures.

[0165] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0166] 1...semiconductor device, 52 to 55, 56s...insulating layer, 56...air gap layer, BTh...lower via hole, BTv...lower via, CH, VY...plug, CN...channel layer, LI...plate-shaped contact, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...laminated body, LVh, LVv...step, M1...upper wiring, MC...memory cell, MR...memory region, NL, OL...insulating layer, PL...pillar, SR...staircase region, SGD, SGS...select gate line, SHE...isolation layer, ST...slit, TPh...upper via hole, TPv...upper via, V1...via, VL...via hole, WL...word line.

Claims

1. a plurality of first wiring layers arranged at predetermined distances from each other; a plurality of air gap layers disposed between the plurality of first wiring layers, each of the air gap layers protruding from a height position of the first wiring layers and extending along the first wiring layers; a plurality of second wiring layers disposed above the plurality of first wiring layers; a plurality of vias extending from the plurality of second wiring layers between the plurality of air gap layers to the plurality of first wiring layers and connecting the plurality of first and second wiring layers, The plurality of vias are an upper structure connected to any of the plurality of second wiring layers and extending above the plurality of air gap layers to the plurality of first wiring layers, the upper structure having a first diameter larger than a width of each of the plurality of first wiring layers in a first direction intersecting an extension direction of the plurality of first wiring layers; a lower structure extending at a height position of the plurality of air gap layers and connected to any one of the plurality of first wiring layers, the lower structure having a second diameter smaller than the first diameter, Semiconductor device.

2. The plurality of vias are a step is provided at a connection portion between the upper structure and the lower structure, The semiconductor device according to claim 1 .

3. The plurality of vias are the connection portions between the upper structure and the lower structure are located at height positions between upper surfaces of the plurality of air gap layers and upper surfaces of the plurality of first wiring layers, The step is each protruding into the plurality of air gap layers; The semiconductor device according to claim 2 .

4. The second diameter of the lower structure is: equal to the width of each of the plurality of first wiring layers in the first direction, The semiconductor device according to claim 1 .

5. a laminated body disposed below the plurality of first wiring layers, in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated one by one; a plurality of pillars extending within the stack in a stacking direction of the stack, each having a semiconductor layer connected to one of the plurality of first wiring layers, and arranged in n columns (n ​​is an integer of 2 or more) in a second direction intersecting the first direction; The semiconductor device according to claim 1 .

6. a first metal layer and a first insulating layer are laminated in this order; forming a plurality of trenches penetrating the first insulating layer and the first metal layer, and forming a plurality of first wiring layers arranged at predetermined distances from each other by the plurality of trenches in a first direction along a surface direction of the first metal layer; filling the plurality of trenches with a second insulating layer; forming a third insulating layer covering the first and second insulating layers; forming a plurality of vias that penetrate the third insulating layer and the first insulating layer and are connected to the plurality of first wiring layers, respectively; removing the second insulating layer filled between the plurality of first wiring layers from positions spaced apart from the plurality of vias in a second direction intersecting the first direction to form a plurality of air gap layers on both sides of the plurality of vias in the first direction; The formation of the plurality of vias includes: forming a plurality of via holes having a first diameter larger than the width of each of the plurality of first wiring layers in the first direction, the via holes penetrating the third and first insulating layers while maintaining a selection ratio with respect to the second insulating layer; and filling the plurality of via holes with a conductive layer. A method for manufacturing a semiconductor device.

7. The formation of the plurality of via holes includes: forming upper via holes each having the first diameter and extending above the second insulating layer to the first wiring layers; forming lower via holes each having a second diameter smaller than the first diameter, the lower via holes extending through the second insulating layer while maintaining a selectivity with respect to the second insulating layer and being connected to the plurality of first wiring layers, The method for manufacturing a semiconductor device according to claim 6 .

8. The plurality of via holes are a step is formed at a connection portion between the upper via hole and the lower via hole, The method for manufacturing a semiconductor device according to claim 7 .

9. The formation of the plurality of air gap layers includes: removing a portion of the first to third insulating layers at the position spaced apart from the plurality of vias in the second direction; removing the entire second insulating layer from a cross section of the second insulating layer exposed by removing the first and third insulating layers. The method for manufacturing a semiconductor device according to claim 6 .

10. The formation of the plurality of first wiring layers includes: forming the plurality of first wiring layers in a loop shape; removing a portion of the first wiring layers to separate the first wiring layers from one another when removing the first to third insulating layers. The method for manufacturing a semiconductor device according to claim 9 .

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