Semiconductor device and method of manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: An insulating film IF2, a conductive film PL formed on the insulating film IF2, an interlayer insulating film IL formed so as to cover the conductive film PL, a contact hole CH1 formed in the interlayer insulating film IL, the conductive film PL, and the insulating film IF2, and a plug CH1 embedded in the contact hole PG1. In the contact hole CH1, the first side surface of the interlayer insulating film IL is separated from the second side surface of the conductive film PL so that a part of the upper surface of the conductive film PL is exposed from the interlayer insulating film IL. In the contact hole CH1, the third side surface of the insulating film IF2 is separated from the second side surface of the conductive film PL so that a part of the lower surface of the conductive film PL is exposed from the insulating film IF2. The plug PG1 includes the silicide layer SC formed on the second side surface of the conductive film PL, the barrier metal film BM2 formed on the silicide layer SC, and the conductive film CF formed on the barrier metal film BM2.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a contact hole formed in an interlayer insulating film and a manufacturing method thereof. [Background technology]

[0002] Known power devices include power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), which use a vertical trench gate structure. Some semiconductor devices (semiconductor chips) equipped with power devices have a resistor region in addition to a cell region where a main device is formed.

[0003] For example, Patent Document 1 discloses a semiconductor device including an IGBT and a resistor element. The resistor element is formed on an insulating layer and covered with an interlayer insulating film. A contact hole is formed in the interlayer insulating film, and a plug is embedded in the contact hole. One end of the resistor element is electrically connected to the gate electrode of the IGBT via the plug and a gate wiring, and the other end of the resistor element is electrically connected to the gate wiring via the plug. A gate pad is formed on a part of the gate wiring to which the other end of the resistor element is connected. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-128002 Summary of the Invention [Problem to be solved by the invention]

[0005] A semiconductor device as an example studied by the present inventors will be described below with reference to FIG. 27. This semiconductor device includes an IGBT and a resistive element. The resistive element is formed on a conductive film PL. One end of the resistive element is electrically connected to the gate electrode of the IGBT via a plug PG, and the other end of the resistive element is electrically connected to the gate pad via the plug PG. In other words, the resistive element is connected between the gate electrode and gate pad of the IGBT. FIG. 27 shows, for example, the structure of a plug PG connected to one end of the resistive element.

[0006] As shown in FIG. 27, the plug PG includes barrier metal films BM1, BM2, and a conductive film CF, and the barrier metal film BM1 is in contact with the conductive film PL that constitutes the resistor element. The conductive film PL that constitutes the resistor element is made of a polycrystalline silicon film. The barrier metal film BM1 is made of a titanium film, the barrier metal film BM2 is made of a titanium nitride film, and the conductive film CF is made of a tungsten film. The contact between the polycrystalline silicon film and the barrier metal film BM1 forms a Schottky junction. Because interfacial defects exist in the polycrystalline silicon film, variations in the Schottky barrier occur, resulting in variations in the resistance value of the resistor element formed in the conductive film PL. For example, variations in the resistance value affect the turn-on time of the IGBT, thereby reducing the reliability of the semiconductor device.

[0007] The main object of the present invention is to suppress the above-mentioned variations in resistance value of the resistor element and improve the reliability of the semiconductor device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] A semiconductor device according to one embodiment includes a semiconductor substrate having an upper surface and a lower surface, an insulating film formed on the upper surface of the semiconductor substrate, a first conductive film formed on the insulating film, an interlayer insulating film formed on the upper surface of the semiconductor substrate to cover the first conductive film, a contact hole formed in the interlayer insulating film, the first conductive film, and the insulating film, and a plug embedded in the contact hole. In the contact hole, a first side surface of the interlayer insulating film is spaced apart from a second side surface of the first conductive film such that a portion of an upper surface of the first conductive film is exposed from the interlayer insulating film, and in the contact hole, a third side surface of the insulating film is spaced apart from the second side surface of the first conductive film such that a portion of a lower surface of the first conductive film is exposed from the insulating film. The plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

[0010] In one embodiment, a method for manufacturing a semiconductor device includes: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the (a) step, forming an insulating film on the upper surface of the semiconductor substrate; (c) after the (b) step, forming a first conductive film on the insulating film; (d) after the (c) step, forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first conductive film; (e) after the (d) step, performing an anisotropic dry etching process on the interlayer insulating film, the first conductive film, and the insulating film to form contact holes; (f) after the (e) step, performing an isotropic etching process on the interlayer insulating film and the insulating film; and (g) after the (f) step, embedding a plug in the contact hole. Then, in the step (f), the first side surface of the interlayer insulating film is separated from the second side surface of the first conductive film in the contact hole so that a portion of the upper surface of the first conductive film is exposed from the interlayer insulating film, and in the step (f), the third side surface of the insulating film is separated from the second side surface of the first conductive film in the contact hole so that a portion of the lower surface of the first conductive film is exposed from the insulating film. Furthermore, the step (g) includes the steps of (g1) after the step (f), performing a heat treatment on the semiconductor substrate in a hydrogen atmosphere, (g2) after the step (g1), forming a silicide layer on the second side surface of the first conductive film in the contact hole, (g3) after the step (g2), forming a barrier metal film on the silicide layer, and (g4) after the step (g3), forming a second conductive film on the barrier metal film.

[0011] A method for manufacturing a semiconductor device according to one embodiment is a method for manufacturing a semiconductor device having a first region and a second region different from the first region, and includes the steps of: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film in the first region from a position higher than the upper surface of the semiconductor substrate to extend into the semiconductor substrate; (c) after the step (b), forming a trench in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate; (d) after the step (c), forming a gate insulating film in the trench; (e) after the step (d), forming a gate electrode on the gate insulating film so as to fill the trench; and (f) after the step (e), forming a gate electrode in the first region. forming a second insulating film having a thickness thinner than the first insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first insulating film and also cover the gate electrode in the second region; (g) after the (f) steps, forming a first conductive film on the second insulating film in the first region and the second region; (h) after the (g) step, removing the first conductive film and the second insulating film so that the first conductive film and the second insulating film are selectively left on the first insulating film; (i) after the (h) step, removing the first conductive film and the second insulating film so that the bottom of the first conductive film is located above the bottom of the trench; (j) after the step (i), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate; (k) after the step (j), forming a second impurity region of a second conductivity type opposite to the first conductivity type in the first impurity region; (k) after the step (j), forming an interlayer insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first conductive film in the first region and to cover the gate electrode, the first impurity region and the second impurity region in the second region; (l) after the step (k), using a CMP method to planarize the upper surface of the interlayer insulating film. Therefore, a step of planarizing the interlayer insulating film in the first region and the second region, and a step of performing an anisotropic dry etching process on the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film after the steps (m) and (l) to form a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film in the first region so that its bottom is located in the first insulating film, and a step of forming a second contact hole in the interlayer insulating film, the second impurity region and the first impurity region in the second region so that its bottom is located in the first impurity region;(n) after the step (m), a step of performing an isotropic etching process on the interlayer insulating film, the second insulating film, and the first insulating film, and (o) after the step (n), a step of embedding a first plug in the first contact hole and embedding a second plug in the second contact hole, wherein by the step (n), in the first contact hole, a first side surface of the interlayer insulating film is separated from a second side surface of the first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film, by the step (n), in the first contact hole, third side surfaces of the first insulating film and the second insulating film are separated from the second side surfaces of the first conductive film so that a part of a lower surface of the first conductive film is exposed from the first insulating film and the second insulating film, and by the step (n), in the second contact hole, a fourth side surface of the interlayer insulating film is separated from a fifth side surface of the second impurity region so that a part of an upper surface of the second impurity region is exposed from the interlayer insulating film. The step (o) includes the steps of (o1) and (n), followed by performing a heat treatment on the semiconductor substrate in a hydrogen atmosphere; (o2) after the step (o1), forming a first silicide layer on the second side surface of the first conductive film in the first contact hole, and forming a second silicide layer on a part of the upper surface of the second impurity region and on a fifth side surface of the second impurity region in the second contact hole; (o3) after the step (o2), forming a first barrier metal film on the first silicide layer and the second silicide layer; and (o4) after the step (o3), forming a second conductive film on the first barrier metal film. [Effects of the Invention]

[0012] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view showing an entire semiconductor device according to an embodiment; [Figure 2] 1 is a plan view showing a semiconductor device according to an embodiment; [Figure 3] 1 is a plan view showing a semiconductor device according to an embodiment; [Figure 4]1 is an equivalent circuit diagram of a semiconductor device according to an embodiment; [Figure 5] 1 is a cross-sectional view showing a semiconductor device according to an embodiment; [Figure 6] 1 is an enlarged cross-sectional view of a portion of a semiconductor device according to an embodiment; [Figure 7] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process following FIG. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Figure 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process following FIG. 23. [Figure 25]FIG. 25 is a cross-sectional view showing a manufacturing process following FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view showing a manufacturing process following FIG. 25. [Figure 27] FIG. 1 is a cross-sectional view showing a semiconductor device in a study example. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0015] <Structure of semiconductor device> A semiconductor device 100 according to an embodiment will be described below with reference to Figures 1 to 6. Figure 1 is a plan view showing a semiconductor chip which is the semiconductor device 100.

[0016] 1, most of the semiconductor device 100 is covered with an emitter electrode EE, and a plurality of cells constituting the IGBT are formed below the emitter electrode EE. A gate wiring GW is formed around the emitter electrode EE. The center of the emitter electrode EE serves as an emitter pad (not shown), and the center of the gate wiring serves as a gate pad GP. External connection terminals such as wire bonding or clips (copper plates) are connected to the emitter pad and the gate pad GP, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0017] The semiconductor device 100 includes a region 1A and a region 2A, which are different regions from each other. Region 1A in FIG. 1 is a resistor region where a resistor element Rg is formed. The resistor element Rg is used as a gate resistor, etc. Region 2A in FIG. 1 is a cell region where multiple cells constituting an IGBT are formed.

[0018] Fig. 2 is a plan view of a main portion corresponding to region 1A. Fig. 3 is a plan view of a main portion corresponding to region 2A. Fig. 4 is an equivalent circuit diagram of semiconductor device 100. Fig. 5 is a cross-sectional view taken along line AA in Fig. 2 and a cross-sectional view taken along line BB in Fig. 3.

[0019] 4, the IGBT includes a collector electrode CE, an emitter electrode EE, and a gate electrode GE, and one end of the resistor element Rg is connected to the gate electrode GE via a gate wiring GW. The other end of the resistor element Rg is connected to a gate pad GP via the gate wiring GW. The collector electrode CE is electrically connected to a collector region PC of the IGBT, and the emitter electrode EE is electrically connected to an emitter region NE.

[0020] 2, the contact hole CH1 has a slit shape in which the opening width in a first direction is wider than the opening width in a second direction perpendicular to the first direction in a plan view. That is, the contact hole CH1 has a rectangular shape in a plan view.

[0021] However, the planar shape of the contact hole CH1 is not limited to a slit shape, and may be a dot shape in which the opening width in the first direction is the same as the opening width in the second direction. That is, a plurality of contact holes CH1 each having a rectangular shape in a planar view may be arranged in the first direction.

[0022] In many cases, the planar shape of the contact hole CH1 has rounded corners after photolithography resolution, so that the contact hole CH1 ultimately has a rectangular shape with rounded corners or a circular shape in plan view.

[0023] 3, the contact hole CH2 has a slit shape in plan view, with an opening width in the first direction narrower than an opening width in the second direction. That is, the contact hole CH2 has a rectangular shape in plan view. The contact hole CH2 is disposed between two trenches TR extending in the second direction and intersects with the emitter region NE extending in the first direction.

[0024] As shown in FIG. 5, semiconductor device 100 includes a semiconductor substrate SUB having a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be a stacked structure of an n-type silicon substrate and a semiconductor layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked structure will also be described as the semiconductor substrate SUB.

[0025] An n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB on the lower surface side thereof. The field stop region NS is provided to prevent a depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0026] A p-type collector region (impurity region) PC is formed on the lower surface side of the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0027] A collector electrode CE is formed below the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE is made of a metal film such as an AlSi film, a Ti film, a Ni film, or an Au film.

[0028] <Resistance element> The structure of the region 1A will be described below. In the semiconductor device 100, the conductive film PL formed in the region 1A is used as a resistor element Rg.

[0029] 5, a p-type well region PW is formed in the semiconductor substrate SUB on the upper surface side of the semiconductor substrate SUB. The well region PW is formed in the same process as the floating region PF of the region 2A, but is physically separated from the floating region PF.

[0030] An insulating layer IFL is formed from the upper surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB. In other words, the insulating layer IFL is formed in the semiconductor substrate SUB, and the lower surface of the insulating layer IFL is located lower than the upper surface of the semiconductor substrate SUB.

[0031] The insulating layer IFL includes insulating films IF1 and IF2. The insulating film IF1 is formed inside the semiconductor substrate SUB and is, for example, a silicon oxide film. The insulating film IF2 is formed on the insulating film IF1 and is, for example, a silicon oxide film. The insulating film IF2 has a thickness thinner than that of the insulating film IF1. The thickness of the insulating film IF1 is, for example, 500 nm to 600 nm. The thickness of the insulating film IF2 is, for example, 50 nm to 100 nm.

[0032] A conductive film PL is formed on the insulating layer IFL. The conductive film PL is, for example, a polycrystalline silicon film doped with p-type impurities. The thickness of the conductive film PL is, for example, 150 nm to 250 nm.

[0033] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the conductive film PL. The interlayer insulating film IL is, for example, a silicon oxide film. The interlayer insulating film IL has been subjected to a planarization process to flatten the upper surface of the interlayer insulating film IL. Therefore, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600 nm to 800 nm, while the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300 nm to 450 nm.

[0034] A contact hole CH1 is formed in the interlayer insulating film IL, the conductive film PL, and the insulating layer IFL. The bottom of the contact hole CH1 is located in the insulating layer IFL (in the insulating film IF1). The conductive film PL has a lower surface in contact with the insulating layer IFL (in other words, the insulating film IF2), an upper surface located opposite the lower surface and in contact with the interlayer insulating film IL, and a side surface connecting the upper surface and the lower surface within the contact hole CH1. A plug PG1 is buried in the contact hole CH1. Within the contact hole CH1, the side surface of the interlayer insulating film IL is spaced apart from the side surface of the conductive film PL so that a portion of the upper surface of the conductive film PL is exposed from the interlayer insulating film IL, and the side surface of the insulating layer IFL is spaced apart from the side surface of the conductive film PL so that a portion of the lower surface of the conductive film PL is exposed from the insulating layer IFL. For example, the distance between the side surface of the conductive film PL and the side surface of the interlayer insulating film IL is 40 to 50 nm, and the distance between the side surface of the conductive film PL and the side surface of the insulating layer IFL is 30 to 40 nm. In other words, within the contact hole CH1, the opening width of the contact hole CH1 formed in the interlayer insulating film IL and the opening width of the contact hole CH1 formed in the insulating layer IFL are wider than the opening width of the contact hole CH1 formed in the conductive film PL.

[0035] The plug PG1 includes a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2 formed on the barrier metal film BM1 and the silicide layer SC, and a conductive film CF formed on the barrier metal film BM2. The barrier metal film BM1 is, for example, a titanium film, the silicide layer SC is, for example, a titanium silicide (TiSi) film, and the barrier metal film BM2 is, for example, a titanium nitride film. The conductive film CF is, for example, a tungsten film. The silicide layer SC is a compound of the barrier metal film BM1 and a polycrystalline silicon film constituting the conductive film PL.

[0036] In contact hole CH1, silicide layer SC is formed on the side surface of conductive film PL, on a part of the upper surface of conductive film PL exposed from interlayer insulating film IL, and on a part of the lower surface of conductive film PL exposed from insulating layer IFL. In contact hole CH1, barrier metal films BM1 are formed on the side surfaces of interlayer insulating film IL and insulating layer IFL, respectively. And, as shown in FIG. 6, in the direction orthogonal to the upper surface of semiconductor substrate SUB, the width b of silicide layer SC formed on the side surface of conductive film PL is larger than the width a of conductive film PL covered by interlayer insulating film IL and insulating layer IFL. This is because the film thickness of silicide layer SC formed at the corner of conductive film PL is larger than the film thickness of silicide layer SC formed on the upper surface, lower surface or side surface of conductive film PL.

[0037] On interlayer insulating film IL, gate wiring GW is formed. Conductive film PL is electrically connected to gate wiring GW via plug PG1. By configuring the electrical path in the middle of gate wiring GW with conductive film PL, conductive film PL can be used as resistance element (gate resistance) Rg.

[0038] <Structure of IGBT cell> The structure of region 2A will be described below. Here, an IGBT to which a vertical trench gate structure is applied is exemplified.

[0039] As shown in FIG. 5, on the upper surface side of semiconductor substrate SUB, a trench TR is formed in semiconductor substrate SUB. The depth of trench TR is, for example, from 3 μm to 4 μm. A gate insulating film GI is formed in trench TR. Gate electrode GE is formed on gate insulating film GI so as to fill trench TR. Gate insulating film GI is, for example, a silicon oxide film, and gate electrode GE is, for example, a polycrystalline silicon film into which n-type impurities are introduced.

[0040] On the upper surface side of the semiconductor substrate SUB, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between a pair of gate electrodes GE. A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The bottom of the base region PB is located higher than the bottom of the trench TR, and the bottom of the emitter region NE is located higher than the bottom of the base region PB.

[0041] Furthermore, on the upper surface side of the semiconductor substrate SUB, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB except for the region in which the hole barrier region NHB is formed. A p-type base region PB is formed in the floating region PF. In order to enhance high-voltage resistance characteristics, the floating region PF is formed to a position deeper than the bottom of the trench TR and is formed so as to cover the bottom of the trench TR.

[0042] The interlayer insulating film IL is also formed on the upper surface of the semiconductor substrate SUB in region 2A so as to cover the gate electrode GE, the emitter region NE, and the base region PB. A contact hole CH2 is formed in the interlayer insulating film IL, the emitter region NE, and the base region PB in region 2A. The bottom of the contact hole CH2 is located in the base region PB. A plug PG2 is buried in the contact hole CH2. The plug PG2 has the same configuration as the plug PG1 and includes a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2, and a conductive film CF.

[0043] A p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB around the bottom of the contact hole CH2. The high-concentration diffusion region PR is provided to reduce the contact resistance with the plug PG2 and to prevent latch-up.

[0044] In region 2A, the interlayer insulating film IL is isotropically etched to increase the contact area between the plug PG2 embedded in the contact hole CH2 and the emitter region NE, so that the side surface of the interlayer insulating film IL is recessed. That is, in contact hole CH2, the side surface of the interlayer insulating film IL is spaced apart from the side surface of the emitter region NE so that part of the upper surface of the emitter region NE is exposed from the interlayer insulating film IL. In contact hole CH2, the silicide layer SC is formed on the upper surface of the emitter region NE exposed from the interlayer insulating film IL and on the side surface of the emitter region NE.

[0045] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, base region PB, and heavily doped diffusion region PR via plugs PG2, and supplies an emitter potential to these regions. Although not shown here, the gate wiring GW is electrically connected to the gate electrode GE via another plug, and supplies a gate potential to the gate electrode GE.

[0046] The emitter electrode EE and the gate wiring GW are each made of, for example, a TiW film and an aluminum film formed on the TiW film. The aluminum film is the main conductor film of the emitter electrode EE and the gate wiring GW and is much thicker than the TiW film.

[0047] <Major Features of Semiconductor Device of the Embodiment> The main features of the embodiment will be described below with reference to Figures 5 and 6. Figure 6 is an enlarged cross-sectional view of the periphery of the contact hole CH1.

[0048] 6, in the contact hole CH1, the plug PG1 includes a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2 formed on the barrier metal film BM1 and the silicide layer SC, and a conductive film CF formed on the barrier metal film BM2. In the contact hole CH1, a portion of the upper surface of the conductive film PL exposed from the interlayer insulating film IL, a portion of the lower surface of the conductive film PL exposed from the insulating layer IFL, and the side surfaces of the conductive film PL are covered with the silicide layer SC. In other words, the silicide layer SC is interposed between the polycrystalline silicon film PL and the barrier metal film BM2 that constitute the resistor element Rg. Therefore, the variation in the resistance value of the resistor element Rg due to the aforementioned interface defects can be suppressed, improving the reliability of the semiconductor device.

[0049] Here, the thickness (150 nm to 250 nm) of the conductive film PL is larger than the length (40 nm to 50 nm) of the upper surface of the conductive film PL exposed from the interlayer insulating film IL and the length (30 nm to 40 nm) of the lower surface of the conductive film PL exposed from the insulating layer IFL in the contact hole CH1. Therefore, forming the silicide layer SC on the side surface of the conductive film PL is effective in suppressing the variation in the resistance value of the resistor element Rg.

[0050] 6, the width b of the silicide layer SC formed on the side surface of the conductive film PL is larger than the width a of the conductive film PL covered with the interlayer insulating film IL and the insulating layer IFL. That is, the contact area between the silicide layer SC covering the conductive film PL and the barrier metal film BM2 can be increased compared to the contact area between the conductive film PL and the barrier metal film BM1 in the study example shown in FIG. 27, and the resistance of the resistor element Rg can be reduced.

[0051] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device 100 according to the embodiment will be described below with reference to FIGS.

[0052] First, as shown in FIG. 7, a semiconductor substrate SUB having an n-type drift region NV is prepared. The semiconductor substrate SUB has an upper surface and a lower surface. Next, a silicon oxide film 10 is formed on the upper surface of the semiconductor substrate SUB by, for example, thermal oxidation. Next, a silicon nitride film 11 is formed on the silicon oxide film 10 by, for example, CVD.

[0053] 8, the silicon nitride film 11 and the silicon oxide film 10 in the region 1A are selectively removed by photolithography and dry etching to form openings in the silicon nitride film 11 and the silicon oxide film 10. Next, a dry etching process is further performed to etch a portion of the semiconductor substrate SUB exposed in the opening, thereby forming a groove in the semiconductor substrate SUB.

[0054] 9, the semiconductor substrate SUB is subjected to a thermal oxidation treatment to form an insulating film IF1 from the upper surface of the semiconductor substrate SUB to the interior of the semiconductor substrate SUB. In this state, the insulating film IF1 is formed up to a position higher than the upper surface of the semiconductor substrate SUB. That is, the insulating film IF1 having a LOCOS structure is formed on the semiconductor substrate SUB in the region 1A. In this state, the thickness of the insulating film IF1 is, for example, 700 nm to 800 nm.

[0055] 10, the silicon nitride film 11 is removed by isotropic etching using a solution containing phosphoric acid. Next, a p-type well region PW is formed in the semiconductor substrate SUB in region 1A by photolithography and ion implantation, and a p-type floating region PF is formed in the semiconductor substrate SUB in region 2A. Next, an n-type hole barrier region NHB is formed in the semiconductor substrate SUB in region 2A by photolithography and ion implantation.

[0056] Next, as shown in FIG. 11, a trench TR is formed in the semiconductor substrate SUB in the region 2A by photolithography and dry etching.

[0057] 12, the silicon oxide film 10 is removed by isotropic etching using a solution containing hydrofluoric acid. At this time, the insulating film IF1 is also exposed to the isotropic etching, so that the upper surface of the insulating film IF1 recedes and the thickness of the insulating film IF1 becomes thinner.

[0058] 13, the semiconductor substrate SUB is subjected to a heat treatment at, for example, 1000 to 1200 degrees Celsius to diffuse the impurities contained in the hole barrier region NHB, the floating region PF, and the well region PW. This heat treatment causes the hole barrier region NHB to diffuse to near the bottom of the trench TR, and the floating region PF to diffuse to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

[0059] Although not shown in the drawings, this heat treatment is performed with a sacrificial silicon oxide film formed on the semiconductor substrate SUB, including the inside of the trench TR. After the heat treatment, the sacrificial silicon oxide film is removed by isotropic etching using a solution containing hydrofluoric acid. At this time, the insulating film IF1 is also exposed to the isotropic etching, so that the upper surface of the insulating film IF1 recedes and the thickness of the insulating film IF1 becomes thinner. In this state, the thickness of the insulating film IF1 is, for example, 500 nm to 600 nm.

[0060] 14, a gate insulating film GI is formed inside the trench TR and on the semiconductor substrate SUB. The gate insulating film GI is formed by thermal oxidation. The thickness of the gate insulating film GI is, for example, 100 nm.

[0061] Next, a gate electrode GE is formed so as to fill the trench TR. To form the gate electrode GE, first, a polycrystalline silicon film doped with n-type impurities is formed on the gate insulating film GI by, for example, a CVD method. Next, the polycrystalline silicon film formed outside the trench TR is removed by a dry etching process. The polycrystalline silicon film formed inside the trench TR is left as the gate electrode GE.

[0062] 15, an insulating film IF2 is formed on the insulating film IF1, the gate electrode GE, and the gate insulating film GI formed outside the trench TR, for example, by a CVD method. The thickness of the insulating film IF2 is, for example, 50 nm to 100 nm. Next, a conductive film PL is formed on the insulating film IF2, for example, by a CVD method. The thickness of the conductive film PL is, for example, 150 nm to 250 nm.

[0063] Next, p-type impurities are introduced into the conductive film PL by ion implantation. Next, a resist pattern RP1 is formed on the conductive film PL in the region 1A so as to selectively cover the conductive film PL located on the insulating film IF1.

[0064] Next, as shown in FIG. 16, the conductive film PL and the insulating film IF2 are patterned by performing a dry etching process using the resist pattern RP1 as a mask. This forms a resistive element Rg in the region 1A. The patterned insulating films IF2 and IF1 form an insulating layer IFL. This dry etching process also removes the gate insulating film GI formed outside the trench TR. Thereafter, the resist pattern RP1 is removed by ashing.

[0065] Next, as shown in FIG. 17, a p-type base region PB is formed in the semiconductor substrate SUB (floating region PF and hole barrier region NHB) on the upper surface side of the semiconductor substrate SUB by photolithography and ion implantation. The bottom of the base region PB is located higher than the bottom of the trench TR. Next, an n-type emitter region NE is formed in the base region PB by photolithography and ion implantation. Thereafter, a heat treatment is performed to activate the impurities contained in each impurity region.

[0066] Next, as shown in FIG. 18, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB in the regions 1A and 2A so as to cover the conductive film PL, the gate electrode GE, the base region PB, and the emitter region NE.

[0067] 19, in order to planarize the upper surface of the interlayer insulating film IL, a planarization process is performed on the interlayer insulating film IL in the region 1A and the region 2A by the CMP method. After the planarization process, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600 nm to 800 nm, and the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300 nm to 450 nm.

[0068] Next, as shown in FIG. 20, in region 1A, a contact hole CH1 is formed in the interlayer insulating film IL, the conductive film PL, the insulating film IF2, and the insulating film IF1 using photolithography and anisotropic dry etching. Simultaneously, in region 2A, a contact hole CH2 is formed in the interlayer insulating film IL, the emitter region NE, and the base region PB. Next, a p-type high-concentration diffusion region PR is formed in the base region PB at the bottom of the contact hole CH2 using ion implantation. The bottom of contact hole CH1 is located in the insulating film IF1, and the bottom of contact hole CH2 is located in the base region PB. The anisotropic dry etching process uses etching gases such as SF or CHF. However, a problem was observed in which F ions or C ions decomposed in the plasma atmosphere penetrated into the conductive film PL from the side. Furthermore, in region 2A, penetration of F ions or C ions into the emitter region NE was observed.

[0069] Next, as shown in FIG. 21 , an isotropic etching process is performed on the interlayer insulating film IL and the insulating layer IFL (insulating films IF2 and IF1) using a solution containing hydrofluoric acid. By this isotropic etching process, in the contact hole CH1, the side surface of the interlayer insulating film IL moves away from the side surface of the conductive film PL so that part of the upper surface of the conductive film PL is exposed from the interlayer insulating film IL. Also, in the contact hole CH1, the side surface of the insulating layer IFL (the side surface of the insulating film IF1 and the side surface of the insulating film IF2) moves away from the side surface of the conductive film PL so that part of the lower surface of the conductive film PL is exposed from the insulating layer IFL. Also, in the contact hole CH2, the side surface of the interlayer insulating film IL moves away from the side surface of the emitter region NE so that part of the upper surface of the emitter region NE is exposed from the interlayer insulating film IL.

[0070] Next, as shown in FIG. 22, the semiconductor substrate SUB is subjected to hydrogen annealing. The semiconductor substrate SUB is placed on a substrate provided in the chamber of a CVD apparatus. The substrate temperature is then set to 600 to 650 degrees Celsius, and the semiconductor substrate SUB is subjected to heat treatment for about 30 seconds while hydrogen gas is introduced into the chamber. This hydrogen annealing process removes F ions or C ions that have penetrated the conductive film PL and the emitter region NE from the conductive film PL and the emitter region NE. In FIG. 22, black circles represent F ions or C ions.

[0071] Next, as shown in FIG. 23, hydrogen plasma processing is performed on the semiconductor substrate SUB. With the semiconductor substrate SUB mounted on the substrate in the CVD apparatus, the substrate temperature is set to 600 to 650 degrees Celsius. Plasma is applied to the semiconductor substrate SUB while hydrogen gas is introduced into the chamber. This hydrogen plasma processing is performed for approximately 5 to 10 seconds. Then, within the contact hole CH1, hydrogen ions are attached to the side surface of the conductive film PL, a portion of the upper surface of the conductive film PL exposed from the interlayer insulating film IL, and a portion of the lower surface of the conductive film PL exposed from the insulating layer IFL. In other words, within the contact hole CH1, dangling bonds on the surface of the polycrystalline silicon film constituting the conductive film PL are terminated with hydrogen ions. In FIG. 23, open circles represent hydrogen ions. Furthermore, within the contact hole CH2, hydrogen ions are attached to a portion of the upper surface of the emitter region NE exposed from the interlayer insulating film IL and the side surface of the emitter region NE. In the contact hole CH1, the upper, side, and lower surfaces of the conductive film PL are covered with hydrogen ions, which prevents impurities from adhering to the upper, side, and lower surfaces of the conductive film PL in the barrier metal film BM1 formation process described later. For example, when a titanium (Ti) film is used as the barrier metal film BM1, the chlorine (Cl) ions contained in titanium tetrachloride (TiCl4), which is the reaction gas, correspond to the impurities. The hydrogen plasma treatment described above allows the formation of a high-quality silicide layer SC that is free of impurities.

[0072] Next, as shown in FIG. 24, a barrier metal film BM1 and a silicide layer SC are formed in the contact holes CH1 and CH2. The barrier metal film BM1 is also formed on the interlayer insulating film IL outside the contact holes CH1 and CH2. With the semiconductor substrate SUB mounted on the substrate of the CVD apparatus, the substrate temperature is set to 600 to 700 degrees Celsius, and a barrier metal film BM1 is deposited on the semiconductor substrate SUB using a plasma CVD method while introducing a reactive gas into the chamber. For example, the reactive gas is TiCl4 and H2, and the barrier metal film BM1 is a titanium (Ti) film. The thickness of the barrier metal film BM1 is, for example, 10 nm.

[0073] In the contact hole CH1, the barrier metal film BM1 is formed to cover a portion of the upper surface of the conductive film PL exposed from the interlayer insulating film IL, a portion of the lower surface of the conductive film PL exposed from the insulating layer IFL, the side surfaces of the conductive film PL, the side surfaces of the interlayer insulating film IL, and the side surfaces of the insulating layer IFL. Because the substrate temperature is set to 600 to 700 degrees Celsius, a silicide reaction progresses during the deposition of the barrier metal film BM1. A silicide layer SC is formed on the upper surface of the conductive film PL exposed from the interlayer insulating film IL, the lower surface of the conductive film PL exposed from the insulating layer IFL, and the side surfaces of the conductive film PL. The silicide layer SC is not formed on the side surfaces of the interlayer insulating film IL and the insulating layer IFL, but the barrier metal film BM1 is formed. In the contact hole CH2, the silicide layer SC is formed at least on the upper surface of the emitter region NE exposed from the interlayer insulating film IL and the side surfaces of the emitter region NE. The silicide layer SC is not formed on the side surface of the interlayer insulating film IL, but the barrier metal film BM1 is formed on the side surface of the interlayer insulating film IL. The silicide layer SC is, for example, a titanium silicide (TiSi) film, and its film thickness is set to 25 nm.

[0074] Although the silicide layer SC is formed during the deposition process of the barrier metal film BM1, the silicide layer SC may be formed by depositing the barrier metal layer BM1 to a desired thickness and then performing a heat treatment that promotes the silicide reaction. That is, the barrier metal film BM1 is formed by a CVD method at a relatively low substrate temperature (400 to 500 degrees Celsius), and then a heat treatment at 600 to 700 degrees Celsius is performed to form the silicide layer SC.

[0075] If F ions or C ions remain in the conductive film PL or the emitter region NE, it becomes difficult to form the silicide layer SC in the conductive film PL or the emitter region NE. However, by performing the hydrogen annealing treatment before forming the silicide layer SC, it becomes possible to form the silicide layer SC in the conductive film PL or the emitter region NE.

[0076] Next, as shown in FIG. 25, a barrier metal film BM2 is formed by a CVD method on the interlayer insulating film IL including inside the contact holes CH1 and CH2. The barrier metal film BM2 is, for example, a titanium nitride (TiN) film. Inside the contact hole CH1, the barrier metal film BM2 is in contact with the silicide layer SC formed on the upper surface, side surface, and lower surface of the conductive film PL. Furthermore, inside the contact hole CH1, the barrier metal film BM2 is in contact with the barrier metal film BM1 formed on the side surface of the interlayer insulating film IL and the side surface of the insulating layer IFL. Inside the contact hole CH2, the barrier metal film BM2 is in contact with the silicide layer SC formed on the upper surface of the emitter region NE exposed from the interlayer insulating film IL and on the side surface of the emitter region NE. Furthermore, the barrier metal film BM2 is in contact with the barrier metal film BM1 formed on the side surface of the interlayer insulating film IL.

[0077] Next, a conductive film CF is formed on the barrier metal film BM2 so as to fill the contact holes CH1 and CH2. The conductive film CF is, for example, a tungsten (W) film, and is formed using WF6 gas.

[0078] 26, the conductive film CF, barrier metal film BM2, and barrier metal film BM1 formed outside the contact holes CH1 and CH2 are removed by a polishing process using the CMP method or an anisotropic dry etching process. As a result, a plug PG1 including the conductive film CF, barrier metal film BM2, silicide layer SC, and barrier metal film BM1 is buried in the contact hole CH1. Then, a plug PG2 including the conductive film CF, barrier metal film BM2, silicide layer SC, and barrier metal film BM1 is buried in the contact hole CH2.

[0079] 5, a gate wiring GW is formed on the interlayer insulating film IL in region 1A, and an emitter electrode EE is formed on the interlayer insulating film IL in region 2A. First, a TiW film is formed on the interlayer insulating film IL by, for example, sputtering, and then an aluminum film is formed on the TiW film by, for example, sputtering. Next, the TiW film and the aluminum film are patterned by photolithography and dry etching to form the gate wiring GW and the emitter electrode EE.

[0080] Next, a field stop region NS, a collector region PC, and a collector electrode CE are formed on the underside of the semiconductor substrate SUB. First, a support tape is attached to the upper side of the semiconductor substrate SUB, and the underside of the semiconductor substrate SUB is ground to reduce the thickness of the semiconductor substrate SUB to, for example, 80 to 90 μm. The underside of the semiconductor substrate SUB is then etched using a solution containing hydrofluoric acid to remove the grinding-damaged layer. Ion implantation is then performed from the underside of the semiconductor substrate SUB to form an n-type field stop region NS and a p-type collector region PC. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film, such as an AlSi film, Ti film, Ni film, or Au film, is formed below the underside of the semiconductor substrate SUB by, for example, sputtering. This metal film becomes the collector electrode CE.

[0081] In this manner, the semiconductor device 100 according to the embodiment is manufactured.

[0082] Next, the features of the method for manufacturing a semiconductor device according to the embodiment will be described.

[0083] In the contact hole CH1, before forming a barrier metal film BM1 on a portion of the conductive film PL exposed from the interlayer insulating film IL and the insulating layer IFL, a hydrogen annealing process is performed on the portion of the conductive film PL exposed from the interlayer insulating film IL and the insulating layer IFL. This hydrogen annealing process removes F ions or C ions that have penetrated into the conductive film PL during the anisotropic dry etching process from within the conductive film PL, thereby forming a silicide layer SC on the surface of the conductive film PL. Electrically connecting the conductive film PL to the barrier metal film BM2 and the conductive film CF through the silicide layer SC suppresses variations in the resistance value of the resistor element Rg and improves the reliability of the semiconductor device. In addition, in the contact hole CH2, before forming a barrier metal film BM1 on the upper surface and side surface of the emitter region NE exposed from the interlayer insulating film IL, a hydrogen annealing process is performed on the upper surface and side surface of the emitter region NE exposed from the interlayer insulating film IL. This hydrogen annealing process can remove F ions or C ions that have penetrated into the emitter region NE in the anisotropic dry etching process from the emitter region NE, thereby forming a silicide layer SC on the upper surface and side surfaces of the emitter region NE.

[0084] By performing the hydrogen annealing treatment, a silicide layer SC can be formed in the conductive film PL and the emitter region NE. Therefore, in the manufacturing method of the semiconductor device according to the embodiment, the hydrogen plasma treatment described with reference to FIG. 23 may be omitted. However, by performing the hydrogen plasma treatment between the hydrogen annealing treatment and the formation of the barrier metal film BM1, the quality of the silicide layer SC can be improved, the variation in the resistance value of the resistor element Rg can be suppressed, and the reliability of the semiconductor device can be improved.

[0085] As a modification, before the hydrogen annealing, a sputter etching process may be performed on a portion of the conductive film PL exposed from the interlayer insulating film IL and the insulating layer IFL. In the sputter etching process, the semiconductor substrate SUB is exposed to a plasma atmosphere containing an inert gas (Ar or N2). Since the upper surface of the conductive film PL exposed from the interlayer insulating film IL is etched away, the F ions or C ions contained in the conductive film PL can be reduced.

[0086] Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0087] For example, a diode element may be formed in the conductive film PL instead of the resistor element Rg.

[0088] Furthermore, although an IGBT is exemplified as a device formed in the region 2A, the technology disclosed in the above embodiment is not limited to an IGBT, and can also be applied to a power MOSFET having a vertical trench gate structure. [Explanation of symbols]

[0089] 100 Semiconductor device 10 Silicon oxide film 11 Silicon nitride film 1A area (resistance element area) 2A area (cell area) BM1 Barrier metal film BM2 barrier metal film CE collector electrode CF conductive film CH1, CH2 contact holes EE emitter electrode GE gate electrode GI gate insulating film GP Gate Pad GW Gate wiring IF1, IF2 insulating film IFL insulating layer IL Interlayer insulating film NE emitter region NHB hole barrier region NS field stop region NV drift region PB Base Area PC Collector Area PF floating area PG, PG1, PG2 plugs PL conductive film PR high concentration diffusion region PW well region Rg Resistance element RP1 resist pattern SC silicide layer SUB Semiconductor substrate TR Trench

Claims

1. a semiconductor substrate having an upper surface and a lower surface; an insulating film formed on the upper surface of the semiconductor substrate; a first conductive film formed on the insulating film; an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the first conductive film; a first contact hole formed in the interlayer insulating film, the first conductive film, and the insulating film; a first plug embedded in the first contact hole; Equipped with In the first contact hole, a first side surface of the interlayer insulating film is spaced apart from a second side surface of the first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film; In the first contact hole, a third side surface of the insulating film is spaced apart from the second side surface of the first conductive film so that a part of a lower surface of the first conductive film is exposed from the insulating film; the first plug includes a first silicide layer formed on the second side surface of the first conductive film, a first barrier metal film formed on the first silicide layer, and a second conductive film formed on the first barrier metal film.

2. 2. The semiconductor device according to claim 1, the first silicide layer is formed in the first contact hole so as to cover a portion of an upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film and a portion of a lower surface of the first conductive film exposed from the third side surface of the insulating film.

3. 3. The semiconductor device according to claim 2, a first width of the first silicide layer formed on the second side surface of the first conductive film in a direction perpendicular to an upper surface of the semiconductor substrate, the first width being larger than a second width of the first conductive film in a region sandwiched between the interlayer insulating film and the insulating film.

4. 3. The semiconductor device according to claim 2, the first plug further includes a second barrier metal film formed in the first contact hole on the first side surface of the interlayer insulating film and on the third side surface of the insulating film.

5. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the first conductive film is a polycrystalline silicon film.

6. 6. The semiconductor device according to claim 5, The semiconductor device, wherein the second barrier metal film is a titanium film, a nickel film, a tantalum film, or a tungsten film.

7. 7. The semiconductor device according to claim 6, the first silicide layer is an alloy film of the polycrystalline silicon film and the second barrier metal film.

8. 8. The semiconductor device according to claim 7, the first barrier metal film is a titanium nitride film, The semiconductor device, wherein the second conductive film is a tungsten film.

9. 2. The semiconductor device according to claim 1, a first region in which the first conductive film is formed; a second region different from the first region; a trench formed in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate; a gate insulating film formed in the trench; a gate electrode formed on the gate insulating film so as to fill the trench; a first impurity region of a first conductivity type formed in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; a second impurity region formed in the first impurity region and having a second conductivity type opposite to the first conductivity type; Further provided with the interlayer insulating film is also formed on the upper surface of the semiconductor substrate in the second region so as to cover the gate electrode, the first impurity region, and the second impurity region; a second contact hole is formed in the interlayer insulating film, the second impurity region, and the first impurity region of the second region so that the bottom of the second contact hole is located in the first impurity region; In the second contact hole, a fourth side surface of the interlayer insulating film is spaced apart from a fifth side surface of the second impurity region so that a part of an upper surface of the second impurity region is exposed from the interlayer insulating film; a second plug is buried in the second contact hole; the second plug includes a second silicide layer formed on a portion of an upper surface of the second impurity region and on the fifth side surface of the second impurity region, a third barrier metal film formed on the second silicide layer, and a third conductive film formed on the third barrier metal film.

10. 10. The semiconductor device according to claim 9, a gate wiring formed on the interlayer insulating film in the first region and electrically connected to the gate electrode; an emitter electrode formed on the interlayer insulating film in the second region; Further provided with the first impurity region and the second impurity region are electrically connected to the emitter electrode via the second plug; the first conductive film is electrically connected to the gate wiring via the first plug.

11. (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) forming an insulating film on the semiconductor substrate after the step (a); (c) after the step (b), forming a first conductive film on the insulating film; (d) after the step (c), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first conductive film; (e) after the step (d), performing an anisotropic dry etching process on the interlayer insulating film, the first conductive film, and the insulating film to form a first contact hole; (f) after the step (e), performing an isotropic etching process on the interlayer insulating film and the insulating film; and (g) after the step (f), burying a first plug in the first contact hole; Equipped with by the step (f), in the first contact hole, the first side surface of the interlayer insulating film is separated from the second side surface of the first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film; by the step (f), in the first contact hole, the third side surface of the insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film; The step (g) (g1) after the step (f), a step of subjecting the semiconductor substrate to a heat treatment in a hydrogen atmosphere; (g2) after the step (g1), forming a first silicide layer on the second side surface of the first conductive film in the first contact hole; (g3) after the step (g2), forming a first barrier metal film on the first silicide layer; and (g4) after the step (g3), forming a second conductive film on the first barrier metal film; A method for manufacturing a semiconductor device, comprising:

12. 12. The method for manufacturing a semiconductor device according to claim 11, a first silicide layer formed on the first contact hole, the first silicide layer being formed on the first conductive film and the second conductive film being formed on the first side surface of the insulating film; a second silicide layer formed on the first conductive film and the second conductive film being formed on the second side surface of the insulating film;

13. 13. The method for manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the (g2) step uses a plasma CVD method in which a substrate temperature is set to 600 to 700 degrees Celsius to deposit a second barrier metal film in the first contact hole to form the first silicide layer.

14. 13. The method for manufacturing a semiconductor device according to claim 12, Between the step (g1) and the step (g2), (g5) attaching hydrogen ions to a part of the upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film, the second side surface of the first conductive film, and a part of the lower surface of the first conductive film exposed from the third side surface of the insulating film, in the first contact hole; A method for manufacturing a semiconductor device, comprising:

15. 13. The method for manufacturing a semiconductor device according to claim 12, Between the step (f) and the step (g1), (g6) performing a sputter etching process using an inert gas on a part of the upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film, the second side surface of the first conductive film, and a part of the lower surface of the first conductive film exposed from the third side surface of the insulating film in the first contact hole; A method for manufacturing a semiconductor device, comprising:

16. 1. A method for manufacturing a semiconductor device having a first region and a second region different from the first region, comprising: (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film in the first region from a position higher than the upper surface of the semiconductor substrate to the inside of the semiconductor substrate; (c) after the step (b), forming a trench in the second region of the semiconductor substrate on the upper surface side of the semiconductor substrate; (d) after the step (c), forming a gate insulating film in the trench; (e) after the step (d), forming a gate electrode on the gate insulating film so as to fill the trench; (f) after the step (e), forming a second insulating film having a thickness thinner than that of the first insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first insulating film in the first region and to cover the gate electrode in the second region; (g) after the step (f), forming a first conductive film on the second insulating film in the first region and the second region; (h) after the step (g), removing the first conductive film and the second insulating film so that the first conductive film and the second insulating film are selectively left on the first insulating film; (i) after the step (h), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; (j) after the step (i), forming a second impurity region of a second conductivity type opposite to the first conductivity type in the first impurity region; (k) after the step (j), forming an interlayer insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first conductive film in the first region and to cover the gate electrode, the first impurity region, and the second impurity region in the second region; (l) after the step (k), performing a planarization process on the interlayer insulating film in the first region and the second region by a CMP method in order to planarize an upper surface of the interlayer insulating film; (m) after the step (l), performing an anisotropic dry etching process on the interlayer insulating film, the first conductive film, the second insulating film, and the first insulating film to form a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film, and the first insulating film in the first region so that the bottom of the first contact hole is located in the first insulating film, and forming a second contact hole in the interlayer insulating film, the second impurity region, and the first impurity region in the second region so that the bottom of the second contact hole is located in the first impurity region; (n) after the step (m), performing an isotropic etching process on the interlayer insulating film, the second insulating film, and the first insulating film; and (o) after the step (n), a step of burying a first plug in the first contact hole and a second plug in the second contact hole; Equipped with In the step (n), in the first contact hole, the first side surface of the interlayer insulating film is separated from the second side surface of the first conductive film so that a part of the upper surface of the first conductive film is exposed from the interlayer insulating film; by the step (n), in the first contact hole, third side surfaces of the first insulating film and the second insulating film are separated from the second side surface of the first conductive film so that a part of a lower surface of the first conductive film is exposed from the first insulating film and the second insulating film; by the step (n), in the second contact hole, a fourth side surface of the interlayer insulating film is separated from a fifth side surface of the second impurity region so that a part of an upper surface of the second impurity region is exposed from the interlayer insulating film; The step (o) (o1) after the step (n), a step of subjecting the semiconductor substrate to a heat treatment in a hydrogen atmosphere; (o2) after the step (o1), forming a first silicide layer on the second side surface of the first conductive film in the first contact hole, and forming a second silicide layer on a part of the upper surface of the second impurity region and the fifth side surface of the second impurity region in the second contact hole; (o3) after the step (o2), forming a first barrier metal film on the first silicide layer and the second silicide layer; and (o4) after the step (o3), forming a second conductive film on the first barrier metal film; A method for manufacturing a semiconductor device, comprising:

17. 17. The method for manufacturing a semiconductor device according to claim 16, a second insulating film formed on the first insulating film and a second insulating film formed on the second insulating film, the second insulating film being formed on the first insulating film and the second insulating film being formed on the second insulating film; a second insulating film formed on the first insulating film and the second insulating film being formed on the first insulating film;

18. 18. The method for manufacturing a semiconductor device according to claim 17, The (o2) step is a method for manufacturing a semiconductor device, in which a second barrier metal film is deposited in the first contact hole and the second contact hole using a plasma CVD method with a substrate temperature set to 600 to 700 degrees Celsius, thereby forming the first silicide layer and the second silicide layer.

19. 18. The method for manufacturing a semiconductor device according to claim 17, Between the step (o1) and the step (o2), (o5) attaching hydrogen ions to a part of the upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film, the second side surface of the first conductive film, and a part of the lower surface of the first conductive film exposed from the third side surface of the second insulating film, in the first contact hole, and to a part of the upper surface of the second impurity region and the fifth side surface of the second impurity region in the second contact hole; A method for manufacturing a semiconductor device, comprising:

20. 20. The method of manufacturing a semiconductor device according to claim 19, Between the step (n) and the step (o1), (o6) performing a sputter etching process using an inert gas on a part of the upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film, the second side surface of the first conductive film, and a part of the lower surface of the first conductive film exposed from the third side surface of the second insulating film in the first contact hole, and on a part of the upper surface of the second impurity region and the fifth side surface of the second impurity region in the second contact hole; A method for manufacturing a semiconductor device, comprising:

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