Semiconductor device and method of manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: An interlayer insulating film having an upper portion and a lower portion is formed on the first main surface of the semiconductor substrate. Further, a contact hole penetrating the interlayer insulating film is formed, and a contact member is formed in the contact hole. In a cross-sectional view, a width of the contact hole in the first direction is wider at an upper end of the contact hole than at a lower end of the contact hole, and is wider at a depth corresponding to an upper portion of the interlayer insulating film than at a depth corresponding to a lower portion of the interlayer insulating film.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a contact member formed in a contact hole and a manufacturing method thereof. [Background technology]

[0002] Trench gate IGBTs (Insulated Gate Bipolar Transistors) are widely used as IGBTs (Insulated Gate Bipolar Transistors) with low collector-emitter saturation voltage VCE(sat).To further enhance conductivity modulation, IE type trench gate IGBTs that utilize the IE (Injection Enhancement) effect have been developed.

[0003] Some IE-type trench-gate IGBTs have active cells connected to the emitter electrode and inactive cells with P-type floating regions arranged alternately in the cell region. This structure facilitates the accumulation of holes on the device's main surface (emitter side) of the semiconductor substrate. In this type of IE-type trench-gate IGBT, holes injected from the collector side are prevented from escaping to the emitter side by the inactive cell region, increasing the hole concentration between the active cell region and the collector side. This increased hole concentration promotes electron injection from the emitter (source) side, thereby increasing the electron concentration. This increased carrier concentration (IE effect) causes conductivity modulation, enabling a lower VCE(sat).

[0004] Furthermore, among IE-type trench gate IGBTs, there is the GE-S-type IGBT, which is composed of two trenches with different potentials: a trench (G) connected to the gate potential and a trench (E) connected to the emitter potential (for example, JP 2019-29434 A). In this GE-S-type IGBT, the P-type floating region and the P-type body region formed in the active cell region and supplied with potential cannot be physically separated using a trench, and instead electrical separation is achieved using a high-concentration N-type layer at the cell edge. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-29434 Summary of the Invention [Problem to be solved by the invention]

[0006] In the IGBT of Patent Document 1, when a conventional interlayer film configuration (a single layer of PSG (Phospho Silicate Glass)) is used as the interlayer insulating film, there is a problem in that the waveform of the voltage-current characteristics related to the gate threshold voltage Vth exhibits a kink waveform. The PSG film is an insulating film containing phosphorus, and it is thought that the phosphorus penetrates into the silicon substrate during heat treatment after PSG formation, resulting in the kink waveform due to the influence of the layout unique to GE-S IGBTs. Furthermore, when forming contacts with a high aspect ratio as contacts that penetrate the interlayer insulating film, the embeddability of contact materials such as tungsten may be deteriorated.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] In one embodiment, a semiconductor device includes an interlayer insulating film formed above a first main surface of a semiconductor substrate, a contact hole penetrating the interlayer insulating film, and a contact member formed in the contact hole. In a cross-sectional view, the width of the contact hole in a first direction is wider at an upper end than at a lower end of the contact hole, and wider at a depth corresponding to an upper portion of the interlayer insulating film than at a depth corresponding to a lower portion of the interlayer insulating film.

[0010] A method for manufacturing a semiconductor device according to one embodiment includes forming an interlayer insulating film having an upper portion and a lower portion above a first main surface of a semiconductor substrate, and forming a contact hole penetrating the interlayer insulating film so that, in a cross-sectional view, the contact member contacts a trench emitter electrode and the interlayer insulating film on one side in a first direction and contacts a body region, an emitter region, and the interlayer insulating film on the other side in the first direction, and forming the contact member in the contact hole. The step of forming the contact hole and the contact member includes forming the contact hole by etching processes including a first etching process, a second etching process, and a third etching process, so that, in a cross-sectional view, the width of the contact hole in the first direction is wider at an upper end than at a lower end of the contact hole and is wider at a depth corresponding to an upper portion of the interlayer insulating film than at a depth corresponding to a lower portion of the interlayer insulating film. [Effects of the Invention]

[0011] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing the entire semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 3] 1 is a cross-sectional view (unit cell region) showing the semiconductor device in the first embodiment. [Figure 4] FIG. 2 is a cross-sectional view showing the shape of a contact hole in the first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] 6 is a cross-sectional view showing a manufacturing step subsequent to the manufacturing step shown in FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing step subsequent to the manufacturing step shown in FIG. [Figure 8] 8 is a cross-sectional view showing a manufacturing step subsequent to the manufacturing step shown in FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing step subsequent to the manufacturing step shown in FIG. 8. [Figure 10] 5A to 5C are cross-sectional views showing a step of forming a contact hole in the first embodiment. [Figure 11] 11 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. [Figure 12] 12 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. [Figure 13] 13 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 12. [Figure 14] 14 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 13. [Figure 15] FIG. 10 is a cross-sectional view showing the shape of a contact hole in the second embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a step of forming a contact hole in the second embodiment. [Figure 17] 17 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 16. [Figure 18] 18 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 17. [Figure 19] 19 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 18. [Figure 20] 20 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 19. [Figure 21] FIG. 11 is a cross-sectional view showing the shape of a contact hole in the third embodiment. [Figure 22]11A to 11C are cross-sectional views showing a step of forming a contact hole in the third embodiment. [Figure 23] 23 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 22. [Figure 24] 24 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 23. [Figure 25] 25 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 24. [Figure 26] 26 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 25. FIG. [Figure 27] FIG. 10 is a cross-sectional view showing the shape of a contact hole in the fourth embodiment. [Figure 28] FIG. 10 is a cross-sectional view showing a step of forming a contact hole in the fourth embodiment. [Figure 29] 29 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 28. [Figure 30] 30 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 29. [Figure 31] 31 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 30. [Figure 32] 32 is a cross-sectional view showing a forming step subsequent to the forming step shown in FIG. 31. DETAILED DESCRIPTION OF THE INVENTION

[0013] Each embodiment will be described below with reference to the drawings. In the following description, identical components are designated by the same reference numerals, and repeated description may be omitted. To clarify the description, the drawings may show the width, thickness, shape, etc. of each part more schematically than in the actual embodiment. Furthermore, the dimensional relationships and ratios of elements between multiple drawings do not necessarily match. When referring to an impurity region as "N+ type," the "+" here means a higher impurity concentration than an "N-type" region. When referring to an impurity region as "P+ type," the "+" here means a higher impurity concentration than a "P-type" region. When referring to an impurity region as "N- type," the "-" here means a lower impurity concentration than an "N-type" region. When referring to a impurity region as "P- type," the "-" here means a lower impurity concentration than a "P-type" region.

[0014] (Embodiment 1) The configuration of a semiconductor device (semiconductor chip) according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a top view of the semiconductor device according to the embodiment. For ease of understanding, Fig. 1 shows a see-through state with insulating film 28 (see Fig. 3) removed, and the peripheries of cell formation region 3, emitter pad 9, and gate pad 7 are indicated by two-dot chain lines. The semiconductor device shown in Fig. 1 is a GE-S type IGBT.

[0015] The semiconductor device 2 according to the embodiment includes a semiconductor substrate 1s. The semiconductor substrate 1s has a front surface as one main surface and a back surface opposite the front surface as the other main surface. The semiconductor substrate 1s also has a cell formation region 3 as a portion of the front surface, and a gate wiring lead-out region 4 as the other portion of the front surface. The gate wiring lead-out region 4 is provided, for example, on the outer periphery of the semiconductor substrate 1s relative to the cell formation region 3.

[0016] An emitter electrode 8 is provided in the cell formation region 3. The center of the emitter electrode 8 serves as an emitter pad 9 for connecting a bonding wire or the like. The emitter pad 9 is made of the emitter electrode 8 exposed from an opening 28e formed in an insulating film 28 (see FIG. 3) formed to cover the emitter electrode 8. The emitter electrode 8 is made of a metal film containing, for example, aluminum as a main component.

[0017] A gate wiring 5 and a gate electrode 6 are provided in the gate wiring extension region 4. The gate wiring 5 is provided, for example, on the outer periphery of the semiconductor substrate 1s relative to the emitter electrode 8. The gate wiring 5 is connected to the gate electrode 6. The center of the gate electrode 6 serves as a gate pad 7 for connecting a bonding wire or the like. The gate pad 7 is made of a portion of the gate electrode 6 exposed from an opening 28g formed in an insulating film 28 (see FIG. 3) formed so as to cover the gate electrode 6. The gate wiring 5 and the gate electrode 6 are made of a metal film containing, for example, aluminum as a main component.

[0018] The configuration of the cell formation region of the semiconductor device 2 will be described with reference to Figures 2 and 3. Figure 2 is a cross-sectional view of the cell formation region. Figure 3 is a cross-sectional view (unit cell region) of the cell formation region shown in Figure 2. Figure 4 is a cross-sectional view showing the shape of a contact hole in embodiment 1. For ease of understanding, Figure 2 shows a see-through state with the insulating film 28 and emitter electrode 8 shown in Figure 3 removed.

[0019] As shown in FIG. 2, two directions that intersect, preferably orthogonal to, each other within the surface of the semiconductor substrate 1s are defined as the X and Y directions, and a direction perpendicular to the surface of the semiconductor substrate 1s, i.e., the up-down direction, is defined as the Z direction. Here, as shown in FIG. 2, the cell formation region 3 is provided with a plurality of active cell regions 40a and a plurality of inactive cell regions 40i. In plan view, the active cell regions 40a each extend in the Y direction and are periodically arranged in the X direction. In other words, the active cell regions 40a are formed in a vertical stripe pattern. In plan view, the inactive cell regions 40i each extend in the Y direction and are periodically arranged in the X direction. Furthermore, the active cell regions 40a and the inactive cell regions 40i are alternately arranged in the X direction. A unit cell region 40 is made up of one active cell region 40a, half of an inactive cell region 40i adjacent to one side of the active cell region 40a, and half of an inactive cell region 40i adjacent to the other side of the active cell region 40a.

[0020] In this specification, "in a plan view" means when viewed from a direction perpendicular to the surface of the semiconductor substrate 1s.

[0021] The active cell region 40a is provided with the trench gate electrode 14 and trench emitter electrode 14e shown in FIG. 3. The trench gate electrode 14 and the trench emitter electrode 14e extend in the Y direction in a plan view. The trench gate electrode 14 and the trench emitter electrode 14e are provided on both sides in the X direction, sandwiching the P-type body region 15 and the N-type hole barrier region 24. The trench gate electrode 14 is electrically connected to the gate electrode 6, and the trench emitter electrode 14e is electrically connected to the emitter electrode 8. The N-type hole barrier region 24 is provided deeper than the P-type body region 15.

[0022] In the active cell region 40a (see FIG. 2), a plurality of N+ type emitter regions 12 are provided in a portion of the P-type body region 15 on the surface side of the semiconductor substrate 1s. The P-type body region 15 is a semiconductor region having a P-type conductivity type, and the N+ type emitter region 12 is a semiconductor region having an N-type conductivity type different from the P-type conductivity type. In the active cell region 40a, the P-type body region 15 is continuously formed along the Y direction in a plan view. In the active cell region 40a, the plurality of N+ type emitter regions 12 are arranged at regular intervals along the Y direction. Thereby, the emitter width (S) can be reduced.

[0023] In this specification, when the conductivity type of a semiconductor is P-type, it means that only holes are charge carriers, or both electrons and holes may be charge carriers, but the concentration of holes is higher than the concentration of electrons and holes are the main charge carriers. Also, in this specification, when the conductivity type of a semiconductor is N-type, it means that only electrons are charge carriers, or both electrons and holes may be charge carriers, but the concentration of electrons is higher than the concentration of holes and electrons are the main charge carriers.

[0024] In the inactive cell region 40i (see FIG. 2), a P-type body region 15 is provided between adjacent trench gate electrodes 14 and trench emitter electrodes 14e. Also, a P-type floating region 16 is provided deeper than the P-type body region 15.

[0025] Also, in the example shown in FIG. 2, the width (Wa) of the active cell region 40a in the X direction is made narrower than the width (Wi) of the inactive cell region 40i in the X direction (Wa < Wi). In such a case, the IE effect of the IGBT can be enhanced.

[0026] In the gate wiring lead-out region 4, there is a portion where, for example, a P-type floating region 16 is provided so as to surround the cell formation region 3. In addition, this P-type floating region 16 is electrically connected to the emitter electrode 8 via a P+ type body contact region 25 in a portion exposed at the bottom surface of the contact hole 11.

[0027] 1, a gate wiring 5 is arranged, and a trench gate electrode 14 (see FIG. 3) extends from within the cell formation region 3 toward this gate wiring 5. In the gate wiring lead-out region 4, ends of two adjacent trench gate electrodes 14 are connected to each other and electrically connected to the gate wiring 5.

[0028] The trench gate electrode 14 and the trench emitter electrode 14e are arranged on both sides of an inactive cell region 40i (see FIG. 2) located between two adjacent active cell regions 40a in plan view.

[0029] In the active cell region 40a (see FIG. 2), a P+ type semiconductor region consisting of the P+ type body contact region 25 and the P+ type latch-up prevention region 23 shown in FIG. 3 is formed continuously along the Y direction. In the active cell region 40a, a contact hole 11 serving as an opening is formed continuously along the Y direction in the P type body region 15 shown in FIG. 3. The contact hole 11 reaches the P+ type body contact region 25 arranged in the active cell region 40a.

[0030] Furthermore, the trench emitter electrode 14e is electrically connected to the emitter electrode 8 in the inactive cell region 40i (see FIG. 2) in the cell formation region 3 (see FIG. 2).

[0031] 3, a P+ type collector region 18 is provided in the semiconductor region on the back surface of the semiconductor device 2, and a collector electrode 17 is provided on the front surface of the P+ type collector region 18. The collector electrode 17 is made of a metal film containing, for example, aluminum as a main component. An N- type field stop region 19 is provided between the N- type drift region 20 and the P+ type collector region 18, which constitute the main portion of the semiconductor substrate 1s.

[0032] In the active cell region 40a, an N-type hole barrier region 24, a P-type body region 15, and an N-type emitter region 12 are provided on the N-type drift region 20, in this order from bottom to top. The N-type emitter region 12 is provided only on the trench gate electrode 14 side. An interlayer insulating film (upper portion 26a and lower portion 26b) is formed on the trench gate electrode 14, the trench emitter electrode 14e, the P-type body region 15, and the N-type emitter region 12. The upper portion 26a of the interlayer insulating film is a PSG (phospho-silicate glass) film, and the lower portion 26b of the interlayer insulating film is an NSG (non-doped silicate glass) film. The PSG film is an insulating film containing phosphorus, and providing an NSG film below the PSG film in this manner prevents phosphorus from leaking into the semiconductor substrate 1s. The interlayer insulating film has a contact hole 11 formed therein, which extends to the trench emitter electrode 14e and the semiconductor substrate 1s. A contact member 11a is buried in the contact hole 11. The contact member 11a contacts the trench emitter electrode 14e and the interlayer insulating film (upper portion 26a, lower portion 26b) on the negative X-direction side, and contacts the P-type body region 15, the N+-type emitter region 12, a P+-type body contact region 25 (described later), and the interlayer insulating film (upper portion 26a, lower portion 26b) on the positive X-direction side. The contact member 11a includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film. In the semiconductor region at the bottom of the contact hole 11, a P+-type body contact region 25 and a P+-type latch-up prevention region 23 are provided from above. Through the contact holes 11 and the like, the P-type body region 15 and the N+-type emitter region 12 are connected to the emitter electrode 8 provided on the interlayer insulating film .

[0033] Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the path from the N- type drift region 20 to the N+ type emitter region 12. The impurity concentration of the N- type hole barrier region 24 is lower than that of the N+ type emitter region 12 and higher than that of the N- type drift region 20. The presence of this N-type hole barrier region 24 effectively prevents holes accumulated in the inactive cell region 40i from entering the emitter path of the active cell region 40a (the path from the N- type drift region 20 to the P+ type body contact region 25).

[0034] In contrast, in the N-type drift region 20 in the inactive cell region 40i, a P-type floating region 16 and a P-type body region 15 are provided in this order from the bottom up. The depth of the P-type floating region 16 is deeper than the depth of the trench 21. The P-type floating region 16 is distributed so as to cover the lower end of the trench 21.

[0035] FIG. 4 is a cross-sectional view showing the shape of contact hole 11 in the first embodiment (the gate insulating film 22 and the ion implantation through insulating film 22a shown in FIG. 3 are omitted; the same applies to FIGS. 15, 21, and 27 described later). In the cross-sectional view, the width of contact hole 11 in the X direction is wider at the upper end than at the lower end of contact hole 11, and wider at a depth corresponding to upper portion 26a of interlayer insulating film than at a depth corresponding to lower portion 26b of the interlayer insulating film. Furthermore, at a depth corresponding to upper portion 26a of the interlayer insulating film, the inclination of contact hole 11 is vertical or nearly vertical (inclination angle Φ1 is 85 to 90 degrees), whereas at a depth corresponding to lower portion 26b, the inclination of contact hole 11 is significantly smaller than vertical (inclination angle Φ2 is significantly smaller than 90 degrees). By adopting such an inclination angle for lower portion 26b of the interlayer insulating film, the embeddability of tungsten in contact member 11a can be improved. As will be explained in the manufacturing method described later, the upper portion of the contact hole 11 (the portion at a depth corresponding to the upper portion 26a of the interlayer insulating film) can be formed by dry etching so as to have a vertical or nearly vertical inclination angle Φ1, thereby suppressing the enlargement of the contact hole diameter. Furthermore, by forming the interlayer insulating film into a two-layer structure of PSG / NSG, it is possible to prevent phosphorus from leaking from the PSG film (upper portion 26a) to the Si substrate side.

[0036] (Method of Manufacturing the Semiconductor Device in the First Embodiment) A method for manufacturing the semiconductor device 2 in the first embodiment will be described with reference to Fig. 5 to Fig. 9. Fig. 5 to Fig. 9 are cross-sectional views showing the manufacturing process of the semiconductor device shown in Fig. 1. Fig. 5 to Fig. 9 are cross-sectional views of the same cross section as the cross-sectional view of Fig. 3.

[0037] First, a semiconductor wafer 1 is prepared, which is a silicon single crystal semiconductor substrate 1s doped with an N-type impurity such as phosphorus, as shown in Fig. 5. The semiconductor wafer 1 has a front surface 1a as a first main surface and a back surface 1b as a second main surface opposite to the front surface 1a.

[0038] The impurity concentration of the N-type impurity in the semiconductor wafer 1 is set to, for example, 2×10 14 cm-3 The thickness of the semiconductor wafer 1 can be set to, for example, about 450 μm (micrometers) to 1,000 μm (micrometers).

[0039] Next, an N-type impurity is introduced into the semiconductor substrate 1s on the front surface 1a side of the semiconductor wafer 1 by ion implantation using a resist pattern as a mask, thereby forming an N-type hole barrier region 24. The ion implantation conditions at this time are, for example, phosphorus as the ion species and 6×10 12 cm -2 A preferable example of the ion implantation conditions is a concentration of about 100 keV and an implantation energy of about 200 keV.

[0040] Next, by ion implantation using a resist pattern as a mask, a P-type impurity is introduced into the semiconductor substrate 1s on the front surface 1a side of the semiconductor wafer 1, thereby forming a P-type floating region 16. The ion implantation conditions at this time are, for example, boron as the ion species and 3.5×10 12 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 75 keV.

[0041] The P-type floating region 16 is formed in the inactive cell region 40i. When forming the P-type floating region 16 in the cell formation region 3, the P-type floating region 16 is formed in the gate line lead-out region 4, for example.

[0042] 6, trenches 21, 21e are formed by, for example, anisotropic dry etching using a hard mask made of, for example, a silicon oxide film. A suitable example of the gas used for this anisotropic dry etching is a Cl / O gas.

[0043] 7, extension diffusion (for example, at 1200° C. (1200 degrees Celsius), for about 30 minutes) is performed on the P-type floating region 16 and the N-type hole barrier region 24. At this time, extension diffusion is performed so that the end of the P-type floating region 16 on the back surface 1b side is positioned at the end of the trenches 21, 21e on the back surface 1b side in the Z direction.

[0044] Next, by, for example, thermal oxidation, a gate insulating film 22 made of, for example, a silicon oxide film is formed on the surface 1a of the semiconductor wafer 1 and on the inner walls of the trenches 21, 21e. The thickness of the gate insulating film 22 is, for example, about 0.12 μm (micrometers).

[0045] The extensional diffusion forms a P-type floating region 16 between the trench 21 and the adjacent trench 21e. Preferably, the P-type floating region 16 contacts the gate insulating film 22 formed on the inner wall of the trench 21 and the gate insulating film 22 formed on the inner wall of the trench 21e.

[0046] Furthermore, an N-type hole barrier region 24 is formed between the trench 21 and the trench 21e. Preferably, the N-type hole barrier region 24 formed between the trench 21 and the trench 21e is in contact with the gate insulating film 22 formed on the inner wall of the trench 21 and the gate insulating film 22 formed on the inner wall of the trench 21e.

[0047] During the extension diffusion, the region of the N-type semiconductor wafer 1 where the P-type floating region 16 and the N-type hole barrier region 24 are not formed becomes the N − -type drift region 20.

[0048] Between trench 21 and trench 21e, the N-type impurity concentration of the N-type hole barrier region 24 is higher than the N-type impurity concentration in the N-type drift region 20 and lower than the N-type impurity concentration in the N+ type emitter region 12 described later.

[0049] Next, a conductive film 27 made of a phosphorus-doped polycrystalline silicon film is formed by, for example, a CVD (Chemical Vapor Deposition) method on the surface 1a of the semiconductor wafer 1 and inside the trenches 21, 21e. The thickness of the conductive film 27 is, for example, about 0.5 μm to 1.5 μm.

[0050] 8, the conductive film 27 is etched back by, for example, dry etching. This forms a trench gate electrode 14 made of the conductive film 27 embedded in the trench 21 via the gate insulating film 22. Also, a trench emitter electrode 14e made of the conductive film 27 embedded in the trench 21e via the gate insulating film 22 is formed. A suitable gas for this etching may be, for example, SF gas.

[0051] Next, the gate insulating film 22 is removed from the inside of the trenches 21 and 21e by, for example, dry etching.

[0052] Next, for example, by thermal oxidation or CVD, an insulating film 22a made of a relatively thin silicon oxide film for subsequent ion implantation is formed on the surface 1a of the semiconductor wafer 1. The insulating film 22a is formed to a thickness of, for example, several nm to 20 nm, and is used as a through film for ion implantation.

[0053] Next, a P-type body region 15 is formed by introducing P-type impurities into the entire surface of the cell formation region 3 and other necessary portions by ion implantation using a resist pattern as a mask.

[0054] Specifically, a P-type body region 15 is formed between trench 21 and trench 21e, in contact with gate insulating film 22 formed on the inner wall of trench 21 and gate insulating film 22 formed on the inner wall of trench 21e. This P-type body region 15 is formed on N-type hole barrier region 24 in active cell region 40a. Furthermore, in inactive cell region 40i, this P-type body region 15 is formed on P-type floating region 16.

[0055] The ion implantation conditions at this time are, for example, boron as the ion species and 3×10 13 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 75 keV.

[0056] Furthermore, an N+ type emitter region 12 is formed by introducing N-type impurities into the upper layer of the P-type body region 15 in the active cell region 40a by ion implantation using a resist pattern as a mask.

[0057] The ion implantation conditions at this time are, for example, arsenic as the ion species and 5×10 15 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 80 keV.

[0058] Next, as shown in FIG. 8, an interlayer insulating film 26 made of, for example, a PSG film (upper portion 26a) and an NSG film (lower portion 26b) is formed on the surface 1a of the semiconductor wafer 1 by, for example, CVD. The interlayer insulating film 26 is formed in each of the active cell region 40a and the inactive cell region 40i so as to cover the P-type body region 15 via, for example, the insulating film 22a. The thickness of the interlayer insulating film 26 is, for example, approximately 0.8 μm (micrometers) for the PSG film (upper portion 26a) and approximately 0.1 μm (micrometers) for the NSG film (lower portion 26b). Suitable materials for the interlayer insulating film 26 include a PSG film, an NSG film, a borophosphosilicate glass (BPSG) film, a spin-on-glass (SOG) film, or a composite film thereof.

[0059] Next, by combining anisotropic dry etching using a resist pattern as a mask and isotropic wet etching, contact holes 11 are formed in the interlayer insulating film (upper and lower portions 26a and 26b) as shown in FIG. 9. Specifically, a semiconductor wafer 1 having upper and lower portions 26a and 27b of the interlayer insulating film formed thereon as shown in FIG. 10 (in FIGS. 10 to 14, 16 to 20, 22 to 26, and 28 to 32, the ion implantation through insulating film 22a and the elements formed on the semiconductor wafer 1 up to the step shown in FIG. 8 are also omitted), is coated with resist (FIG. 11), and then photolithography is performed. Anisotropic dry etching is then performed to form contact holes 11 (FIG. 12). Suitable examples of gases for this anisotropic dry etching include a mixed gas containing, for example, Ar gas, CHF3 gas, CF4 gas, and O2 gas. Anisotropic dry etching is also performed on the silicon region to extend the contact holes 11 (FIG. 13). A suitable example of the gas for this anisotropic dry etching is Cl / O gas. Further, by performing a wet etching process using a solution containing hydrofluoric acid (FIG. 14), the contact hole 11 having the shape shown in FIG.

[0060] Next, for example, P-type impurities are ion-implanted through the contact holes 11 to form the P+ type body contact regions 25. The ion implantation conditions at this time are, for example, boron as the ion species and 5×10 15 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 80 keV.

[0061] Next, for example, a P-type impurity is ion-implanted through the contact hole 11 to form a P+-type latch-up prevention region 23. The ion implantation conditions at this time are, for example, boron as the ion species and 1×10 15 cm -2 The ion implantation conditions may be, for example, a voltage of about 100 keV and an implantation energy of about 100 keV. The P-type impurity concentration in the P+ type body contact region 25 is higher than the P-type impurity concentration in the P+ type latch-up prevention region 23.

[0062] In the active cell region 40a (see FIG. 2), a P+ type body contact region 25 and a P+ type latch-up prevention region 23 are formed in a portion of the P type body region 15 exposed in the contact hole 11. That is, the P+ type body contact region 25 and the P+ type latch-up prevention region 23 are formed in a portion located between the trench 21 and the trench 21e, in contact with the P type body region 15. In the active cell region 40a, the P type impurity concentration in the P+ type body contact region 25 and the P+ type latch-up prevention region 23 is higher than the P type impurity concentration in the P type body region 15.

[0063] Next, a contact member 11a is formed inside the contact hole 11. First, a barrier metal film is formed inside the contact hole 11 and on the interlayer insulating film. For example, a titanium film is formed inside the contact hole 11 and on the interlayer insulating film by sputtering, and then a titanium nitride film is formed on the titanium film by sputtering, thereby forming the barrier metal film.

[0064] Next, a conductive film made of, for example, a tungsten film is formed on the barrier metal film by, for example, a CVD method so as to fill the inside of the contact hole 11. Next, the conductive film and the barrier metal film formed outside the contact hole 11 are removed by anisotropic etching. As a result, a contact member 11a is formed so as to fill the inside of the contact hole 11.

[0065] Next, as shown in Figure 3, the emitter electrode 8 is formed. Specifically, this is performed, for example, by the following procedure. First, a titanium tungsten film is formed as a barrier metal film on the surface 1a of the semiconductor wafer 1, for example, by sputtering. The thickness of the titanium tungsten film is, for example, about 0.2 µm (micrometers).

[0066] Next, silicide annealing is performed in a nitrogen atmosphere at about 600°C (600 degrees Celsius) for about 10 minutes. After that, an aluminum-based metal film (e.g., a few percent silicon added, the remainder aluminum) is formed on the entire surface of the barrier metal film by, for example, sputtering. The thickness of the aluminum-based metal film is, for example, about 5 μm (micrometers).

[0067] Next, an emitter electrode 8 made of an aluminum-based metal film and a barrier metal film is formed by dry etching using a resist pattern as a mask. Suitable examples of gases for this dry etching include Cl2 / BCl3 gas.

[0068] The emitter electrode 8 is electrically connected to the plurality of N+ type emitter regions 12, the plurality of P+ type body contact regions 25, and the P+ type latch-up prevention region 23 formed in the active cell region 40a (see FIG. 2).

[0069] When forming the emitter electrode 8, the gate electrode 6 electrically connected to the trench gate electrode 14 may be formed (see FIG. 1). When forming the emitter electrode 8 in the cell formation region 3, the gate wiring 5 and the gate electrode 6 may be formed in the gate wiring lead-out region 4 (see FIG. 1).

[0070] Next, an insulating film 28 (see FIG. 3) made of an organic film containing, for example, polyimide as a main component, as a passivation film is formed on the emitter electrode 8. The thickness of the insulating film 28 is, for example, about 10.0 μm (micrometers).

[0071] Next, the insulating film 28 is patterned by dry etching using a resist pattern as a mask to form an opening 28e that penetrates the insulating film 28 and reaches the emitter electrode 8 (see FIG. 1). Then, an emitter pad 9 is formed by the portion of the emitter electrode 8 exposed in the opening 28e (see FIG. 1).

[0072] When forming the insulating film 28 on the emitter electrode 8 in the cell formation region 3, the insulating film 28 is also formed on the gate electrode 6 in the gate line lead-out region 4 (see FIG. 1). When forming the opening 28e in the cell formation region 3, an opening 28g is also formed in the gate line lead-out region 4, penetrating the insulating film 28 and reaching the gate electrode 6. Then, a gate pad 7 is formed that is made up of the portion of the gate electrode 6 exposed in the opening 28g (see FIG. 1).

[0073] Next, the back surface 1b (see FIG. 5) of the semiconductor wafer 1 (see FIG. 5) is subjected to a backgrinding process to reduce the thickness from, for example, about 800 μm (micrometers) to, for example, about 30 μm (micrometers) to 200 μm (micrometers) as needed. For example, if the withstand voltage is about 600 V, the final thickness is about 70 μm (micrometers). Also, chemical etching or the like is performed to remove damage to the back surface 1b as needed.

[0074] Next, an N-type field stop region 19 (see FIG. 3) is formed by introducing N-type impurities into the back surface 1b of the semiconductor wafer 1, for example, by ion implantation. The ion implantation conditions at this time are, for example, phosphorus as the ion species and 7×10 dose. 12 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 350 keV. Thereafter, if necessary, laser annealing or the like is performed on the back surface 1b of the semiconductor wafer 1 in order to activate the impurities.

[0075] Next, a P+ type collector region 18 (see FIG. 3) is formed by introducing P-type impurities into the back surface 1b of the semiconductor wafer 1, for example, by ion implantation. The ion implantation conditions at this time are, for example, boron as the ion species and a dose of 1×10 13 cm -2 A preferable example of the ion implantation conditions is a concentration of about 1000 keV and an implantation energy of about 40 keV. Thereafter, if necessary, laser annealing or the like is performed on the back surface 1b of the semiconductor wafer 1 in order to activate the impurities.

[0076] Next, for example, by sputtering, a collector electrode 17 (see FIG. 3) electrically connected to the P+ type collector region 18 is formed on the back surface 1b of the semiconductor wafer 1. Thereafter, the semiconductor substrate 1s is divided into chip regions by dicing or the like, and sealed in a package as necessary, thereby substantially completing the semiconductor device 2.

[0077] To illustrate the device structure more specifically, the following shows an example of the major dimensions of each part of the device (see FIGS. 2 and 3). Specifically, the width (Wa) of the active cell region 40a is approximately 0.8 μm to 0.9 μm, and the width (Wi) of the inactive cell region 40i is approximately 3.3 μm. The width (Wa) of the active cell region 40a is preferably narrower than the width (Wi) of the inactive cell region 40i, and a value of Wi / Wa ranging from 2 to 3 is particularly preferable. The contact width is approximately 0.7 μm (micrometers) to 0.9 μm (micrometers) (the width of the bottom end of the contact hole 11), the trench width is approximately 0.4 μm to 0.5 μm, and the trench depth is approximately 3 μm. The depth of the N+ type emitter region 12 is approximately 250 nm, the depth of the P-type body region 15 (channel region) is approximately 0.8 μm (micrometers), and the depth of the P+ type latch-up prevention region 23 is approximately 1.4 μm (micrometers). The depth of the P-type floating region 16 is approximately 4.5 μm (micrometers), the thickness of the N-type field stop region 19 is approximately 1.5 μm (micrometers), the thickness of the P+ type collector region is approximately 0.5 μm (micrometers), and the thickness of the semiconductor substrate 1 s is approximately 70 μm (micrometers). Here, the thickness of the semiconductor substrate 1 s is shown as an example for a breakdown voltage of approximately 600 volts. Note that the thickness of the semiconductor substrate 1 s is strongly dependent on the required breakdown voltage. Therefore, for a breakdown voltage of 1200 volts, the thickness is approximately 120 μm (micrometers), and for a breakdown voltage of 400 volts, the thickness is approximately 40 μm (micrometers). Note that these values ​​are merely examples.

[0078] The following describes embodiments 2 to 4. In the following description of the embodiments, the same reference numerals as in embodiment 1 above may be used for parts having the same configurations and functions as those described in embodiment 1 above. The description of such parts may be appropriately cited within the scope of not being technically inconsistent. Furthermore, part of embodiment 1 above and all or part of embodiments 2 to 4 may be appropriately applied in combination within the scope of not being technically inconsistent.

[0079] (Embodiment 2) 15 is a cross-sectional view showing the shape of a contact hole in the second embodiment. In the semiconductor device 2 of the second embodiment (the plan view is the same as that of FIG. 1), the configuration other than the shape of the contact hole 11 is basically the same as that of the first embodiment. In FIG. 15, in the cross-sectional view, the width in the X direction of the contact hole 11 is wider at the upper end than at the lower end of the contact hole 11, and is wider at the depth corresponding to the upper portion 26a of the interlayer insulating film than at the depth corresponding to the lower portion 26b of the interlayer insulating film. Furthermore, at the depth corresponding to the upper portion 26a of the interlayer insulating film, the inclination angle Φ1 of the contact hole 11 is larger than the inclination angle Φ2 of the contact hole 11 at the depth corresponding to the lower portion 26b. In other words, in a cross-sectional view, the width of the contact hole 11 in the X direction increases along the Z direction from the interior of the semiconductor wafer 1 toward the surface 1a (see FIG. 5) at a depth corresponding to the lower portion 26b of the interlayer insulating film and a depth corresponding to the upper portion 26a of the interlayer insulating film, respectively, and the rate of increase in the depth corresponding to the lower portion 26b of the interlayer insulating film is greater than the rate of increase in the depth corresponding to the upper portion 26a of the interlayer insulating film. Thus, in addition to the effects described in the first embodiment, by providing a slope in the upper portion 26a of the interlayer insulating film, it is possible to thicken the barrier metal film (TiN / Ti) and improve its barrier performance. Furthermore, by making Φ1 larger than Φ2, it is possible to suppress the expansion of the contact diameter.

[0080] (Method of Manufacturing a Semiconductor Device in the Second Embodiment) The method for manufacturing the semiconductor device 2 in the second embodiment is the same as that in the first embodiment except for the steps relating to the formation of the contact holes 11. The following describes the differences from the first embodiment.

[0081] As shown in FIG. 16, a semiconductor wafer 1 having an upper interlayer insulating film 26a and a lower interlayer insulating film 26b formed thereon is coated with resist (FIG. 17). Photolithography is then performed, followed by an anisotropic dry etching process to form contact holes 11 (FIG. 18). This anisotropic dry etching process stops at the upper interlayer insulating film 26a, without etching the lower interlayer insulating film 26b. Suitable gases for this anisotropic dry etching include a mixed gas containing Ar gas, CHF3 gas, CF4 gas, and O2 gas. Furthermore, an anisotropic dry etching process is performed on the lower interlayer insulating film 26b under different etching conditions, such as by changing the flow rate ratio of the etching gas (O2, etc.) (FIG. 19). The slope of the contact holes 11 can be adjusted by changing the etching gas flow rate ratio as well as by changing conditions such as the stage temperature and the high-frequency output. Adjusting the slope of the contact holes 11 by changing the etching conditions is also performed in Examples 3 and 4 described below. Anisotropic dry etching is also performed on the silicon region to extend the contact hole 11 (FIG. 20). A suitable example of gas for this anisotropic dry etching is Cl2 / O2 gas.

[0082] (Embodiment 3) FIG. 21 is a cross-sectional view showing the shape of a contact hole in the third embodiment. In the semiconductor device 2 of the third embodiment (the plan view is the same as that of FIG. 1), the upper and lower portions 26a and 26b of the interlayer insulating film are both PSG films and are integrated. The shape of the contact hole 11 is the same as that of the first embodiment. In a cross-sectional view, the width of the contact hole 11 in the X direction is wider at the upper end than at the lower end of the contact hole 11, and wider at the depth corresponding to the upper portion 26a of the interlayer insulating film than at the depth corresponding to the lower portion 26b of the interlayer insulating film. At the depth corresponding to the upper portion 26a of the interlayer insulating film, the inclination of the contact hole 11 is vertical or nearly vertical (the inclination angle Φ1 is 85 to 90 degrees), whereas at the depth corresponding to the lower portion 26b, the inclination of the contact hole is significantly smaller than vertical (the inclination angle Φ2 is significantly smaller than 90 degrees). By adopting such an inclination angle for the lower portion 26b of the interlayer insulating film, the embeddability of tungsten in the contact member 11a can be improved. As will be explained later in the manufacturing method, the upper portion of contact hole 11 (the portion at a depth corresponding to upper portion 26a of the interlayer insulating film) can be formed by dry etching to have a vertical or nearly vertical inclination angle Φ1, thereby preventing the contact hole diameter from increasing. Furthermore, by forming the interlayer insulating film as a single layer of PSG film, it is not necessary to change the film formation conditions within the PSG film formation device, thereby reducing manufacturing costs.

[0083] (Method of Manufacturing a Semiconductor Device in Third Embodiment) The manufacturing method of the semiconductor device 2 in the third embodiment is the same as that in the first embodiment, except for the steps relating to the formation of the interlayer insulating film and the formation of the contact hole 11. The interlayer insulating film (upper portion 26a, lower portion 26b) is formed by forming a PSG film by, for example, a CVD method. The following describes the parts relating to the formation of the contact hole 11 that differ from the first embodiment.

[0084] As shown in FIG. 22, a semiconductor wafer 1 with an interlayer insulating film (upper portion 26a, lower portion 26b) formed thereon is coated with resist (FIG. 23). Photolithography is then performed, and an anisotropic oxide film dry etching process is performed to form contact holes 11 (FIG. 24). This anisotropic oxide film dry etching process stops at the upper portion 26a, not the lower portion 26b of the interlayer insulating film. A suitable gas for this anisotropic oxide film dry etching is, for example, a mixed gas containing Ar gas, CHF3 gas, CF4 gas, O2 gas, etc. Furthermore, an anisotropic oxide film dry etching process is performed on the lower portion 26b of the interlayer insulating film under different etching conditions, such as changing the flow rate ratio of the etching gas (O2, etc.) (FIG. 25). An anisotropic dry etching process is also performed on the silicon region to extend the contact holes 11 (FIG. 26). A suitable gas for this anisotropic dry etching is, for example, Cl2 / O2 gas.

[0085] (Fourth embodiment) FIG. 27 is a cross-sectional view showing the shape of a contact hole in the fourth embodiment. In the semiconductor device 2 of the fourth embodiment (the plan view is the same as that of FIG. 1), the upper and lower portions 26a and 26b of the interlayer insulating film are both PSG films and are integrated. The shape of the contact hole 11 is the same as that of the second embodiment. In a cross-sectional view, the width of the contact hole 11 in the X direction is wider at the upper end than at the lower end of the contact hole 11, and wider at a depth corresponding to the upper portion 26a of the interlayer insulating film than at a depth corresponding to the lower portion 26b of the interlayer insulating film. At a depth corresponding to the upper portion 26a of the interlayer insulating film, the inclination angle Φ1 of the contact hole 11 is larger than the inclination angle Φ2 of the contact hole 11 at a depth corresponding to the lower portion 26b. In other words, in a cross-sectional view, the width of the contact hole 11 in the X direction increases along the Z direction from the interior of the semiconductor wafer 1 toward the surface 1a (see FIG. 5) at a depth corresponding to the lower portion 26b of the interlayer insulating film and a depth corresponding to the upper portion 26a of the interlayer insulating film, respectively. The rate of increase in the width at the depth corresponding to the lower portion 26b of the interlayer insulating film is greater than the rate of increase in the width at the depth corresponding to the upper portion 26a of the interlayer insulating film. By providing a slope at the upper portion 26a of the interlayer insulating film in this manner, the barrier metal film (TiN / Ti) can be thickened to enhance its barrier performance. Furthermore, by making Φ1 larger than Φ2, the expansion of the contact diameter can be suppressed. Furthermore, unlike the second embodiment, the interlayer insulating film is a single layer of PSG film, eliminating the need to change film formation conditions within a PSG film formation apparatus, thereby reducing manufacturing costs.

[0086] (Method of Manufacturing a Semiconductor Device in Fourth Embodiment) The manufacturing method of the semiconductor device 2 in the fourth embodiment is the same as that in the first embodiment, except for the steps relating to the formation of the interlayer insulating film and the formation of the contact hole 11. The interlayer insulating film (upper portion 26a, lower portion 26b) is formed by forming a PSG film by, for example, a CVD method. The following describes the parts relating to the formation of the contact hole 11 that differ from the first embodiment.

[0087] As shown in FIG. 28, a semiconductor wafer 1 with an interlayer insulating film (upper portion 26a, lower portion 26b) formed thereon is coated with resist (FIG. 29). Photolithography is then performed, and an anisotropic oxide film dry etching process is performed to create contact holes 11 (FIG. 30). This anisotropic oxide film dry etching process stops at the upper portion 26a, not the lower portion 26b of the interlayer insulating film. A suitable gas for this anisotropic oxide film dry etching is, for example, a mixed gas containing Ar gas, CHF3 gas, CF4 gas, O2 gas, etc. Furthermore, an anisotropic oxide film dry etching process is performed on the lower portion 26b of the interlayer insulating film under different etching conditions, such as changing the flow rate ratio of the etching gas (O2, etc.) (FIG. 31). An anisotropic dry etching process is also performed on the silicon region to extend the contact holes 11 (FIG. 32). A suitable gas for this anisotropic dry etching is, for example, Cl2 / O2 gas.

[0088] Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0089] For example, in the above embodiment, an IGBT is exemplified as a device formed in the cell formation region 3, but the technology disclosed in the above embodiment is not limited to an IGBT and can be applied to any semiconductor device, such as a power MOSFET having a vertical trench gate structure.

[0090] Furthermore, the material used for the semiconductor substrate SUB is not limited to silicon (Si) and may be silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), etc. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc., and the p-type impurity may be, for example, boron (B), indium (In), etc.

[0091] Furthermore, the various configurations described in the respective embodiments can be implemented in combination with one another. This specification describes, for example, the following configurations.

[0092] (Addendum) (Appendix 1) a semiconductor substrate having a first main surface and having a drift region of a first conductivity type therein; an interlayer insulating film having an upper portion and a lower portion formed on the upper side of the first main surface; Equipped with A cell region is provided in the first main surface in a plan view, and in the cell region, an active cell region provided from above the first main surface to the inside of the drift region; a trench gate electrode and a trench emitter electrode, each formed via an insulating film in a pair of trenches, each consisting of a first trench and a second trench, provided on the surface of the first main surface so as to sandwich the active cell region from both sides in a first direction in a cross-sectional view; a body region of a second conductivity type different from the first conductivity type provided in a surface region of the drift region on the first main surface side; an inactive cell region provided to sandwich the active cell region from both sides in the first direction, with the trench gate electrode and the trench emitter electrode as boundaries in a cross-sectional view; an emitter region of the first conductivity type provided in the active cell region and in a surface region closer to the first main surface than the body region; a contact member formed in a contact hole that penetrates the interlayer insulating film and, in a cross-sectional view, contacts the trench emitter electrode and the interlayer insulating film on one side in the first direction and contacts the body region, the emitter region, and the interlayer insulating film on the other side in the first direction; a hole barrier region of the first conductivity type provided in the drift region below the body region in the active cell region, the hole barrier region having an impurity concentration higher than that of the drift region and lower than that of the emitter region; the second conductive type floating region provided below the body region in the inactive cell region; Equipped with A semiconductor device, wherein, in a cross-sectional view, the width of the contact hole in the first direction is wider at the upper end than at the lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film.

[0093] (Appendix 2) In the semiconductor device according to Supplementary Note 1, a semiconductor device in which, in a cross-sectional view, the width of the contact hole in the first direction increases as it progresses from inside the semiconductor substrate toward the first main surface along a second direction perpendicular to the first direction at a depth corresponding to the lower part of the interlayer insulating film and a depth corresponding to the upper part of the interlayer insulating film, and the rate of increase of the increase at the depth corresponding to the lower part of the interlayer insulating film is greater than the rate of increase of the increase at the depth corresponding to the upper part of the interlayer insulating film.

[0094] (Appendix 3) In the semiconductor device according to Supplementary Note 1 or 2, The semiconductor device, wherein the upper and lower portions of the interlayer insulating film have different compositions.

[0095] (Appendix 4) In the semiconductor device according to Supplementary Note 3, The semiconductor device, wherein the upper portion of the interlayer insulating film is a PSG (Phospho Silicate Glass) film, and the lower portion of the interlayer insulating film is an NSG (Non-doped Silicate Glass) film.

[0096] (Appendix 5) In the semiconductor device according to Supplementary Note 1 or 2, the upper and lower portions of the interlayer insulating film are integrated to form an interlayer insulating film.

[0097] (Appendix 6) In the semiconductor device according to Supplementary Note 5, The upper and lower portions of the interlayer insulating film are PSG (Phospho Silicate Glass) films.

[0098] (Appendix 7) (a) providing a semiconductor substrate having a first main surface and a drift region of a first conductivity type therein; (b) forming a first trench and a second trench from the first major surface of the semiconductor substrate; (c) forming an insulating film on the first main surface and on inner walls of the first trench and the second trench; (d) forming floating regions of a second conductivity type on the first main surface side of the semiconductor substrate so as to sandwich a pair of trenches, each of which is made up of the first trench and the second trench, from both sides in a first direction in a cross-sectional view; (e) forming a hole barrier region of the first conductivity type on the first main surface side of the semiconductor substrate so as to be sandwiched between the first trench and the second trench in a cross-sectional view; (f) forming a trench gate electrode in the first trench via the insulating film, and forming a trench emitter electrode in the second trench via the insulating film; (g) removing the insulating film formed outside the first trench and the second trench; (h) forming a body region of a second conductivity type in a surface region of the drift region on the first main surface side; (i) forming an emitter region of the first conductivity type in a surface region between the trench gate electrode and the trench emitter electrode and closer to the first main surface than the body region in a cross-sectional view; (j) forming an interlayer insulating film having an upper portion and a lower portion above the first main surface; (k) forming a contact hole that penetrates the interlayer insulating film and contacts the trench emitter electrode and the interlayer insulating film on one side in the first direction, and contacts the body region, the emitter region, and the interlayer insulating film on the other side in the first direction, and forming the contact member in the contact hole; Including, (k) is a method for manufacturing a semiconductor device, and includes forming the contact hole by an etching process including a first etching process, a second etching process, and a third etching process, so that, in a cross-sectional view, the width of the contact hole in the first direction is wider at an upper end than at a lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film, and forming the contact member in the contact hole.

[0099] (Appendix 8) 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the upper and lower portions of the interlayer insulating film have different compositions.

[0100] (Appendix 9) 9. The method for manufacturing a semiconductor device according to claim 8, The method for manufacturing a semiconductor device, wherein the upper part of the interlayer insulating film is a PSG (Phospho Silicate Glass) film, and the lower part of the interlayer insulating film is an NSG (Non-doped Silicate Glass) film.

[0101] (Appendix 10) 10. The method for manufacturing a semiconductor device according to claim 9, wherein the first etching process and the second etching process are dry etching processes, and the third etching process is wet etching process.

[0102] (Appendix 11) 10. The method for manufacturing a semiconductor device according to claim 9, wherein the first etching process, the second etching process, and the third etching process are dry etching processes.

[0103] (Appendix 12) 8. The method for manufacturing a semiconductor device according to claim 7, The upper and lower portions of the interlayer insulating film form an integrated interlayer insulating film.

[0104] (Appendix 13) 13. The method for manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the upper and lower portions of the interlayer insulating film are PSG (Phospho Silicate Glass) films.

[0105] (Appendix 14) 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first etching process, the second etching process, and the third etching process are dry etching processes.

[0106] (Appendix 15) a semiconductor substrate having a first main surface; an interlayer insulating film having an upper portion and a lower portion formed above the first main surface; a contact member formed in a contact hole that penetrates the interlayer insulating film; Equipped with A semiconductor device, wherein, in a cross-sectional view, the width of the contact hole in a first direction is wider at the upper end than at the lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film. [Explanation of symbols]

[0107] 1. Semiconductor wafer 1a Surface (first main surface) of wafer or chip 1b Back surface (second main surface) of wafer or chip 1s N-type single crystal silicon substrate (semiconductor substrate) 2. Semiconductor Devices 3. Cell formation area 4 Gate wiring pull-out area 5 Gate wiring 6 gate electrode 7 Gate Pad 8 Emitter electrode 9 Emitter Pad 11 Contact Hole 11a Contact member 12 N+ type emitter region 14 Trench gate electrode 14e Trench emitter electrode 14g1 End trench gate electrode 14t1 Edge trench emitter electrode 15 P-type body region 16 P-type floating area 17 Collector electrode 18 P+ type collector region 19 N-type field stop region 20 N-type drift region 21 Trench 21e Trench 22 Gate insulating film 22a Through insulating film for ion implantation 23 P+ latch-up prevention area 24 N-type hole barrier region (first hole barrier region) 24a N-type hole barrier region (second hole barrier region, N-type isolation region) 25 P+ type body contact area 26a Upper part of interlayer insulating film 26b Lower part of interlayer insulating film 28 insulating film 28e,28g opening 40a Active cell area 40i Inactive cell area

Claims

1. a semiconductor substrate having a first main surface and a first conductivity type drift region therein; an interlayer insulating film having an upper portion and a lower portion formed above the first main surface; Equipped with A cell region is provided in the first main surface in a plan view, and in the cell region, an active cell region provided from above the first main surface to the inside of the drift region; a trench gate electrode and a trench emitter electrode, each formed via an insulating film in a pair of trenches, each of which includes a first trench and a second trench, provided on the surface of the first main surface so as to sandwich the active cell region from both sides in a first direction in a cross-sectional view; a body region of a second conductivity type different from the first conductivity type provided in a surface region of the drift region on the first main surface side; an inactive cell region provided to sandwich the active cell region from both sides in the first direction, with the trench gate electrode and the trench emitter electrode as boundaries in a cross-sectional view; an emitter region of the first conductivity type provided in the active cell region and in a surface region closer to the first main surface than the body region; a contact member formed in a contact hole that penetrates the interlayer insulating film and that, in a cross-sectional view, contacts the trench emitter electrode and the interlayer insulating film on one side in the first direction and contacts the body region, the emitter region, and the interlayer insulating film on the other side in the first direction; a hole barrier region of the first conductivity type provided in the drift region below the body region in the active cell region, the hole barrier region having an impurity concentration higher than that of the drift region and lower than that of the emitter region; the second conductive type floating region provided below the body region in the inactive cell region; Equipped with A semiconductor device, wherein, in a cross-sectional view, the width of the contact hole in the first direction is wider at the upper end than at the lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film.

2. 2. The semiconductor device according to claim 1, a semiconductor device, wherein, in a cross-sectional view, the width of the contact hole in the first direction increases as it progresses from inside the semiconductor substrate toward the first main surface along a second direction perpendicular to the first direction at a depth corresponding to the lower part of the interlayer insulating film and a depth corresponding to the upper part of the interlayer insulating film, and the rate of increase of the increase at the depth corresponding to the lower part of the interlayer insulating film is greater than the rate of increase of the increase at the depth corresponding to the upper part of the interlayer insulating film.

3. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the upper and lower portions of the interlayer insulating film have different compositions.

4. 4. The semiconductor device according to claim 3, The upper portion of the interlayer insulating film is a PSG (Phospho Silicate Glass) film, and the lower portion of the interlayer insulating film is an NSG (Non-doped Silicate Glass) film.

5. 2. The semiconductor device according to claim 1, the upper and lower portions of the interlayer insulating film are integrated to form an interlayer insulating film.

6. 6. The semiconductor device according to claim 5, The upper and lower portions of the interlayer insulating film are PSG (Phospho Silicate Glass) films.

7. (a) providing a semiconductor substrate having a first main surface and a drift region of a first conductivity type therein; (b) forming a first trench and a second trench from the first major surface of the semiconductor substrate; (c) forming an insulating film on the first main surface and on inner walls of the first trench and the second trench; (d) forming floating regions of a second conductivity type on the first main surface side of the semiconductor substrate so as to sandwich a pair of trenches, each of which is made up of the first trench and the second trench, from both sides in a first direction in a cross-sectional view; (e) forming a hole barrier region of the first conductivity type on the first main surface side of the semiconductor substrate so as to be sandwiched between the first trench and the second trench in a cross-sectional view; (f) forming a trench gate electrode in the first trench via the insulating film, and forming a trench emitter electrode in the second trench via the insulating film; (g) removing the insulating film formed outside the first trench and the second trench; (h) forming a body region of a second conductivity type in a surface region of the drift region on the first main surface side; (i) forming an emitter region of the first conductivity type in a surface region between the trench gate electrode and the trench emitter electrode and closer to the first main surface than the body region in a cross-sectional view; (j) forming an interlayer insulating film having an upper portion and a lower portion above the first main surface; (k) forming a contact hole that penetrates the interlayer insulating film and contacts the trench emitter electrode and the interlayer insulating film on one side in the first direction, and contacts the body region, the emitter region, and the interlayer insulating film on the other side in the first direction, and forming the contact member in the contact hole; Including, (k) is a method for manufacturing a semiconductor device, and includes forming the contact hole by an etching process including a first etching process, a second etching process, and a third etching process, so that, in a cross-sectional view, the width of the contact hole in the first direction is wider at an upper end than at a lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film, and forming the contact member in the contact hole.

8. 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the upper and lower portions of the interlayer insulating film have different compositions.

9. 9. The method for manufacturing a semiconductor device according to claim 8, The method for manufacturing a semiconductor device, wherein the upper portion of the interlayer insulating film is a PSG (Phospho Silicate Glass) film, and the lower portion of the interlayer insulating film is an NSG (Non-doped Silicate Glass) film.

10. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first etching process and the second etching process are dry etching processes, and the third etching process is wet etching process.

11. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first etching process, the second etching process, and the third etching process are dry etching processes.

12. 8. The method for manufacturing a semiconductor device according to claim 7, The upper and lower portions of the interlayer insulating film form an integrated interlayer insulating film.

13. 13. The method for manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the upper and lower portions of the interlayer insulating film are PSG (Phospho Silicate Glass) films.

14. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the first etching process, the second etching process, and the third etching process are dry etching processes.

15. a semiconductor substrate having a first main surface; an interlayer insulating film having an upper portion and a lower portion formed above the first main surface; a contact member formed in a contact hole that penetrates the interlayer insulating film; Equipped with A semiconductor device, wherein, in a cross-sectional view, the width of the contact hole in a first direction is wider at the upper end than at the lower end of the contact hole, and wider at a depth corresponding to the upper part of the interlayer insulating film than at a depth corresponding to the lower part of the interlayer insulating film.

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