Method of manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of improving reliability.SOLUTION: The method includes forming a first mask 100C having a plurality of openings MO on an upper surface divided into a first region 100E and a second region M1, forming a second mask M1 that exposes a portion of the first mask 100C disposed in the first region M1 and covers a portion of the first mask 100E disposed in the second region M2, etching the substrate SUB in the first region M1 using the first mask and the second mask as a mask, removing the second mask, and etching the substrate SUB in the first region and the second region using the first mask as a mask. 100E M2 100C 100C M1 M2.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which a trench is formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-001723 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for improved reliability of semiconductor devices.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having an upper surface and a lower surface; forming a first mask having a plurality of openings on the upper surface divided into a first region and a second region; forming a second mask that exposes a portion of the first mask located in the first region and covers a portion of the first mask located in the second region; etching the semiconductor substrate in the first region using the first mask and the second mask as masks; removing the second mask; and etching the semiconductor substrate in the first region and the second region using the first mask as a mask.

[0007] According to one embodiment, a method for manufacturing a semiconductor device includes: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate and extend in a first direction in a plan view; (c) after the step (b), forming a first insulating film inside the trench; (d) after the step (c), forming a field plate electrode so as to fill the inside of the trench with the first insulating film interposed therebetween; and (e) after the step (d), (f) after the step (e), a step of selectively recessing the first insulating film so that the position of its upper surface inside the trench is lower than the position of the upper surface of the field plate electrode; (g) after the step (f), a step of forming a gate insulating film on the semiconductor substrate inside the trench and forming a second insulating film on the upper surface and side surfaces of the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the field plate electrode recessed in the step (e) so as to fill the inside of the trench; (i) after the step (h), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench; (j) after the step (i), forming a first hole, a second hole, and a third hole in the interlayer insulating film; and (k) after the step (j), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film, the gate electrode includes a first end in a direction opposite to the first end in the first direction, the contact portion is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end in a plan view, and the third hole is formed to overlap the contact portion in a plan view, the gate wiring is embedded in the first hole and the second hole, and is electrically connected to the gate electrode,the source electrode is embedded in the third hole and is electrically connected to the field plate electrode; in the step (h), a coupling portion connecting the gate electrode on the first end side and the gate electrode on the second end side is formed as a part of the gate electrode inside the trench in which the contact portion is formed; and the step (b) includes the steps of forming a first mask having a plurality of openings on an upper surface of the semiconductor substrate divided into a first region and a second region, forming a second mask exposing a portion of the first mask located in the first region and covering a portion of the first mask located in the second region, etching the semiconductor substrate in the first region using the first mask and the second mask as masks, removing the second mask, etching the semiconductor substrate in the first region and the second region using the first mask as a mask, and removing the first mask. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a method for manufacturing a semiconductor device that can improve reliability. [Brief explanation of the drawings]

[0009] [Figure 1] 10A and 10B are plan views illustrating semiconductor substrates in the methods for manufacturing semiconductor devices according to a comparative example and the first embodiment. [Figure 2] 4A to 4C are cross-sectional views illustrating semiconductor substrates in the methods for manufacturing semiconductor devices according to a comparative example and the first embodiment. [Figure 3] 4A to 4C are cross-sectional views illustrating semiconductor substrates in the methods for manufacturing semiconductor devices according to a comparative example and the first embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating semiconductor substrates in the methods for manufacturing semiconductor devices according to a comparative example and the first embodiment. [Figure 5] 4A to 4C are cross-sectional views illustrating semiconductor substrates in the methods for manufacturing semiconductor devices according to a comparative example and the first embodiment. [Figure 6]2 is a cross-sectional view illustrating a semiconductor substrate in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2 is a cross-sectional view illustrating a semiconductor substrate in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 2 is a cross-sectional view illustrating a semiconductor substrate in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a plan view illustrating a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a plan view illustrating a semiconductor device according to a second embodiment. [Figure 11] 11A and 11B are cross-sectional views illustrating the semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 12] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 13] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 14] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 15] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 16] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 17] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 18] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 19] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 20]11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 21] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 22] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 23] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 24] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 25] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. [Figure 26] 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment, showing cross sections AA and BB in FIG. 10. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Note that in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary. Furthermore, reference numerals have been omitted as appropriate to avoid cluttering the drawings.

[0011] First, in <Comparative Example>, a method for manufacturing a semiconductor device according to the comparative example is described. Then, in <Problems newly discovered by the inventors>, problems newly discovered by the inventors with respect to the comparative example are described. Then, in <Embodiment 1> and <Embodiment 2>, methods for manufacturing semiconductor devices according to embodiments 1 and 2 are described. This makes the semiconductor devices and methods for manufacturing semiconductor devices according to embodiments 1 and 2 clearer. Note that the methods for manufacturing semiconductor devices according to the comparative example and the problems newly discovered by the inventors are also within the technical scope of the embodiments.

[0012] <Comparative Example> FIG. 1 is a plan view illustrating a semiconductor substrate SUB in the manufacturing methods of semiconductor devices according to the comparative example and embodiment 1. FIGS. 2 to 5 are cross-sectional views illustrating the semiconductor substrate SUB in the manufacturing methods of semiconductor devices according to the comparative example and embodiment 1. FIGS. 1 to 5 are also used for the method of dividing the first region 100C and the second region 100E in embodiment 1. As shown in FIGS. 1 and 2, in the manufacturing method of the semiconductor device 101 of the comparative example, first, a semiconductor substrate SUB having a first surface 100a and a second surface 100b is prepared. FIG. 1 also shows dividing lines dividing the first surface 100a of the semiconductor substrate SUB into a plurality of regions for displaying as a map.

[0013] Here, for the convenience of explaining the manufacturing method of the semiconductor device 101, an XYZ Cartesian coordinate system is introduced. For example, the direction perpendicular to the first surface 100a is the Z-axis direction, and the plane parallel to the first surface 100a is the XY plane. The +Z-axis direction is the up direction, and the -Z-axis direction is the down direction. The first surface 100a is referred to as the up surface, and the second surface 100b is referred to as the down surface. Note that up and down are used for the convenience of explaining the manufacturing method of the semiconductor device 101, and do not indicate the directions in which the semiconductor device 101 is actually disposed.

[0014] The semiconductor substrate SUB includes, for example, an n-type drift region NV. Here, the semiconductor substrate SUB itself constitutes the n-type drift region NV, but the drift region NV may be an n-type semiconductor layer grown on the n-type semiconductor substrate SUB by epitaxial growth while introducing phosphorus (P).

[0015] The upper surface of the semiconductor substrate SUB is divided into a first region 100C and a second region 100E. The method of dividing the first region 100C and the second region 100E will be described later. Here, the first region 100C will be described as including a center portion (Center) of the upper surface of the semiconductor substrate SUB when viewed from the Z-axis direction. The second region 100E will be described as including an outer periphery portion (Edge) of the upper surface of the semiconductor substrate SUB when viewed from the Z-axis direction.

[0016] Next, as shown in FIG. 3, a first mask material HM is formed on the upper surface of the semiconductor substrate SUB. The first mask material HM is used to form a first mask M1 on the upper surface of the semiconductor substrate SUB. The first mask material HM includes, for example, a hard mask. As an example, the hard mask may include a silicon oxide film. For example, a hard mask including a silicon oxide film is formed on the semiconductor substrate SUB by a CVD (Chemical Vapor Deposition) method.

[0017] 4, a first mask M1 having a plurality of openings MO is formed on the upper surface of the semiconductor substrate SUB, which is divided into a central portion Center and an outer peripheral portion Edge. The process of forming the first mask M1 includes, for example, the following steps.

[0018] First, as described above, a first mask material HM is formed on the upper surface of the semiconductor substrate SUB. Next, a third mask material is formed on the first mask material HM. The third mask material may include, for example, photoresist. Next, the third mask material is exposed to light in the portions corresponding to the openings MO or the portions other than the openings MO. This allows the portions corresponding to the openings MO to be selectively removed, for example, by a developer or the like. Next, a third mask M3 is formed by removing the portions of the third mask material corresponding to the openings MO and leaving the portions other than the openings MO. In this way, a third mask M3 having openings is formed by photolithography. The third mask M3 includes, for example, a resist pattern.

[0019] Next, the first mask material HM is etched using the third mask M3 as a mask to form a first mask M1. For example, a patterned first mask M1 is formed by performing a dry etching process using the third mask M3 including a resist pattern as a mask. In this way, in the process of forming the first mask M1, openings MO for forming trenches TR in the semiconductor substrate SUB are patterned. The first mask M1 includes a hard mask.

[0020] Next, as shown in FIG. 5, the third mask M3 is removed. For example, the third mask M3 including the resist pattern is removed by ashing. Next, a dry etching process is performed using the patterned first mask M1 as a mask. This forms trenches TR in the semiconductor substrate SUB. Thereafter, the first mask M1 is removed by wet etching using a solution containing hydrofluoric acid or the like.

[0021] In the manufacturing method of the semiconductor device 101 of the comparative example, it may be difficult to make the depth of the trenches TR uniform within the plane of the upper surface of the semiconductor substrate SUB. For example, the depth of the trenches TR in the outer peripheral portion (Edge) of the upper surface of the semiconductor substrate SUB may differ from the depth of the trenches TR in the central portion (Center). Specifically, depending on the dry etching conditions, the depth of the trenches TR in the outer peripheral portion (Edge) may be deeper than the depth of the trenches TR in the central portion (Center).

[0022] For example, a difference in etching depth Dif occurs between the depth of the trench TR in the center portion (Center) and the depth of the trench TR in the outer peripheral portion (Edge). This affects the operation of the semiconductor device 101 and reduces the yield of the semiconductor device 101. As a result, the reliability of the semiconductor device 101 is reduced.

[0023] <Embodiment 1> Next, a description will be given of a method for manufacturing a semiconductor device according to embodiment 1. First, a description will be given of a method for manufacturing a semiconductor device, followed by a description of application to regions other than trenches and a method for dividing the first and second regions.

[0024] <Method of manufacturing a semiconductor device> The method for manufacturing a semiconductor device according to this embodiment improves uniformity between the depth of the trenches TR in the central portion (Ceter) and the depth of the trenches TR in the peripheral portion (Edge) on the upper surface of the semiconductor substrate SUB. Specifically, in this embodiment, when forming the trenches TR in the semiconductor substrate SUB, selective etching is performed using blank exposure. Blank exposure is a process that leaves a mask containing photoresist or the like only in the peripheral portion (Edge) where the trenches TR tend to become deeper. FIGS. 6 to 8 are cross-sectional views illustrating the semiconductor substrate SUB in the method for manufacturing the semiconductor device 1 according to embodiment 1.

[0025] 2 to 4, the method for manufacturing a semiconductor device according to this embodiment includes the same steps as those of the comparative example. As a result, a first mask M1 having a plurality of openings MO is formed on the upper surface of a semiconductor substrate SUB, which is divided into a center portion (Center) and an outer peripheral portion (Edge). Thereafter, a third mask M3 is removed by an ashing process.

[0026] 6, a second mask M2 is formed to expose a portion of the first mask M1 located in the center and to cover a portion of the first mask M1 located in the edge. The process of forming the second mask M2 includes, for example, the following steps.

[0027] First, a second mask material is formed on the first mask M1. The second mask material may include photoresist. Next, the portion of the second mask material corresponding to the center portion (Center) or the portion corresponding to the outer peripheral portion (Edge) is exposed to light. This allows the portion corresponding to the center portion (Center) to be selectively removed using, for example, a developer. Next, the portion of the second mask material corresponding to the center portion (Center) is removed while leaving the portion corresponding to the outer peripheral portion (Edge), thereby forming a second mask M2. In this manner, the second mask M2 is formed by photolithography. The second mask M2 includes photoresist. Therefore, the second mask M2 includes a resist pattern.

[0028] Next, as shown in FIG. 7, the semiconductor substrate SUB is etched in the central portion (Center) using the first mask M1 and the second mask M1 as masks. Specifically, a dry etching process is performed on the central portion (Center) of the upper surface of the semiconductor substrate SUB using the first mask M1 having the opening MO as a mask. When etching using the first mask M1 as a mask, the semiconductor substrate SUB may be etched using plasma. In this manner, a portion of the trench TR is formed in the semiconductor substrate SUB. As will be described later, it is preferable that the etching depth of the portion of the trench TR has a difference Dif. On the other hand, the semiconductor substrate SUB is not etched in the peripheral portion (Edge) of the upper surface because it is covered by the second mask M2.

[0029] Next, as shown in FIG. 8, the second mask M2 is removed. For example, the second mask M2 including the resist pattern is removed by ashing. Next, the semiconductor substrate SUB is etched in the central portion (Center) and the peripheral portion (Edge) using the first mask M1 having the opening MO as a mask. Specifically, for example, a dry etching process is performed to form trenches TR in the semiconductor substrate SUB. When forming the trenches TR, the semiconductor substrate SUB may be etched using plasma. Thereafter, the first mask M1 including the silicon oxide film or the like may be removed by wet etching using a solution including hydrofluoric acid or the like.

[0030] In the manufacturing method of the semiconductor device 1 of the first embodiment, when forming the trenches TR, the central portion (Center) is first etched using the second mask M2 that covers the peripheral portion (Edge). This allows the trenches TR in the central portion (Center) to be pre-etched to a depth equal to the difference (Dif) described above. Then, the entire upper surface of the semiconductor substrate SUB, including the central portion (Center) and the peripheral portion (Edge), is etched. This allows the depth of the trenches TR to be uniform within the plane of the upper surface of the semiconductor substrate SUB. This improves the yield of the semiconductor device 1 and the reliability of the semiconductor device 1.

[0031] <Applications other than trenches> In the manufacturing method of the semiconductor device 1 of this embodiment, the etching of the semiconductor substrate SUB is not limited to etching for forming trenches TR. For example, it may be applied to etching for forming structures other than trenches TR, such as impurity regions of a superjunction. In the following <Method of dividing the first region and the second region>, the etching depth is described as being not limited to the depth of the trenches TR. Therefore, the etching depth includes the depth of the trenches TR, but is not limited to the depth of the trenches TR.

[0032] <Method of dividing the first and second areas> Next, a method for dividing the first region 100C and the second region 100E will be described. In the comparative example and embodiment 1 described above, the first region 100C includes a center portion (Center) of the upper surface of the semiconductor substrate SUB, and the second region 100E includes an outer peripheral portion (Edge) of the upper surface of the semiconductor substrate SUB. However, this is not limited to this. The first region 100C and the second region 100E may be divided using the following method for dividing the first region 100C and the second region 100E. Therefore, depending on the conditions, the first region 100C may include a portion of the upper surface of the semiconductor substrate SUB other than the center portion (Center), and the second region 100E may include a portion of the upper surface of the semiconductor substrate SUB other than the outer peripheral portion (Edge).

[0033] The method for manufacturing a semiconductor device according to this embodiment further includes the steps of acquiring an in-plane distribution of etching depth and dividing the semiconductor substrate into a first region 100C and a second region 100E. The step of acquiring the in-plane distribution of etching depth acquires an in-plane distribution of etching depth on the upper surface of the test semiconductor substrate SUBT when the test semiconductor substrate SUBT, which contains the same material as the semiconductor substrate SUB, is etched using the first mask M1. The step of dividing the semiconductor substrate into the first region 100C and the second region 100E divides the semiconductor substrate into the first region 100C and the second region 100E based on the acquired in-plane distribution.

[0034] The step of acquiring the in-plane distribution of etching depth may include a step of replacing the semiconductor substrate SUB in the comparative example with a test semiconductor substrate SUBT. In the following, the semiconductor substrate SUB in FIGS. 2 to 5 will be described as being replaced with the test semiconductor substrate SUBT. First, as shown in FIG. 2, the test semiconductor substrate SUBT is prepared. The test semiconductor substrate SUBT contains the same material as the semiconductor substrate SUB.

[0035] Next, as shown in Figures 3 and 4, a first mask M1 is formed on the upper surface of the test semiconductor substrate SUBT. Next, as shown in Figure 5, the test semiconductor substrate SUBT is etched using the first mask M1. Next, the etching depths at a plurality of positions on the upper surface of the etched test semiconductor substrate SUBT are obtained. For example, the etching depths at a plurality of positions may be obtained by OCD (Optical Critical Dimension) measurement.

[0036] When dividing the first region 100C and the second region 100E, for example, a threshold value of the etching depth may be set. The portion with an etching depth shallower than the threshold may be divided into the first region 100C, and the portion with an etching depth equal to or greater than the threshold may be divided into the second region 100E.

[0037] 5, the method may further include a step of acquiring a difference Dif between the etching depth of the sectioned first region 100C (e.g., a center portion) and the etching depth of the sectioned second region 100E (e.g., an edge portion). The difference Dif may be the difference Dif between the average value of the first region 100C and the average value of the second region 100E, or another index may be used, such as the difference Dif between the central value of the first region 100C and the central value of the second region 100E. As shown in FIG. 7, in the step of etching the semiconductor substrate SUB in the first region 100C, the semiconductor substrate SUB may be etched based on the acquired difference Dif.

[0038] In this way, by obtaining the in-plane distribution of etching depth in advance using a test semiconductor substrate SUBT containing the same material as the semiconductor substrate SUB, it is possible to optimize the division of the first region 100C and the second region 100E. Therefore, it is possible to make the etching depth of the first region 100C and the second region 100E uniform. This improves the yield of the semiconductor device 1 and the reliability of the semiconductor device 1.

[0039] Furthermore, since the difference Dif between the etching depth of the first region 100C and the etching depth of the second region 100E can be obtained in advance, the depth of the extra etching performed on the first region 100C can be optimized.

[0040] <Embodiment 2> Next, a description will be given of the semiconductor device of embodiment 2. First, the configuration of the semiconductor device will be described, and then the method for manufacturing the semiconductor device will be described.

[0041] <Configuration of semiconductor device> 9 and 10 are plan views illustrating a semiconductor device 2 according to a second embodiment. FIG. 11 is a cross-sectional view illustrating the semiconductor device 2 according to the second embodiment, showing cross sections AA and BB of FIG. 10. As shown in FIGS. 9 and 10, the semiconductor device 2 according to this embodiment includes a MOSFET with a trench gate structure as a semiconductor element. The semiconductor device 2 has a split-gate structure including a gate electrode GE and a field plate electrode FP. The semiconductor devices 2 in the first region 100C (e.g., the center portion) and the second region 100E (e.g., the peripheral portion) of the semiconductor substrate SUB have the same configuration. Therefore, the figures shown in FIG. 9 and subsequent figures illustrate either the semiconductor device 2 in the first region 100C (e.g., the center portion) or the second region 100E (e.g., the peripheral portion).

[0042] Fig. 9 mainly shows a wiring pattern formed above a semiconductor substrate SUB. Fig. 10 shows a structure below the wiring pattern shown in Fig. 9. Specifically, Fig. 10 shows the structure of a trench gate formed in the semiconductor substrate SUB.

[0043] As shown in FIG. 9 , most of the upper surface of the semiconductor device 2 is covered with a source electrode (fixed potential supply wiring) SE. The gate wiring GW is provided along the outer periphery of the semiconductor device 2 and surrounds the source electrode SE in a plan view. Although not shown here, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. Openings are provided in parts of the protective film, and the source electrode SE and gate wiring GW exposed in the openings become source pads SP and gate pads GP. External connection members such as wire bonding or clips (copper plates) are connected to the source pads SP and gate pads GP, thereby electrically connecting the semiconductor device 2 to another semiconductor chip or a wiring board.

[0044] The semiconductor device 2 also includes a region 1A, and regions 2A and 2A' that surround the region 1A in a plan view. The region 1A is a cell region in which main semiconductor elements such as multiple MOSFETs are formed. The regions 2A and 2A' are peripheral regions used for connecting the gate electrode GE to the gate wiring GW, etc. The structure of the region 2A' is the inverted structure of the region 2A in the drawing.

[0045] 10, a plurality of trenches TR extend in the Y-axis direction and are adjacent to each other in the X-axis direction. Inside the trenches TR, a field plate (fixed potential electrode) electrode FP is formed at the bottom of the trenches TR, and a gate electrode GE is formed at the top of the trenches TR. Therefore, in the figure, the gate electrode GE is exposed. The field plate electrode FP and the gate electrode GE extend in the Y-axis direction along the trenches TR.

[0046] A part of the field plate electrode FP forms a contact portion FPa. The field plate electrode FP constituting the contact portion FPa is formed inside the trench TR in region 1A not only in the lower portion of the trench TR but also in the upper portion of the trench TR. Therefore, in the figure, the contact portion FPa is exposed.

[0047] The gate electrode GE is divided into the region 2A side and the region 2A' side by the contact portion FPa. However, the gate electrode GE includes a connecting portion GEa. The connecting portion GEa connects the gate electrode GE on the region 2A side to the gate electrode GE on the region 2A' side inside the trench TR in which the contact portion FPa is formed. The connecting portion GEa is also formed on both side surfaces of the contact portion FPa in the X direction via the insulating film IF2.

[0048] The cross-sectional structure of the semiconductor device 2 will be described below with reference to Fig. 11. As shown in Fig. 11, the semiconductor device 2 includes a semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the following description, the stacked body including an n-type silicon substrate and an n-type semiconductor layer will also be considered as the semiconductor substrate SUB.

[0049] A plurality of trenches TR are formed in the semiconductor substrate SUB, each reaching a predetermined depth from the upper surface of the semiconductor substrate SUB. Inside the trenches TR, a field plate electrode FP is formed at the bottom of the trenches TR with an insulating film IF1 interposed therebetween. The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1. Furthermore, a gate insulating film GI is formed on the semiconductor substrate SUB inside the trenches TR.

[0050] A gate electrode GE is formed inside the trench TR above the trench TR. The gate electrode GE is electrically insulated from the field plate electrode FP by an insulating film IF2 and is also electrically insulated from the semiconductor substrate SUB by a gate insulating film GI. The gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB, with the gate insulating film GI and insulating film IF2 interposed therebetween.

[0051] The upper surface of the gate electrode GE is slightly recessed from the upper surface of the semiconductor substrate SUB. An insulating film IF3 is formed on part of the upper surface of the gate electrode GE so as to be in contact with the gate insulating film GI.

[0052] The gate electrode GE and the field plate electrode FP include, for example, a polycrystalline silicon film doped with n-type impurities. The insulating films IF1, IF2, IF3, and gate insulating film GI include, for example, a silicon oxide film. The thickness of the insulating film IF1 is greater than the thickness of each of the insulating films IF2, IF3, and gate insulating film GI.

[0053] A p-type body region PB is formed in the semiconductor substrate SUB on the upper surface side thereof so as to be shallower than the trench TR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0054] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. The drain electrode DE includes, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated.

[0055] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL may include, for example, a silicon oxide film. The interlayer insulating film IL may be a stacked film of a thin silicon oxide film and a thick silicon oxide film containing phosphorus (PSG: Phospho Silicate Glass film).

[0056] A hole CH1 is formed in the interlayer insulating film IL, the source region NS, and the body region PB. A high-concentration region PR is formed in the body region PB at the bottom of the hole CH1. The high-concentration region PR has a higher impurity concentration than the body region PB.

[0057] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is embedded in the hole CH1. The source electrode SE is electrically connected to the source region NS, the body region PB, and the heavily doped region PR. The source electrode SE supplies a source potential (fixed potential) to these regions.

[0058] 10, the gate electrode GE includes a first end portion on the region 2A side and a second end portion on the region 2A' side in the Y direction. A hole CH2 is formed in the interlayer insulating film IL. The hole CH2 on the region 2A side is formed so as to overlap the first end portion of the gate electrode GE in a planar view. The hole CH2 on the region 2A' side is formed so as to overlap the second end portion of the gate electrode GE in a planar view.

[0059] The first end of the gate electrode GE is a portion of the gate electrode GE where the hole CH2 of the region 2A is provided and adjacent to the body region PB where the source region NS is not formed. Similarly, the second end of the gate electrode GE is a portion of the gate electrode GE where the hole CH2 of the region 2A' is provided and adjacent to the body region PB where the source region NS is not formed.

[0060] A gate wiring GW is formed on the interlayer insulating film IL. The gate wiring GW is buried inside the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE. The gate wiring GW supplies a gate potential to the gate electrode GE.

[0061] 11, a part of the field plate electrode FP forms a contact portion FPa of the field plate electrode FP. The contact portion FPa is formed not only in the lower portion of the trench TR but also in the upper portion of the trench TR, inside the trench TR located between the gate electrode GE on the region 2A side (first end side) and the gate electrode GE on the region 2A' side (second end side).

[0062] Furthermore, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. That is, the position of the upper surface of the insulating film IF1 in the AA cross section is located at a predetermined depth from the upper surface of the semiconductor substrate SUB. The position of the upper surface of the insulating film IF1 in the BB cross section is located at a predetermined depth from the upper surface of the semiconductor substrate SUB. Furthermore, the position of the upper surface of the contact portion FPa is higher than the position of the upper surface of the semiconductor substrate SUB, and is located at a predetermined height from the upper surface of the semiconductor substrate SUB.

[0063] The coupling portion GEa is formed on both side surfaces of the contact portion FPa in the X-axis direction via an insulating film IF2. The coupling portion GEa also extends in the Y-axis direction and connects the gate electrode GE on the region 2A side (first end side) to the gate electrode GE on the region 2A' side (second end side). The gate electrode GE and the coupling portion GEa include an integrated n-type polycrystalline silicon film. Therefore, the gate potential is also supplied to the coupling portion GEa from the gate wiring GW. The coupling portion GEa is also covered with an insulating film IF3.

[0064] A hole CH3 is formed in the interlayer insulating film IL. The hole CH3 is formed so as to overlap the contact portion FPa in a plan view. A source electrode SE is buried inside the hole CH3. The source electrode SE is electrically connected to the field plate electrode FP and supplies a source potential to the field plate electrode FP.

[0065] The source electrode SE and the gate wiring GW may include, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film may include, for example, a titanium nitride film, and the conductive film may include, for example, an aluminum film.

[0066] The source electrode SE and the gate wiring GW may include a plug layer filling the holes CH1 to CH3 and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer includes the barrier metal film and the conductive film. The plug layer includes a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0067] <Method of manufacturing a semiconductor device> 12 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiment 2, showing cross sections AA and BB in FIG. 10. As shown in FIG. 12, a semiconductor substrate SUB having an upper surface and a lower surface and an n-type drift region NV is prepared. Next, a trench TR is formed in the semiconductor substrate SUB. The trench TR is formed by the method of embodiment 1. The semiconductor device 2 including the cross sections AA and BB may be a semiconductor device 2 in the center portion (Center) or a semiconductor device 2 in the peripheral portion (Edge). Note that, although it is preferable not to separate the first region 100C and the second region 100E within the same semiconductor device 2 (semiconductor chip), separation is not excluded.

[0068] As shown in FIG. 13, for example, by performing a thermal oxidation process, an insulating film IF1 is formed on the semiconductor substrate SUB, including the inside of the trench TR. The insulating film IF1 includes, for example, a silicon oxide film. The insulating film IF1 may be a stacked film of a thin silicon oxide film formed by the thermal oxidation process and a thick silicon oxide film formed by a CVD method. Next, a conductive film CF1 is formed on the semiconductor substrate SUB by, for example, a CVD method so as to fill the inside of the trench TR via the insulating film IF1. The conductive film CF1 includes, for example, an n-type polycrystalline silicon film.

[0069] 14, the conductive film CF1 formed outside the trench TR is removed by polishing using a CMP (Chemical Mechanical Polishing) method. In this way, the field plate electrode FP is formed so as to fill the inside of the trench TR via the insulating film IF1.

[0070] As shown in Figure 15, a portion of the field plate electrode FP is selectively recessed (cross section AA) so that a portion of the field plate electrode FP remains as the contact portion FPa (cross section BB). First, a resist pattern RP1 is formed to selectively cover the region that will become the contact portion FPa. Next, dry etching is performed using the resist pattern RP1 as a mask. This selectively recesses the field plate electrode FP other than the contact portion FPa.

[0071] 16 and 17, the insulating film IF1 is recessed inside the trench TR so that the position of its upper surface is lower than the position of the upper surface of the field plate electrode FP. First, as shown in FIG. 16, using the resist pattern RP1 as a mask, wet etching is performed using, for example, a solution containing hydrofluoric acid. As a result, the insulating film IF1 on the semiconductor substrate SUB is removed except for the periphery of the contact portion FPa, and the insulating film IF1 inside the trench TR is recessed. Next, the resist pattern RP1 is removed by ashing.

[0072] 17, the entire semiconductor substrate SUB is subjected to a wet etching process using, for example, a solution containing hydrofluoric acid. As a result, the insulating film IF1 on the semiconductor substrate SUB is removed around the contact portion FPa. The insulating film IF1 formed on the side surface of the field plate electrode FP is receded, and the upper portion of the field plate electrode FP is exposed.

[0073] At this point, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. Moreover, by removing the insulating film IF1 on the semiconductor substrate SUB, the position of the upper surface of the contact portion FPa is higher than the position of the upper surface of the semiconductor substrate SUB.

[0074] By creating a step between the upper surface of the contact portion FPa and the upper surface of the insulating film IF1, the connecting portion GEa described below can be easily processed into a sidewall shape, and the connecting portion GEa can be easily left on both side surfaces of the contact portion FPa.

[0075] 18, a gate insulating film GI including, for example, a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the trench TR by performing a thermal oxidation process. By this thermal oxidation process, an insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1.

[0076] Next, on the field plate electrode FP that has been set back in the process of Fig. 15, a conductive film CF2 is formed on the semiconductor substrate SUB, including the inside of the trench TR, by, for example, a CVD method, so as to fill the inside of the trench TR (cross section AA). Here, the conductive film CF2 is also formed inside the trench TR in which the contact portion FPa is formed (cross section BB). The conductive film CF2 includes, for example, an n-type polycrystalline silicon film.

[0077] 19, anisotropic dry etching is performed on the conductive film CF2 to remove the conductive film CF2 formed outside the trench TR and form a gate electrode GE inside the trench TR (cross section AA). By this anisotropic dry etching, inside the trench TR in which the contact portion FPa is formed, the conductive film CF2 is processed into a sidewall shape as a connecting portion GEa, and the connecting portion GEa is formed on both side surfaces of the contact portion FPa via the insulating film IF2 as part of the gate electrode GE (cross section BB).

[0078] In order to completely remove the conductive film CF2 outside the trench TR, the anisotropic dry etching process is performed by over-etching, so the position of the upper surface of the gate electrode GE is slightly lower than the position of the upper surface of the semiconductor substrate SUB (AA cross section).

[0079] 20, an insulating film IF3 is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR. The insulating film IF3 may include, for example, a silicon oxide film or a silicon nitride film.

[0080] 21, an anisotropic dry etching process is performed on the insulating film IF3. As a result, the insulating film IF3 is left on the upper surface of part of the gate electrode GE so as to be in contact with the gate insulating film GI (AA cross section), and the coupling portion GEa is covered with the insulating film IF3 (BB cross section).

[0081] As shown in FIG. 22, first, a p-type body region PB is formed in the semiconductor substrate SUB by introducing, for example, boron (B) into the upper surface side of the semiconductor substrate SUB by ion implantation. The body region PB is formed to be shallower than the trench TR. Next, after covering the periphery of the contact portion FPa with a resist pattern, an n-type source region NS is formed in the body region PB by introducing, for example, arsenic (As) into the body region PB by ion implantation. Next, the resist pattern is removed by ashing. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0082] Before the ion implantation of the source region NS and the body region PB, a thin silicon oxide film may be formed as a through film on the semiconductor substrate SUB. This through film may be removed after the ion implantation, or may be left as a part of the interlayer insulating film IL.

[0083] 23, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR. The interlayer insulating film IL may include, for example, a silicon oxide film. The interlayer insulating film IL may be a laminated film of a thin silicon oxide film formed by a CVD method and a PSG film formed by a coating method.

[0084] 24 and 25, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Although hole CH2 is not shown here, hole CH2 is formed in the same step as the step of forming hole CH3.

[0085] 24, a resist pattern RP2 having a pattern that opens the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, a dry etching process is performed using the resist pattern RP2 as a mask to form a hole CH1 in the interlayer insulating film IL, the source region NS, and the body region PB. The bottom of the hole CH1 is located in the body region PB.

[0086] Next, for example, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by ion implantation to form a p-type high concentration region PR. Thereafter, the resist pattern RP2 is removed by ashing.

[0087] Next, as shown in FIG. 25, a resist pattern RP3 is formed on the interlayer insulating film IL, the resist pattern RP3 having a pattern that opens over the contact portion FPa, a first end portion of the gate electrode GE on the region 2A side, and a second end portion of the gate electrode GE on the region 2A' side. Next, a dry etching process is performed using the resist pattern RP3 as a mask, thereby forming holes CH3 and CH2 in the interlayer insulating film IL. The hole CH3 is formed so as to overlap the contact portion FPa in a planar view. The hole CH2 is formed so as to overlap the first end portion and the second end portion in a planar view. Thereafter, the resist pattern RP3 is removed by an ashing process. Note that the process of forming the hole CH1 and the process of forming the holes CH2 and CH3 may be performed in any order.

[0088] 26, a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL. First, a laminated film made of, for example, a barrier metal film including a titanium nitride film and a conductive film including, for example, an aluminum film is formed on the interlayer insulating film IL by sputtering or CVD. Next, the laminated film is patterned to form the source electrode SE and the gate wiring GW.

[0089] The gate wiring GW is buried in the hole CH2 and electrically connected to the gate electrode GE. The source electrode SE is buried in the holes CH1 and CH3 and electrically connected to the source region NS, the body region PB, the heavily doped region PR, and the field plate electrode FP.

[0090] Next, although not shown here, a protective film including, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Parts of the protective film are opened to expose the regions of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0091] Thereafter, the semiconductor device 2 shown in FIG. 11 is manufactured through the following steps. First, the lower surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface of the semiconductor substrate SUB by sputtering.

[0092] According to this embodiment, the depth of the trenches TR of the MOSFET having a split gate structure can be made uniform, thereby improving the yield of the semiconductor device 2 and improving the reliability of the semiconductor device 2.

[0093] The invention made by the present inventor has been specifically described above based on the Comparative Example and Embodiments 1 and 2. However, the present invention is not limited to the Comparative Example and Embodiments 1 and 2, and various modifications are possible without departing from the spirit of the invention. For example, an appropriate combination of the configurations of the Comparative Example and Embodiments 1 and 2 is also within the scope of the technical concept of the embodiments. Furthermore, the following configurations are also within the scope of the technical concept of the embodiments.

[0094] (Appendix 1) (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate and extend in a first direction in a plan view; (c) after the step (b), forming a first insulating film inside the trench; (d) after the step (c), forming a field plate electrode so as to fill the trench with the first insulating film therebetween; (e) after the step (d), selectively recessing a portion of the field plate electrode so that another portion of the field plate electrode is left as a contact portion; (f) after the step (e), recessing the first insulating film so that the position of the upper surface of the first insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (g) after the step (f), forming a gate insulating film on the semiconductor substrate inside the trench and forming a second insulating film on the upper surface and side surfaces of the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the field plate electrode recessed in the step (e) so as to fill the inside of the trench; (i) after the step (h), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench; (j) after the step (i), forming a first hole, a second hole, and a third hole in the interlayer insulating film; (k) after the step (j), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film; Equipped with the gate electrode includes a first end in a first direction and a second end located on the opposite side to the first end in the first direction; the contact portion is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end portion in a plan view, the third hole is formed so as to overlap the contact portion in a plan view, the gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode; the source electrode is embedded in the third hole and is electrically connected to the field plate electrode; In the step (h), a coupling portion that connects the gate electrode on the first end side and the gate electrode on the second end side is formed as a part of the gate electrode inside the trench in which the contact portion is formed, The step (b) forming a first mask covering a first region and a second region on the first surface; patterning the first mask in the first region and the second region; forming a second mask covering the patterned first mask; patterning a second mask to expose the first region of the first mask and to cover the second region of the first mask; Etching the semiconductor substrate in the first region using the patterned first mask and the patterned second mask as masks; removing the second mask; Etching the semiconductor substrate in the first region and the second region using the patterned first mask as a mask; having A method for manufacturing a semiconductor device. (Appendix 2) 10. The method for manufacturing a semiconductor device according to claim 1, the contact portion and the coupling portion each extend in the first direction; A method for manufacturing a semiconductor device, wherein the coupling portion is formed on a side surface of the contact portion via the second insulating film in a second direction that intersects the first direction in a plan view. (Appendix 3) In the method for manufacturing a semiconductor device according to Supplementary Note 2, The step (h) (h1) forming a conductive film on a semiconductor substrate including the inside of the trench; (h2) performing an anisotropic etching process on the conductive film to form the gate electrode on the field plate electrode recessed in the step (e), and to form the coupling portion on a side surface of the contact portion via the second insulating film; The method for manufacturing a semiconductor device comprising the steps of: (Appendix 4) 4. The method for manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein the conductive film is made of a polycrystalline silicon film. (Appendix 5) 10. The method for manufacturing a semiconductor device according to claim 1, (l) after the step (h) and before the step (i), forming a body region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate so as to be shallower than the trench; (m) forming a source region of the first conductivity type in the body region after the step (l) and before the step (i); (n) forming fourth holes in the interlayer insulating film, the source region, and the body region after the step (i) and before the step (k); (o) after step (k), forming a drain electrode below the lower surface of the semiconductor substrate; Further provided with the source electrode is embedded in the fourth hole and is electrically connected to the source region and the body region. (Appendix 6) 10. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the gate wiring is in direct contact with at least one of the first end portion and the second end portion. (Appendix 7) 10. The method for manufacturing a semiconductor device according to claim 1, the gate electrode is electrically insulated from the field plate electrode by the second insulating film, and is also electrically insulated from the semiconductor substrate by the gate insulating film. [Explanation of symbols]

[0095] 1, 2, 101 Semiconductor device 100a Page 1 100b 2nd side 100C 1st area 100E 2nd area CF1 conductive film CH1, CH2, CH3 holes DE drain electrode FP field plate electrode FPa contact part GE gate electrode GEa connection part GI gate insulating film GP Gate Pad GW Gate wiring HM 1st mask material IF1, IF2, IF3 insulating films IL Interlayer insulating film M1 1st Mask M2 Second Mask M3 3rd Mask MO opening ND drain region NS Source Region NV drift region PB body region PR high concentration area RP1, RP2, RP3 resist patterns SE source electrode SP sauce pad SUB Semiconductor substrate SUBT Test Semiconductor Substrate TR Trench

Claims

1. providing a semiconductor substrate having an upper surface and a lower surface; forming a first mask having a plurality of openings on an upper surface thereof, the first mask being divided into a first region and a second region; forming a second mask that exposes a portion of the first mask that is located in the first region and covers a portion of the first mask that is located in the second region; Etching the semiconductor substrate in the first region using the first mask and the second mask as a mask; removing the second mask; Etching the semiconductor substrate in the first region and the second region using the first mask as a mask; A method for manufacturing a semiconductor device comprising:

2. the first region includes a central portion of the top surface; The second region includes an outer periphery of the upper surface. The method for manufacturing a semiconductor device according to claim 1 .

3. a step of obtaining an in-plane distribution of etching depth on the upper surface of a test semiconductor substrate when the test semiconductor substrate contains the same material as the semiconductor substrate and is etched using the first mask; dividing the first region and the second region based on the in-plane distribution; Furthermore, The method for manufacturing a semiconductor device according to claim 1 .

4. The step of acquiring the in-plane distribution includes: providing the test semiconductor substrate; forming the first mask on the upper surface; Etching the test semiconductor substrate using the first mask as a mask; obtaining etch depths at a plurality of locations on the top surface of the etched test semiconductor substrate; Including, The method for manufacturing a semiconductor device according to claim 3 .

5. The method further includes a step of obtaining a difference between the etching depth of the divided first region and the etching depth of the divided second region, In the step of etching the semiconductor substrate in the first region, Etching the semiconductor substrate based on the obtained difference. The method for manufacturing a semiconductor device according to claim 3 .

6. In the step of etching the semiconductor substrate in the first region and the step of etching the semiconductor substrate in the first region and the second region, Etching the semiconductor substrate using a plasma; The method for manufacturing a semiconductor device according to claim 5 .

7. In the step of forming the first mask, the opening for forming a trench is patterned in the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1 .

8. the first mask includes a hard mask; the second mask includes photoresist; The method for manufacturing a semiconductor device according to claim 1 .

9. The step of forming the first mask includes: forming a first mask material on the upper surface; forming a third mask material on the first mask material; exposing the third mask material to light in a portion corresponding to the opening or a portion other than the opening; forming a third mask by removing a portion of the third mask material corresponding to the opening and leaving a portion other than the opening; forming the first mask by etching the first mask material using the third mask as a mask; removing the third mask; Including, The method for manufacturing a semiconductor device according to claim 1 .

10. The step of forming the second mask includes: forming a second mask material on the first mask; exposing the second mask material to light in a portion corresponding to the first region or a portion corresponding to the second region; forming a second mask by removing a portion of the second mask material corresponding to the first region and leaving a portion of the second mask material corresponding to the second region; Including, The method for manufacturing a semiconductor device according to claim 1 .

11. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate and extend in a first direction in a plan view; (c) after the step (b), forming a first insulating film inside the trench; (d) after the step (c), forming a field plate electrode so as to fill the trench with the first insulating film therebetween; (e) after the step (d), selectively recessing a portion of the field plate electrode so that another portion of the field plate electrode is left as a contact portion; (f) after the step (e), recessing the first insulating film so that the position of the upper surface of the first insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (g) after the step (f), forming a gate insulating film on the semiconductor substrate inside the trench and forming a second insulating film on an upper surface and a side surface of the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the field plate electrode recessed in the step (e) so as to fill the inside of the trench; (i) after the step (h), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench; (j) after the step (i), forming a first hole, a second hole, and a third hole in the interlayer insulating film; (k) after the step (j), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film; Equipped with the gate electrode includes a first end in a first direction and a second end located on the opposite side to the first end in the first direction; the contact portion is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end in a plan view, the third hole is formed to overlap the contact portion in a plan view, the gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode; the source electrode is embedded in the third hole and is electrically connected to the field plate electrode; In the step (h), a coupling portion that connects the gate electrode on the first end side and the gate electrode on the second end side is formed as a part of the gate electrode inside the trench in which the contact portion is formed, The step (b) comprises: forming a first mask having a plurality of openings on an upper surface of the semiconductor substrate divided into a first region and a second region; forming a second mask that exposes a portion of the first mask that is located in the first region and covers a portion of the first mask that is located in the second region; Etching the semiconductor substrate in the first region using the first mask and the second mask as a mask; removing the second mask; Etching the semiconductor substrate in the first region and the second region using the first mask as a mask; removing the first mask; having A method for manufacturing a semiconductor device.

12. the first region includes a central portion of the top surface; The second region includes an outer periphery of the upper surface. The method for manufacturing a semiconductor device according to claim 11 .

13. a step of obtaining an in-plane distribution of etching depth on the upper surface of a test semiconductor substrate when the test semiconductor substrate contains the same material as the semiconductor substrate and is etched using the first mask; dividing the first region and the second region based on the in-plane distribution; Furthermore, The method for manufacturing a semiconductor device according to claim 11 .

14. The step of acquiring the in-plane distribution includes: providing the test semiconductor substrate; forming the first mask on the upper surface; Etching the test semiconductor substrate using the first mask as a mask; obtaining etch depths at a plurality of locations on the top surface of the etched test semiconductor substrate; Including, The method for manufacturing a semiconductor device according to claim 13.

15. The method further includes a step of obtaining a difference between the etching depth of the divided first region and the etching depth of the divided second region, In the step of etching the semiconductor substrate in the first region, Etching the semiconductor substrate based on the obtained difference. The method for manufacturing a semiconductor device according to claim 13.

16. In the step of etching the semiconductor substrate in the first region and the step of etching the semiconductor substrate in the first region and the second region, Etching the semiconductor substrate using a plasma; The method for manufacturing a semiconductor device according to claim 15.

17. In the step of forming the first mask, the opening for forming a trench is patterned in the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 11 .

18. the first mask includes a hard mask; the second mask includes photoresist; The method for manufacturing a semiconductor device according to claim 11 .

19. The step of forming the first mask includes: forming a first mask material on the upper surface; forming a third mask material on the first mask material; exposing the third mask material to light in a portion corresponding to the opening or a portion other than the opening; forming a third mask by removing a portion of the third mask material corresponding to the opening and leaving a portion other than the opening; forming the first mask by etching the first mask material using the third mask as a mask; removing the third mask; Including, The method for manufacturing a semiconductor device according to claim 11 .

20. The step of forming the second mask includes: forming a second mask material on the first mask; exposing the second mask material to light in a portion corresponding to the first region or a portion corresponding to the second region; forming a second mask by removing a portion of the second mask material corresponding to the first region and leaving a portion of the second mask material corresponding to the second region; Including, The method for manufacturing a semiconductor device according to claim 11 .

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