Controller, target, and communication system

Abstract

To transmit clock information and data by a single signal.SOLUTION: A controller (1) includes a clock signal generation circuit (11) configured to generate a clock signal, and a first pulse signal generation circuit (12) configured to generate a first pulse signal having the same frequency as the clock signal and having one of a rising edge and a falling edge synchronized with the clock signal. The first pulse signal generator circuit is configured to adjust a timing of the other one of the rising edge and the falling edge of each cycle of the first pulse signal in accordance with content of each data of a first data transmission.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a controller, a target, and a communication system. [Background technology]

[0002] Conventionally, communication in which clock information and data are transmitted by separate signals has been known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-144020

[0004] [overview] In communications in which clock information and data are transmitted by separate signals, a first terminal connected to a first signal line transmitting a signal including clock information and a second terminal connected to a second signal line transmitting a signal including data must be provided in each of the transmitting and receiving devices. However, since an increase in the number of terminals leads to an increase in costs, it is desirable to keep the increase in the number of terminals to a minimum.

[0005] The controller disclosed herein includes a clock signal generation circuit configured to generate a clock signal, and a first pulse signal generation circuit configured to generate a first pulse signal having the same frequency as the clock signal and one of a rising edge and a falling edge synchronized with the clock signal, the first pulse signal generation circuit configured to adjust the timing of the other of the rising edge and the falling edge of each period of the first pulse signal in accordance with the content of each data of a first data transmission.

[0006] The target disclosed herein includes a first data receiving circuit configured to recognize one of a rising edge or a falling edge of a first pulse signal sent from a controller as clock information, and to recognize the content of each data of the first data reception based on the timing of the other of the rising edge or the falling edge in each cycle of the first pulse signal.

[0007] The communication system disclosed in this specification comprises a controller having the above configuration and a target having the above configuration. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a power supply system according to an embodiment. [Figure 2] FIG. 2 is a perspective view of the appearance of the sequence IC and the DC / DC converter IC. [Figure 3] FIG. 3 is a conceptual diagram showing an example of a data table stored in the nonvolatile memory. [Figure 4] FIG. 4 is a timing chart showing the case where the sequence IC transmits data to the DC / DC converter IC. [Figure 5] FIG. 5 is a timing chart showing the case where the DC / DC converter IC transmits data to the sequence IC.

[0009] [Detailed explanation] Fig. 1 is a diagram showing the configuration of a power supply system according to an embodiment. The power supply system SYS1 is configured to generate output voltages VOUT1 to VOUT3 from an input voltage VIN. The power supply system SYS1 is also a communication system configured to communicate clock information and data within the system. In this communication, open-drain IO (Input Output) signal control is performed.

[0010] The power supply system SYS1 includes a sequence IC (Integrated Circuit) 1 and DC (Direct Current) / DC converters ICs 2 to 4. In this embodiment, the number of DC / DC converters ICs is four, but may be any number other than four.

[0011] 2 is a perspective view of the appearance of the sequence IC1 and DC / DC converters IC2 to IC4. The sequence IC1 and DC / DC converters IC2 to IC4 are electronic components formed by encapsulating a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of terminals are exposed on the housing of each of the sequence IC1 and DC / DC converters IC2 to IC4. Note that the number of terminals of the sequence IC1 and DC / DC converters IC2 to IC4 and the appearance of the sequence IC1 and DC / DC converters IC2 to IC4 are merely examples.

[0012] 1, the sequence IC1 includes a clock signal generating circuit 11, a first pulse signal generating circuit 12, a control circuit 13, a nonvolatile memory 14, and terminals T11 and T12. The sequence IC1 is driven by a power supply voltage VCC applied to the terminal T11.

[0013] The clock signal generating circuit 11 generates a clock signal CLK1. The clock signal generating circuit 11 is configured by, for example, an oscillator. The clock signal CLK1 generated by the clock signal generating circuit 11 is supplied to a first pulse signal generating circuit 12 and a control circuit 13.

[0014] The first pulse signal generating circuit 12 generates a first pulse signal PLS1 from the clock signal CLK1. The first pulse signal PLS1 generated by the first pulse signal generating circuit 12 is supplied to the DC / DC converters IC2 to IC4 via a terminal T12.

[0015] The first pulse signal PLS1 has the same frequency as the clock signal CLK1 and is a signal whose rising edge is synchronized with the clock signal CLK1. The first pulse signal generation circuit 12 adjusts the timing of the falling edge of each cycle of the first pulse signal PLS1 based on instructions from the control circuit 13. More specifically, the first pulse signal generation circuit 12 adjusts the timing of the falling edge of each cycle of the first pulse signal PLS1 based on instructions from the control circuit 13 in accordance with the content of each piece of first data (data group) to be transmitted.

[0016] The control circuit 13 includes a PLL (Phase Locked Loop) circuit 131. The PLL circuit 131 generates a multiplied clock signal MCLK1 from the clock signal CLK1.

[0017] The multiplied clock signal MCLK1 is synchronized with the rising edge of the clock signal CLK1. In this embodiment, the frequency of the multiplied clock signal MCLK1 is five times the frequency of the clock signal CLK1.

[0018] The nonvolatile memory 14 nonvolatilely stores a data table shown in Fig. 3. The data table shown in Fig. 3 shows the correspondence between the number of cycles of the multiplied clock signal MCLK1 from the rising edge of the first pulse signal PLS1 at which the falling edge of the first pulse signal PLS1 appears and the contents of the data. The data table shown in Fig. 3 also shows the correspondence between the number of cycles of the multiplied clock signal MCLK1 from the rising edge of the second pulse signal PLS2 (described later) at which the falling edge of the second pulse signal PLS2 appears and the contents of the data.

[0019] In this embodiment, there are five types of data: "start condition (signal indicating the start of communication)," "high-level digital value," "low-level digital value," "stop condition (signal indicating the end of communication)," and "NON (signal indicating no data transmission from the sequence IC)." However, the number of data types is merely an example, and the content of each data type is also merely an example. The frequency of the multiplied clock signal MCLK1 is set according to the number of data types. The arrangement of "high-level digital value" and "low-level digital value" expresses addresses, sequence control content, status notification content, etc. Sequence control content includes commands, etc. Status notification content includes normal status notification, abnormal status notification, etc. The protocol of the communication method is not particularly limited.

[0020] The control circuit 13 instructs the first pulse signal generating circuit 12 on the timing of the falling edge of each period of the first pulse signal PLS1 based on the content of each data of the first data transmission (data group to be transmitted), the multiplied clock signal MCLK1, and a data table stored in the non-volatile memory 14.

[0021] The sequence IC1 configured as described above can transmit clock information (the rising edge of the first pulse signal PLS1) and data using the first pulse signal PLS1 (a single signal). Therefore, the sequence IC1 can reduce the number of terminals.

[0022] DC / DC converter IC2 has terminals T21 to T23, DC / DC converter IC3 has terminals T31 to T33, and DC / DC converter IC4 has terminals T41 to T43.

[0023] A terminal T21 of the DC / DC converter IC2, a terminal T31 of the DC / DC converter IC3, and a terminal T41 of the DC / DC converter IC4 are connected to a terminal T12 of the sequence IC1 by signal lines.

[0024] DC / DC converter IC2 converts the input voltage VIN applied to terminal T21 into an output voltage VOUT1 and outputs the output voltage VOUT1 from terminal T22. DC / DC converter IC3 converts the input voltage VIN applied to terminal T31 into an output voltage VOUT2 and outputs the output voltage VOUT2 from terminal T32. DC / DC converter IC4 converts the input voltage VIN applied to terminal T41 into an output voltage VOUT3 and outputs the output voltage VOUT3 from terminal T32.

[0025] Since the internal configurations of the DC / DC converters IC2 to IC4 are similar, the internal configuration of the DC / DC converter IC2 will be described here as a representative.

[0026] The DC / DC converter IC2 includes a conversion circuit 21, a control circuit 22, a nonvolatile memory 23, and a second pulse signal generation circuit 24.

[0027] The conversion circuit 21 converts the input voltage VIN into the output voltage VOUT1. Note that a part of the conversion circuit 21 (e.g., an inductor, an output capacitor, etc.) may be provided outside the DC / DC converter IC2. When a part of the conversion circuit 21 is provided outside the DC / DC converter IC2, for example, a switch voltage having a square wave may be output from the terminal T22 instead of the output voltage VOUT1, which is a DC voltage.

[0028] The control circuit 22 recognizes, as clock information, the rising edge of the first pulse signal PLS1 sent from the sequence IC 1. The control circuit 22 also recognizes the content of each data of the received first data (data group) based on the timing of the falling edge of each cycle of the first pulse signal PLS1.

[0029] The control circuit 22 includes a built-in PLL circuit 221. The PLL circuit 221 generates a multiplied pulse signal MPLS1 from the first pulse signal PLS1.

[0030] The multiplied pulse signal MPLS1 is synchronized with the rising edge of the first pulse signal PLS1. In this embodiment, the frequency of the multiplied pulse signal MPLS1 is five times the frequency of the first pulse signal PLS1.

[0031] The nonvolatile memory 23 nonvolatilely stores a data table shown in Fig. 3. The data table shown in Fig. 3 shows the correspondence between the data content and the number of cycles of the multiplied pulse signal MPLS1 from the rising edge of the first pulse signal PLS1 at which the falling edge of the first pulse signal PLS1 appears. The data table shown in Fig. 3 also shows the correspondence between the data content and the number of cycles of the multiplied pulse signal MPLS1 from the rising edge of the second pulse signal PLS2 at which the falling edge of the second pulse signal PLS2 appears, as will be described later.

[0032] The second pulse signal generating circuit 24 sets the second pulse signal PLS2 to a signal fixed at a HIGH level, except for the period from the end of data transmission from sequence IC1 to the start of the next data transmission from sequence IC1, and outputs the signal fixed at a HIGH level.

[0033] The control circuit 22 controls the conversion circuit 21 based on the received first data (data group). For example, if the received first data indicates that output should be stopped, the control circuit 22 stops the operation of the conversion circuit 21.

[0034] The DC / DC converter IC2 configured as described above can receive clock information (rising edges of the first pulse signal PLS1) and data in the first pulse signal PLS1 (a single signal), thereby reducing the number of terminals required for the DC / DC converter IC2.

[0035] As described above, when the first data (data group) is transmitted from the sequence IC1 and received by the DC / DC converter IC2, the waveforms of the signals are as shown in the timing chart in Fig. 4. Note that PLS1+PLS2 in Fig. 4 and Fig. 5, which will be described later, is a composite signal of the first pulse signal PLS1 and the second pulse signal PLS2, and is an actual communication signal transmitted between the terminal T12 and the terminals T23, T33, and T43.

[0036] The power supply system SYS1 is capable of bidirectional communication. That is, data can be transmitted from the DC / DC converter IC2 to the sequence IC1. The DC / DC converter IC2 can transmit data to the sequence IC1 during the period from when the sequence IC1 finishes transmitting data until the sequence IC1 starts transmitting the next data.

[0037] When data is transmitted from the DC / DC converter IC2 to the sequence IC1, the second pulse signal generating circuit 24 generates the second pulse signal PLS2 from the first pulse signal PLS1. The second pulse signal PLS2 generated by the second pulse signal generating circuit 24 is supplied to the sequence IC1 via the terminal T23.

[0038] When data is transmitted from the DC / DC converter IC2 to the sequencer IC1, the second pulse signal PLS2 has the same frequency as the first pulse signal PLS1 and is a signal whose rising edge is synchronized with the first pulse signal PLS1. The second pulse signal generating circuit 24 adjusts the timing of the falling edge of each cycle of the second pulse signal PLS2 based on instructions from the control circuit 22. More specifically, the second pulse signal generating circuit 24 adjusts the timing of the falling edge of each cycle of the second pulse signal PLS2 in accordance with the content of each piece of second data (data group) to be transmitted based on instructions from the control circuit 22.

[0039] The control circuit 13 of the sequence IC1 recognizes the content of each data of the received second data (data group) based on the timing of the falling edge of each cycle of the second pulse signal PLS2.

[0040] As described above, when the second data (data group) is transmitted from the DC / DC converter IC2 and received by the sequencer IC1, the waveforms of the signals are as shown in the timing chart of FIG.

[0041] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0042] For example, instead of a sequence IC, a PMIC (Power Management Integrated Circuit) with multiple built-in DC / DC converters may be used. Note that the DC / DC converter provided outside the PMIC and communicating with the PMIC may be either single or multiple.

[0043] The communication described in the above embodiment may be used in devices, equipment, systems, etc. other than the power supply system.

[0044] In the above embodiment, the rising edge of the first pulse signal PLS1 is synchronized with the clock signal CLK1, but the falling edge of the first pulse signal PLS1 may be synchronized with the clock signal CLK1.

[0045] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0046] The controller (1) of the present disclosure includes a clock signal generation circuit (11) configured to generate a clock signal, and a first pulse signal generation circuit (12) configured to generate a first pulse signal having the same frequency as the clock signal and one of the rising edge or the falling edge of which is synchronized with the clock signal, and the first pulse signal generation circuit is configured to adjust the timing of the other of the rising edge or the falling edge of each period of the first pulse signal according to the content of each data of a first data transmission (first configuration).

[0047] The controller of the first configuration can transmit clock information (either the rising edge or the falling edge of the first pulse signal) and data in the first pulse signal (a single signal), thereby reducing the number of terminals required for the controller.

[0048] The controller of the first configuration may be configured (second configuration) to include a second data receiving circuit (13) configured to recognize the content of each data of the second data reception based on the timing of the other of the rising edge or falling edge of each cycle of the second pulse signal sent from the target (2, 3, 4).

[0049] The targets (2, 3, 4) of the present disclosure are configured (third configuration) to include a first data receiving circuit (22), and the first data receiving circuit is configured to recognize one of the rising edge or falling edge of a first pulse signal sent from a controller (1) as clock information, and to recognize the content of each data of the first data reception based on the timing of the other of the rising edge or falling edge in each cycle of the first pulse signal.

[0050] The target in the third configuration can receive clock information and data in the first pulse signal (single signal), thereby reducing the number of terminals required for the target.

[0051] The target of the third configuration may be further provided with a multiplied pulse signal generating circuit (221) configured to generate a multiplied pulse signal synchronized with one of the rising edge or the falling edge of the first pulse signal and having a frequency that is a multiple of the first pulse signal, and the first data receiving circuit may be configured to recognize the content of each data item of the first data reception depending on the number of cycles of the multiplied pulse signal in which the other of the rising edge or the falling edge of each cycle of the first pulse signal appears from the one of the rising edge or the falling edge of the first pulse signal (fourth configuration).

[0052] The target of the third or fourth configuration may be further configured (fifth configuration) to include a second pulse signal generating circuit (24) configured to generate a second pulse signal having the same frequency as the first pulse signal and one of the rising edge or the falling edge of which is synchronized with the first pulse signal, and the second pulse signal generating circuit is configured to adjust the timing of the other of the rising edge or the falling edge of each period of the second pulse signal depending on the content of each data of the second data transmission.

[0053] The communication system (SYS1) of the present disclosure has a configuration (sixth configuration) including the controller of the first or second configuration and any one of the third to fifth targets.

[0054] In the communication system of the sixth configuration, the types of data may include sequence control content and status notification content (seventh configuration). [Explanation of symbols]

[0055] 1 Sequence IC 11 Clock signal generation circuit 12 First pulse signal generating circuit 13 Control circuit 131 PLL circuit 14 Non-volatile memory 2~4 DC / DC converter ICs 21 Conversion circuit 22 Control circuit 221 PLL circuit 23 Non-volatile memory 24 Second pulse signal generating circuit SYS1 Power System T11, T12, T21 to T23, T31 to T33, T41 to T43 terminals

Claims

1. a clock signal generation circuit configured to generate a clock signal; a first pulse signal generating circuit configured to generate a first pulse signal having the same frequency as the clock signal and one of a rising edge and a falling edge of which is synchronized with the clock signal; Equipped with The first pulse signal generating circuit is configured to adjust the timing of the other of the rising edge or the falling edge of each period of the first pulse signal depending on the content of each data of the first data transmission.

2. 2. The controller according to claim 1, further comprising a second data receiving circuit configured to recognize the content of each data of the second data reception based on the timing of the other of the rising edge or falling edge of each period of the second pulse signal sent from the target.

3. a first data receiving circuit; The target is configured such that the first data receiving circuit recognizes one of the rising edge or falling edge of the first pulse signal sent from the controller as clock information, and recognizes the content of each data of the first data reception based on the timing of the other of the rising edge or falling edge of each period of the first pulse signal.

4. a multiplied pulse signal generating circuit configured to generate a multiplied pulse signal synchronized with one of the rising edge or the falling edge of the first pulse signal and having a frequency that is a multiple of the first pulse signal; 4. The target of claim 3, wherein the first data receiving circuit is configured to recognize the content of each data of the first data reception depending on the number of periods of the multiplied pulse signal in which the other of the rising edge or the falling edge of each period of the first pulse signal appears from the rising edge or the falling edge of the first pulse signal.

5. a second pulse signal generating circuit configured to generate a second pulse signal having the same frequency as the first pulse signal and one of a rising edge and a falling edge of which is synchronized with the first pulse signal; 5. The target according to claim 3 or claim 4, wherein the second pulse signal generating circuit is configured to adjust the timing of the other of the rising edge or the falling edge of each period of the second pulse signal depending on the content of each data of the second data transmission.

6. A communication system comprising: a controller according to claim 1; and a target according to claim 3.

7. 7. The communication system according to claim 6, wherein the types of data include sequence control content and status notification content.

Images