Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of reducing a chip area, and to provide a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device according to an embodiment includes a first chip having a first substrate in which a first transistor is formed, and a second chip provided above the first chip and having a second substrate in which a second transistor is formed. The second substrate includes a first insulating film region and a second insulating film region each penetrating the second substrate. The first chip and the second chip are electrically connected via a first through via group including at least a first via and a second via each penetrating the first insulating film region, and a second through via group including at least a third via and a fourth via each penetrating the second insulating film region. The first through via group is arranged at a pitch different from that of the second through via group.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] NAND flash memory is known as a semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0420007 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-39005 [Non-patent literature]

[0004] [Non-Patent Document 1] K. Nakazawa, J. Yamamoto, S. Mori, S. Okamoto, A. Shimizu, K. Baba, N. Fujii, M. Uehara, K. Hiramatsu, H. Kumano, A. Matsumoto, K. Zaitsu, H. Ohnuma, K. Tatani, T. Hirano, and H. Iwamoto, "3D Sequential Process Integration for CMOS Image Sensor", 2021 IEEE International Electron Devices Meeting (IEDM), 2021 Summary of the Invention [Problem to be solved by the invention]

[0005] A semiconductor device and a method for manufacturing the semiconductor device that can reduce the chip area are provided. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a first chip having a first substrate on which a first transistor is formed, and a second chip provided above the first chip and having a second substrate on which a second transistor is formed. The second substrate includes a first insulating film region and a second insulating film region, each of which penetrates the second substrate. The first chip and the second chip are electrically connected via a first through via group including at least a first via and a second via that each penetrate the first insulating film region, and a second through via group including at least a third via and a fourth via that each penetrate the second insulating film region. The first through via group is arranged at a different pitch from the second through via group. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a memory system including a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a semiconductor device according to the embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the semiconductor device according to the embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a sense amplifier module included in a semiconductor device according to the embodiment. [Figure 5] FIG. 1 is a perspective view showing an example of the appearance of a semiconductor device according to an embodiment. [Figure 6] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor device according to an embodiment. [Figure 7] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array in a core region of a semiconductor device according to the embodiment. [Figure 8] FIG. 2 is a plan view showing an example of a planar layout of a memory region of a memory cell array included in a semiconductor device according to the embodiment. [Figure 9]FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure in a memory region of a memory cell array included in a semiconductor device according to the embodiment. [Figure 10] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a memory pillar included in a semiconductor device according to the embodiment. [Figure 11] FIG. 2 is a plan view showing an example of a planar layout of a contact region of a memory cell array included in a semiconductor device according to the embodiment. [Figure 12] 1 is a cross-sectional view showing an example of a cross-sectional structure in a contact region of a memory cell array included in a semiconductor device according to an embodiment. [Figure 13] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a core region of a semiconductor device according to an embodiment. [Figure 14] FIG. 1 is a plan view showing an example of a planar layout of through-vias in a memory region of a semiconductor device according to an embodiment. [Figure 15] FIG. 10 is a plan view showing another example of a planar layout of through vias in the memory region of the semiconductor device according to the embodiment. [Figure 16] FIG. 2 is a plan view showing an example of a planar layout of through-vias in a contact region of a semiconductor device according to an embodiment. [Figure 17] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a peripheral region of a semiconductor device according to an embodiment. [Figure 18] FIG. 2 is a plan view showing an example of a planar layout of through-vias in a peripheral region of a semiconductor device according to an embodiment. [Figure 19] FIG. 2 is a plan view showing an example of a planar layout of bonding pads in a peripheral region of a semiconductor device according to an embodiment. [Figure 20] FIG. 10 is a plan view showing another example of a planar layout of through vias in the peripheral region of the semiconductor device according to the embodiment. [Figure 21] FIG. 10 is a plan view showing another example of a planar layout of bonding pads in the peripheral region of the semiconductor device according to the embodiment. [Figure 22] 1 is a cross-sectional view showing an example of a cross-sectional structure of a wall region of a semiconductor device according to an embodiment. [Figure 23]FIG. 2 is a plan view showing an example of a planar layout of through-vias in a wall region of a semiconductor device according to an embodiment. [Figure 24] 1 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 26] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 27] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 28] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 29] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 30] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 31] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 32] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 33] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 34] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 35] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 36] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 37] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 38] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 39]1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 40] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 41] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 42] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 43] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device according to an embodiment during manufacturing. [Figure 44] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a core region of a semiconductor device according to a first modified example. [Figure 45] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a peripheral region of a semiconductor device according to a first modified example. [Figure 46] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a wall region of a semiconductor device according to a first modified example. [Figure 47] 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a first modified example. [Figure 48] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a semiconductor device according to a first modified example. [Figure 49] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a semiconductor device according to a first modified example. [Figure 50] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a peripheral region of a semiconductor device according to a second modification. [Figure 51] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure when a plurality of semiconductor devices according to a second modification are stacked. [Figure 52] FIG. 10 is a cross-sectional view in the XZ plane showing an example of the structure of another transistor applicable to the semiconductor devices according to the embodiment, the first modification, and the second modification. [Figure 53] 53 is a cross-sectional view of the transistor of FIG. 52 in the YZ plane. [Figure 54] FIG. 10 is a cross-sectional view in the XZ plane showing an example of the structure of another transistor applicable to the semiconductor devices according to the embodiment, the first modification, and the second modification. [Figure 55] 55 is a cross-sectional view of the transistor of FIG. 54 in the YZ plane. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate devices and methods for embodying the technical ideas of the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components are omitted as appropriate. Hatching added to plan views does not necessarily relate to the material or characteristics of the components. In this specification, components having substantially the same functions and configurations are assigned the same reference symbols. Numbers and letters added to reference symbols are used to refer to the same reference symbols and to distinguish between similar elements.

[0009] <1> Embodiment The configuration of a semiconductor device according to an embodiment will be described. The semiconductor device according to the embodiment includes memory cells and CMOS circuits for accessing the memory cells, and has a structure in which the CMOS circuits are arranged on multiple stacked substrates.

[0010] <1-1> Overall structure of semiconductor device 1 is a block diagram showing an example of the overall configuration of a memory system including a semiconductor device according to an embodiment. As shown in FIG. 1, the semiconductor device 1 is controlled by an external memory controller 2. The semiconductor device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner. The semiconductor device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and a plurality of word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0012] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals to and from the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, commands, etc. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the semiconductor device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated under the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes a block address, a page address, a column address, etc. The commands include instructions regarding various operations of the semiconductor device 1.

[0015] The sequencer 14 controls the overall operation of the semiconductor device 1. Based on the command and address information stored in the register circuit 13, the sequencer 14 executes read operations, write operations, erase operations, and the like.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc.

[0017] The row decoder module 16 is a circuit used to select a block BLK to be operated and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0018] The sense amplifier module 17 is a circuit used to transfer voltages to each bit line BL and to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0019] The combination of the semiconductor device 1 and the memory controller 2 may constitute one semiconductor device. An example of such a semiconductor device is an SD TM Examples include memory cards and solid state drives (SSDs).

[0020] <1-2> Circuit configuration of semiconductor devices The circuit configuration of the semiconductor device 1 will be described.

[0021] <1-2-1> Circuit configuration of memory cell array 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in a semiconductor device 1 according to the embodiment. FIG. 2 shows one block BLK among a plurality of blocks BLK included in the memory cell array 10. As shown in FIG. 2, the block BLK includes, for example, five string units SU0 to SU4. Select gate lines SGD0 to SGD4 and SGS and word lines WL0 to WL7 are provided for each block BLK. Bit lines BL0 to BLm and source lines SL are shared by a plurality of blocks BLK.

[0022] Each string unit SU includes multiple NAND strings NS. The multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. That is, each bit line BL is shared by NAND strings NS assigned the same column address among multiple blocks BLK. Each NAND string NS is connected between the associated bit line BL and source line SL. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select a string unit SU.

[0023] In each NAND string NS, a select transistor ST1, memory cell transistors MT7 to MT0, and a select transistor ST2 are connected in series in this order. Specifically, the drain and source of the select transistor ST1 are connected to the associated bit line BL and the drain of the memory cell transistor MT7, respectively. The drain and source of the select transistor ST2 are connected to the source of the memory cell transistor MT0 and a source line SL, respectively. The memory cell transistors MT0 to MT7 are connected in series between the select transistors ST1 and ST2.

[0024] The select gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each select gate line SGD is connected to the gates of the select transistors ST1 included in the associated string unit SU. The select gate line SGS is connected to the gates of the select transistors ST2 included in the associated block BLK. The word lines WL0 to WL7 are connected to the control gates of the memory cell transistors MT0 to MT7, respectively.

[0025] A set of multiple memory cell transistors MT connected to a common word line WL within the same string unit SU is called, for example, a "cell unit CU." For example, the storage capacity of a cell unit CU when each memory cell transistor MT stores one bit of data is defined as "one page of data." A cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored in each memory cell transistor MT.

[0026] The circuit configuration of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other configurations. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS may be designed to be any number.

[0027] <1-2-2> Circuit configuration of row decoder module 3 is a circuit diagram showing an example of the circuit configuration of the row decoder module 16 included in the semiconductor device 1 according to the embodiment. FIG. 3 shows the connection relationship between the row decoder module 16 and the driver circuit 15 and the memory cell array 10, as well as a detailed circuit configuration of the row decoder RD0. As shown in FIG. 3, each row decoder RD is connected to the driver circuit 15 via signal lines CG0 to CG7, SGDD0 to SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to the associated block BLK via word lines WL0 to WL7 and select gate lines SGS and SGD0 to SGD4.

[0028] The following describes the connection relationships between each element of the row decoder RD and the driver circuit 15 and the block BLK0, focusing on the row decoder RD0. The configuration of the other row decoders RD is the same as that of the row decoder RD0, except that the associated blocks BLK are different. The row decoder RD0 includes, for example, transistors TR0 to TR19, transfer gate lines TG and bTG, and a block decoder BD.

[0029] Each of the transistors TR0 to TR19 is a high-voltage N-type MOS transistor (hereinafter also referred to as an "HV (High-Voltage) transistor"). The drain and source of the transistor TR0 are connected to a signal line SGSD and a select gate line SGS, respectively. The drains of the transistors TR1 to TR8 are connected to signal lines CG0 to CG7, respectively. The sources of the transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. The drains of the transistors TR9 to TR13 are connected to signal lines SGDD0 to SGDD4, respectively. The sources of the transistors TR9 to TR13 are connected to select gate lines SGD0 to SGD4, respectively. The drain and source of the transistor TR14 are connected to a signal line USGS and a select gate line SGS, respectively. The drains of the transistors TR15 to TR19 are connected to a signal line USGD. The sources of the transistors TR15 to TR19 are connected to select gate lines SGD0 to SGD4, respectively. The gates of the transistors TR0 to TR13 are connected to a transfer gate line TG, and the gates of the transistors TR14 to TR19 are connected to a transfer gate line bTG.

[0030] The block decoder BD is a circuit that has the function of decoding a block address. The block decoder BD applies a predetermined voltage to each of the transfer gate lines TG and bTG based on the decoded block address. Specifically, the block decoder BD corresponding to the selected block BLK applies "H" level and "L" level voltages to the transfer gate lines TG and bTG, respectively. The block decoder BD corresponding to the unselected block BLK applies "L" level and "H" level voltages to the transfer gate lines TG and bTG, respectively. As a result, the voltages of the signal lines CG0 to CG7 are transferred to the word lines WL0 to WL7 of the selected block BLK, respectively, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are transferred to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively, and the voltages of the signal lines USGD and USGS are transferred to the select gate lines SGD and SGS of the unselected blocks BLK, respectively.

[0031] The row decoder module 16 may have other circuit configurations. For example, the number of transistors TR included in the row decoder module 16 may be changed depending on the number of wirings provided in each block BLK. The signal line CG may be called a "global word line" because it is shared among multiple blocks BLK. The word line WL may be called a "local word line" because it is provided for each block BLK. The signal lines SGDD and SGSD may be called "global transfer gate lines" because they are shared among multiple blocks BLK. The select gate lines SGD and SGS may be called "local transfer gate lines" because they are provided for each block BLK.

[0032] <1-2-3> Circuit configuration of the sense amplifier module 4 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module 17 included in the semiconductor device 1 according to the embodiment. FIG. 4 shows the circuit configuration of one sense amplifier unit SAU. As shown in FIG. 4, the sense amplifier unit SAU includes, for example, a sense amplifier unit SA, a bit line connection unit BLHU, latch circuits SDL, ADL, BDL, CDL, and XDL, and a bus LBUS. The sense amplifier unit SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are configured to be able to transmit and receive data via, for example, the bus LBUS.

[0033] The sense amplifier unit SA is a circuit used to determine data based on the voltage of the bit line BL and to apply a voltage to the bit line BL. When a control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. Each of the latch circuits SDL, ADL, BDL, CDL, and XDL is a circuit capable of temporarily holding data. The latch circuit XDL is used for inputting and outputting data DAT between the sense amplifier unit SAU and the input / output circuit 11. The latch circuit XDL can also be used as a cache memory.

[0034] The sense amplifier unit SA includes transistors TR30 to TR37, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection unit BLHU is a switch circuit that prevents the high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the circuits in the sense amplifier unit SA. The bit line connection unit BLHU includes a transistor TR38. The latch circuit SDL includes inverters IV0 and IV1, transistors TR40 and TR41, and nodes SINV and SLAT. The transistor TR30 is a P-type MOS transistor. The transistors TR31 to TR38, TR40, and TR41 are each an N-type MOS transistor. The transistor TR38 is an N-type MOS transistor (HV transistor) with a higher breakdown voltage than the N-type transistors in the sense amplifier unit SA. Hereinafter, transistors with a lower breakdown voltage than HV transistors will also be referred to as "LV (Low-Voltage) transistors."

[0035] The gate of transistor TR30 is connected to node SINV. The source of transistor TR30 is connected to the power supply line. The drain of transistor TR30 is connected to node ND1. Node ND1 is connected to the drains of transistors TR31 and TR32. The sources of transistors TR31 and TR32 are connected to nodes ND2 and SEN, respectively. Nodes ND2 and SEN are connected to the source and drain of transistor TR33, respectively. Node ND2 is connected to the drains of transistors TR34 and TR35. The source of transistor TR35 is connected to node SRC. The gate of transistor TR35 is connected to node SINV. Node SEN is connected to the gate of transistor TR36 and one electrode of capacitor CP. The source of transistor TR36 is grounded. The drain and source of transistor TR37 are connected to bus LBUS and the drain of transistor TR36, respectively. The drain of transistor TR38 is connected to the source of transistor TR34. The source of the transistor TR38 is electrically connected to the bit line BL associated with the sense amplifier unit SAU.

[0036] For example, a power supply voltage VDD is applied to the source of transistor TR30. For example, a ground voltage VSS is applied to node SRC. Control signals BLX, HLL, XXL, BLC, and STB are input to the gates of transistors TR31, TR32, TR33, TR34, and TR37, respectively. A control signal BLS is input to the gate of transistor TR38. A clock signal CLK is input to the other electrode of capacitor CP.

[0037] The input node and output node of inverter IV0 are connected to nodes SLAT and SINV, respectively. The input node and output node of inverter IV1 are connected to nodes SINV and SLAT, respectively. One end and the other end of transistor TR40 are connected to node SINV and bus LBUS, respectively. A control signal STI is input to the gate of transistor TR40. One end and the other end of transistor TR41 are connected to node SLAT and bus LBUS, respectively. A control signal STL is input to the gate of transistor TR41. Latch circuit SDL holds data at node SLAT and holds inverted data of the data held at node SLAT at node SINV.

[0038] The circuit configuration of the latch circuits ADL, BDL, CDL, and XDL is similar to that of the latch circuit SDL. For example, the latch circuit ADL holds data at a node ALAT and its inverted data at a node AINV. A control signal ATI is input to the gate of the transistor TR40 of the latch circuit ADL, and a control signal ATL is input to the gate of the transistor TR41 of the latch circuit ADL. The latch circuit BDL holds data at a node BLAT and its inverted data at a node BINV. A control signal BTI is input to the gate of the transistor TR40 of the latch circuit BDL, and a control signal BTL is input to the gate of the transistor TR41 of the latch circuit BDL. The latch circuits CDL and XDL are similar, so their explanations are omitted.

[0039] The control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, and the clock signal CLK are each generated by, for example, the sequencer 14. The sense amplifier module 17 may have other circuit configurations. For example, the number of latch circuits provided in each sense amplifier unit SAU may be changed depending on the number of bits stored in the memory cell transistor MT. The sense amplifier unit SAU may have an arithmetic circuit capable of performing simple logical operations. In a read operation of each page, the sense amplifier module 17 can determine (determine) the data stored in the memory cell transistor MT by appropriately performing arithmetic processing using the latch circuit.

[0040] <1-3> Structure of semiconductor devices The structure of the semiconductor device 1 will be described. In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the reference substrate. In this specification, "upper" and "lower" are defined based on the direction along the Z direction, with the direction away from the reference substrate being the positive direction (upward). For example, the substrate placed at the bottom in the drawings is used as the reference substrate. The front surface of the substrate corresponds to the surface on which transistors (CMOS circuits) are formed. The back surface of the substrate corresponds to the surface opposite to the front surface.

[0041] <1-3-1> Appearance of semiconductor device The appearance of the semiconductor device 1 according to the embodiment will be described. The semiconductor device 1 according to the embodiment is formed by bonding three semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. That is, the semiconductor device 1 according to the embodiment has a bonding surface formed by bonding semiconductor substrates W1 and W2, and a bonding surface formed by bonding semiconductor substrates W2 and W3. The following describes a case in which the semiconductor substrate W3 is removed during the manufacturing process of the semiconductor device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W3 may remain after bonding the semiconductor substrates W2 and W3.

[0042] Fig. 5 is a perspective view showing an example of the appearance of the semiconductor device 1 according to the embodiment. As shown in Fig. 5, the semiconductor device 1 has a structure in which, for example, a semiconductor substrate W1, a first CMOS layer 100, a semiconductor substrate W2, a second CMOS layer 200, a memory layer 300, and a wiring layer 400 are stacked in this order from the bottom up.

[0043] The first CMOS layer 100 includes a CMOS circuit formed using a semiconductor substrate W1. The second CMOS layer 200 includes a CMOS circuit formed using a semiconductor substrate W2. The set of the first CMOS layer 100 and the second CMOS layer 200 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17. The memory layer 300 includes a memory cell array 10 formed using a semiconductor substrate W3 (not shown). The wiring layer 400 includes, for example, a plurality of pads PD used to connect the semiconductor device 1 and the memory controller 2. The pads PD are connected to the input / output circuit 11 and exposed on the surface of the semiconductor device 1. Hereinafter, the semiconductor substrate W1 and the first CMOS layer 100 will be collectively referred to as the "first CMOS chip CCP1." The semiconductor substrate W2 and the second CMOS layer 200 will be collectively referred to as the "second CMOS chip CCP2." The memory layer 300 and the wiring layer 400 are collectively referred to as an "array chip ACP."

[0044] Each of the semiconductor substrates W1, W2, and W3 is, for example, a silicon substrate. Each of the semiconductor substrates W1 and W2 has an impurity diffusion region according to the circuit design of the semiconductor device 1. The thickness of the semiconductor substrate W2 is, for example, thinner than the thickness of the semiconductor substrate W1. The semiconductor device 1 has a bonding surface between adjacent substrates. In the embodiment, the contact (boundary) portion between the first CMOS layer 100 and the semiconductor substrate W2 and the contact (boundary) portion between the second CMOS layer 200 and the memory layer 300 correspond to the bonding surface. The bonding surface is a surface formed by bonding two wafers (substrates) and corresponds to the boundary portion of the two bonded substrates. A layer on which a circuit, such as the first CMOS layer 100, is formed may be sandwiched between the two bonded substrates. In this specification, the process of bonding two substrates is referred to as a "bonding process."

[0045] <1-3-2> Planar layout of semiconductor devices 6 is a plan view showing an example of a planar layout of the semiconductor device 1 according to the embodiment. As shown in Fig. 6, the semiconductor device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a kerf region KR.

[0046] The core region CR is, for example, a rectangular region provided near the center of the semiconductor substrate W1. In the core region CR, for example, a memory cell array 10, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17 are arranged.

[0047] The peripheral region PR is a rectangular ring-shaped region provided to surround the outer periphery of the core region CR. The peripheral region PR is provided with, for example, an input / output circuit 11 and a logic controller 12. The peripheral region PR is also provided with, for example, contacts for connecting wiring provided in the wiring layer 400 with circuits provided in the first CMOS layer 100, the second CMOS layer 200, and the memory layer 300.

[0048] The wall region WR is a rectangular ring-shaped region that surrounds the outer periphery of the peripheral region PR. At least one sealing portion ES (not shown) is disposed in the wall region WR so as to surround the outer periphery of the peripheral region PR. Details of the sealing portion ES will be described later.

[0049] The kerf region KR is a quadrangular ring-shaped region provided to surround the outer periphery of the wall region WR. The kerf region KR is in contact with the outermost periphery of the semiconductor device 1. For example, alignment marks and the like used during the manufacture of the semiconductor device 1 are arranged in the kerf region KR.

[0050] <1-3-3> Planar layout of memory cell array 7 is a plan view showing an example of a planar layout of the memory cell array 10 in the core region CR of the semiconductor device 1 according to the embodiment. Fig. 7 shows regions corresponding to four blocks BLK0 to BLK3 included in the memory cell array 10. As shown in Fig. 7, the memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE. The memory cell array 10 also includes, for example, memory regions MA and contact regions CA aligned in the X direction.

[0051] Each slit SLT has a portion extending along the X direction and crosses the contact area CA and the memory area MA along the X direction. Multiple slits SLT are aligned in the Y direction. Each slit SLT separates adjacent wirings (e.g., word lines WL0 to WL7 and select gate lines SGD and SGS) through the slit SLT. In each slit SLT, a conductor with an insulating spacer on its sidewall may be arranged insulated from the wirings, or an insulator may be embedded. In the memory cell array 10, each of the areas separated by the slits SLT corresponds to one block BLK.

[0052] Each slit SHE has a portion extending along the X direction and crosses the memory area MA along the X direction. The multiple slits SHE are aligned in the Y direction. In this example, four slits SHE are arranged between each pair of adjacent slits SLT in the Y direction. Each slit SHE has, for example, a structure in which an insulator is embedded. Each slit SHE separates adjacent wirings (at least select gate lines SGD) via the slit SHE. In the memory cell array 10, each of the regions separated by the slits SLT and SHE corresponds to one string unit SU.

[0053] The planar layout of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other layouts. For example, the number of slits SHE arranged between two adjacent slits SLT may be designed to be any number. The number of string units SU included in each block BLK may be changed based on the number of slits SHE arranged between two adjacent slits SLT.

[0054] <1-3-4> Planar layout of memory area 8 is a plan view showing an example of a planar layout of a memory region MA of a memory cell array 10 included in a semiconductor device 1 according to the embodiment. Fig. 8 shows a region including one block BLK (string units SU0 to SU4). As shown in Fig. 8, the semiconductor device 1 includes, for example, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MA.

[0055] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 24 rows in the region between two adjacent slits SLT. For example, counting from the top of the page, one slit SHE is arranged to overlap the fifth, tenth, fifteenth, and twentieth memory pillars MP, respectively.

[0056] Each bit line BL has a portion extending in the Y direction. Multiple bit lines are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CV. Note that the contact CV between the memory pillar MP and the bit line BL that are in contact with two different select gate lines SGD may be omitted.

[0057] The planar layout of the memory region MA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other layouts. For example, the number and arrangement of the memory pillars MP and slits SHE arranged between two adjacent slits SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0058] <1-3-5> Cross-sectional structure of memory area 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of the cross-sectional structure of the memory region MA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. Fig. 9 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W3 before being bonded to the semiconductor substrate W2, and indicates coordinate axes based on the semiconductor substrate W3. As shown in Fig. 9, the memory cell array 10 includes, in the memory region MA, for example, conductor layers 21-25, insulator layers 31-35, an insulating member 36, and contacts CV, V1, and V2.

[0059] A conductor layer 21 is provided on a semiconductor substrate W3. An insulator layer 31 is provided on the conductor layer 21. Conductor layers 22 and insulator layers 32 are alternately provided on the insulator layer 31. That is, a plurality of conductor layers 22 are arranged side by side in the Z direction. The number of conductor layers 22 corresponds to the number of layers of stacked wiring (select gate lines SGS, word lines WL, and select gate lines SGD). An insulator layer 33, a conductor layer 23, an insulator layer 34, and an insulator layer 35 are provided in this order on the uppermost conductor layer 22. Each of the conductor layers 21 and 22 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 23 has, for example, a portion formed in a line shape extending in the Y direction. The conductor layer 21 is used as a source line SL. In this example, ten conductor layers 22 arranged in the Z direction are used as, in order from the source line SL side, select gate lines SGS, word lines WL0 to WL7, and select gate lines SGD. Conductor layer 23 is used as bit lines BL. Conductor layer 21 contains, for example, polysilicon (Si). Conductor layer 22 contains, for example, tungsten (W). Conductor layer 23 contains, for example, copper (Cu). Conductor layer 23 is included in wiring layer M0.

[0060] A conductor layer 24 is provided above the conductor layer 23. The conductor layer 24 is a wiring that relays the connection between the bit line BL and the sense amplifier module 17. The conductor layer 23 and the conductor layer 24 are connected via a contact V1. A conductor layer 25 is provided above the conductor layer 24. The conductor layer 25 corresponds to a bonding pad BP used to bond the semiconductor substrate W2 and the semiconductor substrate W3. The conductor layer 24 and the conductor layer 25 are connected via a contact V2. The side surfaces of the conductor layer 24 and the contacts V1 and V2 are covered with an insulator layer 34. The insulator layer 34 may be composed of multiple insulating films. The side surfaces of the conductor layer 25 are covered with the insulator layer 35. The memory cell array 10 may include multiple conductor layers 24 and multiple conductor layers 25. The conductor layer 24 includes, for example, copper. The conductor layer 24 is included in the wiring layer M1. The conductive layer 25 includes, for example, copper. The insulating layer 35 and the conductive layer 25 are included in the bonding layer B1.

[0061] The insulating member 36 has a plate-like portion extending along the XZ plane. The insulating member 36 separates the insulating layer 31 from the alternately arranged conductor layers 22 and 32. In this example, the insulating member 36 is embedded in the slit SLT. A conductor having an insulating spacer on its side wall may be arranged in the slit SLT so as to be insulated from each of the conductor layers 21 and 22.

[0062] Each memory pillar MP extends along the Z direction, penetrates the insulator layer 31, and the alternately arranged conductor layers 22 and insulator layers 32, and is connected to the conductor layer 21. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator extending along the Z direction. The semiconductor layer 41 covers the core member 40. A portion of the side surface of the semiconductor layer 41 contacts the conductor layer 21. That is, the semiconductor layer 41 and the conductor layer 21 (source line SL) in the memory pillar MP are connected via the side surface of the memory pillar MP. The stacked film 42 covers the side surface and bottom surface of the semiconductor layer 41, except for the contact portion between the semiconductor layer 41 and the conductor layer 21. The associated semiconductor layer 41 (memory pillar MP) and the conductor layer 23 (bit line BL) are connected via a contact CV.

[0063] The portion where the conductive layer 22 used as the select gate line SGS intersects with the memory pillar MP functions as a select transistor ST2. The portion where the conductive layer 22 used as the word line WL intersects with the memory pillar MP functions as a memory cell transistor MT. The portion where the conductive layer 22 used as the select gate line SGD intersects with the memory pillar MP functions as a select transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0064] <1-3-6> Cross-sectional structure of memory pillar FIG. 10 is a cross-sectional view taken along line XX in FIG. 9 , showing an example of the cross-sectional structure of a memory pillar MP included in the semiconductor device 1 according to the embodiment. FIG. 10 illustrates a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W3. As shown in FIG. 10 , the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 contains, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 contains, for example, silicon nitride (SiN).

[0065] <1-3-7> Planar layout of contact area 11 is a plan view showing an example of a planar layout of a contact region CA of a memory cell array 10 included in a semiconductor device 1 according to the embodiment. Fig. 11 also shows a memory region MA near the contact region CA. As shown in Fig. 11, in the contact region CA, for example, each end of the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD has a terrace portion.

[0066] The terrace portions correspond to the portions of the stacked wiring that do not overlap with the upper wiring layer (conductive layer). The structure formed by the multiple terrace portions is similar to steps, terraces, rimstones, etc. In this example, a staircase structure having steps in the X direction is formed by the end of the select gate line SGS, the ends of each of the word lines WL0 to WL7, and the end of the select gate line SGD. In other words, steps are formed between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ..., between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD.

[0067] The semiconductor device 1 also includes a plurality of contacts CC in the block BLK of the contact region CA. The contacts CC are members used for connection between the row decoder module 16 and the stacked wiring. Each contact CC is connected to one of the terrace portions of the stacked wiring provided in the memory cell array 10 in the block BLK, i.e., the plurality of conductor layers 22 (select gate line SGS, word lines WL0 to WL7, and select gate line SGD).

[0068] Although the case where the contacts CC are connected to terrace portions formed in the contact area CA has been exemplified, the present invention is not limited to this. Even if no terrace portion is provided in the contact area CA, the semiconductor device 1 only needs to have a structure in which a pair of a certain contact CC and an associated wiring are electrically connected without short-circuiting with other wiring.

[0069] <1-3-8> Cross-sectional structure of the contact area FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11 , showing an example of a cross-sectional structure in a contact region CA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. FIG. 12 shows the structure in the contact region CA of the memory cell array 10 formed on the semiconductor substrate W3 before the bonding process, and the memory region MA near the contact region CA. As shown in FIG. 12 , each end of the plurality of conductor layers 22 is provided in a stepped shape and covered with an insulator layer 33. In the contact region CA, insulator layers 34 and 35 are stacked on the insulator layer 33. In addition, the semiconductor device 1 includes, for example, a plurality of contacts CC, a plurality of contacts V1 and V2, and a plurality of conductor layers 26, 27, and 28 in the contact region CA.

[0070] A plurality of contacts CC are provided on the terrace portions of the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD, respectively. Each contact CC penetrates the insulator layer 33. One conductor layer 26 is provided on each of the plurality of contacts CC. A contact V1 is provided on each conductor layer 26. FIG. 12 shows only the contact V1 corresponding to the select gate line SGS among the plurality of contacts V1. A conductor layer 27 is provided on the contact V1. A contact V2 is provided on the conductor layer 27. The conductor layers 26 and 27 and the plurality of contacts V1 and V2 are covered by the insulator layer 34. A conductor layer 28 is provided on the contact V2, penetrating the insulator layer 35. The conductor layer 28 corresponds to a bonding pad BP used to bond the semiconductor substrates W2 and W3. The conductor layer 26 includes, for example, copper. The conductor layer 26 is included in the wiring layer M0. The conductor layer 27 includes, for example, copper. The conductor layer 27 is included in the wiring layer M1. The conductor layer 28 includes, for example, copper. The conductor layer 28 is included in the bonding layer B1.

[0071] The above-described combinations of the conductive layers 26, 27, and 28 and the contacts CC, V1, and V2 correspond to wiring and contacts for connecting any of the plurality of conductive layers 22 to the row decoder module 16. Although not shown in the figure, each of the plurality of conductive layers 22 other than the select gate line SGS is similarly connected to the row decoder module 16 via the combinations of the conductive layers 26, 27, and 28 and the contacts CC, V1, and V2.

[0072] <1-3-9> Cross-sectional structure of semiconductor device FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure of the core region CR of the semiconductor device 1 according to the embodiment. FIG. 13 shows a cross section including the memory region MA and the contact region CA in the core region CR of the semiconductor device 1, and indicates coordinate axes based on the semiconductor substrate W1. Note that FIG. 13 shows a state after the semiconductor substrate W3 has been removed. As shown in FIG. 13, the semiconductor device 1 has a structure in which the structure of the memory region MA shown in FIG. 9 is inverted vertically, corresponding to the memory layer 300, and a structure in which the structure of the contact region CA shown in FIG. 12 is inverted vertically. The semiconductor device 1 includes insulator layers 50 and 51, conductor layers GC1 and 52-54, and contacts 55-59, corresponding to the first CMOS layer 100. The semiconductor device 1 includes insulator layers 70 and 71, conductor layers GC2 and 72-75, and contacts 59 and 76-80, corresponding to the second CMOS layer 200. The semiconductor device 1 includes an insulator layer 91 , an insulator layer 92 , a conductor layer 93 , an insulator layer 94 , an insulator layer 95 , and an insulator layer 96 corresponding to the wiring layer 400 .

[0073] Hereinafter, the area corresponding to the memory area MA of the first CMOS chip CCP1 will be referred to as "area A1m." The area corresponding to the contact area CA of the first CMOS chip CCP1 will be referred to as "area A1c." The area corresponding to the memory area MA of the second CMOS chip CCP2 will be referred to as "area A2m." The area corresponding to the contact area CA of the second CMOS chip CCP2 will be referred to as "area A2c."

[0074] The insulator layer 50 is provided on the semiconductor substrate W1. The insulator layer 50 covers circuits (e.g., conductor layers GC1 and 52-54, and contacts 55-59) provided on the semiconductor substrate W1. The insulator layer 50 may be composed of multiple insulator layers. The insulator layer 50 also includes, in order from the semiconductor substrate W1 side, wiring layers D0, D1, and D2. The wiring layers D0, D1, and D2 are provided with wiring of the first CMOS layer 100. The insulator layer 51 is provided on the insulator layer 50. The insulator layer 51 is in contact with the back surface of the semiconductor substrate W2. The boundary between the insulator layer 51 and the semiconductor substrate W2 corresponds to the bonding surface between the semiconductor substrate W1 and the semiconductor substrate W2 (the first CMOS chip CCP1 and the second CMOS chip CCP2). The insulator layer 51 includes, for example, silicon oxide. Hereinafter, the layer including the insulator layer 51 will be referred to as the "bonding layer B2."

[0075] The insulator layer 70 is provided on the semiconductor substrate W2. The insulator layer 70 covers circuits (e.g., conductor layers GC2 and 72 to 74, and contacts 59 and 76 to 80) provided on the semiconductor substrate W2. The insulator layer 70 may be composed of multiple insulator layers. The insulator layer 70 also includes, in order from the semiconductor substrate W1 side, wiring layers D3, D4, and D5. Wiring of the second CMOS layer 200 is provided in the wiring layers D3, D4, and D5. The number of wiring layers of the second CMOS layer 200 may differ from the number of wiring layers of the first CMOS layer 100. The insulator layer 71 is provided on the insulator layer 70. The insulator layer 71 is in contact with the insulator layer 35 included in the memory layer 300. The boundary between the insulator layer 71 and the insulator layer 35 corresponds to the bonding surface between the semiconductor substrate W2 and the semiconductor substrate W3 (the second CMOS chip CCP2 and the array chip ACP). The insulator layer 71 includes, for example, silicon oxide. Hereinafter, the layer including the insulator layer 71 will be referred to as the "bonding layer B3."

[0076] The conductor layer GC1 is provided on a gate insulating film provided on the semiconductor substrate W1. The contact 55 is provided on the conductor layer GC1. Two contacts 56 included in the region A1m are connected to two impurity diffusion regions provided in the semiconductor substrate W1. For example, these two impurity diffusion regions correspond to the source and drain of the transistor TRa, respectively. Similarly, two contacts 56 included in the region A1c are connected to two impurity diffusion regions provided in the semiconductor substrate W1. For example, these two impurity diffusion regions correspond to the source and drain of the transistor TRc, respectively. Shallow trench isolation (STI) is provided in the semiconductor substrate W1 as appropriate depending on the transistor layout. The STI is provided to electrically isolate the transistor from other elements. The STI (hereinafter also referred to as the "insulating film region STI") surrounds the active region AA of the transistor. The active region AA is the region where the transistor is provided. The active region AA includes, for example, a gate insulating film, the conductor layer GC1, and two impurity diffusion regions. The insulating film region STI is in contact with the impurity diffusion region. The transistor TRa is included in, for example, the sense amplifier module 17. The transistor TRa is, for example, an HV transistor (transistor TR38) in the sense amplifier unit SAU. The transistor TRc is included in, for example, the row decoder module 16. The transistor TRc is, for example, an HV transistor (transistor TR0) in the row decoder RD. The row decoder RD is included in the first CMOS chip CCP1.

[0077] The semiconductor substrate W1 and the transistors provided on the semiconductor substrate W1 are subjected to heat of approximately 1000°C in an activation annealing process described below during the manufacture of the semiconductor device 1. Therefore, in consideration of heat resistance, the thickness of the semiconductor substrate W1 is set to be thicker than the thickness of the semiconductor substrate W2. Also, in consideration of heat resistance, an HV transistor, for example, is disposed on the semiconductor substrate W1. The reason why the thickness of the semiconductor substrate W1 on which the HV transistor is provided is made relatively thick is that the depletion layer in the HV transistor is relatively easy to expand. The transistors provided on the semiconductor substrate W1 may be LV transistors that can withstand the heat in the activation annealing process.

[0078] A conductor layer 52 is provided on each of the contacts 55 and 56. The conductor layer 52 is included in the wiring layer D0. A conductor layer 53 is provided on the conductor layer 52 via a contact 57. The conductor layer 53 is included in the wiring layer D1. A conductor layer 54 is provided on the conductor layer 53 via a contact 58. The conductor layer 54 is included in the wiring layer D2. The conductor layers 52 to 54 are subjected to heat of about 1000°C during activation annealing treatment during manufacturing. For this reason, a conductive material with a relatively high melting point is used as the material for the conductor layers 52 to 54. The conductor layers 52 to 54 include, for example, tungsten. A contact 59 is provided on the conductor layer 54. The contact 59 is provided so as to penetrate the semiconductor substrate W2 and the insulator layer 51. The contact 59 and the semiconductor substrate W2 are insulated from each other by an insulating film region INS. That is, the semiconductor substrate W2 includes an insulating film region INS penetrating the semiconductor substrate W2. The semiconductor substrate W2 includes a plurality of insulating film regions INS. The thickness of the insulating film region STI is thinner than the thickness of the insulating film region INS. The contacts 59 correspond to through vias. A plurality of contacts 59 penetrate the insulating film region INS. That is, the plurality of contacts 59 penetrate the insulating film region INS provided in the semiconductor substrate W2. The contacts 59 include, for example, tungsten or copper. The insulating film region INS includes, for example, silicon oxide or silicon nitride. Hereinafter, the contacts 59 will be referred to as "through vias 59." A plurality of through vias 59 penetrating one insulating film region INS will be referred to as a "through via group Gv." A plurality of wirings each provided in the same layer and in contact with the through via group Gv will be referred to as a "wiring group Gi."

[0079] The conductor layer GC2 is provided on a gate insulating film provided on the semiconductor substrate W2. The contact 76 is provided on the conductor layer GC2. Two contacts 77 included in the region A2m are connected to two impurity diffusion regions provided in the semiconductor substrate W2. For example, these two impurity diffusion regions correspond to the source and drain of the transistor TRb, respectively. STI is provided in the semiconductor substrate W2 as appropriate depending on the transistor layout. The transistor TRb is included in, for example, the sense amplifier module 17. The transistor TRb is, for example, an LV transistor (transistor TR34) in the sense amplifier unit SAU. The LV transistor operates faster than the HV transistor. The sense amplifier unit SAU is included in the first CMOS chip CCP1 and the second CMOS chip CCP2.

[0080] In order to thin the semiconductor device 1, the thickness of the semiconductor substrate W2 is set to be thinner than the thickness of the semiconductor substrate W1. For this reason, for example, an LV transistor is disposed on the semiconductor substrate W2. Note that the transistor provided on the semiconductor substrate W2 may be, for example, a MOS transistor with a lower breakdown voltage than the LV transistor (hereinafter also referred to as a "VLV (Very-Low-Voltage) transistor"), or a high-breakdown-voltage MOS transistor that can operate even when the thickness of the semiconductor substrate W2 is relatively thin (hereinafter also referred to as an "HVN (High-Voltage-Negative) transistor"). The HVN transistor is an N-type HV transistor.

[0081] The gate lengths of transistors TRa and TRc, which are HV transistors, are longer than the gate length of transistor TRb, which is a LV transistor. The relationship of the gate lengths of the VLV transistor, LV transistor, and HV transistor is, for example, VLV transistor < LV transistor < HV transistor. Also, the film thickness of the gate insulating film of transistors TRa and TRc is thicker than the film thickness of the gate insulating film of transistor TRb. The relationship of the film thicknesses of the gate insulating films of the VLV transistor, LV transistor, and HV transistor is VLV transistor < LV transistor < HV transistor.

[0082] A conductor layer 72 is provided on each of contacts 76 and 77, and through via 59. The conductor layer 72 is included in wiring layer D3. The position of the upper surface of each of the plurality of through vias 59 penetrating the insulating film region INS is the same as the position of the upper surfaces of contacts 76 and 77. A conductor layer 73 is provided on the conductor layer 72 via contact 78. The conductor layer 73 is included in wiring layer D4. The conductor layer 73 may be provided in the current path between contact 77 and through via 59, or may be provided in the current path between through via 59 and bonding pad BP. In the example of FIG. 13, the source or drain of transistor TRa is electrically connected to the source or drain of transistor TRb via contacts 56 to 58, through via 59, contacts 78 and 77, and conductor layers 52 to 54, 72, and 73. A conductor layer 74 is provided on the conductor layer 73 via contact 79. The conductor layer 74 is included in wiring layer D5. The conductor layers 72 to 74 include, for example, copper. A conductor layer 75 is provided on the conductor layer 74 via contact 80. The conductor layer 75 is included in bonding layer B3. The conductor layer 75 corresponds to the bonding pad BP used for bonding the semiconductor substrate W2 and the semiconductor substrate W3. The conductor layer 75 includes, for example, copper.

[0083] With the above structure, in the memory region MA and the contact region CA, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via a through via group Gv penetrating the insulating film region INS.

[0084] In the memory region MA, a through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS is connected to a wiring group Gi including a plurality of conductor layers 54 (wiring) provided in the wiring layer D2. One of the plurality of conductor layers 54 included in the wiring group Gi in the wiring layer D2 is electrically connected to a conductor layer 52 (wiring) electrically connected to one of the source or drain of the transistor TRa. The other of the plurality of conductor layers 54 included in the wiring group Gi in the wiring layer D2 is electrically connected to a conductor layer 52 (wiring) electrically connected to the other of the source or drain of the transistor TRa. In addition, the through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS is connected to a wiring group Gi including a plurality of conductor layers 72 provided in the wiring layer D3. Of the multiple conductive layers 72 included in the wiring group Gi of the wiring layer D3, the conductive layers 52 and 54, and the conductive layer 72 electrically connected to the other of the source or drain of the transistor TRa via the through via 59 are electrically connected to the conductive layer 72 (wiring) electrically connected to one of the source or drain of the transistor TRb.

[0085] In the contact region CA, a through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS is connected to a wiring group Gi including a plurality of conductor layers 54 (wiring) provided in the wiring layer D2. One of the plurality of conductor layers 54 included in the wiring group Gi in the wiring layer D2 is electrically connected to a conductor layer 52 (wiring) electrically connected to one of the source or drain of the transistor TRc. In addition, the through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS is connected to a wiring group Gi including a plurality of conductor layers 72 provided in the wiring layer D3.

[0086] In the memory area MA, a conductor layer 25 disposed opposite to the conductor layer 75 is in contact with the conductor layer 25. The conductor layer 25 is connected to the associated conductor layer 23 (bit line BL) via contacts V1 and V2 and the conductor layer 24. This connects the conductor layer 23 (bit line BL) to the transistor TRa provided on the semiconductor substrate W1 via contacts V1, V2, 78-80, and 56-58, the through via 59, and the conductor layers 24, 25, 72-75, and 52-54. Each of the other conductor layers 23 is similarly connected to the other transistors provided on the semiconductor substrate W1.

[0087] In the contact region CA, a conductive layer 28 disposed opposite to the conductive layer 75 is in contact with the conductive layer 28. The conductive layer 28 is connected to the associated conductive layer 22 (e.g., select gate line SGS) via contacts V1, V2, and CC and conductive layers 26 and 27. This connects the conductive layer 22 (e.g., select gate line SGS) to the transistor TRc provided on the semiconductor substrate W1 via contacts CC, V1, V2, 78-80, and 56-58, the through via 59, and conductive layers 26-28, 72-75, and 52-54. Each of the other conductive layers 22 is similarly connected to the other transistors provided on the semiconductor substrate W1.

[0088] An insulator layer 91, an insulator layer 92, a conductor layer 93, an insulator layer 94, an insulator layer 95, and an insulator layer 96 are provided in this order on the conductor layer 21. A portion of the conductor layer 93 penetrates the insulator layers 91 and 92. The conductor layer 93 may have a portion in contact with the conductor layer 21. Each of the insulator layers 91, 92, and 94 includes, for example, silicon oxide. The insulator layer 95 includes, for example, silicon nitride. The insulator layer 96 includes, for example, polyimide.

[0089] FIG. 14 is a plan view showing an example of the planar layout of the through vias 59 in the memory region MA of the semiconductor device 1. FIG. 14 shows an example in which 14 through vias 59 penetrate the insulating film region INS, and the conductor layers 54 connected to the through vias 59 are indicated by dotted lines. As shown in FIG. 14, the through vias 59 have, for example, a circular cross-sectional shape in the XY plane (a cross section parallel to the surface of the semiconductor substrate W1). If the diameter of the through via 59 is "diameter Dv1" and the pitch (distance) between two adjacent through vias 59 is "pitch Pv1," the multiple through vias 59 having the diameter Dv1 are arranged in a 60° staggered pattern at the pitch Pv1 (60° staggered pattern). In other words, each of the multiple through vias 59 is arranged at each vertex of an equilateral triangle. This arrangement corresponds to a honeycomb structure. The multiple through vias 59 may be arranged, for example, in a square pattern or a 45° staggered pattern.

[0090] 15 is a plan view showing another example of the planar layout of the through vias 59 in the memory region MA of the semiconductor device 1. As shown in Fig. 15, a plurality of through vias 59 having a diameter Dv1 are arranged in a 45° staggered pattern at a pitch Pv1 (45° staggered pattern). In other words, each of the plurality of through vias 59 is arranged at each vertex of a square and at the intersection of the diagonal of the square.

[0091] In the memory area MA, the insulating film area INS formed on the semiconductor substrate W2 is formed in, for example, an area where the sense amplifier module 17 is arranged (hereinafter referred to as the "sense amplifier area"). In the sense amplifier area, the plurality of through vias 59 are connected to corresponding bit lines BL. The plurality of through vias 59 are each drawn out and connected to corresponding HV transistors of the sense amplifier unit SAU. The HV transistors are also connected to LV transistors. The through vias 59 for connecting the HV transistors and the LV transistors are also provided in the insulating film area INS. Therefore, the plurality of through vias 59 are respectively connected to different conductor layers 54 (wiring). Furthermore, since the number of through vias 59 is relatively large, the plurality of through vias 59 are arranged as densely as possible within the insulating film area INS. In order to arrange the maximum number of vias in the minimum area, the plurality of through vias 59 are preferably arranged in a honeycomb structure.

[0092] FIG. 16 is a plan view showing an example of the planar layout of the through vias 59 in the contact region CA of the semiconductor device 1. FIG. 16 shows an example in which four through vias penetrate the insulating film region INS, and the conductor layers 54 connected to the through vias 59 are indicated by dotted lines. As shown in FIG. 16, the through vias 59 have, for example, a circular cross-sectional shape in the XY plane. If the diameter of the through via 59 is "diameter Dv1" and the pitch between two adjacent through vias 59 is "pitch Pv2," the multiple through vias 59 having the diameter Dv1 are arranged in a square at the pitch Pv2. That is, the arrangement of the through via groups Gv penetrating the insulating film region INS formed in the contact region CA is different from the arrangement of the through via groups Gv penetrating the insulating film region INS formed in the memory region MA. The multiple through vias 59 may be arranged, for example, in a 60° staggered pattern or a 45° staggered pattern.

[0093] In the contact area CA, the insulating film region INS formed on the semiconductor substrate W2 is formed in, for example, a region where the row decoder module 16 is arranged (hereinafter referred to as the "row decoder region"). In the row decoder region, the plurality of through vias 59 are connected to corresponding word lines WL. The plurality of through vias 59 are each drawn out and connected to corresponding transistors of the row decoder RD. Therefore, the plurality of through vias 59 are respectively connected to different conductor layers 54 (wiring). Although the number of through vias 59 is relatively large, a relatively high voltage is applied to the row decoder RD, so the pitch between two adjacent through vias 59 is set to a distance that ensures a breakdown voltage between the two adjacent through vias 59. Therefore, the pitch Pv2 is larger than the pitch Pv1. That is, the through via groups Gv that penetrate the insulating film region INS formed in the contact area CA are arranged at a different pitch from the through via groups Gv that penetrate the insulating film region INS formed in the memory area MA.

[0094] Fig. 17 is a cross-sectional view showing an example of the cross-sectional structure of the peripheral region PR of the semiconductor device 1 according to the embodiment. Fig. 17 shows a cross-section including the peripheral region PR of the semiconductor device 1, and indicates coordinate axes based on the semiconductor substrate W1. Note that Fig. 17 shows the state after the semiconductor substrate W3 has been removed.

[0095] In the peripheral region PR, the first CMOS layer 100, like the core region CR, includes insulator layers 50 and 51, conductor layers GC1 and 52 to 54, contacts 55 to 58, and a through via 59. The first CMOS layer 100 further includes a conductor layer 61. Like the core region CR, the semiconductor substrate W1 includes two impurity diffusion regions provided in regions corresponding to the source and drain of the transistor, and an insulating film region STI provided according to the layout of the transistor.

[0096] The conductor layer GC1 is provided on a gate insulating film provided on the semiconductor substrate W1. The contact 55 is provided on the conductor layer GC1. Two contacts 56 are connected to two impurity diffusion regions provided in the semiconductor substrate W1. For example, of these two impurity diffusion regions, the impurity diffusion region on the left side of the drawing corresponds to the drain of the transistor TRd, and the impurity diffusion region on the right side of the drawing corresponds to the source. A plurality of conductor layers 52 are provided on the contact 55 connected to the gate, the contact 56 connected to the drain, and the contact 56 connected to the source, respectively. A plurality of contacts 57 are provided on the plurality of conductor layers 52, respectively. A plurality of conductor layers 53 are provided on the plurality of contacts 57, respectively. The conductor layer 53 provided on the contact 57 electrically connected to the gate and the contact 57 electrically connected to the drain is composed of a single conductor layer 53. That is, the transistor TRd is, for example, a diode-connected transistor in which the gate and the drain are connected. The conductor layer 53 electrically connected to the source is connected to the conductor layer 54 via a contact 58.

[0097] The conductor layer 61 is provided on an insulating film provided on the semiconductor substrate W1. The conductor layer 61 is, for example, a resistor R1. The conductor layer 61 includes, for example, polysilicon. Two contacts 55 are provided on both ends of the conductor layer 61. A plurality of conductor layers 52 are provided on the plurality of contacts 55, respectively. A plurality of contacts 57 are provided on the plurality of conductor layers 52, respectively. A plurality of conductor layers 53 are provided on the plurality of contacts 57, respectively. The conductor layer 53 electrically connected to one end of the resistor R1 is connected to the conductor layer 54 via a contact 58. The contact 58 electrically connected to the source of the transistor TRd and the conductor layer 54 provided on the contact 58 electrically connected to one end of the resistor R1 are configured as a single conductor layer 54. The resistor R1 may be provided in the second CMOS layer 200.

[0098] In the peripheral region PR, the second CMOS layer 200 includes, similarly to the core region CR, insulator layers 70 and 71, conductor layers GC2 and 72 to 75, through vias 59, and contacts 76 to 80. Similarly to the core region CR, the semiconductor substrate W2 includes an insulating film region INS through which the plurality of through vias 59 penetrate, two impurity diffusion regions provided in regions corresponding to the source and drain of the transistor, and an insulating film region STI provided according to the transistor layout. The conductive layer 74 is connected to a transistor TRe provided on the semiconductor substrate W2 via, for example, a contact 79 (not shown), contacts 77 and 78, and conductive layers 72 and 73. The transistor TRe is included, for example, in the input / output circuit 11. The transistor TRe is, for example, an LV transistor. The transistor TRe may be, for example, a VLV transistor or an HVN transistor. The conductive layer 72 provided on the plurality of through vias 59 penetrating the insulating film region INS is composed of a single conductive layer 72. Of the multiple conductive layers 73 provided via contacts 78 on conductive layers 72 connected to multiple through vias 59, the conductive layer 73 on the left side of the paper and the conductive layer 73 on the right side of the paper are connected to conductive layer 75 (bonding pad BP) via contacts 79, conductive layer 74, and contact 80.

[0099] With the above structure, in the peripheral region PR, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via the through via group Gv that penetrates the insulating film region INS. The through via group Gv, which includes a plurality of through vias 59 that penetrate the insulating film region INS, is connected to one conductor layer 54 (wiring) provided in the wiring layer D2. Furthermore, the through via group Gv, which includes a plurality of through vias 59 that penetrate the insulating film region INS, is connected to one conductor layer 72 (wiring) provided in the wiring layer D3.

[0100] In the peripheral region PR, the memory layer 300, like the core region CR, includes insulator layers 33 to 35, conductor layers 21 and 26 to 28, and contacts CC, V1, and V2. The memory layer 300 also includes a sacrificial member 37. The conductor layer 21 includes a conductor layer 21a and a conductor layer 21b. The sacrificial member 37 is provided between the conductor layer 21a and the conductor layer 21b.

[0101] The set of the conductor layer 21a, the sacrificial member 37, and the conductor layer 21b is provided at the same height as the conductor layer 21. Specifically, the height of the lower surface of the conductor layer 21a is aligned with the height of the lower surface of the conductor layer 21 (source line SL). The height of the upper surface of the conductor layer 21b is aligned with the height of the upper surface of the conductor layer 21 (source line SL). The conductor layer 21 in the core region CR corresponds to a structure in which the conductor layer 21a, the sacrificial member 37, and the conductor layer 21b are stacked, and then the sacrificial member 37 is replaced with a conductor. In other words, the height of the sacrificial member 37 is the same as the height at which the conductor layer 21 and the semiconductor layer 41 in each memory pillar MP are connected. Each of the conductor layers 21a and 21b contains, for example, polysilicon. The sacrificial member 37 contains, for example, silicon nitride.

[0102] A plurality of contacts CC are provided on the conductive layer 26. The tops of the contacts CC reach at least the height of the conductive layer 21.

[0103] In the peripheral region PR, the wiring layer 400 includes an insulator layer 91, an insulator layer 92, a conductor layer 93, an insulator layer 94, an insulator layer 95, and an insulator layer 96, similar to the core region CR.

[0104] A portion of the conductive layer 93 penetrates the conductive layer 21a, the sacrificial member 37, the conductive layer 21b, and the insulator layers 91 and 92. The conductive layer 93 may have a portion in contact with the contact CC. The upper portion of the contact CC is covered with the conductive layer 93 and is electrically connected to the conductive layer 93. The conductive layer 93 is insulated from the conductive layers 21a and 21b by the insulator layer 92. A portion of the upper portion of the conductive layer 93 is not covered with the insulator layers 94 to 96. This portion functions as the pad PD. As a result, the pad PD is connected to the transistors and resistor elements provided on the semiconductor substrate W1 via the contact CC, V1, V2, 78 to 80, and 56 to 58, the through via 59, and the conductive layers 26 to 28, 72 to 75, and 52 to 54. Furthermore, the pads PD are connected to transistors provided on the semiconductor substrate W2 via contacts CC, V1, V2, and 77-80, and conductive layers 26-28 and 72-75.

[0105] Furthermore, the pads PD of one semiconductor device 1 can be connected by wire bonding to the pads PD of another semiconductor device 1. In the same manner, three or more semiconductor devices 1 can be connected.

[0106] FIG. 18 is a plan view showing an example of the planar layout of through vias 59 in the peripheral region PR of the semiconductor device 1. FIG. 18 shows an example in which 14 through vias 59 penetrate the insulating film region INS, and the conductor layers 54 connected to the through vias 59 are indicated by dotted lines. As shown in FIG. 18, the through vias 59 have, for example, a circular cross-sectional shape in the XY plane. If the diameter of the through via 59 is "diameter Dv1" and the pitch between two adjacent through vias 59 is "pitch Pv3," multiple through vias 59 having diameter Dv1 are arranged in a 60° staggered pattern at the pitch Pv3. This arrangement corresponds to a honeycomb structure. The multiple through vias 59 may be arranged, for example, in a square or a 45° staggered pattern.

[0107] FIG. 19 is a plan view showing an example of the planar layout of the bond pads BP (conductor layers 75) in the peripheral region PR of the semiconductor device 1. FIG. 19 shows four conductor layers 75, and the through vias 59 shown in FIG. 18 are also indicated by dotted lines. As shown in FIG. 19, the conductor layers 75 have, for example, a rectangular cross-sectional shape in the XY plane. If the pitch between two adjacent conductor layers 75 is defined as "pitch Pp1," the multiple conductor layers 75 are arranged in a square at the pitch Pp1. The pitch Pp1 of the conductor layers 75 is larger than the pitch Pv3 of the through vias 59. Furthermore, if the cross-sectional area of ​​the conductor layer 75 in the XY plane is defined as "Sp1" and the cross-sectional area of ​​the through via 59 in the XY plane is defined as "Sv1," the cross-sectional area Sp1 of the conductor layer 75 is larger than the cross-sectional area Sv1 of the through via 59 in the XY plane.

[0108] 20 is a plan view showing another example of the planar layout of the through vias 59 in the peripheral region PR of the semiconductor device 1. As shown in Fig. 20, a plurality of through vias 59 having a diameter Dv1 are arranged in a 45° staggered pattern at a pitch Pv3.

[0109] 21 is a plan view showing another example of the planar layout of the bonding pads BP (conductor layers 75) in the peripheral region PR of the semiconductor device 1. In FIG. 21, four conductor layers 75 are shown, and the through vias 59 shown in FIG. 20 are also shown by dotted lines. As shown in FIG. 21, the pitch Pp1 of the conductor layers 75 is larger than the pitch Pv3 of the through vias 59. In addition, the area Sp1 of the conductor layers 75 is larger than the area Sv1 of the through vias 59.

[0110] In the peripheral region PR, the insulating film region INS formed on the semiconductor substrate W2 is formed in, for example, a region where the input / output circuit 11 is arranged (hereinafter referred to as the "input / output circuit region"). In the input / output circuit region, the plurality of through vias 59 are connected to the pads PD. The plurality of through vias 59 are each drawn out and connected to transistors (transistors formed on the semiconductor substrate W1 and transistors formed on the semiconductor substrate W2) included in the input / output circuit 11. It is preferable that the resistance of the wiring path connected to the pad PD be as low as possible. For this reason, the plurality of through vias 59 are connected to one conductor layer 54 (wiring) and one conductor layer 72 (wiring). Furthermore, since the number of through vias 59 is relatively large, the plurality of through vias 59 are arranged as densely as possible in the insulating film region INS. For this reason, the pitch Pv3 is smaller than the pitch Pv2. Furthermore, the pitch Pv3 may be equal to the pitch Pv1, smaller than the pitch Pv1, or larger than the pitch Pv1. In order to arrange the maximum number of vias in the minimum area, the plurality of through vias 59 are preferably arranged in a manner corresponding to a honeycomb structure.

[0111] Fig. 22 is a cross-sectional view showing an example of the cross-sectional structure of the wall region WR of the semiconductor device 1 according to the embodiment. Fig. 22 shows a cross-section including the wall region WR of the semiconductor device 1, and indicates coordinate axes based on the semiconductor substrate W1. Note that Fig. 22 shows a state after the semiconductor substrate W3 has been removed.

[0112] In the wall region WR, the first CMOS layer 100 includes, similarly to the core region CR, insulator layers 50 and 51, conductor layers 52 to 54, contacts 56 to 58, and a through via 59. The semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region of P-type impurities (p + The N-type well region NW is a diffusion region of N-type impurities provided in the vicinity of the upper surface of the semiconductor substrate W1 (n + The P-type well region PW and the N-type well region NW correspond to the sealing portions ES1 and ES2, respectively.

[0113] In the wall region WR, the second CMOS layer 200, like the core region CR, includes insulator layers 70 and 71, conductor layers 72 to 75, through vias 59, and contacts 78 to 80. Like the core region CR, the semiconductor substrate W2 includes an insulating film region INS through which the plurality of through vias 59 penetrate.

[0114] With the above structure, in the wall region WR, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via the through via group Gv that penetrates the insulating film region INS. The through via group Gv, which includes a plurality of through vias 59 that penetrate the insulating film region INS, is connected to a wiring group Gi, which includes a plurality of conductor layers 54 (wiring) provided in the wiring layer D2. One of the plurality of conductor layers 54 included in the wiring group Gi in the wiring layer D2 is electrically connected to the P-type well region PW provided in the semiconductor substrate W1. The other of the plurality of conductor layers 54 included in the wiring group Gi in the wiring layer D2 is electrically connected to the N-type well region NW provided in the semiconductor substrate W1.

[0115] In the wall region WR, the memory layer 300 includes, similarly to the peripheral region PR, insulator layers 33 to 35, conductor layers 21a, 21b, and 26 to 28, a sacrificial member 37, and contacts CC, V1, and V2.

[0116] In the wall region WR, the wiring layer 400 includes an insulator layer 91, an insulator layer 92, a conductor layer 93, an insulator layer 94, an insulator layer 95, and an insulator layer 96, similar to the core region CR.

[0117] A portion of the conductive layer 93 penetrates the conductive layer 21a, the sacrificial member 37, the conductive layer 21b, and the insulator layers 91 and 92. The conductive layer 93 may have a portion in contact with the contact CC. An upper portion of the contact CC is covered with the conductive layer 93 and is electrically connected to the conductive layer 93. As a result, the conductive layer 93 is connected to the P-type well region PW via the contact CC, V1, V2, 78-80, and 56-58, the through via 59, and the conductive layers 26-28, 72-75, and 52-54, which correspond to the sealing portion ES1. The conductive layer 93 is also connected to the N-type well region NW via the contact CC, V1, V2, 78-80, and 56-58, the through via 59, and the conductive layers 26-28, 72-75, and 52-54, which correspond to the sealing portion ES2.

[0118] Although not shown, the contacts CC, V1, V2, 78-80, and 56-58, the through via 59, and the conductor layers 26-28, 72-75, and 52-54 are arranged in a ring shape in plan view. The insulating film region INS is arranged in a ring shape in plan view. That is, in the wall region WR, the sealing portions ES1 and ES2 are each arranged in a quadrangular ring shape so as to surround the outer periphery of the core region CR and surround the peripheral region PR. The sealing portion ES2 is disposed outside the sealing portion ES1. The insulating film region INS is also arranged in a quadrangular ring shape so as to surround the outer periphery of the core region CR and surround the peripheral region PR.

[0119] The sealing portions ES1 and ES2 described above are structures that can release positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1. Furthermore, each of the sealing portions ES1 and ES2 can prevent moisture and the like from penetrating from the outside of the wall region WR into the core region CR. Each of the sealing portions ES1 and ES2 can suppress stress generated in an interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the semiconductor device 1. Furthermore, each of the sealing portions ES1 and ES2 can also be used as a crack stopper.

[0120] FIG. 23 is a plan view showing an example of a planar layout of through vias 59 in the wall region WR of the semiconductor device 1. FIG. 23 shows an example in which two through vias 59 penetrate the insulating film region INS, and the conductor layer 54 connected to the through vias 59 is indicated by a dotted line. As shown in FIG. 23, the through vias 59 are spaced apart from one another. As described above, the through vias 59 are arranged in a ring shape in a plan view, and therefore the through vias 59 are spaced apart in the X direction or the Y direction. In FIG. 23, the through vias 59 are spaced apart from one another in the Y direction. The through vias 59 have, for example, a linear cross-sectional shape in the XY plane. That is, the cross-sectional shape of each of the through vias 59 penetrating the insulating film region INS formed in the wall region WR is different from the cross-sectional shape of each of the through vias 59 penetrating the insulating film region INS formed in the memory region MA. Hereinafter, the pitch between two adjacent through vias 59 will be referred to as a "pitch Pv4."

[0121] In the wall region WR, the insulating film region INS formed on the semiconductor substrate W2 is formed, for example, in a region where a sealing portion is arranged. In this region, the pitch between two adjacent through vias 59 is set to a distance that allows positive charges generated inside and outside the wall region WR to escape to the N-type well region NW of the semiconductor substrate W1, and allows negative charges generated inside and outside the wall region WR to escape to the P-type well region PW of the semiconductor substrate W1. Therefore, the pitch Pv4 is larger than the pitch Pv1. That is, the through via groups Gv penetrating the insulating film region INS formed in the wall region WR are arranged at a pitch different from the through via groups Gv penetrating the insulating film region INS formed in the memory region MA. Furthermore, the pitch Pv4 may be equal to, smaller than, or larger than the pitch Pv2.

[0122] In the above description, an example has been given in which HV transistors are arranged in the first CMOS layer 100 and LV transistors are arranged in the second CMOS layer 200, but the present invention is not limited to this. The arrangement of the transistors in the first CMOS layer 100 and the second CMOS layer 200 can be changed as appropriate depending on the design of the semiconductor device 1.

[0123] <1-4> Manufacturing methods for semiconductor devices Fig. 24 is a flowchart showing an example of a method for manufacturing a semiconductor device 1 according to the embodiment. Each of Fig. 25 to Fig. 43 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device 1 according to the embodiment during manufacturing. The method for manufacturing a semiconductor device 1 according to the embodiment will be described below with appropriate reference to Fig. 24.

[0124] First, a semiconductor substrate W3 on which a memory layer 300 is formed and a semiconductor substrate W1 on which a first CMOS layer 100 is formed are fabricated (S11). In the memory layer 300 on the fabricated semiconductor substrate W3, the insulator layer 35 and the bonding pads BP (conductor layers 25 and 28) provided on the bonding layer B1 are exposed, as shown in FIGS. 25 to 27. FIG. 25 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. FIG. 26 is a cross-sectional view showing an example of the cross-sectional structure in the peripheral region PR. FIG. 27 is a cross-sectional view showing an example of the cross-sectional structure in the wall region WR. In the fabricated first CMOS layer 100 on the semiconductor substrate W1, the insulator layer 51 provided on the bonding layer B2 is exposed, as shown in FIGS. 28 to 30. That is, a first CMOS chip CCP1 having a transistor (CMOS circuit) and the insulator layer 51 located above the transistor is formed. FIG. 28 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. FIG. 29 is a cross-sectional view showing an example of the cross-sectional structure in the peripheral region PR. 30 is a cross-sectional view showing an example of the cross-sectional structure in the wall region WR. At the time of S11, the structure corresponding to the through via 59 has not been formed in the semiconductor substrate W1 and the first CMOS layer 100.

[0125] Next, the semiconductor substrate W1 and the semiconductor substrate W2 are bonded to form a first bonding substrate BW1 (S12). Specifically, before the process of S12, a silicon oxide film (insulating film) is formed on the bonding surface of the semiconductor substrate W2. That is, a second CMOS chip CCP2 is formed, which has the semiconductor substrate W2 and the silicon oxide film provided on the semiconductor substrate W2. Then, the silicon oxide film of the second CMOS chip CCP2 is bonded onto the insulator layer 51 of the first CMOS chip CCP1. By the bonding process of the semiconductor substrate W1 and the semiconductor substrate W2, the insulator layer 51 (silicon oxide film) of the first CMOS chip CCP1 and the silicon oxide film of the second CMOS chip CCP2 come into contact with each other and are bonded together. As a result, a first bonding substrate BW1 is formed, which has a structure in which the semiconductor substrate W2 is provided on the insulator layer 51, as shown in FIG. 31. FIG. 31 is a cross-sectional view showing an example of a cross-sectional structure in the core region CR.

[0126] Next, a CMP (Chemical Mechanical Polishing) process is performed on the semiconductor substrate W2 included in the first bonding substrate BW1 (S13). By the process of S13, the semiconductor substrate W2 of the first bonding substrate BW1 is polished (thinned) as shown in FIG. 32. FIG. 32 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. The thickness of the semiconductor substrate W2 that has been polished and thinned corresponds to the thickness of the semiconductor substrate W2 shown in FIG. 13. The thickness of the semiconductor substrate W2 after the process of S13 is, for example, about 0.5 μm to 2.0 μm.

[0127] Next, the second CMOS layer 200 is formed on the first junction substrate BW1 (S14). Specifically, the following processes are performed.

[0128] First, an insulating film region STI is provided near the upper surface of the semiconductor substrate W2 so as to surround the active region AA of the transistor. The insulating film region STI is in contact with the upper surface of the semiconductor substrate W2. A gate insulating film is provided on the semiconductor substrate W2. A conductor layer GC2 is provided on the gate insulating film. As shown in FIG. 33, the conductor layer GC2 is processed. Using the conductor layer GC2 as a mask, an impurity diffusion region is provided on the semiconductor substrate W2. As a result, a transistor (CMOS circuit) is formed on the semiconductor substrate W2. FIG. 33 is a cross-sectional view showing an example of a cross-sectional structure in the core region CR.

[0129] Next, a first hole is formed through the semiconductor substrate W2 so as to overlap the conductor layer 54 (wiring) in the Z direction. In the memory region MA, contact region CA, and wall region WR, the first hole is formed through the semiconductor substrate W2 so as to overlap multiple conductor layers 54 in the Z direction. In the peripheral region PR, the first hole is formed through the semiconductor substrate W2 so as to overlap one conductor layer 54. An insulator is then filled into the first hole. As a result, an insulating film region INS that penetrates the semiconductor substrate W2 is formed, as shown in FIG. 34. FIG. 34 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. The insulating film region INS that penetrates the semiconductor substrate W2 is formed in each of the memory region MA, contact region CA, peripheral region PR, and wall region WR. The insulating film region INS may be formed simultaneously with the insulating film region STI. In this case, the number of processes and costs can be reduced.

[0130] Next, activation annealing is performed on the semiconductor substrate W2 included in the first bond substrate BW1. This forms a source and a drain in the impurity diffusion region of the semiconductor substrate W2. The activation annealing is performed, for example, at 1000°C to 1100°C for 0 to 30 seconds. For example, spike annealing is used to minimize impurity diffusion. Spike annealing is performed by simply increasing and decreasing the temperature, with the time at the maximum temperature set to 0 seconds. As described above, a conductive material with a relatively high melting point is used as the material for the conductor layers 52 to 54 provided in the first CMOS layer 100, and an HV transistor is provided on the semiconductor substrate W1. This prevents deterioration of the characteristics of the transistor provided on the semiconductor substrate W1. The activation annealing may also be performed on both the semiconductor substrates W1 and W2.

[0131] Next, the insulating layer 70 is formed as shown in Fig. 35. Fig. 35 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR.

[0132] Next, as shown in Fig. 36, contacts 76 and 77 and through via 59 are formed. Fig. 36 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. After the contacts 76 and 77 and through via 59 are formed, a wiring layer D3 (conductor layer 72) is formed as shown in Fig. 37. Fig. 37 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. For example, the contacts 76 and 77, the through via 59, and the wiring layer D3 are formed by single damascene.

[0133] First, holes corresponding to the contacts 76 and 77, and a plurality of second holes penetrating the insulating film region INS formed in the semiconductor substrate W2 are simultaneously formed, for example, by etching. As a result, holes reaching the conductor layer GC2 of the transistor (CMOS circuit) are formed. Holes reaching the source or drain of the transistor (CMOS circuit) are formed. A plurality of second holes penetrating the insulating film region INS are formed in each of the memory region MA, contact region CA, peripheral region PR, and wall region WR. At this time, for example, the plurality of second holes penetrating the insulating film region INS of the memory region MA and the plurality of second holes penetrating the insulating film region INS of the contact region CA are formed at different pitches.

[0134] Thereafter, a conductor is buried in the holes corresponding to the contacts 76 and 77, respectively, and in the second hole penetrating the insulating film region INS, thereby forming the contacts 76 and 77 and the through vias 59. As a result, for example, the contact 76 connected to the conductor layer GC2 of the transistor (CMOS circuit) is formed. The contact 77 connected to the source or drain of the transistor (CMOS circuit) is formed. Furthermore, for example, a through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS of the memory region MA and a through via group Gv including a plurality of through vias 59 penetrating the insulating film region INS of the contact region CA are formed at different pitches.

[0135] Next, a trench corresponding to the wiring layer D3 is formed by, for example, etching. Thereafter, a conductor is buried in the trench corresponding to the wiring layer D3 to form the wiring layer D3. As a result, for example, a conductor layer 72 is formed on a contact 77 connected to the source or drain of a transistor (CMOS circuit). Furthermore, for example, in each of the memory region MA, contact region CA, peripheral region PR, and wall region WR, a wiring group Gi is formed on a through-via group Gv penetrating the insulating film region INS and in the same layer as the conductor layer 72.

[0136] Next, as shown in Figures 38 to 40, the structure of wiring layers D4 and D5 and bonding layer B3 is formed, and the process of S14 is completed. Figure 38 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure in the peripheral region PR. Figure 40 is a cross-sectional view showing an example of the cross-sectional structure in the wall region WR.

[0137] Next, the first bonding substrate BW1 and the semiconductor substrate W3 are bonded to form the second bonding substrate BW2 (S15). Specifically, the bonding process of the first bonding substrate BW1 and the semiconductor substrate W3 brings the insulator layer 71 of the second CMOS layer 200 and the insulator layer 35 of the memory layer 300 into contact with each other and bond them together. Furthermore, pairs of opposing bonding pads BP between the second CMOS layer 200 and the memory layer 300 come into contact with each other and bond them together. As a result, the second bonding substrate BW2 is formed as shown in FIGS. 41 to 43. FIG. 41 is a cross-sectional view showing an example of a cross-sectional structure in the core region CR. FIG. 42 is a cross-sectional view showing an example of a cross-sectional structure in the peripheral region PR. FIG. 43 is a cross-sectional view showing an example of a cross-sectional structure in the wall region WR.

[0138] Next, a CMP process is performed on the semiconductor substrate W3 included in the second bonding substrate BW2 (S16). The process of S16 removes the semiconductor substrate W3 of the second bonding substrate BW2. Note that the semiconductor substrate W3 may be left unremoved by merely being thinned.

[0139] Next, the wiring layer 400 is formed on the second bonding substrate BW2 (S17). An insulator layer 91, an insulator layer 92, a conductor layer 93, an insulator layer 94, an insulator layer 95, and an insulator layer 96 are formed in this order on the conductor layer 21. When the process of S17 is completed, the semiconductor device 1 is completed.

[0140] <1-5> Effects of the embodiment The semiconductor device 1 according to the embodiment can reduce the chip area of ​​the semiconductor device 1. The effects of the embodiment will be described in detail below.

[0141] There is a semiconductor device having an array chip including a memory cell array 10, a first CMOS chip on a semiconductor substrate on which a CMOS circuit for controlling the memory cell array 10 is arranged, and a second CMOS chip on a semiconductor substrate on which a CMOS circuit for controlling the memory cell array 10 is arranged.

[0142] In such a semiconductor device, for example, a first CMOS chip and a second CMOS chip may be electrically connected using through vias whose periphery is covered with an insulating film region. Furthermore, for example, CMOS circuits may be arranged in different regions depending on their intended use. The number of CMOS circuits arranged in each region may vary depending on the intended use. That is, the number of CMOS circuits arranged may vary from region to region. Therefore, the number of through vias connecting the first CMOS chip and the second CMOS chip may also vary depending on the intended use and from region to region.

[0143] A memory cell array in which memory cells are stacked three-dimensionally can increase its storage capacity by increasing the number of stacked word lines WL. However, increasing the number of stacked word lines WL to increase capacity may also increase the number of through vias connected to the word lines WL and connecting the first CMOS chip and the second CMOS chip. As the number of through vias increases, the area of ​​the insulating film region surrounding the through vias increases accordingly, which may increase the chip area of ​​the semiconductor device 1.

[0144] Furthermore, the voltage supplied to the CMOS circuit may differ depending on the application, so if the distance between two adjacent through vias is made the same in all areas regardless of the application, for example, dielectric breakdown may occur between the two adjacent through vias depending on the voltage supplied to the CMOS circuit.

[0145] In contrast, in the semiconductor device 1 according to this embodiment, the semiconductor substrate W2 includes an insulating film region INS penetrating the semiconductor substrate W2 in each of the core region CR, peripheral region PR, and wall region WR. Each insulating film region INS includes a plurality of through vias 59 electrically connecting the first CMOS chip CCP1 and the second CMOS chip CCP2. In other words, a plurality of through vias 59 electrically connecting the first CMOS chip CCP1 and the second CMOS chip CCP2 penetrate one insulating film region INS. Furthermore, in each of the core region CR, peripheral region PR, and wall region WR, the plurality of through vias 59 are arranged in the insulating film region INS at different pitches depending on the application. This allows the pitch arrangement within the insulating film region INS to be optimized. Therefore, the area of ​​the insulating film region INS can be reduced compared to when a plurality of through vias 59 are arranged in the insulating film region INS at the same pitch regardless of the application. This allows the chip area of ​​the semiconductor device 1 to be reduced.

[0146] There is also a semiconductor device in which a first CMOS chip and a second CMOS chip are bonded together by bonding pads provided on the first CMOS chip and bonding pads provided on the second CMOS chip.

[0147] In such semiconductor devices, the placement of the through vias connecting the first and second CMOS chips is limited by the distance between two adjacent bonding pads, and bonding failures may occur when bonding the bonding pads together.

[0148] In contrast, in this embodiment, an insulating film (silicon oxide film) of a semiconductor substrate W2 is bonded to an insulating layer 51 of a semiconductor substrate W1 that has a CMOS circuit and an insulating layer 51 located above the CMOS circuit. In other words, no bonding pads are used. This allows the through vias 59 connecting the first CMOS chip CCP1 and the second CMOS chip CCP2 to be arranged without being limited by the distance between the bonding pads. This allows the chip area of ​​the semiconductor device 1 to be reduced. Furthermore, since bonding pads are not used, bonding defects between the bonding pads do not occur. Furthermore, the process can be simplified compared to when the first CMOS chip and the second CMOS chip are bonded using bonding pads.

[0149] <1-6> First modified example A semiconductor device 1A according to a first modified example of the embodiment will be described. The semiconductor device 1A according to this modified example differs from the embodiment in the structure near the top surface of the through via 59. The following description will focus on the differences from the embodiment.

[0150] <1-6-1> Cross-sectional structure of semiconductor device FIG. 44 is a cross-sectional view showing an example of the cross-sectional structure of the core region CR of the semiconductor device 1A according to the first modification. FIG. 45 is a cross-sectional view showing an example of the cross-sectional structure of the peripheral region PR of the semiconductor device 1A according to the first modification. FIG. 46 is a cross-sectional view showing an example of the cross-sectional structure of the wall region WR of the semiconductor device 1A according to the first modification. As shown in FIGS. 44 to 46, in the semiconductor device 1A, the wiring group Gi provided on the through via group Gv penetrating the insulating film region INS and in the same layer as the conductor layer 72 is eliminated from the semiconductor device 1 according to the embodiment. The position of the upper surface of each of the plurality of through vias 59 penetrating the insulating film region INS is the same as the position of the upper surface of the conductor layer 72 electrically connected to one of the source or drain of the transistor TRb. Each of the plurality of through vias 59 penetrating the insulating film region INS is connected to a contact 78.

[0151] Other structures of the semiconductor device 1A are similar to those of the semiconductor device 1 according to the embodiment.

[0152] <1-6-2> Manufacturing methods for semiconductor devices Fig. 47 is a flowchart showing an example of a method for manufacturing a semiconductor device 1A according to the first modification. In the flowchart of the method for manufacturing a semiconductor device 1A shown in Fig. 47, S14 in the flowchart of Fig. 24 shown in the embodiment is replaced with S14A. The steps other than S14A are the same as those in the flowchart of Fig. 24 shown in the embodiment. Figs. 48 and 49 are cross-sectional views showing an example of a cross-sectional structure of a semiconductor device 1A according to the first modification during its manufacture. The method for manufacturing a semiconductor device 1A will be described below with reference to Fig. 47 as appropriate.

[0153] In S14A, the second CMOS layer 200 is formed on the first junction substrate BW1. Specifically, the following processes are performed.

[0154] The steps from the formation of the transistor (CMOS circuit) to the formation of the insulating layer 70 are the same as those in the embodiment.

[0155] Next, as shown in Fig. 48, contacts 76 and 77 and a wiring layer D3 (conductor layer 72) are formed. Fig. 48 is a cross-sectional view showing an example of a cross-sectional structure in the core region CR. For example, the contacts 76 and 77 and the wiring layer D3 are integrally formed by dual damascene.

[0156] First, holes corresponding to the contacts 76 and 77 and a trench corresponding to the wiring layer D3 are formed, for example, by etching. As a result, holes reaching the conductor layer GC2 of the transistor (CMOS circuit) are formed. Holes reaching the source or drain of the transistor (CMOS circuit) are formed. A trench corresponding to the wiring layer D3 is formed.

[0157] Thereafter, conductors are buried in the holes corresponding to the contacts 76 and 77 and the groove corresponding to the wiring layer D3, thereby integrally forming the contacts 76 and 77 and the wiring layer D3. As a result, for example, the contact 76 connected to the conductor layer GC2 of the transistor (CMOS circuit) is formed. The contact 77 connected to the source or drain of the transistor (CMOS circuit) is formed. Furthermore, for example, the conductor layer 72 is formed on the contact 76 connected to the conductor layer GC2 of the transistor (CMOS circuit). The conductor layer 72 is formed on the contact 77 connected to the source or drain of the transistor (CMOS circuit).

[0158] Next, a through via 59 is formed as shown in Fig. 49. Fig. 49 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR.

[0159] First, for example, by etching, a plurality of second holes are formed penetrating the insulating film region INS formed in the semiconductor substrate W2. As a result, a plurality of second holes penetrating the insulating film region INS are formed in each of the memory region MA, the contact region CA, the peripheral region PR, and the wall region WR. At this time, for example, the plurality of second holes penetrating the insulating film region INS in the memory region MA and the plurality of second holes penetrating the insulating film region INS in the contact region CA are formed at different pitches.

[0160] Thereafter, a conductor is embedded in the second hole that penetrates the insulating film region INS to form the through via 59. As a result, for example, a through via group Gv including a plurality of through vias 59 that penetrate the insulating film region INS in the memory region MA and a through via group Gv including a plurality of through vias 59 that penetrate the insulating film region INS in the contact region CA are formed at different pitches.

[0161] The subsequent steps of forming the structure of the wiring layers D4 and D5 and the bonding layer B3 are the same as those in the embodiment.

[0162] <1-6-3> Effects of the first modified example According to this modification, the same effects as those of the embodiment can be achieved.

[0163] Furthermore, when forming the conductive layer 72 on the through via 59, for example, the lower resist film may be sucked into the through via 59 during photolithography of the conductive layer 72, which may cause the photolithography pattern to collapse. To avoid this, it is necessary to repeatedly apply and etch back the lower resist film, which increases the number of steps.

[0164] In contrast to this, in this modification, the conductive layer 72 is not provided on the through via 59. Therefore, according to this modification, the number of steps can be reduced compared to when the conductive layer 72 is provided on the through via 59.

[0165] <1-7> Second modified example A semiconductor device 1B according to a second modification of the embodiment will be described. In the semiconductor device 1B according to this modification, the structure of the peripheral region PR is different from that of the embodiment. The following description will focus on the differences from the embodiment.

[0166] <1-7-1> Cross-sectional structure of semiconductor device 50 is a cross-sectional view showing an example of the cross-sectional structure of the peripheral region PR of a semiconductor device 1B according to the second modification. As shown in Fig. 50, in the semiconductor device 1B, a chip connection portion CP is added to the peripheral region PR of the semiconductor device 1 according to the embodiment.

[0167] The chip connection portion CP is disposed, for example, spaced apart from the insulating film region INS in the Y direction. The chip connection portion CP includes an insulator layer 81, a through via 82, an insulating film region INSc, conductive layers 74 and 75, contacts 79 and 80, conductive layers 26 to 28, contacts CC, V1, and V2, and a conductive layer 93.

[0168] In the chip connection part CP, an insulator layer 81 is provided near the upper surface of the semiconductor substrate W1. A through via 82 is provided on the insulator layer 81. The through via 82 is included in the first CMOS chip CCP1 and the second CMOS chip CCP2. The side surface and bottom surface of the lower end of the through via 82 are covered with the insulator layer 81. The upper surface of the through via 82 is located higher than the upper surfaces of each of the plurality of through vias 59 included in the through via group Gv. The lower surface of the through via 82 is located lower than the lower surfaces of each of the plurality of through vias 59 included in the through via group Gv. In the XY plane, the cross-sectional area of ​​the upper surface of the through via 82 is larger than the cross-sectional area of ​​each of the plurality of through vias 59 included in the through via group Gv. The semiconductor substrate W2 is provided with an insulating film region INSc penetrating the semiconductor substrate W2. That is, the semiconductor substrate W2 includes the insulating film region INSc penetrating the semiconductor substrate W2. The through via 82 penetrates the insulator layers 50 and 51 and the insulating film region INSc. The through via 82 contacts the semiconductor substrate W1 via the insulator layer 81. The through via 82 has, for example, a tapered shape in which the cross-sectional area decreases from the top surface to the bottom surface. In the example of FIG. 50, two through vias 82 are provided. Two contacts 79 are provided on the through vias 82. Conductor layers 75 are provided on each of the two contacts 79 connected to one through via 82. That is, in the XY plane, the cross-sectional area of ​​the top surface of the through via 82 is larger than the cross-sectional area of ​​the bonding pad BP (conductive layer 75). The through via 82 is connected to the conductive layer 93 via the contact 79, the conductive layer 74, the contact 80, the conductive layer 75, the conductive layer 28, the contact V2, the conductive layer 27, the contact V1, the conductive layer 26, and the contact CC. As a result, the pad PD is connected to the through via 82 via the contacts CC, V1, V2, 79, and 80 and the conductive layers 26 to 28, 74, and 75. The lower end of the through via 82 does not have to reach the semiconductor substrate W1, and the lower end of the through via 82 may be in contact with the wiring layer D0 (conductive layer 52).

[0169] With the above structure, wiring that is included in the first CMOS chip CCP1 and the second CMOS chip CCP2 and penetrates the insulating film region INSc provided on the semiconductor substrate W2, i.e., through vias 82, are formed in the peripheral region PR. The through vias 82 are used, for example, for electrical connection between the semiconductor device 1B and another semiconductor device 1B. In contrast, the through vias 59 are used, for example, for electrical connection between the first CMOS chip CCP1 and the second CMOS chip CCP2.

[0170] FIG. 51 is a cross-sectional view showing an example of a cross-sectional structure when a plurality of semiconductor devices 1B are stacked. In the example of FIG. 51, a semiconductor device 1B (hereinafter referred to as a "semiconductor chip SCP2") is stacked on top of another semiconductor device 1B (hereinafter referred to as a "semiconductor chip SCP1"). As shown in FIG. 51, in the semiconductor chip SCP1, the conductor layer 93 is exposed, a portion of the insulator layer 94 is exposed, and a portion of the insulator layer 95 is exposed. In the semiconductor chip SCP2, the insulator layer 81 is removed. The through vias 82 of the semiconductor chip SCP2 are provided on the conductor layer 93 of the semiconductor chip SCP1. As a result, the semiconductor chips SCP1 and SCP2 are electrically connected via the through vias 82. Three or more semiconductor devices 1B can be stacked in the same manner as in FIG. 51.

[0171] <1-7-2> Effects of the second modified example This modification provides the same effects as the embodiment, and the first modification can also be applied to this modification.

[0172] Furthermore, according to this modification, a plurality of semiconductor devices 1B can be stacked, and the pads PD can be electrically connected to each semiconductor device 1B via the through vias .

[0173] <2> others As described above, the semiconductor device (1) according to the embodiment includes a first chip (CCP1) having a first substrate (W1) on which a first transistor (TRa) is formed, and a second chip (CCP2) provided above the first chip and having a second substrate (W2) on which a second transistor (TRb) is formed. The second substrate (W2) includes a first insulating film region (INS) and a second insulating film region (INS), each of which penetrates the second substrate. The first chip (CCP1) and the second chip (CCP2) are electrically connected via a first through via group (Gv) including at least a first via (59) and a second via (59), each of which penetrates the first insulating film region (INS), and a second through via group (Gv) including at least a third via (59) and a fourth via (59), each of which penetrates the second insulating film region (INS). The first through via group (Gv) is arranged at a different pitch from that of the second through via group (Gv).

[0174] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0175] Furthermore, in the flowcharts described in the above embodiments, the order of the processes can be changed as much as possible.

[0176] A FinFET (Fin Field-Effect Transistor) may be used as the transistor provided on the semiconductor substrate W2. The FinFET is applicable to the embodiment, the first modified example, and the second modified example. Fig. 52 is a cross-sectional view in the XZ plane showing an example of the structure of a FinFET. Fig. 53 is a cross-sectional view in the YZ plane of the FinFET of Fig. 52.

[0177] As shown in Figures 52 and 53, a semiconductor layer 201 is provided on a semiconductor substrate W2. The semiconductor layer 201 functions as a channel of the FinFET. A gate insulating film 202 is provided on two of the four side surfaces of the semiconductor layer 201 and on the top surface. That is, the two side surfaces and the top surface (three surfaces) of the semiconductor layer 201 are covered with the gate insulating film 202. A gate electrode 203 is provided on the gate insulating film 202. An electrode 204 is provided so as to be in contact with one of the two side surfaces of the semiconductor layer 201 that are not covered with the gate insulating film 202. The electrode 204 is one of a source electrode or a drain electrode. The electrode 204 is connected to a contact 77. An electrode 205 is provided so as to be in contact with the other of the two side surfaces of the semiconductor layer 201 that are not covered with the gate insulating film 202. The electrode 205 is the other of a source electrode or a drain electrode. The electrode 205 is connected to the contact 77. An insulating film region 206 (insulating film region STI) is provided under the gate insulating film 202 of the semiconductor substrate W2. By using a FinFET, leakage current can be reduced.

[0178] A transistor having a GAA (Gate All Around) structure (hereinafter also referred to as a "GAA transistor") may be used as the transistor provided on the semiconductor substrate W2. The GAA transistor is applicable to the embodiment, the first modified example, and the second modified example. FIG. 54 is a cross-sectional view in the XZ plane showing an example of the structure of a GAA transistor. FIG. 55 is a cross-sectional view in the YZ plane of the GAA transistor of FIG. 54. In the examples of FIGS. 54 and 55, two semiconductor layers 201 and two gate insulating films 202 are provided.

[0179] As shown in FIGS. 54 and 55 , a gate electrode 203 is provided on a semiconductor substrate W2. The semiconductor layer 201 has a plate-like shape extending in the X direction and penetrates the gate electrode 203. The two semiconductor layers 201 are arranged spaced apart from each other in the Z direction. The gate insulating film 202 has a ring-like shape extending in the X direction and penetrates the gate electrode 203. The two gate insulating films 202 are arranged spaced apart from each other in the Z direction. The gate insulating film 202 is provided on two of the four side surfaces, the top surface, and the bottom surface of the semiconductor layer 201. That is, the two side surfaces, the top surface, and the bottom surface (four surfaces) of the semiconductor layer 201 are covered with the gate insulating film 202. An electrode 204 is provided so as to be in contact with one of the two side surfaces of the semiconductor layer 201 that are not covered with the gate insulating film 202. The electrode 204 is either a source electrode or a drain electrode. An electrode 205 is provided in contact with the other of the two side surfaces of the semiconductor layer 201 that are not covered with the gate insulating film 202. The electrode 205 is the other of the source electrode and the drain electrode. An insulating film region 206 (insulating film region STI) is provided near the upper surface of the semiconductor substrate W2. An epitaxial layer 207 is provided on the semiconductor substrate W2 in contact with the electrode 204. An epitaxial layer 207 is provided on the semiconductor substrate W2 in contact with the electrode 205. A contact 77 is provided on the epitaxial layer 207. By using a GAA transistor, leakage current can be reduced more than in a FinFET.

[0180] When HV transistors are arranged in the first CMOS layer 100 and LV transistors are arranged in the second CMOS layer 200, the impurity concentrations of the semiconductor substrates W1 and W2 can be set according to the types of transistors to be arranged.

[0181] For example, the impurity concentration of the semiconductor substrate W1 on which the HV transistor is formed is 1.0×10 14 ~1.0×10 15 [cm -3 The impurity concentration of the semiconductor substrate W2 in which the LV transistor is formed can be set to 5.0×10 14 ~1.0×10 16 [cm -3] can be set to

[0182] When HV transistors are arranged in the first CMOS layer 100 and LV transistors are arranged in the second CMOS layer 200, the notches in the semiconductor substrates W1 and W2 may be set according to the types of transistors to be arranged. In this specification, the term "notch" refers to a portion provided in correspondence with the crystal orientation of the semiconductor substrate, and is used as a reference for the orientation in which the semiconductor manufacturing equipment holds the substrate.

[0183] For example, in a semiconductor substrate W1 on which an HV transistor is formed, the Miller indices of the crystal orientations corresponding to the X direction and the Y direction, i.e., the Miller indices of the crystal orientations corresponding to the extension direction of the channel of the transistor, are as follows: <110> In this case, the semiconductor substrate W1 can be set as follows: <110> The semiconductor substrate W1 may be called a "0-degree notch substrate."

[0184] In the semiconductor substrate W2 on which the LV transistor is formed, the Miller indices of the crystal orientations corresponding to the X direction and the Y direction, i.e., the Miller indices of the crystal orientations corresponding to the extension direction of the channel of the transistor, are as follows: <100> In this case, the semiconductor substrate W2 can be set as follows: <100> The semiconductor substrate W2 has a notch disposed corresponding to the semiconductor substrate W1. The semiconductor substrate W2 may be called a "45-degree notch substrate" because the notch is disposed at a position rotated 45 degrees from the semiconductor substrate W1. By using a 45-degree notch substrate as the semiconductor substrate W2, carrier mobility can be increased, and the LV transistor can operate at a higher speed.

[0185] When HV transistors are arranged in the first CMOS layer 100 and LV transistors are arranged in the second CMOS layer 200, the channel structures of the transistors formed in each of the semiconductor substrates W1 and W2 may be set according to the types of transistors to be arranged.

[0186] For example, the channel structure of the HV transistor formed in the semiconductor substrate W1 may be silicon.

[0187] For example, the channel structure of the LV transistor formed on the semiconductor substrate W2 may be a structure in which SiGe is epitaxially grown on the semiconductor substrate W2, thereby improving the characteristics of the LV transistor.

[0188] When HV transistors are arranged in the first CMOS layer 100 and LV transistors are arranged in the second CMOS layer 200, the structures of the gate electrodes of the transistors formed on each of the semiconductor substrates W1 and W2 may be set according to the types of transistors to be arranged.

[0189] For example, a WSi gate structure, a W polymetal structure, or the like can be applied to the gate electrode of the HV transistor formed on the semiconductor substrate W1.

[0190] An HV transistor with a WSi gate structure has a structure in which, for example, polysilicon (Poly-Si), tungsten silicide (WSi), and titanium nitride (TiN) are stacked in this order on a gate insulating film (oxide film) as a gate electrode, and silicon nitride (SiN) is formed on the gate electrode as a cap layer.

[0191] A W polymetal HV transistor has a structure in which, for example, polysilicon (Poly-Si), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W) are stacked in this order on a gate insulating film (oxide film) as a gate electrode, and silicon nitride (SiN) is formed on the gate electrode as a cap layer. Such a gate electrode structure may be called a "W polymetal gate."

[0192] For example, a salicide structure can be applied to the gate electrode of the LV transistor formed on the semiconductor substrate W2.

[0193] An LV transistor with a salicide structure has, for example, a structure in which polysilicon (Poly-Si) or nickel platinum silicide (NiPtSi) is formed as a gate electrode on a gate insulating film (oxide film). Such a gate electrode structure may be called a "NiPtSi gate."

[0194] The structure of each gate electrode of the semiconductor substrate W1 and the semiconductor substrate W2 is designed in accordance with, for example, reduction in chip area, performance requirements of the input / output circuit 11, and the like.

[0195] The semiconductor device 1 is not limited to a NAND flash memory, but may also be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The semiconductor device 1 may also be a memory device using a transition metal oxide element having variable resistance characteristics as a memory element (e.g., a resistance change memory such as ReRAM (Resistive Random Access Memory)), a memory device using a phase change element as a memory element (e.g., a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device using a ferroelectric element as a memory element (e.g., a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)). Furthermore, the semiconductor device 1 may also be used in other memories and other devices.

[0196] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0197] 1, 1A, 1B... semiconductor device, 2... memory controller, 10... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21 to 28... conductive layer, 31 to 35... insulating layer, 36... insulating member, 37... sacrificial member, 40... core member, 41... semiconductor layer, 42... stacked film, 43... tunnel insulating film, 44... insulating film, 45... Block insulating film, 50, 51...insulating layer, 52 to 54...conductive layer, 55 to 59...contact, 61...conductive layer, 70, 71...insulating layer, 72 to 75...conductive layer, 76 to 80...contact, 81...insulating layer, 82...through via, 91, 92...insulating layer, 93...conductive layer, 94 to 96...insulating layer, 100...first CMOS layer, 200...second CMOS layer, 300...memory layer, 400...wiring layer, W1 to W3...semiconductor substrate, BW1...first bonding substrate, BW2...second bonding substrate

Claims

1. a first chip having a first substrate on which a first transistor is formed; a second chip provided above the first chip and having a second substrate on which a second transistor is formed; and Equipped with the second substrate includes a first insulating film region and a second insulating film region, each of which penetrates the second substrate; the first chip and the second chip are electrically connected via a first through via group including at least a first via and a second via that each penetrate the first insulating film region, and a second through via group including at least a third via and a fourth via that each penetrate the second insulating film region; the first through via group is arranged at a pitch different from that of the second through via group; Semiconductor devices.

2. the second substrate further includes a third insulating film region surrounding an active region of the second transistor; the thickness of the third insulating film region is thinner than the thicknesses of the first insulating film region and the second insulating film region; The semiconductor device of claim 1 .

3. The arrangement of the first through via group is different from the arrangement of the second through via group; The semiconductor device of claim 1 .

4. the pitch of the second through via group is larger than the pitch of the first through via group; the first through via groups are arranged in a staggered pattern; The second through via group is arranged in a square configuration. The semiconductor device of claim 3.

5. In a cross section parallel to a surface of the first substrate, the cross-sectional shape of each of the plurality of vias included in the first through via group is different from the cross-sectional shape of each of the plurality of vias included in the second through via group. The semiconductor device of claim 1 .

6. the cross-sectional shape of each of the plurality of vias included in the first through via group is circular; the cross-sectional shape of each of the plurality of vias included in the second through via group is a line shape; The semiconductor device of claim 5.

7. The first chip comprises: a first wiring group including at least a first wiring and a second wiring, each of which is provided in the same layer; a third wiring electrically connected to the first transistor; and the first via is connected to the first wiring; the second via is connected to the second wiring; The first wiring is electrically connected to the third wiring. The semiconductor device of claim 1 .

8. The first chip comprises: A fourth wiring provided in the same layer as the first wiring group and the third via and the fourth via are connected to the fourth wiring; The semiconductor device of claim 7.

9. The first chip comprises: a second wiring group including at least fifth wirings and sixth wirings, each of which is provided in the same layer as the first wiring group; and the first substrate includes a first impurity diffusion region and a second impurity diffusion region; the third via is connected to the fifth wiring, the fourth via is connected to the sixth wiring, the fifth wiring is electrically connected to the first impurity diffusion region, the sixth wiring is electrically connected to the second impurity diffusion region; The semiconductor device of claim 7.

10. The second chip is a seventh wiring electrically connected to the second transistor; and The position of the top surface of each of the first via and the second via is the same as the position of the top surface of the seventh wiring. The semiconductor device of claim 7.

11. 5th via Further provided with the second substrate further includes a fourth insulating film region penetrating the second substrate; the fifth via is included in the first chip and the second chip and penetrates the fourth insulating film region; The semiconductor device of claim 1 .

12. an upper surface of the fifth via is located higher than an upper surface of each of the plurality of vias included in the first through via group; a lower surface of the fifth via is located lower than a lower surface of each of the vias included in the first through via group; In a cross section parallel to the surface of the first substrate, a cross-sectional area of ​​an upper surface of the fifth via is larger than a cross-sectional area of ​​each of the plurality of vias included in the first through via group. The semiconductor device of claim 11.

13. an array chip provided above the second chip, electrically connected to the first transistor and the second transistor, and including a memory cell array including a plurality of memory cells arranged in a stacking direction of the first substrate and the second substrate; Further comprising: The semiconductor device of claim 1 .

14. the second chip includes a plurality of pads bonded to the array chip; In a cross section parallel to a surface of the first substrate, a cross-sectional area of ​​each of the plurality of pads is larger than a cross-sectional area of ​​each of the plurality of vias included in the first through-via group; a pitch between the pads is larger than a pitch between the first through vias; The semiconductor device of claim 13.

15. a first sense amplifier having the first transistor and the second transistor; Further provided with the first sense amplifier is included in the first chip and the second chip; The memory cell array a first bit line electrically connected to a first memory cell of the plurality of memory cells; and the first via and the second via are electrically connected to the first transistor; the second transistor is electrically connected to the first transistor through the second via; the first transistor is electrically connected to the first bit line through the first via; The semiconductor device of claim 13.

16. a first row decoder having a third transistor; Further provided with the first row decoder is included in the first chip; The memory cell array a first word line electrically connected to a first memory cell of the plurality of memory cells; and the third via is electrically connected to the third transistor; the third transistor is electrically connected to the first word line through the third via; The semiconductor device of claim 13.

17. the pitch of the second through via group is larger than the pitch of the first through via group; 17. The semiconductor device of claim 16.

18. forming a first chip having a first transistor and a first insulator layer overlying the first transistor; forming a second chip having a substrate and a first insulating film disposed on the substrate; bonding a first insulating film of the second chip onto the first insulator layer of the first chip; forming a first insulating film region and a second insulating film region, each of which extends through the substrate; forming a first through via group, each including a plurality of vias penetrating the first insulating film region, and a second through via group, each including a plurality of vias penetrating the second insulating film region, at different pitches; Equipped with A method for manufacturing semiconductor devices.

19. forming a second transistor over the substrate; forming a first contact connected to the second transistor; forming the first contacts, the first through via group, and the second through via group, and then forming a first wiring on the first contacts; forming a first wiring group on the first through via group and in the same layer as the first wiring; and forming a second wiring group on the second through via group and in the same layer as the first wiring. Further comprising:

20. The method for manufacturing a semiconductor device according to claim 18.

20. forming a second transistor over the substrate; forming a first contact connected to the second transistor; forming a first wiring on the first contact; Further provided with The forming of the first through via group and the second through via group includes: After forming the first wiring, the first through via group and the second through via group are formed to the same height as an upper surface of the first wiring. Including, 20. The method for manufacturing a semiconductor device according to claim 18.

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