Semiconductor device

Abstract

To provide a semiconductor device which improves performance by increasing the degree of integration, and to provide a method of forming the same.SOLUTION: The semiconductor device 1 may include a transistor, a first device 15a, a backside isolation structure 92, a front side conductive structure 61, a passivation structure 65, a backside conductive pattern, and a backside interconnection structure. The first device includes a semiconductor body 5a including a first semiconductor region 5pa and a second semiconductor region 5na forming a p-n junction with the first semiconductor region, a first semiconductor pattern 10pa disposed on the first semiconductor region of the semiconductor body and having an impurity concentration higher than that of the first semiconductor region, and a second semiconductor pattern 10na disposed on the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region, a passivation structure including a first passivation layer 65a in contact with a lower surface of the semiconductor body and a second passivation layer 66a disposed under the first passivation layer. And a second passivation layer having a thickness greater than a thickness of the first passivation layer.SELECTED DRAWING: Figure 3a

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and methods for forming the same. [Background technology]

[0002] As demands for higher performance, higher speed, and / or more functionality of semiconductor devices increase, the integration level of semiconductor devices is increasing. To manufacture fine-patterned semiconductor devices that meet the trend toward higher integration of semiconductor devices, it is necessary to realize patterns with fine widths or fine separations. Furthermore, to overcome limitations in operational characteristics due to size reduction of planar metal oxide semiconductor FETs (MOSFETs), efforts are underway to develop semiconductor devices including transistors with three-dimensional channel structures. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device capable of increasing the integration density and improving the performance.

[0004] Another object of the present invention is to provide a method for forming the above semiconductor device. [Means for solving the problem]

[0005] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a transistor, a first element spaced apart from the transistor, a backside insulating structure disposed under the transistor and the first element, a front side conductive structure disposed on the transistor and the first element, a passivation structure disposed between the first element and the backside insulating structure, a backside conductive pattern disposed between the backside insulating structure and the transistor, and a backside wiring structure embedded in the backside insulating structure and electrically connected to the backside conductive pattern, wherein the transistor includes first and second source / drain patterns spaced apart from each other, active layers disposed between the first and second source / drain patterns and spaced apart from each other in a vertical direction, gate electrodes surrounding the active layers, and a gate dielectric layer between the gate electrodes and the active layer. the first element includes a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region; a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than that of the first semiconductor region; and a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type and an impurity concentration higher than that of the second semiconductor region; the passivation structure includes a first passivation layer in contact with a lower surface of the semiconductor body and a second passivation layer disposed below the first passivation layer, the second passivation layer having a thickness greater than that of the first passivation layer, and one of the first conductivity type and the second conductivity type is P-type and the other is N-type.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a transistor, a first element spaced apart from the transistor, a backside insulating structure disposed under the transistor and the first element, a front side conductive structure disposed on the transistor and the first element, a passivation structure disposed between the first element and the backside insulating structure, a backside conductive pattern disposed between the backside insulating structure and the transistor, and a backside wiring structure embedded in the backside insulating structure and electrically connected to the backside conductive pattern, wherein the transistor has a first source / drain pattern and a second source / drain pattern spaced apart from each other, and a passivation structure disposed between the first source / drain pattern and the backside wiring structure. the first element includes active layers vertically spaced apart from each other and disposed between the first and second source / drain patterns, gate electrodes surrounding the active layers, and a gate dielectric layer between the gate electrodes and the active layers, and the first element includes a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region, a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than the impurity concentration of the first semiconductor region, and a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second conductivity type and an impurity concentration higher than the impurity concentration of the second semiconductor region. At least a portion of one of the first and second semiconductor patterns is disposed at the same level as a portion of at least one of the first and second source / drain patterns, a bottom surface of the semiconductor body is disposed at a level lower than a center between an upper surface and a lower surface of the backside conductive pattern, the passivation structure includes a high-dielectric layer having a dielectric constant higher than a dielectric constant of silicon dioxide, and one of the first conductivity type and the second conductivity type is P-type and the other is N-type.

[0007] According to still another aspect of the present invention, there is provided a semiconductor device comprising: a lower base; and a semiconductor chip disposed on the lower base and electrically connected to the lower base, the semiconductor chip comprising: a transistor; a first element spaced apart from the transistor; a backside insulating structure disposed under the transistor and the first element; a front side conductive structure disposed on the transistor and the first element; a passivation structure disposed between the first element and the backside insulating structure; a backside conductive pattern disposed between the backside insulating structure and the transistor; and a backside wiring structure embedded in the backside insulating structure and electrically connected to the backside conductive pattern, the transistor comprising: a first source / drain pattern and a second source / drain pattern spaced apart from each other; the first element includes a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region; a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than that of the first semiconductor region; and a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type and an impurity concentration higher than that of the second semiconductor region; the passivation structure includes a high-dielectric layer having a dielectric constant higher than that of silicon dioxide, and one of the first conductivity type and the second conductivity type is P-type and the other is N-type. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor element including a transistor having a channel with a three-dimensional structure and an element including a semiconductor region forming a PN junction.

[0009] According to the present invention, a front conductive structure above the transistor and a back wiring structure below the transistor can be provided, which can minimize power and signal paths, thereby improving the performance of the semiconductor device.

[0010] According to the present invention, there is provided a passivation structure that contacts a lower surface of a semiconductor body including a semiconductor region of the device, and can prevent or reduce surface defects of the semiconductor body, thereby improving the performance of the device.

[0011] The various yet significant advantages and effects of the present invention are not limited to the above, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 2a] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 2b] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 3a] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 3b] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 4a] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 4b] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 5a] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 5b] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 6]1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 7a] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 7b] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 9] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 10] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 12] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 15] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 16] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 18] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1 illustrates an illustrative example of a semiconductor device according to one embodiment of the present invention. [Figure 20] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 21] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 22a] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 22b] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 23] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 24] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 25] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 26] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 27] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 28] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 29] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 30] 1 is a cross-sectional view illustrating an illustrative example of a semiconductor device according to an embodiment of the present invention. [Figure 31] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 32a] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 32b] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 33a] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 33b] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 34a] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. [Figure 34b] 1A-1D illustrate an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, terms such as "upper," "middle," and "lower" are used to describe components in the specification, replacing other terms such as "first," "second," and "third." Terms such as "first," "second," and "third" are used to describe various components, but the components are not limited by these terms, and a "first component" may be called a "second component." In the specification, terms such as "lower," "top," "top end," and "bottom end" are terms that are explained with reference to the drawings.

[0014] An illustrative example of a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1, 2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b, 6, 7a, and 7b. In Figures 1 to 7b, Figure 1 is a conceptual perspective view for describing an illustrative example of a semiconductor device 1 according to an embodiment of the present invention, Figure 2a is a plan view showing a portion of a first element region DA_A of the semiconductor device 1 according to an embodiment of the present invention, Figure 2b is a plan view showing some components of Figure 2a, Figure 3a is a cross-sectional view showing an area taken along line Ia-Ia' in Figure 2a, Figure 3b is a cross-sectional view showing an area taken along line IIa-IIa' and line IIIa-IIIa' in Figure 2a, Figure 4a is a plan view showing a portion of a second element region DA_B of the semiconductor device 1 according to an embodiment of the present invention, and Figure 4b is a cross-sectional view showing some components of Figure 4a. 5a is a cross-sectional view showing an area taken along line Ib-Ib' in FIG. 4a; FIG. 5b is a cross-sectional view showing an area taken along line IIb-IIb' and line IIIb-IIIb' in FIG. 4a; FIG. 6 is a plan view showing a portion of a transistor region CA of a semiconductor element 1 according to one embodiment of the present invention and a portion of a coupling region IA of a semiconductor element 1 according to one embodiment of the present invention; FIG. 7a is a cross-sectional view showing an area taken along line IVa-IVa' and line IVI-IVb' in FIG. 6; and FIG. 7b is a cross-sectional view showing an area taken along line V-V', line VI-VI', and line VII-VII' in FIG. 6.

[0015] First, referring to FIG. 1, a semiconductor device 1 according to an embodiment of the present invention includes a plurality of device regions DA_A, DA_B, a transistor region CA, and a connection region IA.

[0016] The plurality of element regions DA_A, DA_B include a first element region DA_A and a second element region DA_B.

[0017] The plurality of element regions DA_A and DA_B are regions including elements using PN junctions, for example, the plurality of element regions DA_A and DA_B include at least one of a first diode of an LPN (Lateral PN) type in which a side surface of a P-type semiconductor region is joined to a side surface of an N-type semiconductor region, a second diode of a VPN (Vertical PN) type in which a P-type semiconductor region is joined to an N-type semiconductor region in a vertical direction, a PNP BJT (Bipolar Junction Transistor) element, and an NPN BJT element.

[0018] The transistor region CA is a region including a transistor such as a MOSFET including a source, a drain, a channel region, and a gate. For example, the transistor region CA includes a transistor with an MBCFET (registered trademark) structure, which is a gate-all-around field effect transistor. The interconnect region IA is a region for routing input / output signals. The transistor region CA includes a front conductive structure disposed above the transistor and a back wiring structure disposed below the transistor.

[0019] Next, referring to FIGS. 2a, 2b, 3a, and 3b in addition to FIG. 1, an illustrative example of the first element region DA_A of the semiconductor element 1 will be described.

[0020] 2a, 2b, 3a, and 3b in conjunction with FIG. 1, first element region DA_A of semiconductor device 1 includes first element 15a.

[0021] The first element 15a includes a first semiconductor body 5a, a first semiconductor pattern 10pa, and a second semiconductor pattern 10na.

[0022] The first semiconductor body 5a is formed of a semiconductor material. For example, the first semiconductor body 5a includes at least one of silicon (Si), silicon germanium (SiGe), germanium (Ge), and silicon carbide (SiC). For example, the first semiconductor body 5a includes monocrystalline silicon.

[0023] The first semiconductor body 5a includes a first semiconductor region 5pa having a first conductivity type, and a second semiconductor region 5na having a second conductivity type and forming a PN junction with the first semiconductor region 5pa.

[0024] In an illustrative example, one of the first conductivity type and the second conductivity type is a P-type conductivity type, and the other is an N-type conductivity type. For example, the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type. In another example, the first conductivity type can be an N-type conductivity type, and the second conductivity type can be a P-type conductivity type.

[0025] The first semiconductor pattern 10pa is connected to the first semiconductor region 5pa on the first semiconductor region 5pa, and the second semiconductor pattern 10na is connected to the second semiconductor region 5na on the second semiconductor region 5na.

[0026] In an exemplary embodiment, a plurality of first semiconductor regions 5pa are arranged, a plurality of second semiconductor regions 5na are arranged, a plurality of first semiconductor patterns 10pa are arranged, and a plurality of second semiconductor patterns 10na are arranged.

[0027] The first semiconductor body 5a has a bar shape extending in the first direction X. The first semiconductor regions 5pa and the second semiconductor regions 5na are arranged alternately in the first direction X.

[0028] The first semiconductor patterns 10pa are disposed on the first semiconductor regions 5pa of the first semiconductor body 5a and have a first conductivity type. One of the first semiconductor patterns 10pa is disposed on one of the first semiconductor regions 5pa. The width of each of the first semiconductor patterns 10pa in the first direction X is smaller than the width of each of the first semiconductor regions 5pa in the first direction X. The first semiconductor patterns 10pa and the first semiconductor regions 5pa have the same conductivity type, for example, P-type. The first semiconductor patterns 10pa and the first semiconductor regions 5pa are doped with an impurity such as a Group 13 element of the periodic table, for example, B or Al. The impurity concentration of the first semiconductor patterns 10pa is higher than the impurity concentration of the first semiconductor regions 5pa. The first semiconductor patterns 10pa are formed of an epitaxial layer epitaxially grown on the first semiconductor body 5a. Each of the first semiconductor patterns 10pa includes at least one of silicon, silicon germanium, and germanium.

[0029] The second semiconductor patterns 10na are disposed on the second semiconductor regions 5na of the first semiconductor body 5a and have a second conductivity type. One of the second semiconductor patterns 10na is disposed on one of the second semiconductor regions 5na. The width of each of the second semiconductor patterns 10na in the first direction X is smaller than the width of each of the second semiconductor regions 5na in the first direction X. The second semiconductor patterns 10na and the second semiconductor regions 5na have the same conductivity type, for example, N-type. The second semiconductor patterns 10na and the second semiconductor regions 5na are doped with an impurity such as a Group 15 element of the periodic table, for example, P or As. The impurity concentration of the second semiconductor patterns 10na is higher than the impurity concentration of the second semiconductor regions 5na. The second semiconductor patterns 10na are formed of an epitaxial layer epitaxially grown on the first semiconductor body 5a. Each of the second semiconductor patterns 10na includes silicon.

[0030] In the illustrative example, the first semiconductor pattern 10pa includes silicon germanium, and the second semiconductor pattern 10na does not include silicon germanium.

[0031] Throughout the drawings, regions represented by N- are N-type lightly doped semiconductor regions having N-type conductivity and a relatively low impurity concentration, regions represented by P- are P-type lightly doped semiconductor regions having P-type conductivity and a relatively low impurity concentration, regions represented by N+ are N-type heavily doped semiconductor regions having N-type conductivity and a relatively high impurity concentration, and regions represented by P+ are P-type heavily doped semiconductor regions having P-type conductivity and a relatively high impurity concentration. Here, the lightly doped semiconductor regions and heavily doped semiconductor regions are defined by the relative impurity concentrations in semiconductor regions having the same conductivity type.

[0032] The first device region DA_A of the semiconductor device 1 further includes first dummy active structures 28a, 28ad. The first dummy active structures 28a, 28ad include a first edge dummy active structure 28ad and a first dummy active structure 28a between the first edge dummy active structures 28ad. Each of the first edge dummy active structures 28ad includes a first edge dummy active layer spaced apart from each other in the vertical direction Z. Each of the first dummy active structures 28a includes a first dummy active layer spaced apart from each other in the vertical direction Z. The first edge dummy active layer and the first dummy active layer of the first dummy active structures 28a, 28ad are formed of a semiconductor material. For example, the first edge dummy active layer and the first dummy active layer of the first dummy active structures 28a, 28ad include at least one of silicon, silicon germanium, germanium, and silicon carbide.

[0033] The first and second semiconductor patterns 10pa and 10na are disposed between adjacent ones of the dummy active structures 28a and 28ad. The first dummy active structure 28a is disposed between adjacent ones of the first and second semiconductor patterns 10pa and 10na. The dummy active structures 28a and 28ad are connected to the first and second semiconductor patterns 10pa and 10na.

[0034] The first element region DA_A of the semiconductor element 1 further includes an element isolation layer 25 on the side surface of the first semiconductor body 5a. The element isolation layer 25 surrounds the side surface of the first semiconductor body 5a. The element isolation layer 25 is made of an insulating material.

[0035] The first device region DA_A of the semiconductor device 1 further includes first gate structures 40a and 40ad.

[0036] The first gate structures 40a, 40ad include a first edge gate structure 40ad and a first gate structure 40a disposed between the first edge gate structures 40ad. Each of the first edge gate structures 40ad is disposed on the first semiconductor body 5a and the element isolation layer 25.

[0037] The first edge gate structures 40ad include portions that vertically overlap the first edge dummy active structures 28ad. Each of the first edge gate structures 40ad includes a gate electrode 32ad surrounding a first edge active layer of the first edge active structure 28ad, insulating spacers 35ad on side surfaces of the gate electrode 32ad, a gate dielectric layer 30ad disposed between the gate electrode 32ad and the first edge active layer of the first edge active structure 28ad, covering a lower surface of the gate electrode 32ad, and an insulating capping pattern 38ad on the gate electrode 32ad.

[0038] The first gate structures 40a vertically overlap the first dummy active structures 28a. Each of the first gate structures 40a includes a gate electrode 32a surrounding a first dummy active layer of the first dummy active structure 28a, insulating spacers 35a on side surfaces of the gate electrode 32a, a gate dielectric layer 30a disposed between the gate electrode 32a and the first dummy active layer of the first dummy active structure 28a, covering a lower surface of the gate electrode 32a, and an insulating capping pattern 38a on the gate electrode 32a.

[0039] The first gate structure 40a is disposed on the PN junction region between the first semiconductor region 5pa and the second semiconductor region 5na.

[0040] During operation of the first element 15a or when the first element 15a is turned off, a voltage capable of suppressing or preventing leakage current from flowing through the first dummy active layer of the first dummy active structure 28a disposed between the first and second semiconductor patterns 10pa and 10na is applied to the gate electrode 32a of the first gate structure 40a. For example, approximately 0 V is applied to the gate electrode 32a of the first gate structure 40a. Therefore, the first gate structure 40a can improve the performance of the first element 15a.

[0041] The first element region DA_A of the semiconductor element 1 is disposed on the first and second semiconductor patterns 10pa, 10na and the element isolation layer 25, and further includes a first interlayer insulating layer 43 disposed on the sides of the first gate structures 40a, 40ad, a second interlayer insulating layer 49 disposed on the first gate structures 40a, 40ad and the first interlayer insulating layer 43, and a front insulating structure 61 on the second interlayer insulating layer 49.

[0042] The first element region DA_A of the semiconductor element 1 further includes a first front surface conductive structure 58a.

[0043] The first front conductive structure 58a includes a first lower contact plug 46a1 that penetrates the first interlayer insulating layer 43 and is electrically connected to the first semiconductor pattern 10pa, and a second lower contact plug 46a2 that penetrates the first interlayer insulating layer 43 and is electrically connected to the second semiconductor pattern 10na.

[0044] The first front conductive structure 58a includes a first upper contact plug 52a1 that penetrates the second interlayer insulating layer 49 and is electrically connected to the first lower contact plug 46a1, and a second upper contact plug 52a2 that penetrates the second interlayer insulating layer 49 and is electrically connected to the second lower contact plug 46a2.

[0045] The first front conductive structure 58a further includes a gate contact plug 54a that penetrates the second interlayer insulating layer 49 and the insulating capping pattern 38a and is electrically connected to the gate electrode 32a.

[0046] The first front conductive structure 58a further includes, on the second interlayer insulating layer 49, a first wiring 55a1 electrically connected to the first upper contact plug 52a1, a second wiring 55a2 electrically connected to the second upper contact plug 52a2, and a gate wiring 55a3 electrically connected to the gate contact plug 54a.

[0047] The front insulating structure 61 covers the first wiring 55a1, the second wiring 55a2, and the gate wiring 55a3.

[0048] In an illustrative example, the first wiring 55a1 and the second wiring 55a2 are arranged so that the first element 15a constitutes a PN diode, as shown in FIG. 2a. However, embodiments are not limited thereto. For example, the first and second wirings 55a1 and 55a2 may be modified in various forms so that the first element 15a constitutes a PNP BJT element or an NPN BJT element. Therefore, the first element 15a may be configured as a PN diode, a PNP BJT element, or an NPN BJT element depending on the shape of the first front conductive structure 58a.

[0049] The first element region DA_A of the semiconductor element 1 further includes a backside insulating structure 92 disposed below the first element 15a and a passivation structure 65 disposed between the backside insulating structure 92 and the first element 15a.

[0050] The backside insulating structure 92 includes, in order away from the passivation structure 65, a first backside etch-stop layer 76, a first backside interlayer insulating layer 78, a second backside etch-stop layer 82, a second backside interlayer insulating layer 84, a third backside etch-stop layer 88, and a third backside interlayer insulating layer 90. The first, second, and third backside interlayer insulating layers 78, 84, and 90 include silicon oxide or a low-k dielectric having a dielectric constant lower than that of silicon oxide. The first, second, and third backside etch-stop layers 76, 82, and 88 include a material different from silicon oxide or a low-k dielectric. For example, the first, second, and third backside etch-stop layers 76, 82, and 88 include an insulating material such as SiN, SiBN, SiCN, or AlN.

[0051] The passivation structure 65 includes a first passivation layer 65a in contact with the lower surface of the first semiconductor body 5a and a second passivation layer 65b disposed below the first passivation layer 65a, the second passivation layer 65b having a thickness greater than that of the first passivation layer 65a.

[0052] In an illustrative example, the thickness of the first passivation layer 65a is in the range of 0.5 nm to 1.5 nm, and the thickness of the second passivation layer 65b is in the range of 1 nm to 100 nm.

[0053] The first passivation layer 65a includes a first dielectric, and the second passivation layer 65b includes a second dielectric having a higher dielectric constant than the first dielectric and a fixed charge. The first passivation layer 65a is an oxide layer, and the second passivation layer 65b is a high-k dielectric layer having a higher dielectric constant than the dielectric constant of silicon oxide and a fixed charge. For example, the first passivation layer 65a is a silicon oxide layer, and the second passivation layer 65b is a high-k dielectric layer having a higher dielectric constant than the dielectric constant of silicon oxide and a fixed charge. For example, the first passivation layer 65a is a silicon oxide layer, and the second passivation layer 65b is a high-k dielectric layer having a material selected from the group consisting of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3).

[0054] The first passivation layer 65a contacts the lower surface of the first semiconductor body 5a and reduces surface defects, such as dangling bonds, on the lower surface of the first semiconductor body 5a. The second passivation layer 65b is made of a high-dielectric material with a fixed charge, which affects the charge distribution near the lower surface of the first semiconductor body 5a and adjusts the surface charge density. Therefore, the second passivation layer 65b reduces the recombination probability on the lower surface of the first semiconductor body 5a.

[0055] Therefore, the passivation structure 65 including the first passivation layer 65a and the second passivation layer 65b can prevent or reduce leakage current due to generation-recombination current (GR) generated at the bottom surface of the first semiconductor body 5a of the first element 15a, thereby improving the performance of the first element 15a.

[0056] Next, with reference to FIGS. 4a, 4b, 5a, and 5b in addition to FIGS. 1 to 3b, an illustrative example of the second element region DA_B of the semiconductor element 1 will be described.

[0057] Referring to FIGS. 4a, 4b, 5a, and 5b in addition to the above-described FIGS. 1 to 3b, the second element region DA_B of the semiconductor element 1 includes a second element 15b.

[0058] The second element 15b includes a second semiconductor body 5b, a third semiconductor pattern 10pb, and a fourth semiconductor pattern 10nb.

[0059] The second semiconductor body 5b is formed of the same semiconductor material as the first semiconductor body 5a.

[0060] The second semiconductor body 5b includes a third semiconductor region 5pb having the first conductivity type, and a fourth semiconductor region 5nb having the second conductivity type and forming a PN junction with the third semiconductor region 5pb.

[0061] The third semiconductor pattern 10pb is connected to the third semiconductor region 5pb on the third semiconductor region 5pb, and the fourth semiconductor pattern 10nb is connected to the fourth semiconductor region 5nb on the fourth semiconductor region 5nb.

[0062] In an illustrative embodiment, a plurality of third semiconductor regions 5pb are arranged, a plurality of fourth semiconductor regions 5nb are arranged, a plurality of third semiconductor patterns 10pb are arranged, and a plurality of fourth semiconductor patterns 10nb are arranged.

[0063] The second semiconductor body 5b has a bar shape extending in the first direction X. The third semiconductor regions 5pb and the fourth semiconductor regions 5nb are arranged alternately in the first direction X.

[0064] The third semiconductor patterns 10pb are disposed on the third semiconductor regions 5pb of the second semiconductor body 5b and have the first conductivity type. A plurality of the third semiconductor patterns 10pb are disposed on one of the third semiconductor regions 5pb. For example, two of the third semiconductor patterns 10pb are disposed on one of the third semiconductor regions 5pb.

[0065] The width in the first direction X of each of the third semiconductor patterns 10pb is smaller than the width in the first direction X of each of the third semiconductor regions 5pb. The third semiconductor patterns 10pb and the third semiconductor regions 5pb have the same conductivity type, for example, P-type. The impurity concentration of the third semiconductor patterns 10pb is higher than the impurity concentration of the third semiconductor regions 5pb. The third semiconductor patterns 10pb are formed of an epitaxial layer epitaxially grown from the second semiconductor body 5b. Each of the third semiconductor patterns 10pb includes at least one of silicon, silicon germanium, and germanium.

[0066] The fourth semiconductor patterns 10nb are disposed on the fourth semiconductor regions 5nb of the second semiconductor body 5b and have a second conductivity type. A plurality of fourth semiconductor patterns 10nb are disposed on one second semiconductor region of the fourth semiconductor regions 5nb. For example, two fourth semiconductor patterns 10nb are disposed on one second semiconductor region of the fourth semiconductor regions 5nb. The width in the first direction X of each of the fourth semiconductor patterns 10nb is smaller than the width in the first direction X of each of the fourth semiconductor regions 5nb. The fourth semiconductor patterns 10nb and the fourth semiconductor regions 5nb have the same conductivity type, for example, N-type. The impurity concentration of the fourth semiconductor patterns 10nb is higher than the impurity concentration of the fourth semiconductor region 5nb. The fourth semiconductor patterns 10nb are formed of an epitaxial layer epitaxially grown on the second semiconductor body 5b. Each of the fourth semiconductor patterns 10nb includes silicon.

[0067] In the illustrative example, the third semiconductor pattern 10pb includes silicon germanium, and the fourth semiconductor pattern 10nb does not include silicon germanium.

[0068] In the illustrative example, the width (in the first direction X) of each of the third and fourth semiconductor patterns 10pb, 10nb is greater than the width (in the first direction X) of each of the first and second semiconductor patterns 10pa, 10na.

[0069] The second device region DA_B of the semiconductor device 1 further includes second dummy active structures 28b, 28bd. The second dummy active structures 28b, 28bd include a second edge dummy active structure 28bd and a second dummy active structure 28b between the second edge dummy active structures 28bd. Each of the second edge dummy active structures 28bd includes a second edge dummy active layer spaced apart from each other in the vertical direction Z. Each of the second dummy active structures 28b includes a second dummy active layer spaced apart from each other in the vertical direction Z. The second edge dummy active layer and the second dummy active layer of the second dummy active structures 28b, 28bd are formed of a semiconductor material. For example, the second edge dummy active layer and the second dummy active layer of the second dummy active structures 28b, 28bd include at least one of silicon, silicon germanium, and germanium.

[0070] The third and fourth semiconductor patterns 10pb and 10nb are disposed between adjacent ones of the dummy active structures 28b and 28bd. The second dummy active structure 28b is disposed between adjacent ones of the third and fourth semiconductor patterns 10pb and 10nb. The dummy active structures 28b and 28bd are connected to the third and fourth semiconductor patterns 10pb and 10nb.

[0071] The second element region DA_B of the semiconductor element 1 further includes an element isolation layer 25. The element isolation layer 25 is disposed on a side surface of the second semiconductor body 5b. The element isolation layer 25 surrounds the side surface of the second semiconductor body 5b. The element isolation layer 25 is formed of an insulating material.

[0072] The second device region DA_B of the semiconductor device 1 further includes second gate structures 40b and 40bd.

[0073] The second gate structures 40b, 40bd include a second edge gate structure 40bd and a second gate structure 40b disposed between the second edge gate structures 40bd. Each of the second edge gate structures 40bd is disposed on the second semiconductor body 5b and the element isolation layer 25.

[0074] The second edge gate structures 40bd include portions that vertically overlap the second edge dummy active structures 28bd. Each of the second edge gate structures 40bd includes a gate electrode 32bd that surrounds the second edge active layer of the second edge active structure 28bd, insulating spacers 35bd on side surfaces of the gate electrode 32bd, a gate dielectric layer 30bd that is disposed between the gate electrode 32bd and the second edge active layer of the second edge active structure 28bd, covers the lower surface of the gate electrode 32bd, and is disposed between the gate electrode 32bd and the insulating spacers 35bd, and an insulating capping pattern 38bd on the gate electrode 32bd.

[0075] The second gate structures 40b vertically overlap the second dummy active structures 28b. Each of the second gate structures 40b includes a gate electrode 32b surrounding the second dummy active layer of the second dummy active structure 28b, insulating spacers 35b on the side surfaces of the gate electrode 32b, a gate dielectric layer 30b disposed between the gate electrode 32b and the second dummy active layer of the second dummy active structure 28b, covering the lower surface of the gate electrode 32b, and an insulating capping pattern 38b on the gate electrode 32b.

[0076] The second gate structure 40b includes a 2-1 gate structure 40b1 and a 2-2 gate structure 40b2. The 2-1 gate structure 40b1 is disposed on a PN junction region between the third semiconductor region 5pb and the fourth semiconductor region 5nb. The 2-2 gate structure 40b2 is disposed in a region other than the PN junction region, i.e., on the third semiconductor region 5pb and the fourth semiconductor region 5nb.

[0077] During operation of the second element 15b or when the second element 15b is turned off, a voltage capable of suppressing or preventing leakage current from flowing to the second dummy active layer of the second dummy active structure 28b disposed between the third and fourth semiconductor patterns 10pb and 10nb is applied to the gate electrode 32b of the second-1 gate structure 40b1. For example, approximately 0 V is applied to the gate electrode 32b of the second-1 gate structure 40b1. Therefore, the second gate structure 40b can improve the performance of the second element 15b.

[0078] The second device region DA_B of the semiconductor device 1 further includes a first interlayer insulating layer 43, a second interlayer insulating layer 49, and a front insulating structure 61. The first interlayer insulating layer 43 is disposed on the second and second semiconductor patterns 10pa and 10na and the device isolation layer 25, and on the side surfaces of the second gate structures 40b and 40bd. The second interlayer insulating layer 49 is disposed on the first interlayer insulating layer 43 and the second gate structures 40b and 40bd.

[0079] The second device region DA_B of the semiconductor device 1 further includes a second front surface conductive structure 58b.

[0080] The second front conductive structure 58b includes a third lower contact plug 46b1 that penetrates the first interlayer insulating layer 43 and is electrically connected to the third semiconductor pattern 10pb, and a fourth lower contact plug 46b2 that penetrates the first interlayer insulating layer 43 and is electrically connected to the fourth semiconductor pattern 10nb.

[0081] The second front conductive structure 58b includes a third upper contact plug 52b1 that penetrates the second interlayer insulating layer 49 and is electrically connected to the third lower contact plug 46b1, and a fourth upper contact plug 52b2 that penetrates the second interlayer insulating layer 49 and is electrically connected to the fourth lower contact plug 46b2.

[0082] The second front conductive structure 58b further includes a gate contact plug 54b that penetrates the second interlayer insulating layer 49 and the insulating capping pattern 38b and is electrically connected to the gate electrode 32b.

[0083] The second front conductive structure 58b further includes, on the second interlayer insulating layer 49, a third wiring 55b1 electrically connected to the third upper contact plug 52b1, a fourth wiring 55b2 electrically connected to the fourth upper contact plug 52b2, and a gate wiring 55b3 electrically connected to the gate contact 54b.

[0084] The front insulating structure 61 covers the third wiring 55b1, the fourth wiring 55b2, and the gate wiring 55b3.

[0085] In the illustrative example, the third wiring 55b1 and the fourth wiring 55b2 are arranged so that the second element 15b constitutes a PN diode, as in FIG. 4a. However, embodiments are not limited thereto. For example, the third and fourth wirings 55b1 and 55b2 may be modified in various forms so that the second element 15b constitutes a PNP BJT element or an NPN BJT element. Therefore, the second element 15b may be constituted as a PN diode, a PNP BJT element, or an NPN BJT element depending on the shape of the second front conductive structure 58b.

[0086] The second element region DA_B of the semiconductor element 1 further includes a backside insulating structure 92 and a passivation structure 65. The backside structure 92 is disposed below the second element 15b. The passivation structure 65 is disposed between the backside insulating structure 92 and the second element 15b. The passivation structure 65 is disposed below the first element 15a and the second element 15b, and the backside insulating structure 92 is disposed below the passivation structure 65.

[0087] Similar to that described above, the passivation structure 65 includes a first passivation layer 65a in contact with the lower surface of the second semiconductor body 5b and a second passivation layer 65b disposed below the first passivation layer 65a. Thus, the passivation structure 65 located below the first element 15a can improve the performance of the first element 15a, and the passivation structure 65 located below the second element 15b can improve the performance of the second element 15b.

[0088] At least one of the first element 15a and the second element 15b with improved performance is used in a BGR (Band Gap Reference) or a temperature sensor, thereby improving the performance of the semiconductor element 1 including the BGR (Band Gap Reference) or the temperature sensor.

[0089] Illustrative examples of the transistor region CA and the coupling region IA of the semiconductor device 1 will now be described with reference to FIGS. 6, 7a and 7b in addition to FIGS. 1 to 5b.

[0090] 6, 7a, and 7b, as well as the above-described FIGS. 1 to 5b, the transistor region CA of the semiconductor device 1 includes a first transistor pTR and a second transistor nTR. The first transistor pTR is a PMOS transistor, and the second transistor nTR is an NMOS transistor.

[0091] The first transistor pTR includes a first source / drain pattern 10c1 and a second source / drain pattern 10c2 spaced apart from each other, a first active layer 28c disposed between the first source / drain pattern 10c1 and the second source / drain pattern 10c2 and spaced apart from each other in the vertical direction Z, a gate electrode 32c surrounding the first active layer 28c, and a gate dielectric layer 30c between the gate electrode 32c and the first active layer 28c. The gate dielectric layer 30c covers the bottom and side surfaces of the gate electrode 32c. The first active layer 28c is a channel layer. The first active layer 28c includes at least one of a semiconductor material, such as silicon, silicon germanium, germanium, and silicon carbide. The first source / drain pattern 10c1 and the second source / drain pattern 10c2 are formed of a semiconductor material having P-type conductivity. The first source / drain pattern 10c1 and the second source / drain pattern 10c2 include the same semiconductor material as the first semiconductor pattern 10pa and the third semiconductor pattern 10pb described above. For example, the first source / drain pattern 10c1 and the second source / drain pattern 10c2 include epitaxial silicon germanium.

[0092] The second transistor nTR includes a third source / drain pattern 10d1 and a fourth source / drain pattern 10d2 spaced apart from each other, a second active layer 28d disposed between the third source / drain pattern 10d1 and the fourth source / drain pattern 10d2 and spaced apart from each other in the vertical direction Z, a gate electrode 32d surrounding the second active layer 28d, and a gate dielectric layer 30d between the gate electrode 32d and the second active layer 28d. The gate dielectric layer 30d covers the bottom and side surfaces of the gate electrode 32d. The second active layer 28d is a channel layer. The second active layer 28d includes at least one of a semiconductor material, such as silicon, silicon germanium, germanium, and silicon carbide. The third source / drain pattern 10d1 and the fourth source / drain pattern 10d2 are formed of a semiconductor material having N-type conductivity. The third source / drain pattern 10d1 and the fourth source / drain pattern 10d2 include the same semiconductor material as the first semiconductor pattern 10na and the third semiconductor pattern 10nb described above. For example, the third source / drain pattern 10d1 and the fourth source / drain pattern 10d2 include epitaxial silicon but do not include epitaxial silicon germanium.

[0093] The first and second active layers 28c, 28d and the dummy active layers of the first and second dummy active structures 28a, 28b are disposed at the same level as each other.

[0094] At least a portion of at least one of the first to fourth source / drain patterns 10c1, 10c2, 10d1, and 10d2 is disposed at the same level as at least a portion of at least one of the first to fourth semiconductor patterns 10pa, 10na, 10pb, and 10nb.

[0095] The transistor region CA of the semiconductor element 1 further includes an insulating spacer 35c on the side of the gate electrode 32c of the first transistor pTR and an insulating capping pattern 38c on the gate electrode 32c, and further includes an insulating spacer 35d on the side of the gate electrode 32d of the second transistor nTR and an insulating capping pattern 38d on the gate electrode 32d.

[0096] The transistor region CA of the semiconductor device 1 further includes a first semiconductor layer 5c below the first transistor nTR and a second semiconductor layer 5d below the second transistor pTR. The first and second semiconductor layers 5c, 5d are formed of the same semiconductor material as the first and second semiconductor bodies 5a, 5b.

[0097] The first and second semiconductor bodies 5a, 5b are arranged at the same level and have the same thickness. The first and second semiconductor layers 5c, 5d are arranged at the same level and have the same thickness. The thickness of each of the first and second semiconductor bodies 5a, 5b is greater than the thickness of each of the first and second semiconductor layers 5c, 5d. The lower surfaces of the first and second semiconductor bodies 5a, 5b are arranged at a lower level than the lower surfaces of the first and second semiconductor layers 5c, 5d.

[0098] In the illustrative example, the passivation structure 65 is not disposed below the first and second transistors pTR, nTR.

[0099] The transistor region CA of the semiconductor device 1 further includes an isolation layer 25 , a first interlayer insulating layer 43 , a second interlayer insulating layer 49 , and a front insulating structure 61 .

[0100] The element isolation layer 25 is disposed on the side surfaces of the first and second semiconductor layers 5c and 5d. The first interlayer insulating layer 43 is disposed on the element isolation layer 25 and the first to fourth source / drain patterns 10c1, 10c2, 10d1, and 10d2. The second interlayer insulating layer 49 is disposed on the first interlayer insulating layer 43 and the insulating capping patterns 38c and 38d, and the front insulating structure 61 is disposed on the second interlayer insulating layer 49.

[0101] The transistor region CA of the semiconductor device 1 further includes a third front conductive structure 58c and a fourth front conductive structure 58d.

[0102] The third front conductive structure 58c includes a first lower contact plug 46c that penetrates the first interlayer insulating layer 43 and is electrically connected to the first source / drain pattern 10c1, a first upper contact plug 52c that penetrates the second interlayer insulating layer 46 and is electrically connected to the first lower contact plug 46c, and a first gate wiring 55c that is electrically connected to the first upper contact plug 52c on the second interlayer insulating layer 46.

[0103] The fourth front conductive structure 58d includes a second lower contact plug 46d that penetrates the first interlayer insulating layer 43 and is electrically connected to the third source / drain pattern 10d1, a second upper contact plug 52d that penetrates the second interlayer insulating layer 46 and is electrically connected to the second lower contact plug 46d, and a second gate wiring 55d that is electrically connected to the second upper contact plug 52d on the second interlayer insulating layer 46.

[0104] The transistor region CA of the semiconductor device 1 further includes a gate contact plug 54g that penetrates the second interlayer insulating layer 49 and the insulating capping pattern 38d and is electrically connected to the gate electrode 32d, and a gate wiring 55g that is electrically connected to the gate contact plug 54g on the second interlayer insulating layer 49.

[0105] The connection region IA of the semiconductor device 1 includes an element isolation layer 25, a first interlayer insulating layer 43 on the element isolation layer 25, a second interlayer insulating layer 49 on the first interlayer insulating layer 43, and a front insulating structure 61 on the second interlayer insulating layer 49.

[0106] The transistor region CA and the coupling region IA of the semiconductor device 1 further include a backside insulating structure 92. The backside insulating structure 92 is disposed below the first and second transistors pTR and nTR and the device isolation layer 25.

[0107] The back insulating structures 92 are arranged at the same level as one another in the transistor region CA, the coupling region IA, the first element region DA_A, and the second element region DA_B.

[0108] The transistor region CA of the semiconductor element 1 includes a first back conductive pattern 74a arranged between the back insulating structure 92 and the first transistor pTR and a second back conductive pattern 74b arranged between the back insulating structure 92 and the second transistor nTR.

[0109] The transistor region CA of the semiconductor device 1 further includes a buffer insulating layer 68 disposed below the lower surfaces of the first and second semiconductor layers 5c and 5d.

[0110] The first back conductive pattern 74a includes a first portion 74a2 disposed under the buffer insulating layer 68 and a second portion 74a1 extending upward from the first portion 74a2, penetrating the buffer insulating layer 68 and the first semiconductor layer 5c, and electrically connected to the second source / drain pattern 10c2. The first back conductive pattern 74a is a first back source / drain contact plug.

[0111] The second back conductive pattern 74b includes a first portion 74b2 disposed under the buffer insulating layer 68 and a second portion 74b1 extending upward from the first portion 74b2, penetrating the buffer insulating layer 68 and the second semiconductor layer 5d, and electrically connected to the fourth source / drain pattern 10d2. The second back conductive pattern 74b is a second back source / drain contact plug.

[0112] The transistor region CA of the semiconductor element 1 further includes a first dummy conductive pattern 74d1 disposed below the buffer insulating layer 68 and vertically overlapping the first source / drain pattern 10c1, and a second dummy conductive pattern 74d2 disposed below the buffer insulating layer 68 and vertically overlapping the third source / drain pattern 10d1.

[0113] The first and second rear conductive patterns 74a, 74b and the first and second dummy conductive patterns 74d1, 74d2 have coplanar bottom surfaces.

[0114] In the illustrative example, the lower surfaces of the first and second semiconductor bodies 5a, 5b are located at a level lower than the center between the respective upper and lower surfaces of the first and second back conductive patterns 74a, 74b.

[0115] At least a portion of each of the first and second backside conductive patterns 74a, 74b is arranged at the same level as at least a portion of each of the first and second semiconductor bodies 5a, 5b.

[0116] The transistor region CA of the semiconductor device 1 further includes an insulating isolation structure 71 and an insulating layer 70. The insulating isolation structure 71 extends downward through the first and second semiconductor layers 5c and 5d and the buffer insulating layer 68 disposed below the gate electrodes 32c and 32d, and the insulating layer 70 is disposed on a side of the insulating structure 71 below the buffer insulating layer 68. The first back conductive pattern 74a and the first dummy conductive pattern 74d1 are separated from each other by the insulating isolation structure 71, and the second back conductive pattern 74b and the first dummy conductive pattern 74d2 are separated from each other by the insulating isolation structure 71.

[0117] The transistor region CA of the semiconductor device 1 further includes backside wiring structures 96a and 96b embedded in the backside insulating structure 92 and electrically connected to the first and second backside conductive patterns 74a and 74b.

[0118] The rear wiring structures 96a, 96b include a first rear wiring structure 96a electrically connected to the first rear conductive pattern 74a and a second rear wiring structure 96b electrically connected to the second rear conductive pattern 74b.

[0119] The first back conductive pattern 74a is electrically connected to the first back conductive pattern 74a and includes a first-1 back wiring structure 80a that penetrates the first back etch stop layer 76 and the first back interlayer insulating layer 78, a first-2 back wiring structure 86a that penetrates the second back etch stop layer 82 and the second back interlayer insulating layer 84, and a first-3 back wiring structure 94a that penetrates the third back etch stop layer 88 and the third back interlayer insulating layer 90. The second back conductive pattern 74b is electrically connected to the second back conductive pattern 74b and includes a second-1 back wiring structure 80b that penetrates the first back etch stop layer 76 and the first back interlayer insulating layer 78, a second-2 back wiring structure 86b that penetrates the second back etch stop layer 82 and the second back interlayer insulating layer 84, and a second-3 back wiring structure 94b that penetrates the third back etch stop layer 88 and the third back interlayer insulating layer 90.

[0120] The connection region CA of the semiconductor device 1 includes a front input / output wiring structure 55io, a back input / output wiring structure 96io, and a connection contact structure 79 between the front input / output wiring structure 55io and the back input / output wiring structure 96io, electrically connecting the front input / output wiring structure 55io and the back input / output wiring structure 96io. The front input / output wiring structure 55io is disposed on the second interlayer insulating layer 49. The back input / output wiring structure 96io is embedded in at least a portion of the back insulating structure 92. For example, the back input / output wiring structure 96io includes a first back input / output wiring structure 86io that penetrates the second back etch stop layer 82 and the second back interlayer insulating layer 84, and a second back input / output wiring structure 94io that penetrates the third back etch stop layer 88 and the third back interlayer insulating layer 90. The interconnect contact structure 79 penetrates the isolation layer 25 , the first and second interlayer insulating layers 43 and 49 , and a portion of the backside insulating structure 92 .

[0121] The backside wiring structures 96a, 96b, 96io, the backside conductive patterns 74a, 74b, and the interconnecting contact structure 79 are used as paths for input / output signals, power voltages, and ground voltages.

[0122] Next, various modifications of the components of the above-described embodiments will be described. The various modifications of the components of the above-described embodiments will be described below, focusing on modified or alternative components. Here, the above-described components will be directly referenced without further detailed description, or the description will be omitted. Furthermore, the modified or alternative components described below will be described with reference to the following drawings, and the modified or alternative components may be combined with each other or with the above-described components to form a semiconductor device according to an embodiment of the present invention.

[0123] FIG. 8 is a cross-sectional view corresponding to an area taken along line Ia-Ia' in FIG. 2a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0124] 8, in an illustrative example, the first semiconductor body (5a in FIG. 3a) including the first and second semiconductor regions 5pa, 5na in FIG. 3a is replaced with a first semiconductor body 105a as shown in FIG. 8. For example, the first semiconductor body 105a includes first semiconductor regions 105pa and second semiconductor regions 105na alternately arranged in the first direction X, and a connecting semiconductor region 105pac extending from a lower region of the first semiconductor region 105pa to below the second semiconductor region 105na. Therefore, the first element 15a in FIG. 3a is replaced with a first element 115a including the first and second semiconductor patterns 10pa, 10na together with the first semiconductor body 105a.

[0125] FIG. 9 is a cross-sectional view corresponding to an area taken along line Ia-Ia' in FIG. 2a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0126] 9, in an illustrative example, the first semiconductor body (5a in FIG. 3a) including the first and second semiconductor regions 5pa, 5na in FIG. 3a is replaced with a first semiconductor body 205a as shown in FIG. 9. For example, the first semiconductor body 205a includes first semiconductor regions 205pa and second semiconductor regions 205na alternately arranged in the first direction X, and a connecting semiconductor region 205pac extending from a lower region of the second semiconductor region 205na below the first semiconductor region 205pa. Therefore, the first element 15a in FIG. 3a is replaced with a first element 215a including the first and second semiconductor patterns 10pa, 10na together with the first semiconductor body 205a.

[0127] FIG. 10 is a cross-sectional view corresponding to an area taken along line Ib-Ib' in FIG. 4a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0128] 10, in an illustrative example, the second semiconductor body (5b in FIG. 5a) including the third and fourth semiconductor regions 5pb, 5nb in FIG. 5a is replaced with a second semiconductor body 105b as shown in FIG. 10. For example, the second semiconductor body 105b includes third semiconductor regions 105pb and fourth semiconductor regions 105nb alternately arranged in the first direction X, and a connecting semiconductor region 105pbc extending from a lower region of the third semiconductor region 105pb to below the fourth semiconductor region 105nb. Therefore, the second element 15b in FIG. 5a is replaced with a second element 115b including the third and fourth semiconductor patterns 10pb, 10nb together with the second semiconductor body 105b.

[0129] FIG. 11 is a cross-sectional view corresponding to an area taken along line Ib-Ib' in FIG. 4a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0130] 11, in an illustrative example, the second semiconductor body (5b in FIG. 5a) including the third and fourth semiconductor regions 5pb, 5nb in FIG. 5a is replaced with a second semiconductor body 205b as shown in FIG. 11. For example, the second semiconductor body 205b includes third semiconductor regions 205pb and fourth semiconductor regions 205nb alternately arranged in the first direction X, and a connecting semiconductor region 205nbc extending from a lower region of the fourth semiconductor region 205nb to below the third semiconductor region 205pb. Therefore, the second element 15b in FIG. 5a is replaced with a second element 215b including the third and fourth semiconductor patterns 10pb, 10nb together with the second semiconductor body 205b.

[0131] 12 and 13 are explanatory diagrams showing an illustrative example of a semiconductor device according to one embodiment of the present invention, where FIG. 12 is a plan view showing an area corresponding to FIG. 2b, and FIG. 13 is a cross-sectional view showing an area taken along line Ia-Ia' in FIG. 12 and corresponding to the area taken along line Ia-Ia in FIG. 2b.

[0132] 12 and 13, the first semiconductor body (5a in FIG. 3a) including the first and second semiconductor regions 5pa and 5na in FIGS. 2a, 2b, and 3a is replaced with a first semiconductor body 305a as shown in FIGS. 12 and 13. For example, the first semiconductor body 305a includes a second semiconductor region 305na extending in a first direction X, first semiconductor regions 305pa disposed on both sides of the second semiconductor region 305na in the first direction X, and a connecting semiconductor region 305pac extending from a lower region of the first semiconductor region 305pa to below the second semiconductor region 305na. The first and second semiconductor patterns 10pa and 10na in FIGS. 2a, 2b, and 3a are replaced with a first semiconductor pattern 310pa disposed on the first semiconductor region 305pa and a second semiconductor pattern 310na disposed on the second semiconductor region 305na. Thus, the first element 15a in FIG. 3a is replaced by a first element 315a comprising first and second semiconductor patterns 310pa, 310na together with a first semiconductor body 305a.

[0133] 14 and 15 are explanatory diagrams showing an illustrative example of a semiconductor device according to one embodiment of the present invention, where FIG. 14 is a plan view showing an area corresponding to FIG. 2b, and FIG. 15 is a cross-sectional view showing an area taken along line Ia-Ia' in FIG. 14 and corresponding to the area taken along line Ia-Ia' in FIG. 2b.

[0134] 14 and 15, the first semiconductor body (5a in FIG. 3a) including the first and second semiconductor regions 5pa and 5na in FIGS. 2a, 2b, and 3a is replaced with a first semiconductor body 405a as shown in FIGS. 14 and 15. For example, the first semiconductor body 405a includes a first semiconductor region 405pa extending in a first direction X, second semiconductor regions 405na disposed on both sides of the first semiconductor region 405pa in the first direction X, and a connecting semiconductor region 405pac extending from a lower region 405 of the second semiconductor region 405na to below the first semiconductor region 405pa. The first and second semiconductor patterns 10pa and 10na in FIGS. 2a, 2b, and 3a are replaced with a first semiconductor pattern 410pa disposed on the first semiconductor region 405pa and a second semiconductor pattern 410na disposed on the second semiconductor region 405na. Thus, the first element 15a in FIG. 3a is replaced by a first element 415a comprising first and second semiconductor patterns 410pa, 410na together with a first semiconductor body 405a.

[0135] 16 and 17 are explanatory diagrams showing an illustrative example of a semiconductor device according to one embodiment of the present invention, where FIG. 16 is a plan view showing an area corresponding to FIG. 4b, and FIG. 17 is a cross-sectional view showing an area taken along line Ib-Ib' in FIG. 16 and corresponding to the area taken along line Ib-Ib' in FIG. 4b.

[0136] 16 and 17, the second semiconductor body (5b in FIG. 5a) including the third and fourth semiconductor regions 5pb and 5nb in FIGS. 4a, 4b, and 5a is replaced with a second semiconductor body 305b as shown in FIGS. 16 and 17. For example, the second semiconductor body 305b includes a fourth semiconductor region 305nb extending in the first direction X, third semiconductor regions 305pb disposed on both sides of the fourth semiconductor region 305nb in the first direction X, and a connection semiconductor region 305pbc extending from a lower region of the third semiconductor region 305p3 to below the fourth semiconductor region 305nb. The third and fourth semiconductor patterns 10pb and 10nb in FIGS. 4a, 4b, and 5a are replaced with a third semiconductor pattern 310pb disposed on the third semiconductor region 305pb and a fourth semiconductor pattern 310nb disposed on the fourth semiconductor region 305nb. Thus, the second element 15b in FIG. 5a is replaced by a second element 315b including third and fourth semiconductor patterns 310pb, 310nb together with a second semiconductor body 305b.

[0137] 18 and 19 are explanatory diagrams showing an illustrative example of a semiconductor device according to one embodiment of the present invention, where FIG. 18 is a plan view showing an area corresponding to FIG. 4b, and FIG. 19 is a cross-sectional view showing an area taken along line Ib-Ib' in FIG. 18 and corresponding to the area taken along line Ib-Ib' in FIG. 4b.

[0138] 18 and 19, the second semiconductor body (5b in FIG. 5a) including the third and fourth semiconductor regions 5pb and 5nb in FIGS. 4a, 4b, and 5a is replaced with a second semiconductor body 405b as shown in FIGS. 18 and 19. For example, the second semiconductor body 405b includes a third semiconductor region 405pb extending in the first direction X, fourth semiconductor regions 405nb disposed on both sides of the third semiconductor region 405pb in the first direction X, and a semiconductor region 405nbc extending from a lower region of the fourth semiconductor region 405nb to below the third semiconductor region 405pb. The third and fourth semiconductor patterns 10pb and 10nb in FIGS. 4a, 4b, and 5a are replaced with a third semiconductor pattern 410pb disposed on the third semiconductor region 405pb and a fourth semiconductor pattern 410nb disposed on the fourth semiconductor region 405nb. Thus, the second element 15b in FIG. 5a is replaced by a second element 415b including third and fourth semiconductor patterns 410pb, 410nb together with a second semiconductor body 405b.

[0139] FIG. 20 is a cross-sectional view corresponding to an area taken along line Ia-Ia' in FIG. 2a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0140] 20, the gate structures 40ad and 40a in FIGS. 3a and 3b are replaced with insulating structures 140ad and 140a. The insulating structures 140ad and 140a do not include the conductive material of the gate electrode. The insulating structures 140ad and 140a are formed of an insulating material such as silicon oxide or silicon nitride.

[0141] FIG. 21 is a cross-sectional view corresponding to an area taken along line Ib-Ib' in FIG. 4a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0142] 21, the gate structures 40bd and 40b in FIGS. 5a and 5b are replaced with insulating structures 140bd and 140b. The insulating structures 140bd and 140b do not include the conductive material of the gate electrode. The insulating structures 140bd and 140b are formed of an insulating material such as silicon oxide or silicon nitride.

[0143] FIG. 22a is a cross-sectional view corresponding to an area taken along line Ia-Ia' in FIG. 2a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0144] 22a, the gate structures 40ad, 40a and the dummy active structures 28ad, 28a in FIGS. 3a and 3b are replaced with insulating structures 240ad, 240a. The insulating structures 240ad, 240a do not include the conductive material of the gate electrode or the semiconductor material of the active layer. The insulating structures 240ad, 240a are formed of an insulating material such as silicon oxide or silicon nitride.

[0145] FIG. 22b is a cross-sectional view corresponding to an area taken along line Ib-Ib' in FIG. 4a to explain an illustrative example of a semiconductor device according to one embodiment of the present invention.

[0146] 22b, in an illustrative example, the gate structures 40bd, 40b and the dummy active structures 28bd, 28b in FIGS. 5a and 5b are replaced with insulating structures 240bd, 240b. The insulating structures 240bd, 240b do not include the conductive material of the gate electrode or the semiconductor material of the active layer. The insulating structures 240bd, 240b are formed of an insulating material such as silicon oxide or silicon nitride.

[0147] FIG. 23 is a cross-sectional view corresponding to the area taken along lines IVa-IVa' and IVb-IVb' in FIG. 6 to illustrate an illustrative example of a semiconductor element according to one embodiment of the present invention, showing a modified portion in the cross-sectional structure of FIG. 7a.

[0148] 23, in an illustrative example, the first and second back conductive patterns 74a, 74b and the first and second dummy conductive patterns 74d1, 74d2 described in FIG. 7a are replaced with first and second back conductive patterns 174a, 174b and first and second dummy conductive patterns 174d1, 174d2 having reduced thicknesses, and the insulating isolation structure 71 is replaced with an insulating isolation structure 171 having reduced thickness. For example, the bottom surfaces of the first and second back conductive patterns 174a, 174b, the first and second dummy conductive patterns 174d1, 174d2, and the insulating isolation structure 171 are disposed at a higher level than the bottom surfaces of the first and second semiconductor bodies (5a in FIG. 3a and 5b in FIG. 5a).

[0149] The first back conductive pattern 174a includes a first portion 174a2 disposed below the buffer insulating layer 68 and a second portion 174a1 extending upward from the first portion 174a2 to penetrate the buffer insulating layer 68 and the first semiconductor layer 5c and electrically connected to the second source / drain pattern 10c2. The second back conductive pattern 174b includes a first portion 174b2 disposed below the buffer insulating layer 68 and a second portion 174b1 extending upward from the first portion 174b2 to penetrate the buffer insulating layer 68 and the second semiconductor layer 5d and electrically connected to the fourth source / drain pattern 10d2.

[0150] The transistor region CA of the semiconductor device 1 further includes a first connecting wiring structure 175a between the first rear wiring structure 96a and the first rear conductive pattern 174a, electrically connecting the first rear wiring structure 96a and the first rear conductive pattern 174a, and a second connecting wiring structure 175b between the second rear wiring structure 96b and the second rear conductive pattern 174b, electrically connecting the second rear wiring structure 96b and the second rear conductive pattern 174b.

[0151] The center between the upper and lower surfaces of the first and second interconnection wiring structures 175a, 175b is positioned at a higher level than the lower surfaces of the first and second semiconductor bodies (5a in Figure 3a and 5b in Figure 5a).

[0152] The transistor region CA of the semiconductor device 1 further includes an intermediate insulating layer 175i surrounding the sides of the first and second interconnection wiring structures 175a and 175b. The upper surface of the back surface insulating structure 96a contacts the lower surface of the intermediate insulating layer 175i.

[0153] FIG. 24 is a cross-sectional view corresponding to the area taken along lines IVa-IVa' and IVb-IVb' in FIG. 6 to illustrate an illustrative example of a semiconductor element according to one embodiment of the present invention, showing a modified portion in the cross-sectional structure of FIG. 7a.

[0154] 24, in an illustrative example, the buffer insulating layer 68 described in FIG. 7a is omitted, and the first and second semiconductor layers 5c, 5d described in FIG. 7a are replaced with first and second semiconductor layers 205c, 205d arranged at the same level as the first and second semiconductor bodies (5a in FIG. 3a and 5b in FIG. 5a) and having the same thickness as the first and second semiconductor bodies (5a in FIG. 3a and 5b in FIG. 5a). An insulating isolation structure 71 penetrates the first and second semiconductor layers 205c, 205d in the vertical direction Z. The dummy conductive patterns (74d1 and 74d2 in FIG. 7a) described in FIG. 7a are omitted, the first rear conductive pattern (74a in FIG. 7a) described in FIG. 7a is replaced with a first rear conductive pattern 274a that penetrates the first semiconductor layer 205c and is electrically connected to the second source / drain pattern 10c2, and the second rear conductive pattern (74b in FIG. 7a) described in FIG. 7a is replaced with a second rear conductive pattern 274b that penetrates the second semiconductor layer 205d and is electrically connected to the fourth source / drain pattern 10d2.

[0155] FIG. 25 is a cross-sectional view corresponding to the area taken along lines IVa-IVa' and IVb-IVb' in FIG. 6 to explain an illustrative example of a semiconductor element according to one embodiment of the present invention, and shows a modified portion in the cross-sectional structure of FIG.

[0156] 25, in an illustrative example, the first and second semiconductor layers (205c and 205d in FIG. 24) and the insulating isolation structure (71 in FIG. 24) described in FIG. 24 are replaced with an insulating structure 369. The insulating structure 369 is disposed between the first and second transistors pTR and nTR and the back insulating structure 92. The first back conductive pattern (274a in FIG. 24) described in FIG. 24 is replaced with a first back conductive pattern 374a that penetrates the insulating structure 369 and is electrically connected to the second source / drain pattern 10c2, and the second back conductive pattern (274b in FIG. 24) described in FIG. 24 is replaced with a second back conductive pattern 374b that penetrates the insulating structure 369 and is electrically connected to the fourth source / drain pattern 10d2.

[0157] FIG. 26 is a cross-sectional view corresponding to the area taken along lines IVa-IVa' and IVb-IVb' in FIG. 6 to explain an illustrative example of a semiconductor element according to one embodiment of the present invention, and shows a modified portion in the cross-sectional structure of FIG.

[0158] 26 , the transistor region CA of the semiconductor device 1 further includes a first buffer semiconductor pattern 509c below and in contact with the first source / drain pattern 10c1, and a second buffer semiconductor pattern 509d below and in contact with the third source / drain pattern 10d1. The first and second buffer semiconductor patterns 509c and 509d include an epitaxial semiconductor material, for example, at least one of epitaxial germanium and epitaxial silicon germanium. The bottom and side surfaces of the first and second buffer semiconductor patterns 509c and 509d contact the insulating structure 369.

[0159] FIG. 27 is a cross-sectional view corresponding to the area taken along line Ia-Ia' in FIG. 2a to illustrate an illustrative example of a semiconductor element according to one embodiment of the present invention, showing a modified portion in the cross-sectional structure of FIG. 3a.

[0160] 27, the first element 15a described above is replaced with a first element 515a that further includes a first buffer semiconductor pattern 509pa between the first semiconductor pattern 10pa and the first semiconductor region 5pa and a second buffer semiconductor pattern 509na between the second semiconductor pattern 10na and the second semiconductor region 5na. The first buffer semiconductor pattern 509pa has the same conductivity type as the first semiconductor pattern 10pa and the first semiconductor region 5pa. The second buffer semiconductor pattern 509na has the same conductivity type as the second semiconductor pattern 10na and the second semiconductor region 5na. The first and second buffer semiconductor patterns 509pa, 509na include an epitaxial semiconductor material, for example, at least one of epitaxial germanium and epitaxial silicon germanium.

[0161] Such first and second buffer semiconductor patterns 509pa, 509na may be similarly disposed below the lower surfaces of the first and second semiconductor patterns 10pa, 10na in Figures 8, 9, 20, and 22a, the first and second semiconductor patterns 310pa, 310na in Figure 13, and the first and second semiconductor patterns 410pa, 410na in Figure 15.

[0162] FIG. 28 is a cross-sectional view corresponding to the area taken along line Ib-Ib' in FIG. 4a to illustrate an illustrative example of a semiconductor element according to one embodiment of the present invention, showing a modified portion in the cross-sectional structure of FIG. 5a.

[0163] 28, the second element 15b described above is replaced with a second element 515b that further includes a third buffer semiconductor pattern 509pd between the third semiconductor pattern 10pb and the third semiconductor region 5pb and a fourth buffer semiconductor pattern 509nb between the fourth semiconductor pattern 10nb and the fourth semiconductor region 5nb. The third buffer semiconductor pattern 509pd has the same conductivity type as the third semiconductor pattern 10pb and the third semiconductor region 5pb. The fourth buffer semiconductor pattern 509nb has the same conductivity type as the fourth semiconductor pattern 10nb and the fourth semiconductor region 5nb. The third and fourth buffer semiconductor patterns 509pb, 509nb include an epitaxial semiconductor material, for example, at least one of epitaxial germanium and epitaxial silicon germanium.

[0164] Such third and fourth buffer semiconductor patterns 509pb, 509nb may be similarly disposed below the lower surfaces of the third and fourth semiconductor patterns 10pb, 10nb in Figures 5a, 10, 11, 21, and 22b, the third and fourth semiconductor patterns 310pd, 310nb in Figure 17, and the third and fourth semiconductor patterns 410pb, 410nb in Figure 19.

[0165] Figure 29 is a cross-sectional view corresponding to the area taken along lines IVa-IVa' and IVb-IVb' in Figure 6 to explain an illustrative example of a semiconductor element according to one embodiment of the present invention, and shows a modified portion in the cross-sectional structure of Figure 26.

[0166] In an illustrative example, referring to FIG. 29, the above-mentioned first rear conductive pattern (374a in FIG. 26) is replaced with a plurality of first rear conductive patterns 674a1, 674a2, 175a, and the above-mentioned second rear conductive pattern (374b in FIG. 26) is replaced with a plurality of second rear conductive patterns 674b1, 674b2, 175b.

[0167] The plurality of first rear conductive patterns 674a1, 674a2, 175a includes a first-first rear conductive pattern 674a1 connected to the second source / drain pattern 10c2, a first-second rear conductive pattern 674a2 below the first-first rear conductive pattern 674a1, and a first-third rear conductive pattern 175a below the first-second rear conductive pattern 674a2. The plurality of second rear conductive patterns 674b1, 674b2, 175b includes a second-first rear conductive pattern 674b1 connected to the fourth source / drain pattern 10d2, a second-second rear conductive pattern 674b2 below the second-first rear conductive pattern 674b1, and a second-third rear conductive pattern 175b below the second-second rear conductive pattern 674b2.

[0168] The above-mentioned insulating structure (369 in FIG. 26) is replaced by a first insulating layer 668 surrounding the sides of the 1-1 rear conductive pattern 674a1 and the 2-1 rear conductive pattern 674b1, a second insulating layer 673 surrounding the sides of the 1-2 rear conductive pattern 674a2 and the 2-2 rear conductive pattern 674b2, and a third insulating layer 175i surrounding the sides of the 1-3 rear conductive pattern 175a and the 2-3 rear conductive pattern 175b.

[0169] FIG. 30 is an illustrative cross-sectional view showing an example of a semiconductor device according to an embodiment of the present invention.

[0170] In an illustrative example, referring to FIG. 30, a semiconductor device 901 in the illustrative example includes a lower base 701, a semiconductor chip 1a disposed on the lower base 701, and an upper chip 801 on the semiconductor chip 1a.

[0171] The lower base 701 may be a buffer chip, a logic chip, a control chip, a memory chip, an interposer, a rewiring substrate, or a printed circuit board. The lower base 701 includes a body portion 705, pads 703 on the body portion 705, and bumps 715 below the body portion 705. The body portion 705 includes circuits, rewiring, and / or through-connect wiring structures.

[0172] The semiconductor chip 1a includes a semiconductor element 1 of any one of the embodiments described in Figures 1 to 29. In Figure 30, the semiconductor chip 1a is shown as including the Ia-Ia' cross-sectional structure of Figure 3a, the IVb-IVb' cross-sectional structure of Figure 7a, and the VII-VII' cross-sectional structure of Figure 7b, as illustrative examples, but the semiconductor chip 1a may include any one of the embodiments described in Figures 1 to 29 that is not shown in Figure 30.

[0173] The semiconductor chip 1a includes a lower pad 625 under the backside wiring structure (96a in FIG. 7a, 96b, 96io in FIG. 30), an upper frontside wiring structure 62 in the frontside insulating structure 61, and an upper pad 620 on the upper frontside wiring structure 62.

[0174] The upper chip 801 is a control chip, a logic chip, or a memory chip. The upper chip 801 includes a body 805 containing a circuit and pads 803 below the body 805.

[0175] The semiconductor device 901 further includes conductive bumps 707 connecting the pads 703 of the lower base 701 to the lower pads 625 of the semiconductor chip 1a, and conductive bumps 807 connecting the upper pads 620 of the semiconductor chip 1a to the pads 803 of the upper chip 801.

[0176] Next, an illustrative example of a method for forming a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 31 and 32a to 34b. In Figures 31 and 32a to 34b, Figure 31 is a process flow diagram for explaining a method for forming a semiconductor device according to an embodiment of the present invention, Figures 32a, 33a, and 34a are cross-sectional views showing an area taken along line Ia-Ia' in Figure 2a for explaining a method for forming a semiconductor device according to an embodiment of the present invention, and Figures 32b, 33b, and 34b are cross-sectional views showing an area taken along line IVa-IVa' and line IVb-IVb' in Figure 6 for explaining a method for forming a semiconductor device according to an embodiment of the present invention.

[0177] 31, 32a, and 32b, transistors pTR and nTR and a plurality of elements 15a (15b in FIG. 5a) different from the transistors pTR and nTR can be formed. The transistors pTR and nTR are the first and second transistors pTR and nTR described in FIGS. 6, 7a, and 7b, and the plurality of elements 15a (15b in FIG. 5a) include the first element 15a described in FIGS. 2a-3b and the second element 15b described in FIGS. 3a-5b. Subsequently, semiconductor processes are performed to form the front insulating structure 61 in FIGS. 2a-7b and the upper front wiring structure 62 in FIG. 30. Subsequently, a process for reducing the thickness of the semiconductor wafer is performed to expose the bottom surface of the first semiconductor body 5a of the first element 15a and the bottom surface of the second semiconductor body (5b in FIG. 5a) of the second element (15b in FIG. 5a). Here, the remaining semiconductor layers 4c and 4d are formed below the first and second transistors pTR and nTR, and the bottom surfaces of the semiconductor layers 4c and 4d are coplanar with the bottom surfaces of the first semiconductor body 5a of the first element 15a and the second semiconductor body (5b in FIG. 5a) of the second element (15b in FIG. 5a).

[0178] Referring to Figures 31, 33a and 33b, a passivation structure 65 is formed in contact with the lower surface of the semiconductor layer (4c, 4d in Figure 32b), the lower surface of the first semiconductor body 5a of the first element 15a and the lower surface of the second semiconductor body (5b in Figure 5a) of the second element (15b in Figure 5a).

[0179] Forming the passivation structure 65 includes forming a first passivation layer 65a in contact with the lower surface of the semiconductor layer (4c, 4d in Figure 32b), the lower surface of the first semiconductor body 5a of the first element 15a, and the lower surface of the second semiconductor body (5b in Figure 5a) of the second element (15b in Figure 5a), and forming a second passivation layer 65b in contact with the first passivation layer 65a.

[0180] The first passivation layer 65a is formed of an oxide layer that reduces surface defects, such as dangling bonds, on the lower surface of the first semiconductor body 5a of the first element 15a and the lower surface of the second semiconductor body (5b in FIG. 5a) of the second element (15b in FIG. 5a). The first passivation layer 65a is formed of a high-dielectric layer that uses fixed charges to reduce surface defects on the lower surface of the first semiconductor body 5a of the first element 15a and the lower surface of the second semiconductor body (5b in FIG. 5a) of the second element (15b in FIG. 5a).

[0181] A mask pattern 66 is formed to expose the passivation structure 65 in the transistor region CA and to cover the passivation structures 65 in the first and second element regions DA_A and DA_B.

[0182] Next, an etching process is performed using the mask pattern 66 as an etching mask to etch and remove the passivation structure 65 in the transistor region CA, and the semiconductor layers (4c and 4d in FIG. 32b) are partially etched to form first and second semiconductor layers 5c and 5d with reduced thicknesses. In some embodiments, the semiconductor layers (4c and 4d in FIG. 32b) are completely etched and removed.

[0183] Referring to Figures 31, 34a and 34b, a buffer insulating layer 68 is formed to cover the lower surfaces of the semiconductor layers (4c and 4d in Figure 32b), an insulating layer (70 in Figure 7b) is formed below the buffer insulating layer 68, and an insulating isolation structure 171 is formed that penetrates the insulating layer 70, the buffer insulating layer 68 and the first and second semiconductor layers 5c and 5d in the vertical direction Z.

[0184] Subsequently, first and second rear conductive patterns 74a, 74b and first and second dummy conductive patterns 74d1, 74d2 are formed.

[0185] The first back conductive pattern 74a includes a first portion 74a2 disposed under the buffer insulating layer 68 and penetrating the insulating layer 70, and a second portion 74a1 extending upward from the first portion 74a2 to penetrate the buffer insulating layer 68 and the first semiconductor layer 5c and electrically connected to the second source / drain pattern 10c2. The second back conductive pattern 74b includes a first portion 74b2 disposed under the buffer insulating layer 68 and penetrating the insulating layer 70, and a second portion 74b1 extending upward from the first portion 74b2 to penetrate the buffer insulating layer 68 and the second semiconductor layer 5d and electrically connected to the fourth source / drain pattern 10d2.

[0186] The first dummy conductive pattern 74d1 is disposed below the buffer insulating layer 68, penetrates the insulating layer 70, and vertically overlaps the first source / drain pattern 10c1. The second dummy conductive pattern 74d2 is disposed below the buffer insulating layer 68, penetrates the insulating layer 70, and vertically overlaps the third source / drain pattern 10d1. The first back conductive pattern 74a and the first dummy conductive pattern 74d1 are separated from each other by an insulating isolation structure 171, and the second back conductive pattern 74b and the first dummy conductive pattern 74d2 are separated from each other by an insulating isolation structure 171.

[0187] The mask pattern (66 in FIG. 33a) is removed.

[0188] 1 to 7b, a rear insulating structure 92 and rear wiring structures 96a, 96b are formed. The rear wiring structures 96a, 96b include a first rear wiring structure 96a electrically connected to the first rear conductive pattern 74a and a second rear wiring structure 96b electrically connected to the second rear conductive pattern 74b.

[0189] The back surface insulating structure 92 includes a first back surface etch stop layer 76, a first back surface interlayer insulating layer 78, a second back surface etch stop layer 82, a second back surface interlayer insulating layer 84, a third back surface etch stop layer 88, and a third back surface interlayer insulating layer 90, which are formed in this order in a direction away from the passivation structure 65.

[0190] The first back conductive pattern 74a includes a first-1 back wiring structure 80a electrically connected to the first back conductive pattern 74a and penetrating the first back etch stop layer 76 and the first back interlayer insulating layer 78, a first-2 back wiring structure 86a penetrating the second back etch stop layer 82 and the second back interlayer insulating layer 84, and a first-3 back wiring structure 94a penetrating the third back etch stop layer 88 and the third back interlayer insulating layer 90. The second back conductive pattern 74b includes a second-1 back wiring structure 80b electrically connected to the second back conductive pattern 74b and penetrating the first back etch stop layer 76 and the first back interlayer insulating layer 78, a second-2 back wiring structure 86b penetrating the second back etch stop layer 82 and the second back interlayer insulating layer 84, and a second-3 back wiring structure 94b penetrating the third back etch stop layer 88 and the third back interlayer insulating layer 90.

[0191] In one embodiment, before forming the second backside etch stop layer 82, a connection contact structure 79 is formed that penetrates the element isolation layer 25, the first and second interlayer insulating layers 43, 49, the first backside etch stop layer 76, and the first backside interlayer insulating layer 78.

[0192] In some embodiments, a backside input / output wiring structure 96io is formed, electrically connected to the interconnection contact structure 79 and embedded in the backside insulating structure 92.

[0193] Although the embodiments of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0194] 1. Semiconductor element 5a First semiconductor body 5pa First semiconductor region 5na Second semiconductor region 5b second semiconductor body 5pb Third semiconductor region 5nb 4th semiconductor region 5c First semiconductor layer 5d Second semiconductor layer 10c1 First source / drain pattern 10c2 Second source / drain pattern 10d1 Third source / drain pattern 10d2 4th source / drain pattern 10pa First semiconductor pattern 10na Second semiconductor pattern 10pb Third semiconductor pattern 10nb 4th semiconductor pattern 15a First element 15b Second element 25 Element isolation layer 28a First dummy active structure 28ad First edge dummy active structure 28b Second dummy active structure 28bd Second edge dummy active structure 28c 1st active layer 28d 2nd active layer 30a, 30ad, 30b, 30bd, 30c, 30d gate dielectric layers 32a, 32ad, 32b, 35bd, 32c, 32d gate electrodes 35a, 35ad, 35b, 35bd, 35c, 35d Insulating spacers 38a, 38ad, 38b, 38bd, 38c, 38d Insulating capping patterns 40a First Gate Structure 40ad First Edge Gate Structure 40b Second Gate Structure 40bd Second Edge Gate Structure 43 First interlayer insulating layer 49 Second interlayer insulating layer 61 Front insulation structure 65 Passivation Structures 65a First passivation layer 65b Second passivation layer 68 Buffer insulation layer 70 insulating layer 71 Insulating isolation structures 74a, 74b (first, second) rear conductive patterns 79 Interlocking Contact Structure 92 Rear insulation structure 96a, 96b (1st, 2nd) Rear wiring structure pTR First transistor nTR Second transistor

Claims

1. A transistor, a first element spaced apart from the transistor; a backside insulating structure disposed below the transistor and the first element; a front conductive structure disposed over the transistor and the first element; a passivation structure disposed between the first element and the backside insulating structure; a backside conductive pattern disposed between the backside insulating structure and the transistor; a rear wiring structure embedded in the rear insulating structure and electrically connected to the rear conductive pattern; The transistor is a first source / drain pattern and a second source / drain pattern spaced apart from each other; active layers disposed between the first source / drain pattern and the second source / drain pattern and spaced apart from each other in a vertical direction; a gate electrode surrounding each of the active layers; a gate dielectric layer between the gate electrode and the active layer; The first element is a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region; a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than an impurity concentration of the first semiconductor region; a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type and an impurity concentration higher than an impurity concentration of the second semiconductor region; the passivation structure includes a first passivation layer in contact with a lower surface of the semiconductor body and a second passivation layer disposed below the first passivation layer; the second passivation layer has a thickness greater than a thickness of the first passivation layer; 1. A semiconductor device, wherein one of the first conductivity type and the second conductivity type is P-type, and the other is N-type.

2. The semiconductor device of claim 1 , wherein the passivation structure is not disposed between the backside insulating structure and the transistor.

3. the first passivation layer comprises a first dielectric; 2. The semiconductor device of claim 1, wherein the second passivation layer comprises a second dielectric having a higher dielectric constant than the first dielectric.

4. 2. The semiconductor device of claim 1, wherein at least a portion of the backside conductive pattern is disposed at the same level as at least a portion of the semiconductor body.

5. further comprising a semiconductor layer disposed between the backside insulating structure and the transistor; the first and second source / drain patterns contact the semiconductor layer; The semiconductor device of claim 1 , wherein the backside conductive pattern penetrates the semiconductor layer and is connected to the second source / drain pattern.

6. further comprising an intermediate insulating structure between the transistor and the backside insulating structure; The semiconductor device of claim 1 , wherein the backside conductive pattern penetrates the intermediate insulating structure and is connected to the second source / drain pattern.

7. 7. The semiconductor device of claim 6, further comprising a buffer semiconductor pattern contacting a lower surface of the first source / drain pattern.

8. the semiconductor body is bar-shaped and extends in a first direction; a plurality of the first semiconductor regions are arranged; a plurality of second semiconductor regions are arranged; The semiconductor device according to claim 1 , wherein the plurality of first semiconductor regions and the plurality of second semiconductor regions are alternately arranged in the first direction.

9. the semiconductor body is bar-shaped and extends in a first direction; a plurality of the first semiconductor regions are arranged; a plurality of second semiconductor regions are arranged; the plurality of first semiconductor regions and the plurality of second semiconductor regions are alternately arranged in the first direction, the semiconductor body further includes a linking semiconductor region having the first conductivity type, the linking semiconductor region extending from lower regions of the plurality of first semiconductor regions to below the plurality of second semiconductor regions; The semiconductor device according to claim 1 , wherein the plurality of second semiconductor regions are disposed on the connecting semiconductor region.

10. a plurality of the first semiconductor regions are arranged; a plurality of second semiconductor regions are arranged; a plurality of first semiconductor patterns are arranged; a plurality of second semiconductor patterns are arranged; 2. The semiconductor device of claim 1, wherein a plurality of the first semiconductor patterns are disposed on one of the first semiconductor regions.

11. a plurality of the first semiconductor regions are arranged; a plurality of second semiconductor regions are arranged; a plurality of first semiconductor patterns are arranged; a plurality of second semiconductor patterns are arranged; The semiconductor device according to claim 1 , wherein one of the plurality of first semiconductor patterns is disposed on one of the plurality of first semiconductor regions.

12. further comprising a dummy active structure disposed on the semiconductor body; a plurality of the first semiconductor regions are arranged; a plurality of second semiconductor regions are arranged; a plurality of first semiconductor patterns are arranged; a plurality of second semiconductor patterns are arranged; each of the dummy active structures is disposed between adjacent ones of the first and second semiconductor patterns; The semiconductor device of claim 1 , wherein each of the dummy active structures includes dummy active layers spaced apart from each other in the vertical direction.

13. a first gate structure on the dummy active structure; 13. The semiconductor device of claim 12, wherein each of the first gate structures includes a first gate electrode surrounding the dummy active layer, and a first gate dielectric layer between the dummy active layer and the first gate electrode.

14. further comprising a dummy insulating structure on the dummy active structure; each of the dummy insulating structures surrounds the corresponding dummy active layer; The semiconductor device of claim 12 , wherein the dummy insulating structure does not contain a conductive material at the same level as the gate electrode.

15. 13. The semiconductor device of claim 12, wherein at least a portion of one of the first and second source / drain patterns is disposed at the same level as at least a portion of one of the first and second semiconductor patterns.

16. A transistor, a first element spaced apart from the transistor; a backside insulating structure disposed below the transistor and the first element; a front conductive structure disposed over the transistor and the first element; a passivation structure disposed between the first element and the backside insulating structure; a backside conductive pattern disposed between the backside insulating structure and the transistor; a rear wiring structure embedded in the rear insulating structure and electrically connected to the rear conductive pattern; The transistor is a first source / drain pattern and a second source / drain pattern spaced apart from each other; active layers disposed between the first source / drain pattern and the second source / drain pattern and spaced apart from each other in a vertical direction; a gate electrode surrounding each of the active layers; a gate dielectric layer between the gate electrode and the active layer; The first element is a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region; a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than an impurity concentration of the first semiconductor region; a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type and an impurity concentration higher than an impurity concentration of the second semiconductor region; At least a portion of the first and second semiconductor patterns is disposed at the same level as a portion of at least one of the first and second source / drain patterns; a lower surface of the semiconductor body is disposed at a level lower than a center between an upper surface and a lower surface of the backside conductive pattern; the passivation structure includes a high-k dielectric layer having a dielectric constant higher than that of silicon dioxide; 1. A semiconductor device, wherein one of the first conductivity type and the second conductivity type is P-type, and the other is N-type.

17. the passivation structure further comprises an oxide layer between the high-k dielectric layer and the semiconductor body; 17. The semiconductor device of claim 16, wherein the oxide layer has a thickness less than the thickness of the high-k dielectric layer.

18. The lower base and a semiconductor chip disposed on the lower base and electrically connected to the lower base; The semiconductor chip comprises: A transistor, a first element spaced apart from the transistor; a backside insulating structure disposed below the transistor and the first element; a front conductive structure disposed over the transistor and the first element; a passivation structure disposed between the first element and the backside insulating structure; a backside conductive pattern disposed between the backside insulating structure and the transistor; a rear wiring structure embedded in the rear insulating structure and electrically connected to the rear conductive pattern; The transistor is a first source / drain pattern and a second source / drain pattern spaced apart from each other; active layers disposed between the first source / drain pattern and the second source / drain pattern and spaced apart from each other in a vertical direction; a gate electrode surrounding each of the active layers; a gate dielectric layer between the gate electrode and the active layer; The first element is a semiconductor body including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and forming a PN junction with the first semiconductor region; a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type and an impurity concentration higher than an impurity concentration of the first semiconductor region; a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type and an impurity concentration higher than an impurity concentration of the second semiconductor region; one of the first conductivity type and the second conductivity type is a P-type conductivity type, and the other is an N-type conductivity type; The semiconductor device, wherein the passivation structure is not disposed between the backside insulating structure and the transistor.

19. the passivation structure includes a high-k dielectric layer having a dielectric constant higher than that of silicon dioxide and an oxide layer between the high-k dielectric layer and the semiconductor body; 20. The semiconductor device of claim 18, wherein the oxide layer has a thickness less than the high-k dielectric layer.

20. At least a portion of one of the first and second source / drain patterns is disposed at the same level as at least a portion of one of the first and second semiconductor patterns; 20. The semiconductor device of claim 18, wherein at least a portion of the backside conductive pattern is disposed at the same level as at least a portion of the semiconductor body.

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