Semiconductor device

Abstract

One embodiment of the present invention achieves high mobility in a device including an oxide semiconductor and provides a highly reliable display device.SOLUTION: An oxide semiconductor layer including a crystal region in which a c-axis is aligned in a direction substantially perpendicular to a surface is formed, an oxide insulating layer in contact with the oxide semiconductor layer is formed, third heat treatment is performed to supply oxygen to the oxide semiconductor layer, a nitride insulating layer including hydrogen is formed over the oxide insulating layer, and fourth heat treatment is performed to supply hydrogen to at least an interface between the oxide semiconductor layer and the oxide insulating layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] A semiconductor device having a circuit that includes a semiconductor element such as a transistor as at least one element. For example, the present invention relates to power devices mounted on power supply circuits and memory devices. semiconductor integrated circuits including transistors, thyristors, converters, image sensors, etc., and liquid crystal display panels. The components include electro-optical devices, such as LEDs, and light-emitting display devices with organic light-emitting elements. Regarding electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, it is difficult to use a glass substrate. However, it has the drawback that it is not suitable for large areas.

[0004] For a transistor using silicon, a transistor using an oxide semiconductor is manufactured. The technology is attracting attention for its application to electronic and optical devices. For example, as an oxide semiconductor, , zinc oxide, and In-Ga-Zn-O oxide were used to fabricate transistors, and The technology used for pixel switching elements is disclosed in Patent Documents 1 and 2. do. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] Larger display devices are also becoming more common. Even in home televisions, the diagonal of the display screen is 4. Televisions ranging from 0 to 50 inches are also becoming popular.

[0007] The field-effect mobility of transistors using conventional oxide semiconductors is 10 to 20 cm 2 / Vs Transistors using oxide semiconductors are superior to amorphous silicon transistors. Since the field effect mobility is 10 times higher than that of conventional MOS transistors, the pixel shift can be reduced even in large display devices. As a switching element, sufficient performance can be obtained.

[0008] However, when a transistor using an oxide semiconductor is used as a driving device of a semiconductor device, for example, a large There is a limit to its use as a switching element in a drive circuit for a display device or the like.

[0009] One embodiment of the present invention is to provide an oxide semiconductor having excellent crystallinity that enables a substrate to have a large area. The layer is formed, and a transistor having a desired high field effect mobility can be manufactured. One of the goals is to commercialize display devices and high-performance semiconductor devices. [Means for solving the problem]

[0010] One method for increasing the field-effect mobility of a transistor is to crystallize the oxide semiconductor layer. After the first oxide semiconductor layer is formed, annealing is performed, and the second oxide semiconductor layer is formed on the upper surface of the first oxide semiconductor layer. Then, crystal growth is performed from the surface of the film toward the surface of the second oxide semiconductor layer. The crystal of the first crystal layer corresponds to a seed crystal for the second oxide semiconductor layer. It is important that a second crystal layer is formed on the upper side of the first crystal layer. The method for forming the crystal layer is effective for all oxide semiconductors that form hexagonal crystals. The crystal layer and the second crystal layer have a-axis and b-axis oriented in the channel forming region, and The first oxide semiconductor layer is a non-single-crystal layer with its c-axis oriented perpendicular to the surface of the first oxide semiconductor layer.

[0011] One method for increasing the field-effect mobility of a transistor is to increase the purity of an oxide semiconductor layer. The decomposition is carried out simultaneously with the crystallization or in a separate step. After removing hydrogen and further reducing oxygen vacancies, the oxide semiconductor layer is The oxide semiconductor layer is highly purified by supplying a sufficient amount of oxygen.

[0012] As a method for supplying oxygen to the oxide semiconductor layer, a method for forming an oxide insulating layer in contact with the oxide semiconductor layer is described below. Alternatively, heat treatment may be performed after forming an oxide insulating layer.

[0013] After supplying oxygen to the oxide semiconductor layer, an interlayer film is formed above the oxide semiconductor layer. and then, by heating, the nitride insulating film is heated to form a nitride insulating layer containing hydrogen at the interface of the oxide semiconductor layer. (Specifically, at the interface with the oxide insulating layer) or in the film, hydrogen is diffused to improve the characteristics. For example, when a silicon oxide layer (SiOx layer) is used as the oxide insulating layer, the nitride layer is formed by heating. The hydrogen diffused from the insulating film is absorbed by the dangling bonds of Si at the interface between the oxide semiconductor layer and the SiOx layer, In this case, dangling bonds such as oxygen in the oxide semiconductor are terminated. Therefore, an appropriate amount of hydrogen is intentionally added to the oxide semiconductor layer after the c-axis alignment, and the interface In this specification, "containing hydrogen" means means that the insulating layer contains more hydrogen than the insulating layer in contact with the oxide semiconductor layer. The hydrogen concentration in the insulating layer containing hydrogen is 1×10 19 atoms / cm 3 More than 1×10 22 at oms / cm 3 It is preferable to do the following:

[0014] One embodiment of the present invention disclosed in this specification is a method for forming a first oxide semiconductor layer over a substrate having an insulating surface. and performing first heat treatment to form a first oxide semiconductor layer. The crystal grows to form a crystalline region in which the c-axis is oriented in a direction substantially perpendicular to the surface, and the first oxide A second oxide semiconductor layer is formed on the oxide semiconductor layer, and a second heat treatment is performed. crystal growth from the crystalline region to crystallize at least a portion of the second oxide semiconductor layer; A conductive layer is formed on the oxide semiconductor layer, and the conductive layer is etched to form a source electrode layer and a and forming a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer. An oxide insulating layer is formed to cover the layer, and a third heat treatment is performed to form a second oxide insulating layer. Oxygen is supplied to the semiconductor layer, and a gate insulating film is formed in a region that overlaps with the second oxide semiconductor layer on the oxide insulating layer. a nitride insulating layer containing hydrogen is formed on the oxide insulating layer and the gate electrode layer; and then performing fourth heat treatment to separate at least the second oxide semiconductor layer and the oxide insulating layer. The present invention relates to a method for manufacturing a semiconductor device that supplies hydrogen to the interface between layers.

[0015] The structure obtained by the above method is also one aspect of the present invention, and the structure has an insulating surface. a first oxide semiconductor layer having a c-axis oriented in a direction perpendicular to the surface thereof on a substrate; a second oxide semiconductor layer in contact with the first oxide semiconductor layer and having a c-axis oriented in a direction perpendicular to the surface; A source electrode is formed on the oxide semiconductor layer, the first oxide semiconductor layer, and the second oxide semiconductor layer. a first oxide semiconductor layer and a second oxide insulating layer, the first oxide semiconductor layer being in contact with the first or second oxide semiconductor layer; A semiconductor having a gate electrode layer on an insulating layer and a nitride insulating layer containing hydrogen on the gate electrode layer. It is a device.

[0016] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, A first oxide insulating layer is formed to cover the electrode layer, and the gate electrode layer and the first oxide insulating layer are formed. A first oxide semiconductor layer is formed on the first oxide semiconductor layer and subjected to first heat treatment. Crystals grow from the surface of the semiconductor layer toward the inside, and the c-axis is oriented in a direction approximately perpendicular to the surface. A crystalline region is formed, a second oxide semiconductor layer is formed over the first oxide semiconductor layer, and a second process is performed. By performing heat treatment, crystals are grown from the crystalline region to form at least the second oxide semiconductor layer. a conductive layer is formed over the second oxide semiconductor layer, and the conductive layer is etched. By this, a source electrode layer and a drain electrode layer are formed, and a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer are formed. A second oxide insulating layer is formed to cover the source electrode layer and the drain electrode layer, and a third heat treatment is performed. By performing the treatment, oxygen is supplied to the second oxide semiconductor layer, and a By forming a nitride insulating layer containing hydrogen and performing a fourth heat treatment, at least the first A method for manufacturing a semiconductor device in which hydrogen is supplied to an interface between an oxide semiconductor layer and a first oxide insulating layer. do.

[0017] The structure obtained by the above method is also one aspect of the present invention, and the structure has an insulating surface. a gate electrode layer having a flat surface on a substrate; a gate insulating layer on the gate electrode layer; A second insulating layer is at least partially in contact with the first insulating layer and has a c-axis orientation perpendicular to the surface. a first oxide semiconductor layer and a second oxide semiconductor layer, the first oxide semiconductor layer being in contact with the first oxide semiconductor layer and being on the surface of the first oxide semiconductor layer; a second oxide semiconductor layer having a c-axis oriented in a direction perpendicular to the surface; and a first oxide semiconductor layer. a source electrode layer or a drain electrode layer and a second oxide semiconductor layer over the stack of the first oxide semiconductor layer and the second oxide semiconductor layer; an oxide insulating layer in contact with the nitride semiconductor layer; and a hydrogen-containing nitride insulating layer in contact with the oxide insulating layer. The semiconductor device has a layer.

[0018] The field-effect mobility of a transistor can be increased by the configuration of each of the above manufacturing methods, for example: In a display device, the switching time can be shortened and the display characteristics can be improved. [Effects of the Invention]

[0019] Whether the underlying substrate material is oxide, nitride, or metal, it can be highly We will fabricate transistors with high field effect mobility and use them in large-scale display devices and high-performance semiconductor devices. Be realized. [Brief explanation of the drawings]

[0020] [Figure 1]FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] FIG. 1 is an equivalent circuit diagram illustrating one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 12] FIG. 1 illustrates an example of an electronic device. [Figure 13] FIG. 1 illustrates an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0022] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0023] FIG. 1 is a cross-sectional view showing a transistor 150, which is an example of the configuration of a semiconductor device. The transistor 150 is an n-channel IGFET (insulator field effect transistor) in which the carriers are electrons. ed Gate Field Effect Transistor) As will be explained, it is also possible to fabricate a p-channel IGFET.

[0024] A method for fabricating the transistor 150 will be described below with reference to FIG. 2 or FIG.

[0025] First, an insulating layer 102 is formed on a substrate 100. Then, a first oxide film is formed on the insulating layer 102. a first oxide semiconductor layer, and a first heat treatment is performed to form a first oxide semiconductor layer on the surface of the first oxide semiconductor layer; The region containing the oxide semiconductor layer is crystallized to form the first oxide semiconductor layer 104 (see FIG. 2A).

[0026] The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. In particular, a large-area glass substrate can be used for mass-producing semiconductor devices according to one embodiment of the present invention at low cost. In addition, the glass substrate is preferably an alkali-free glass substrate. The alkali-free glass substrate is preferably made of, for example, aluminosilicate glass, aluminum Glass materials such as borosilicate glass and barium borosilicate glass are used. The substrate 100 may be an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, or a substrate made of silicon or the like. The surface of a semiconductor substrate made of semiconductor material is covered with an insulating material, and metal or stainless steel is used. A conductive substrate made of a conductor and having its surface covered with an insulating material can be used.

[0027] The insulating layer 102 functions as a base and is formed by using a CVD method, a sputtering method, or the like. The insulating layer 102 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. It is formed to contain silicon, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 102 may have either a single-layer structure or a stacked-layer structure. The thickness of the insulating layer 102 is not particularly limited, but is set to, for example, 10 nm or more and 500 nm or less. The insulating layer 102 is not an essential component, so the insulating layer 102 may be omitted. It is also possible to have a configuration in which this is not the case.

[0028] The first oxide semiconductor layer formed on the insulating layer 102 is a ternary metal oxide, In-M X -Zn Y -O Z Even if oxide semiconductor materials expressed by (Y=0.5~5) are used, Here, M is one of gallium (Ga), aluminum (Al), boron (B), etc. It represents one or more elements selected from the group 3 elements. Note that In, M, Zn, and O The content of is arbitrary, including the case where the content of M is zero (i.e., X=0). The content of In and Zn is not zero. That is, the above notation includes In-Ga-Zn-O and These include In-Zn-O.

[0029] In addition, the first oxide semiconductor layer may be made of a quaternary metal oxide, In-Sn-Ga-Z nO, and ternary metal oxides such as In-Sn-Zn-O, Sn-Ga-Zn-O, and Al -Ga-Zn-O, Sn-Al-Zn-O, and binary metal oxides such as Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O and single-component metal oxides Materials such as In-O, Sn-O, and Zn-O can also be used.

[0030] In this embodiment, the first oxide semiconductor layer is an In—Ga—Zn—O-based oxide semiconductor material. The film is formed by sputtering using a film target.

[0031] Examples of targets for forming the first oxide semiconductor layer by sputtering include oxide A target for forming an oxide semiconductor film containing zinc as a main component can be used. The composition ratio of the oxide semiconductor film formation target containing Ga and Zn is In:Ga:Zn= The formula is 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In:Ga:Zn= 1:1:1 [atom ratio] (x=1, y=1) (i.e., In2O3:Ga2O3:Z A target having a composition ratio of nO=1:1:2 (molar ratio) may also be used. The oxide semiconductor film deposition target was In:Ga:Zn=1:1:0.5 [atomic ratio] or a target having a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio], A ternary quartz crystal with a composition ratio of In:Ga:Zn=1:0:1 (atom ratio) (x=0, y=1) In this embodiment, a first oxide semiconductor is formed by performing heat treatment later. In order to intentionally crystallize the oxide layer, a target for oxide semiconductor film formation that is prone to crystallization is used. It is preferable to use

[0032] The relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 90% or more. 5% or more, more preferably 99.9% or more. For forming oxide semiconductor films with high relative density By using the target, a dense first oxide semiconductor layer is formed. In this embodiment, the first oxide semiconductor layer is intentionally crystallized by performing heat treatment later. It is preferable to use a target for forming an oxide semiconductor film that is likely to crystallize.

[0033] The atmosphere for forming the first oxide semiconductor layer may be a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, for example, the concentration of impurities such as hydrogen, water, hydroxyl groups, and hydrides is about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to a few ppb. .

[0034] When the first oxide semiconductor layer is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the sputtering gas from which hydrogen and water have been removed is used to remove the remaining moisture in the processing chamber. The first oxide semiconductor layer is formed using a metal oxide as a target without heating the substrate. By forming the first oxide semiconductor layer, impurities contained in the first oxide semiconductor layer can be removed. The first oxide semiconductor can reduce damage caused by sputtering. Moisture remaining in the sputtering equipment before, during, or after the deposition of the layer It is preferable to remove the residual moisture in the processing chamber. It is preferable to use a pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. A cold trap can be attached to the turbo pump. The processing chamber evacuated using a cryopump contains hydrogen, water, etc. Since the impurities are removed, the impurity concentration of the first oxide semiconductor layer can be reduced.

[0035] Before the first oxide semiconductor layer is formed, moisture remaining in the sputtering apparatus is removed. It is advisable to perform a preheating process to remove the ions. A method of heating to 200℃-600℃ under reduced pressure, or introducing nitrogen or inert gas while heating, After the preheating process is completed, the substrate or sputtering equipment is cooled. After cooling, the oxide semiconductor layer is formed without being exposed to the air. It is better to use oil or fat as the cooling liquid instead of water. This will have a certain effect, but it is even better if you do it while heating.

[0036] The conditions for forming the first oxide semiconductor layer include, for example, a distance between the substrate and the target of 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen flow rate It is possible to apply conditions such as a 100% ratio atmosphere. ) power supply, powdery substances (also called particles or dust) generated during film formation can be reduced. This is preferable because it reduces the variation in the film thickness. It is preferable that the thickness is 15 nm or less, and in this embodiment, it is set to 5 nm as an example. However, the appropriate thickness varies depending on the oxide semiconductor material and application, and the thickness is The material may be selected depending on the material used and the application.

[0037] In addition, the first oxide semiconductor layer is crystallized by performing first heat treatment. The region including the surface of the oxide semiconductor layer is crystallized to form the first oxide semiconductor layer 104. Furthermore, the first heat treatment can remove water (including a hydroxyl group) from the first oxide semiconductor layer. The temperature of the first heat treatment is 450°C or higher and 850°C or lower. Preferably, the temperature is 550°C or higher and 750°C or lower. The heating time is 1 minute or higher and 24 hours or lower. In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After heat treatment and dehydration or dehydrogenation, the atmosphere is switched to an oxygen atmosphere. This allows oxygen to be supplied to the inside of the first oxide semiconductor layer.

[0038] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1pp It is preferable that the concentration of H2O is 20 ppm or less, preferably 0.1 ppm or less. In dry air with a concentration of 1 ppm or less of H2O, more preferably in dry air with a concentration of 1 ppm or less of H2O, By such first heat treatment, the first oxide semiconductor layer 1 It is possible to remove water (including hydroxyl groups) and hydrogen from 04.

[0039] A first oxide semiconductor having a crystalline region at least in a region including a surface thereof by a first heat treatment. The crystalline region formed in the region including the surface is a layer 104. The crystal region is formed by crystal growth. The average thickness of the crystal region is 2 nm to 10 nm. The crystal region has a c-axis oriented in a direction substantially perpendicular to the surface. Here, "substantially perpendicular" refers to a state within ±10° from the perpendicular direction. This shall be the case.

[0040] The heat treatment device used for the first heat treatment is not particularly limited, and may be a heat treatment device that uses a heat source such as a resistance heat source. A device that heats the object to be treated by thermal conduction or thermal radiation from the object can be used. For example, electric furnaces and LRTA (Lamp Rapid Thermal Anneal) RTA equipment, GRTA (Gas Rapid Thermal Anneal) equipment, etc. A Rapid Thermal Anneal (LRTA) device can be used. The lamps are halogen lamps, metal halide lamps, xenon arc lamps, and carbon arc lamps. of light (electromagnetic waves) emitted from lamps such as high-pressure sodium lamps and high-pressure mercury lamps. This is a device that heats the object to be treated by radiation. The GRTA device uses high-temperature gas for heating. It is a device that performs processing.

[0041] Next, a crystalline layer is formed on the first oxide semiconductor layer 104 having a crystalline region at least in a region including a surface thereof. A second oxide semiconductor layer 105 is formed (see FIG. 2B).

[0042] The second oxide semiconductor layer 105 is a quaternary metal oxide, similar to the first oxide semiconductor layer. In-Sn-Ga-Zn-O, which is a ternary metal oxide, and In-Ga-Zn-O, which is a ternary metal oxide. -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn- O, Sn-Al-Zn-O, and binary metal oxides In-Zn-O and Sn-Zn-O , Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using oxides such as In-O, Sn-O, and Zn-O.

[0043] The second oxide semiconductor layer 105 is made of a material having the same main component as the first oxide semiconductor layer 104. or the same crystal structure and close lattice constants (there is no mismatch in the lattice constants) 1% or less). Alternatively, it may be formed using materials with different main components. .

[0044] When materials having the same main component are used, the second oxide semiconductor layer 105 is crystallized later. In this case, crystal growth can be easily performed using the crystals in the crystalline region of the first oxide semiconductor layer 104 as seed crystals. In addition, the effective film thickness can be increased, making it suitable for applications such as power devices. Furthermore, when the materials are the same main component, the interface properties such as adhesion and electrical The mechanical properties are also good.

[0045] In this embodiment, the second oxide semiconductor layer 105 is made of an In—Ga—Zn—O-based oxide semiconductor. The second oxide semiconductor layer 10 is formed by sputtering using a target for forming a conductive film. The film formation by sputtering in step 5 is the same as the film formation by sputtering in step 1 of the first oxide semiconductor layer described above. However, the thickness of the second oxide semiconductor layer 105 is set to be equal to that of the first oxide semiconductor layer. The thickness of the first oxide semiconductor layer 104 is preferably larger than that of the second oxide semiconductor layer 104. The second oxide semiconductor layer 105 is formed so that the total thickness of the oxide semiconductor layer 105 is 3 nm or more and 50 nm or less. It is preferable to form an oxide semiconductor layer 105. The appropriate thickness varies depending on the material and application, so the thickness should be selected according to the material and application. That's fine.

[0046] Next, the second oxide semiconductor layer 105 is subjected to second heat treatment, and the first oxide semiconductor layer 10 The crystal region of the fourth oxide semiconductor layer is used as a seed crystal region for crystal growth to form the second oxide semiconductor layer 106. (See Figure 2(C)).

[0047] The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heating time of the second heat treatment is 1 minute to 100 hours, preferably 5 hours. The time limit is from 10 to 20 hours, typically 10 hours.

[0048] In the second heat treatment, nitrogen, oxygen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, and preferably 7N (99.999999%) or more. In addition, in dry air with H2O of 20 ppm or less, more preferably in dry air with H2O of 1 ppm or less The second heat treatment may be carried out in dry air under the following conditions. Water (including a hydroxyl group), hydrogen, and the like in the second oxide semiconductor layer 106 can be removed. Therefore, the first oxide is highly purified by reducing impurities and is made i-type or substantially i-type. The semiconductor layer 104 and the second oxide semiconductor layer 106 can be formed.

[0049] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise of the second heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be switched to a nitrogen atmosphere, and after dehydration or dehydration is performed in a nitrogen atmosphere, The atmosphere is then changed to an oxygen atmosphere, thereby introducing oxygen into the second oxide semiconductor layer 106. can be supplied.

[0050] In this manner, by performing the second heat treatment, the second oxide semiconductor layer 105 and the first oxide semiconductor layer 106 are bonded to each other. The entire second oxide semiconductor layer 105 is formed from the crystalline region formed at the interface of the oxide semiconductor layer 104. The second oxide semiconductor layer 106 can be formed by crystallization. Therefore, the first oxide semiconductor layer 104 is made of a crystalline layer having a higher degree of crystal orientation. It is possible.

[0051] The oxide semiconductor layer is InMO3(ZnO) m (m>0 and m is not a natural number) The thin film described below can be used, where M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co. Also, InGa x Zn y O z Using a material expressed as Here, x, y, and z are arbitrary numbers. Also, x, y, and z are integers. It is not necessary for x to be 0, and it can be a non-integer. For example, this notation includes In—Zn—O crystals where x is 0. In addition, the crystal represented by In-Ga-Zn-O in this specification is InGaO3 (ZnO ) m (m>0 and m is not a natural number), and the fact that m is not a natural number is This can be confirmed using RBS analysis. Also, it is expressed as x=1, y=1. This includes crystals with x=1, y=0.5. The heat treatment causes the c-axis to be oriented in a direction substantially perpendicular to the surface of the second oxide semiconductor layer 106. The orientation is as follows.

[0052] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or or Zn-containing layers) are stacked in the c-axis direction. The oxide semiconductor layer includes a region having crystallinity, and the region having crystallinity is a- It consists of crystals whose b-plane is approximately parallel to the film surface and whose c-axis is approximately perpendicular to the film surface. The crystalline region included in the oxide semiconductor layer is c-axis oriented. Since the oxide semiconductor layer includes a region having crystallinity in which the c-axis is oriented, the oxide semiconductor layer is s Aligned Crystalline Oxide Semiconductor That is, the oxide semiconductor layer including the crystalline region is non-crystalline. It is crystalline, and the entire film is not in an amorphous state.

[0053] In the In-Ga-Zn-O oxide semiconductor crystal, the a-axis and The conductivity in the direction parallel to the b-axis is good. In semiconductor crystals, electrical conduction is mainly controlled by In, and The 5s orbital of In overlaps with the 5s orbital of the adjacent In, forming a carrier path. It depends on what is achieved.

[0054] In addition, the first oxide semiconductor layer 104 may have an amorphous region at the interface with the insulating layer 102. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 104. Crystal growth occurs from the crystalline region formed on the first oxide semiconductor layer 104 toward the bottom surface of the first oxide semiconductor layer 104. In some cases, the amorphous region is crystallized. Depending on the processing conditions, the amorphous region may remain.

[0055] The first oxide semiconductor layer 104 and the second oxide semiconductor layer 105 are made of oxide semiconductors having the same main component. When a crystalline material is used, as shown in FIG. 2C, the crystal of the first oxide semiconductor layer 104 is crystalline. The crystals were grown upward toward the surface of the second oxide semiconductor layer 105 as seed crystals for crystal growth. Then, a second oxide semiconductor layer 106 is formed, and the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 are interdigitated. The compound semiconductor layer 106 has the same crystal structure. However, the boundary between the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 becomes indistinguishable. Therefore, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 can be regarded as the same layer. It also says:

[0056] The heat treatment device used for the second heat treatment is also used under the same conditions as those for the first heat treatment. can be done.

[0057] Next, the first oxide semiconductor layer 104 and the The second oxide semiconductor layer 106 is processed to form an island-shaped first oxide semiconductor layer 104a and an island-shaped A second oxide semiconductor layer 106a is formed (see FIG. 2D).

[0058] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0059] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), Carbon tetrachloride (CCl4, etc.) and gases containing fluorine (fluorine-based gases, e.g. For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and A gas to which a rare gas such as uranium (He) or argon (Ar) is added may also be used.

[0060] The etching solution that can be used for wet etching is phosphoric acid, acetic acid, and nitric acid. There are also etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.). It may be used.

[0061] Next, the conductive layer 108 is formed so as to be in contact with the island-shaped second oxide semiconductor layer 106a (FIG. 2(E)).

[0062] The conductive layer 108 is formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 108 can be formed using a method such as a metal thin film deposition (MgSO 4 ) or a metal thin film deposition (MgSO 4 ). An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements The conductive layer 108 can be formed using an alloy containing manganese, ma Materials containing one or more of magnesium, zirconium, and beryllium may also be used. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, A material containing one or more elements selected from odymium and scandium may also be used. Other materials for the conductive layer 108 include titanium nitride and tantalum nitride, which have high barrier properties. A material with high barrier properties, such as titanium nitride or tantalum nitride, may be used as the island-shaped first layer. By using the second oxide semiconductor layer 106a in contact with the second oxide semiconductor layer 106b, the second oxide semiconductor layer 106a can be formed as an island-shaped It is possible to prevent impurities from entering 106a and to prevent adverse effects on transistor characteristics. .

[0063] The conductive layer 108 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0064] The conductive layer 108 may be formed by depositing an aluminum layer on a titanium layer and a titanium layer on the aluminum layer. It is preferable that the metal conductive film has a three-layer structure in which aluminum is laminated. Two-layer laminated structure consisting of a rubber layer and a tungsten layer, two-layer laminated structure consisting of a copper layer and a tungsten layer It can also be a laminated structure of two layers, one of which is an aluminum layer and the other is a molybdenum layer. Of course, the metal conductive film may have a single layer or a laminated structure of four or more layers. A single layer structure of titanium film is applied. When a single layer structure of titanium film is used, it is possible to prevent the film from being damaged during subsequent etching. Etching that forms a good tapered shape can be achieved.

[0065] Next, the conductive layer 108 is selectively etched to form the source electrode layer 108a and the drain electrode layer 108b. The pole layer 108b is formed (see FIG. 3(A)).

[0066] For exposure when forming the mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. Therefore, the channel length (L) of the transistor to be formed later can be It is also possible to make the thickness between 10 nm and 1000 nm (1 μm). By reducing the channel length, the operating speed can be improved. Since transistors using semiconductors have extremely low off-state current, power consumption can be reduced by miniaturization. The increase can be suppressed.

[0067] When the conductive layer 108 is etched, the island-shaped second oxide semiconductor layer 106a is not removed. The materials and etching conditions are adjusted appropriately so that the Depending on the etching conditions, in this step, a part of the island-shaped second oxide semiconductor layer 106a may be In some cases, the oxide semiconductor layer is etched to have a groove (depression).

[0068] In addition, the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 106a In the side surface of the semiconductor substrate, the portion in contact with the source electrode layer 108a or the drain electrode layer 108b is It may also be in an amorphous state.

[0069] Next, a film of the second oxide semiconductor layer 106a in contact with the island-shaped film was removed without exposing the film to the air. The gate insulating layer 112 is formed by a CVD method (see FIG. 3(B)). The gate insulating layer 112 can be formed by a silicon oxide method, a sputtering method, or the like. , silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 112 may have a single-layer structure. In the case of using a stacked structure, the layer in contact with the oxide semiconductor may be The thickness of the gate insulating layer 112 is not particularly limited. Although not limited thereto, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 2 00 nm or less.

[0070] In this embodiment, a silicon oxide film is formed in an oxygen atmosphere by sputtering to form a gate insulating film. When the gate insulating layer 112 is formed, oxygen is introduced into the second oxide semiconductor layer 112. Oxygen can be supplied by adding it to a portion of 106a.

[0071] The gate insulating layer 112 is 1×10 11 / cm 3 Plasma density above Using a high-density plasma device, a dense, high-quality gate insulating layer with high dielectric strength can be formed. good.

[0072] Thereafter, it is desirable to carry out a third heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is 200°C or higher and 450°C or lower, preferably 250°C or higher and 350°C or lower. For example, heat treatment may be performed at 250° C. for 1 hour in an atmosphere containing oxygen. When the third heat treatment is performed, oxygen is supplied to the island-shaped second oxide semiconductor layer 106a, and the island-shaped Oxygen vacancies in the second oxide semiconductor layer 106a can be reduced.

[0073] Next, the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 104b on the gate insulating layer 112 are A gate electrode layer 114 is formed in a region overlapping with the nitride semiconductor layer 106a (see FIG. 3C). The gate electrode layer 114 is formed by forming a conductive layer on the gate insulating layer 112 and then insulating the conductive layer. can be formed by selectively patterning.

[0074] The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed using aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or a material containing the above elements. The alloy may be formed using titanium nitride, which is a nitride of the above-mentioned elements. It may be formed using manganese, magnesium, zirconium, etc. Alternatively, a material containing one or more of aluminum and beryllium may be used. , titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Materials containing one or more selected elements may also be used.

[0075] Next, an interlayer insulating layer 116 containing hydrogen is formed on the gate insulating layer 112 and the gate electrode layer 114. After forming the insulating film containing hydrogen, a fourth heat treatment is performed (see FIG. 3(D)). The hydrogen concentration in layer 116 is 1×10 19 atoms / cm 3 More than 1×10 22 atoms / cm 3 The interlayer insulating layer 116 containing hydrogen is preferably formed by using a CVD method or the like. In this embodiment, the nitride insulating layer obtained by the CVD method can be formed. One of these is a silicon nitride film.

[0076] The fourth heat treatment is carried out in a nitrogen atmosphere at a temperature of 150° C. or higher and 450° C. or lower, preferably 250° C. or higher. The temperature is set to 440° C. or lower. The fourth heat treatment is not limited to a nitrogen atmosphere, but may be performed in an oxygen atmosphere. , a rare gas atmosphere, or a dry air atmosphere.

[0077] The fourth heat treatment after forming the interlayer insulating layer 116 containing hydrogen is performed to remove the hydrogen contained in the interlayer insulating layer 116. The hydrogen is diffused to form the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 104b. Defects in the semiconductor layer 106a (for example, dangling bonds such as oxygen in the oxide semiconductor) This is a process to terminate the dangling bonds of Si at the interface. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 112 are formed on the first oxide semiconductor layer 104a and the second oxide semiconductor layer 112, respectively. In the oxide semiconductor layer 106a or between the oxide semiconductor layer and the SiOx layer (gate insulating layer), Hydrogen can be diffused to the interface of the layer 112).

[0078] As a result, island-shaped crystals formed by crystal growth from the crystalline regions of the island-shaped first oxide semiconductor layer 104a were obtained. The second oxide semiconductor layer 106a is used to diffuse hydrogen contained in the interlayer insulating layer 116, thereby forming a defect. The transistor 150 is completed with the recess terminated.

[0079] Next, an interlayer insulating layer 118 is formed on the interlayer insulating layer 116, resulting in the cross-sectional structure shown in FIG. The interlayer insulating layer 118 is made of silicon oxide or silicon nitride oxide obtained by a PVD method, a CVD method, or the like. , silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, and other inorganic insulating materials. The interlayer insulating layer 118 is formed using a material such as polyimide, acrylic, Organic resins such as benzocyclobutene, polyamide, and epoxy can also be used. In this embodiment, the interlayer insulating layer 116 and the interlayer insulating layer 118 are stacked. One embodiment of the present invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. That's fine.

[0080] It is desirable that the interlayer insulating layer 118 be formed so that its surface is flat. By forming the interlayer insulating layer 118 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 118. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0081] The transistor 150 shown in FIG. 1 is an island-shaped transistor provided on a substrate 100 with an insulating layer 102 interposed therebetween. The first oxide semiconductor layer 104a and the island-shaped oxide semiconductor layer 104b provided on the first oxide semiconductor layer 104a The island-shaped second oxide semiconductor layer 106a and the island-shaped second oxide semiconductor layer 106a are electrically connected to each other. The source electrode layer 108a and the drain electrode layer 108b are electrically connected to each other, and the island-shaped second covering the oxide semiconductor layer 106a, the source electrode layer 108a, and the drain electrode layer 108b. It has a gate insulating layer 112 and a gate electrode layer 114 on the gate insulating layer 112 .

[0082] In addition, the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 106a So, what is the carrier concentration in a typical silicon wafer (1×10 14 / cm 3 degree) compared to In comparison, a sufficiently small value of carrier concentration (e.g., 1×10 12 / cm 3 Less than, more preferred Or 1.45 x 10 10 / cm 3 Also, the drain voltage is set to 1V to 10V. V, the channel length is 10 μm, and the total thickness of the oxide semiconductor layer is When the total film thickness is 30 nm, the off-state current (when the voltage between the gate and source is 0 V or less) The current flowing between the source and drain of -13 A or less, or off current density (off The current divided by the transistor channel width is 100 aA (a (atom) is 10 -18 ) / μm or less, preferably 10 aA / μm or less, and more preferably 1 aA / μm or less If the values ​​of the off-state current and drain voltage are known, then it is possible to The resistance value when the transistor is off (off resistance R) can be calculated from the channel shape. If the cross-sectional area A of the formed region and the channel length L are known, the off-resistance can be calculated from the equation ρ=RA / L (R is the off-resistance). The resistivity ρ can also be calculated. The off-resistivity is 1×10 9 Ω·m or more (or 1×10 1 0 Here, the cross-sectional area A is the thickness of the channel forming region, d, and the When the width of the hole is W, it can be calculated as A=dW.

[0083] In addition, hydrogen contained in the interlayer insulating layer 116 is removed by heating to form island-shaped first oxide semiconductor layers 104a In addition, the amount of hydrogen diffused into the island-shaped second oxide semiconductor layer 106a is determined depending on the amount of hydrogen diffused. For example, the carrier concentration is 1×10 14 / cm 3 More than 1×10 18 / cm 3 Less than do.

[0084] The off-state current of an amorphous silicon transistor is 1×10 -12 While it is about A The off-state current of a transistor including an oxide semiconductor is 1 / 10,000 or less of that of the oxide semiconductor. In this way, by using an i-type or substantially i-type oxide semiconductor, extremely excellent Therefore, the transistor 150 can have good off-state current characteristics.

[0085] In addition, the materials of the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 106a are When the same material is used (so-called homo-epitaxial growth), the island-shaped first oxide semiconductor layer 1. Therefore, the boundary between the second oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 106a cannot be distinguished. As indicated by the dotted lines, the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 1 06a can be regarded as the same layer (see Figure 1). Both the layer 104a and the island-shaped second oxide semiconductor layer 106a are non-single-crystal.

[0086] Of course, the island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 106a The island-shaped first oxide semiconductor layer 104a and the island-shaped second oxide semiconductor layer 104b may be made of different materials. When the oxide semiconductor layer 106a is made of a different material (so-called hetero epitaxial growth), In this case, for example, the island-shaped first oxide semiconductor layer 104a is doped with In, which is a binary metal oxide. The island-shaped second oxide semiconductor layer 106a is made of In—Zn—O, and the ... A structure using Ga—Zn—O or the like can be adopted.

[0087] In addition, a region of the oxide semiconductor layer that serves as a channel formation region has at least a flat surface. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer preferably have the same c The second oxide semiconductor layer is a non-single-crystal body with an axial orientation. In the region overlapping with the electrode layer (channel forming region), the thickness is 1 nm or less (preferably 0.2 nm or less).

[0088] (Embodiment 2) In Embodiment 1, an example of manufacturing a top-gate transistor is shown. A manufacturing example of a bottom-gate transistor will be described.

[0089] First, a conductive film is formed on a substrate having an insulating surface, and then a photolithography is performed using a photomask. A gate electrode layer 401 is formed by a lithography process.

[0090] The substrate 400 may be made of aluminosilicate glass, aluminoborosilicate glass, barium A glass material such as borosilicate glass, a silicon substrate, a quartz substrate, or the like is used.

[0091] In this embodiment, a glass substrate is used as the substrate 400, and a substrate for bonding an oxide semiconductor layer to be formed later is used. To heat the substrate for crystallization, the substrate was heated twice at 650°C for 6 minutes. By heating the substrate before film formation, film peeling due to substrate shrinkage and the position of the mask can be prevented. Reduce the shift.

[0092] In addition, an insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The layer has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of silicon nitride, silicon oxide, A laminated structure of one or more layers selected from silicon nitride oxide or silicon oxynitride It can be formed.

[0093] A metal conductive layer can be used as the gate electrode layer 401. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the elements mentioned above. It is preferable to use an alloy containing the above elements or an alloy combining the above elements. A three-layer stack consisting of an aluminum layer on a titanium layer and a titanium layer on the aluminum layer. Of course, the metal conductive layer may be a single layer, a two-layer structure, or a four-layer structure. In the case where heat treatment is performed later, the gate electrode layer 401 may have a stacked structure of more than one layer. It is preferable to select a material that can withstand the heat treatment temperature.

[0094] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 is A silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, or the like is formed by using a plasma CVD method or a sputtering method. The silicon nitride layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a silicon nitride film and a silicon oxide film are stacked. The upper limit is 200 nm or less.

[0095] In this embodiment mode, the gate insulating layer 402 is formed using a high-density plasma apparatus. Here, the high-density plasma device is 1×10 11 / cm 3 Plasma density above For example, a device that generates plasma by applying microwave power of 3kW to 6kW. This allows the formation of an insulating film.

[0096] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and insulating materials such as glass are An insulating film is formed on a substrate having a surface. Then, monosilane gas (SiH4) is supplied. Nitrous oxide (N2O) and rare gases are introduced without exposing the insulating film to the atmosphere. Plasma treatment may be performed. At least nitrous oxide (N2O) and rare gases are introduced to provide insulation. The plasma treatment on the film surface is carried out after the insulating film is formed. The insulating film is thin, and reliability can be ensured even if it is less than 100 nm. It is an insulating film.

[0097] In this embodiment, the gate insulating layer 402 is formed by a high density plasma device. A silicon oxynitride film (also called SiOxNy, where x>y>0) is used.

[0098] Next, a first oxide semiconductor layer having a thickness of 2 nm to 15 nm is formed on the gate insulating layer 402. The first oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere. The sputtering is carried out under an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen. In this embodiment, a heat treatment is performed later to intentionally form a crystal. In order to crystallize the oxide semiconductor film, it is preferable to use a target for forming an oxide semiconductor film that is prone to crystallization. stomach.

[0099] Next, the first oxide semiconductor layer is subjected to a first heat treatment to be at least partially crystallized. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heating time is 1 minute to 24 hours. The first oxide semiconductor layer 404 is a non-single-crystal layer grown from the surface (FIG. 4( A)). The crystal layer formed near the surface has a c-axis orientation perpendicular to the surface. It is heading in that direction.

[0100] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, and preferably 7N (99.99999%) or more. The first heat treatment may also be performed in a dry air atmosphere with an H2O concentration of 20 ppm or less.

[0101] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise of the first heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be switched to a nitrogen atmosphere, and after dehydration or dehydration is performed in a nitrogen atmosphere, Then, the atmosphere is changed to an oxygen atmosphere, whereby oxygen is supplied to the inside of the first oxide semiconductor layer. It can be made into an i-type.

[0102] Next, at least a first oxide semiconductor film was formed on the first oxide semiconductor layer 404 which was a plate-like crystal. A second oxide semiconductor layer having a thickness greater than that of the oxide layer 404 is formed. The thickness of the body layer can be determined by the practitioner depending on the device to be fabricated. In the case of manufacturing a bottom-gate transistor, the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 are The total thickness of the oxide semiconductor layers is set to 10 nm or more and 200 nm or less.

[0103] The first oxide semiconductor layer and the second oxide semiconductor layer may be made of materials containing the same components. Or the same crystal structure and close lattice constants (lattice constant mismatch of 1% or less) When materials containing the same components are used, it is preferable that the materials have the same structure in the subsequent crystallization. This facilitates crystal growth using the plate-like crystals of the first oxide semiconductor layer as seed crystals. In the case of a material containing one component, the interfacial properties such as adhesion and electrical properties are also good.

[0104] Next, second heat treatment is performed to crystallize the crystal layer of the first oxide semiconductor layer using the crystal of the first oxide semiconductor layer as a seed crystal. The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or lower. The heating temperature is between 650°C and 650°C. The heating time is between 1 minute and 24 hours. The second oxide semiconductor layer is crystallized by the treatment. A conductor layer 406 can be obtained (see FIG. 4(B)).

[0105] Next, an oxide semiconductor layer consisting of the first oxide semiconductor layer and the second oxide semiconductor layer is formed by photolithography. The island-shaped first oxide semiconductor layer 404a and the island-shaped second oxide semiconductor layer 404b are formed by a lithography process. The gate insulating layer 402 and the island-shaped first oxide semiconductor layer 406a are then processed. A gold film is formed on the conductor layer 404a and the island-shaped second oxide semiconductor layer 406a by a sputtering method or the like. After forming the metal conductive film, a resist mask is formed by a photolithography process. The metal electrode layer is then formed by etching.

[0106] Gold that will later become the source electrode layer and drain electrode layer (including wiring formed in the same layer) Materials for metal conductive films include metal materials such as Al, Cu, Cr, Ta, Ti, Mo, and W, or an alloy material containing the metal material as a component. Elements such as Cr, Nd, Sc, and Y prevent the occurrence of hillocks and whiskers in Al films. The added Al material can improve heat resistance.

[0107] For example, the metal conductive film may be a titanium layer on an aluminum layer, and a titanium layer on the aluminum layer. It is preferable to use a three-layer laminate structure in which an aluminum layer is laminated. Two-layer laminated structure consisting of aluminium layer and tungsten layer, and copper layer and tungsten layer a two-layer laminated structure with an aluminum layer and a molybdenum layer, Of course, the metal conductive film may have a single layer structure or a laminated structure of four or more layers.

[0108] Next, the resist mask is removed, and a resist mask is formed by a photolithography process. The source electrode layer 408a and the drain electrode layer 408b are formed by selectively etching the silicon dioxide film. After the formation, the resist mask is removed. Only a part of the oxide semiconductor layer 406a is etched to form a groove (a recess). It may also be a body layer.

[0109] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0110] Next, an oxide insulating layer 412 serving as a protective insulating film in contact with part of the oxide semiconductor layer was formed. Thereafter, a third heat treatment is performed (see FIG. 4(C)).

[0111] In this embodiment, a silicon oxide film having a thickness of 300 nm is deposited by sputtering as the oxide insulating layer 412. The substrate temperature during film formation may be set to between room temperature and 300° C. The temperature is set at 100°C in this case. The silicon oxide film is formed by sputtering using a rare gas (typically, In a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of rare gas (typically argon) and oxygen. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used to oxidize oxygen and nitrogen. Silicon oxide can be formed by sputtering in a silicon atmosphere. The second oxide semiconductor layer 404a and the crystallized island-shaped second oxide semiconductor layer 406a are in contact with each other. The oxide insulating layer 412 formed by this method has a thickness of 10 nm to 500 nm. The film may be a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film. etc. are used.

[0112] The temperature of the third heat treatment is 200°C or higher and 450°C or lower, preferably 250°C or higher and 300°C or lower. For example, heat treatment at 250°C for 1 hour in an oxygen-containing atmosphere is sufficient. By performing the third heat treatment, the island-shaped first oxide semiconductor layer 404a and the island-shaped second oxide semiconductor layer 404b are formed. Oxygen is supplied to the oxide semiconductor layer 406a, and the island-shaped first oxide semiconductor layer 404a and the island-shaped Therefore, oxygen vacancies in the second oxide semiconductor layer 406a having a crystalline structure can be reduced.

[0113] Next, an interlayer insulating layer 416 containing hydrogen is formed over the oxide insulating layer 412, and then a fourth process is performed. Heat treatment is performed (see FIG. 4D). The interlayer insulating layer 416 containing hydrogen is formed by a CVD method or the like. In this embodiment, a nitride containing hydrogen obtained by a CVD method can be formed. A silicon nitride film, which is one of the insulating layers, is used.

[0114] The fourth heat treatment is carried out in a nitrogen atmosphere at a temperature of 150° C. or higher and 450° C. or lower, preferably 250° C. or higher. The temperature is set to 440° C. or lower. The fourth heat treatment is not limited to a nitrogen atmosphere, but may be performed in an oxygen atmosphere. , a rare gas atmosphere, or a dry air atmosphere.

[0115] The fourth heat treatment after forming the interlayer insulating layer 416 containing hydrogen is performed to remove the hydrogen contained in the interlayer insulating layer 416. The hydrogen is diffused to form the island-shaped first oxide semiconductor layer 404a and the island-shaped second oxide semiconductor layer 404b. This is a process for terminating defects in the semiconductor layer 406a. The first oxide semiconductor island 404a and the second oxide semiconductor island 412 are formed on the first oxide semiconductor layer 404a. The oxide semiconductor layer 406a or the oxide semiconductor layer and the SiOx layer (silicon oxide film) Hydrogen can be diffused to the interface.

[0116] As a result, island-shaped crystals formed by crystal growth from the crystalline regions of the island-shaped first oxide semiconductor layer 404a were obtained. The second oxide semiconductor layer 406a is used, and hydrogen contained in the interlayer insulating layer 416 is diffused to form a defect. The recessed terminated transistor 450 is completed.

[0117] Next, an interlayer insulating layer 418 is formed on the interlayer insulating layer 416, resulting in the cross-sectional structure shown in FIG. 4(E). The interlayer insulating layer 418 is made of silicon oxide, oxynitride, or the like obtained by a PVD method, a CVD method, or the like. Inorganic insulating materials such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The interlayer insulating layer 418 is formed using a material containing an organic compound such as acrylic. Resin may also be used. In this embodiment, the interlayer insulating layer 416 and the interlayer insulating layer 4 However, one embodiment of the disclosed invention is not limited to this. Alternatively, a laminated structure of three or more layers may be used.

[0118] As shown in FIG. 4E, the gate electrode layer 401 is connected to the source electrode layer 408a (or Another feature is that the island-shaped acid has a region overlapping with the drain electrode layer 408b. The oxide semiconductor layer is formed at a step between the edge of the source electrode layer 408a and the gate insulating layer 402, i.e., The area between the flat surface and the tapered surface of the gate insulating layer (here, Figure 4) (E) OV L OV The region occurs at the edge of the gate electrode layer. This is important to prevent carriers from flowing into the grain boundaries where the crystal grains are located.

[0119] Further, an electrode layer functioning as a back gate may be formed over the oxide insulating layer 412. An example of fabrication in this case is shown in Figures 5(A) and 5(B). After obtaining the state shown in Figure 4(C), A contact hole (not shown) reaching the electrode layer 401 is formed, and a metal oxide film is formed on the oxide insulating layer 412. The electrode layer 414 is formed on the oxide insulating layer 414 (see FIG. 5A). An interlayer insulating layer 416 containing hydrogen is formed on the insulating layer 412. Then, a fourth heat treatment is performed to form the insulating layer 416 shown in FIG. 5(B) can be obtained. By placing it at a position overlapping with the channel formation region of the The amount of change in the threshold voltage of the transistor 451 before and after the test can be reduced. In addition, a transistor using an oxide semiconductor layer having a c-axis-oriented non-single-crystal layer The threshold voltage of the transistor remains constant even before and after the BT test, which is conducted by continuously irradiating the transistor with light. This reduces the amount of voltage change, making it possible to fabricate transistors with stable electrical characteristics. The electrode layer 414 has a potential different from that of the gate electrode layer 401 of the transistor 451. The potential of the electrode layer 414 may be GND, 0 V, or in a floating state. It is also possible.

[0120] (Embodiment 3) In this embodiment, an example of a channel-stop transistor will be described with reference to FIGS.

[0121] This embodiment is only partially different from the second embodiment, so a detailed description will be omitted here. It will be decided.

[0122] The steps are explained below in order. As in the second embodiment, a gate electrode layer 501 is formed on a substrate 500. Then, a gate insulating layer 502 is formed. Then, as in Embodiment 2, a first oxide semiconductor A first oxide semiconductor layer is formed, and the first heat treatment is performed to crystallize the first oxide semiconductor layer. As in the second embodiment, a second oxide semiconductor layer is formed and subjected to second heat treatment. The nitride semiconductor layer is crystallized.

[0123] Next, an oxide insulating layer is formed and third heat treatment is performed. The same material as the oxide insulating layer 412 described in Embodiment 2 is used. The first oxide semiconductor layer and the second oxide semiconductor layer were heated under the same conditions as those in the third heat treatment described above. oxygen is supplied to the first oxide semiconductor layer and the second oxide semiconductor layer, thereby reducing oxygen vacancies in the first oxide semiconductor layer and the second oxide semiconductor layer; do.

[0124] Next, a resist mask is formed on the oxide insulating layer by a photolithography process. The first oxide semiconductor layer 504a and the second oxide semiconductor layer 504b are selectively etched. A semiconductor layer 506a is formed.

[0125] Next, the resist mask is removed, and a resist mask is formed by a photolithography process. Then, selective etching is performed to form an island-shaped oxide insulating layer 520.

[0126] Next, the island-shaped oxide insulating layer 520, the island-shaped first oxide semiconductor layer 504a, and the island-shaped oxide insulating layer 520 are formed. After forming a metal conductive film on the second oxide semiconductor layer 506a by a sputtering method or the like, A resist mask is formed by a photolithography process, and selective etching is performed. A source electrode layer 508a and a drain electrode layer 508b are formed.

[0127] Next, the island-shaped oxide insulating layer 520, the source electrode layer 508a, and the drain electrode layer 508 After forming an interlayer insulating layer 516 containing hydrogen on the substrate 51b, a fourth heat treatment is performed. The heat treatment was also performed under the same conditions as those in the fourth heat treatment described in Embodiment 2. and supplying hydrogen to the first oxide semiconductor layer and the second oxide semiconductor layer. Reduce defects in the body layers.

[0128] As a result, island-shaped crystals formed by crystal growth from the crystalline regions of the island-shaped first oxide semiconductor layer 504a were formed. The second oxide semiconductor layer 506a is used, and hydrogen contained in the interlayer insulating layer 516 is diffused to form a defect. A channel stop type transistor 550 is completed with the recess terminated.

[0129] Next, an interlayer insulating layer 518 for planarization is formed on the interlayer insulating layer 516, and the cross-sectional surface shown in FIG. A planar structure can be obtained.

[0130] This embodiment mode can be freely combined with Embodiment Mode 2.

[0131] (Fourth embodiment) In this embodiment, the semiconductor device described in the previous embodiment is used in a semiconductor integrated circuit. As an example of the case where a semiconductor material different from that of the semiconductor device described in the previous embodiment is used, A semiconductor device having a stacked structure with the semiconductor device will be described with reference to FIG.

[0132] 7 is a cross-sectional view showing an example of the configuration of a semiconductor device according to this embodiment. 1-A2 is a cross section of the transistor 250 taken parallel to the channel length direction, and B1 -B2 is a cross section taken parallel to the channel length direction of the transistor 150. The semiconductor device shown in the figure uses a material other than an oxide semiconductor (for example, silicon) in the lower part. The transistor 250 includes a transistor 150 using an oxide semiconductor thereon. The transistor 150 including an oxide semiconductor has the same structure as the transistor 15 shown in FIG. 0. Note that both the transistor 250 and the transistor 150 are n-type transistors. Although the description will be given using a p-type transistor, a p-type transistor may also be used. 0 can easily be made p-type.

[0133] The transistor 250 includes a channel forming region 21 provided in a substrate 200 including a semiconductor material. 6, and the impurity region 214 and the high concentration impurity region 215 provided so as to sandwich the channel forming region 216. The pure region 220 (collectively referred to as the impurity region) and the channel forming region 21 6, and a gate insulating layer 208a provided on the gate insulating layer 208a. The electrode layer 210a and the source electrode layer or the drain electrode layer electrically connected to the impurity region 214 are 7, the source electrode layer 230a and the drain electrode layer 230b. ).

[0134] Here, a sidewall insulating layer 218 is provided on the side surface of the gate electrode layer 210a. In addition, when viewed from a direction perpendicular to the main surface of the substrate 200, the sidewall insulating layer 218 is not overlapped. The region without the high concentration impurity layer has a high concentration impurity region 220, and the metallization layer contacting the high concentration impurity region 220 is The substrate 200 also has an alloy region 224. An isolation insulating layer 206 is provided, and an interlayer insulating layer 22 is provided to cover the transistor 250. 6 and an interlayer insulating layer 228. A source or drain electrode layer 230 a, the source electrode layer or the drain electrode layer 230b is formed between the interlayer insulating layer 226 and the interlayer insulating layer 228 is electrically connected to the metal compound region 224 through an opening formed therein. That is, the source or drain electrode layer 230a, the source or drain electrode layer 230b is connected to the high concentration impurity region 220 and the impurity region 230b via the metal compound region 224. 14. The source electrode layer or drain electrode layer 230a, Similar to the electrode or drain electrode layer 230b, the electrode 230c is formed between the interlayer insulating layer 226 and the layer The insulating layer 228 is formed in an opening in the insulating layer 228. The insulating layer 234 is provided, and the electrodes 236a, the electrodes 236b, the electrodes 236c, the electrodes 236d, the electrodes 236e, the electrodes 236f, the electrodes 236g, the electrodes 236h, the electrodes 236h, the electrodes 236h, the electrodes 236i, the electrodes 236j ... The electrode 236a is a source electrode layer or The electrode 236b is in contact with the drain electrode layer 230a, and the electrode 236b is in contact with the source or drain electrode layer. The electrode 236c contacts the electrode layer 230c.

[0135] The transistor 150 includes an island-shaped first oxide semiconductor layer 104 provided over an insulating layer 102. a, the island-shaped second oxide semiconductor layer 106a, and the island-shaped first oxide semiconductor layer 104a. and an island-shaped first oxide semiconductor layer 106a provided on the island-shaped second oxide semiconductor layer 106b. The source electrode 104a and the island-shaped second oxide semiconductor layer 106a are electrically connected to the source electrode 104a and the island-shaped second oxide semiconductor layer 106a. The electrode layer 108a, the drain electrode layer 108b, the island-shaped first oxide semiconductor layer 104a, the island-shaped The second oxide semiconductor layer 106a, the source electrode layer 108a, and the drain electrode layer 108 a gate insulating layer 112 provided to cover the gate insulating layer 112; a gate electrode layer 114 provided in a region overlapping with the oxide semiconductor layer 106a; (See Figure 7).

[0136] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Here, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118 have , and openings reaching the source electrode layer 108a and the drain electrode layer 108b are provided. Through the openings, the electrode 254d and the electrode 254e are respectively connected to the source electrode layer 108a and the source electrode layer 108b. The electrode 254d and the electrode 254e are formed in contact with the drain electrode layer 108b. Similarly, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118 are provided with The electrodes 254a, 254b, and 254c are in contact with the electrodes 236a, 236b, and 236c through the openings. 254b and an electrode 254c are formed.

[0137] An insulating layer 256 is provided on the interlayer insulating layer 118, and a buried insulating layer 256 is provided on the insulating layer 256. Electrodes 258a, 258b, 258c, and 258d are provided so that the electrodes are embedded in the Here, electrode 258a is in contact with electrode 254a, and electrode 258b is in contact with electrode 254. b, electrode 258c is in contact with electrode 254c and electrode 254d, and electrode 2 58d is in contact with electrode 254e.

[0138] That is, the source electrode layer 108a or the drain electrode layer 108b of the transistor 150 is Through the electrodes 230c, 236c, 254c, 258c, and 254d, etc. (e.g., a transistor using a material other than an oxide semiconductor) (See FIG. 7). Furthermore, the source electrode layer 108a or the drain electrode Layer 108b is electrically connected to other elements via electrodes 254e and 258d. In addition, the electrodes involved in the connection (electrode 230c, electrode 236c, electrode 254c, electrode 258c) , electrode 254d, etc.) is not limited to the above, and may be added or omitted as appropriate.

[0139] In addition, various electrodes (for example, electrode 258a, electrode 258b, electrode 258c, electrode 258d, etc.) It is preferable to use a material containing copper for a part of these. By using copper, the conductivity can be improved. It can be formed by a silicon process or the like.

[0140] In the above, a typical example of a semiconductor device having a stacked structure has been described in this embodiment. However, one embodiment of the disclosed invention is not limited thereto. The number and arrangement of the electrodes and wiring, the number and connection relationship of the electrodes and wiring, etc. can be changed as appropriate. As an example of the connection relationship between the electrodes, the gate electrode layer 210a of the transistor 250 and the The source electrode layer 108a or the drain electrode layer 108b of the transistor 150 is electrically connected to the It is also possible to adopt a configuration in which

[0141] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor with an oxide semiconductor, Semiconductor devices with different electrical characteristics can be realized.

[0142] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0143] (Embodiment 5) In this embodiment, a memory device and a semiconductor device according to one embodiment of the disclosed invention are used as specific examples. Here, a structure example of a semiconductor device that functions as a transistor using an oxide semiconductor will be described. a transistor using a material other than an oxide semiconductor (for example, silicon); A semiconductor device including the above will be described.

[0144] In the semiconductor device shown in FIG. 8, the gate electrode of the transistor 300 and the gate electrode of the transistor 302 are The first wiring is electrically connected to one of the source electrode and the drain electrode. (1st Line: also called source line) and the source electrode of the transistor 300 are electrically The second line (also called a bit line) and the transistor 30 The drain electrode of the third wiring (3rd Lin e: also referred to as a first signal line) and the other of the source electrode or the drain electrode of the transistor 302. The fourth line (also called the second signal line) and the The gate electrode of the transistor 302 is electrically connected. 00 uses a material other than an oxide semiconductor (for example, silicon), and the transistor The layer 302 is made of an oxide semiconductor material.

[0145] The transistor 300 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to the memory 302, it can operate at a higher speed. It is possible to read out the contents at high speed. The transistor 302 has a feature that the off-current is extremely small. By turning off the transistor 302, the potential of the gate electrode of the transistor 300 is maintained for a very long time. It is possible to maintain it for a long time.

[0146] The source or drain electrode of transistor 302 is connected to the gate electrode of transistor 300. By electrically connecting the floating gate electrode to the electrode, a nonvolatile memory element can be formed. This has the same effect as the floating gate of a floating gate type transistor. In this embodiment, the source electrode or the drain electrode of the transistor 302 and the transistor The portion to which the gate electrode of the capacitor 300 is electrically connected is called a floating gate portion FG. The floating gate portion FG is buried in an insulator and therefore holds charge. The transistor 302 is the same as the transistor 300 formed of a silicon semiconductor. In comparison, the off-state current is less than one-hundred-thousandth, so there is no accumulation in the floating gate FG. The loss of the charge stored in the transistor 302 due to leakage can be ignored.

[0147] By adopting this configuration, the conventional floating gate type transistor This can avoid the deterioration of the gate insulating film (tunnel insulating film) that has been pointed out. The gate insulating film is then insulated by the tunnel current that occurs when electrons are injected into the floating gate. Therefore, in principle, the semiconductor device shown in FIG. This allows you to ignore the limit on the number of writes.

[0148] A capacitance element may be added to the floating gate portion FG. By adding a capacitance element to the FG of the gate part, it becomes easier to hold the charge and the potential change of each wiring This makes it easier to suppress the potential fluctuation of the floating gate portion FG caused by the movement.

[0149] The semiconductor device shown in FIG. 8 has a feature that the potential of the gate electrode of the transistor 300 can be maintained. By utilizing this characteristic, it is possible to write, store, and read information as follows.

[0150] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The potential is set to turn on the transistor 302, thereby turning on the transistor 302. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 300 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 302 is turned off. By turning off the transistor 302, the gate electrode of the transistor 300 The potential is maintained (retention).

[0151] Since the off-state current of the transistor 302 is extremely small, the gate electrode of the transistor 300 For example, if the potential of the gate electrode of transistor 300 is If the potential is such that the transistor 300 is turned on, the transistor 300 will remain on for a long time. The potential of the gate electrode of the transistor 300 is maintained for a certain period of time. If the potential is such that the transistor 300 is in an off state, the transistor 300 will remain in an off state for a long time. is maintained over time.

[0152] Next, the reading of information will be described. As described above, when the transistor 300 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 300 is turned on, the potential of the second wiring changes depending on whether the transistor 300 is turned on or off. For example, when the transistor 300 is on, the potential of the first wiring is On the other hand, the potential of the second wiring is decreased. In this case, the potential of the second wiring does not change.

[0153] In this way, in a state where information is held, the potential of the first wiring and the potential of the second wiring are By comparing, information can be read out.

[0154] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held in the same manner as when the transistor 302 is turned on. This turns on the transistor 302. (a potential related to new information) is applied to the gate electrode of transistor 300. The potential of the fourth wiring is set to a potential at which the transistor 302 is turned off. By turning off 02, the new information is held.

[0155] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0156] Furthermore, in the semiconductor device according to this embodiment, the transistor 302 has a low off-state current. It is possible to retain information for an extremely long period of time. This eliminates the need for a refresh operation, which reduces power consumption. The semiconductor device can be used as a nonvolatile semiconductor memory device.

[0157] In addition, since information is written by the switching operation of the transistor 302, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized.

[0158] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0159] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0160] The semiconductor device according to this embodiment is, for example, a transistor as described in the previous embodiment. Of course, the disclosed invention can be applied to transistors. For example, the transistor 300 and the transistor 30 2 may be formed on the same surface. Since the off-state current of the transistor 302 is small, For example, in this embodiment, a material other than an oxide semiconductor is used. However, an oxide semiconductor may be used instead.

[0161] In addition, in this embodiment, for ease of understanding, the minimum unit semiconductor device has been described. The configuration of the semiconductor device is not limited to this. It is also possible to configure a more advanced semiconductor device. For example, by using a plurality of the above-described semiconductor devices, It is possible to configure NAND type and NOR type semiconductor devices. The wiring configuration is not limited to the one shown in Figure 8. It is not fixed and can be changed as appropriate.

[0162] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0163] (Embodiment 6) In this embodiment, a transistor including a c-axis aligned oxide semiconductor layer is manufactured. A semiconductor device (also called a display device) having a display function is manufactured by using a transistor in a pixel portion and further in a driver circuit. In addition, a part or the whole of the driver circuit is formed in the pixel portion. They can be integrally formed on the same substrate to form a system-on-panel.

[0164] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 9. FIG. 9(A) shows a c-axis oriented oxide semiconductor formed on a first substrate 4001. A transistor 4010 including a semiconductor layer, a transistor 4011, and a liquid crystal element 4013 are 4006. The panel is sealed with a sealing material 4005 between the panel and the substrate 4006. FIG. 9B corresponds to a cross-sectional view taken along line MN in FIG. 9A.

[0165] A pixel portion 4002, a signal line driver circuit 4003, and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4002 is disposed on the signal line driver circuit 4003 and the scanning line driver circuit 4004. 006 is provided. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scanning line The driver circuit 4004 is formed on a first substrate 4001, a sealing material 4005, and a second substrate 4006. Therefore, it is sealed together with the liquid crystal layer 4008 .

[0166] A pixel portion 4002 and a signal line driver circuit 4003 are provided on a first substrate 4001. The scanning line driver circuit 4004 has a plurality of transistors. The transistor 4010 included in the scanning line driver circuit 4002 and the transistor 4010 included in the scanning line driver circuit 4004 The transistor 4010 and the transistor 4011 are shown as examples. An insulating layer 4020, an insulating layer 4014, and an insulating layer 4021 are provided.

[0167] The transistors 4010 and 4011 are made of the c-axis oriented oxide semiconductor shown in Embodiment 2. In this embodiment, a transistor including a nitride semiconductor layer can be applied. The transistor 4010 and the transistor 4011 are n-channel transistors.

[0168] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By placing it at a position that overlaps with the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the transistor 4011. A transistor using an oxide semiconductor layer having a non-single-crystal layer is The amount of change in the threshold voltage of the transistor is reduced even before and after the BT test, which is conducted by continuously irradiating the Therefore, a transistor having stable electrical characteristics can be manufactured. The potential of the gate electrode layer of the transistor 4011 may be the same as or different from that of the gate electrode layer of the transistor 4011. The conductive layer 4040 may also function as a second gate electrode layer. The potential may be GND, 0V, or floating.

[0169] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 and the counter electrode 4031 are formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as an alignment film. The liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033 .

[0170] The second substrate 4006 can be made of glass or plastic.

[0171] The columnar spacers 4035 are obtained by selectively etching the insulating layer, and the pixel electrodes The electrode layer 4030 and the counter electrode layer 4031 are provided to control the distance (cell gap). A spherical spacer may be used. The transistor 4010 is electrically connected to a common potential line provided on the same insulating substrate. In addition, the common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0172] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. sec or less, and because it is optically isotropic, alignment treatment is not required, and viewing angle dependency is small. stomach.

[0173] In addition, when a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, in a transistor including an oxide semiconductor layer, the influence of static electricity can The electrical characteristics of the transistor may fluctuate significantly and deviate from the design range. of a blue phase liquid crystal material in a liquid crystal display device having transistors using a nitride semiconductor layer - Patents.com That is more effective.

[0174] Although the liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, a reflective liquid crystal display device may also be used. The display device may be a display device or a semi-transmissive liquid crystal display device.

[0175] In addition, in the liquid crystal display device described in this embodiment mode, a polarizing plate is provided on the outer side (viewing side) of the substrate, and In this example, a colored layer (color filter) and an electrode layer used for a display element are provided on the side in this order. The polarizing plate may be provided on the inner side of the substrate. Also, the laminated structure of the polarizing plate and the colored layer is also applicable to the present embodiment. It is not limited to this, and may be appropriately set depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions. If necessary, a light-shielding layer that functions as a black matrix may be provided.

[0176] In this embodiment, in order to reduce the surface unevenness of the transistor and To improve reliability, the transistor is covered with an insulating layer ( The insulating layer 4020, the insulating layer 4014, and the insulating layer 4021 are used to cover the insulating layer. The protective layer is designed to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective layer is preferably a silicon oxide layer or a silicon nitride layer formed by sputtering. silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer, oxide The aluminum oxide nitride layer may be formed as a single layer or a multilayer of an aluminum nitride oxide layer. .

[0177] Here, a laminate of insulating layers is formed as a protective layer. Then, a silicon oxide layer is formed by sputtering. When a silicon oxide layer is used as a protective layer, Oxygen vacancies can be reduced by adding oxygen to the oxide semiconductor layer in contact with the protective layer.

[0178] Further, an insulating layer 4014 is formed as the second layer of the protective layer. 14, a silicon nitride layer, which is one of the nitride insulating layers containing hydrogen, is formed using the plasma CVD method. Then, heat treatment is performed to diffuse hydrogen into the oxide semiconductor layer. If a silicon nitride layer is used, ions such as sodium may penetrate into the semiconductor region, causing transistor This can prevent the electrical characteristics of the capacitor from changing.

[0179] An insulating layer 4021 is formed as a planarizing insulating layer. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass) It is possible to use a plurality of insulating layers made of these materials. Then, the insulating layer 4021 may be formed.

[0180] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0181] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or Various signals and potentials to be applied to the pixel portion 4002 are supplied from an FPC 4018 .

[0182] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive layer as the transistor 4010. The source electrode layer and the drain electrode layer of the transistor 4011 are formed of the same conductive layer.

[0183] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. are electrically connected.

[0184] If necessary, a color filter is provided corresponding to each pixel. A polarizing plate and a diffusing plate are provided on the outside of the first and second substrates 4001 and 4006. The source is composed of cold cathode fluorescent lamps and LEDs, forming a liquid crystal display module.

[0185] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0186] Through the above steps, a liquid crystal display device can be manufactured.

[0187] The transistor including the c-axis aligned oxide semiconductor layer described in Embodiment 2 has excellent crystallinity. Since the oxide semiconductor layer is included and the field-effect mobility is high, By manufacturing a liquid crystal display device using the above, a liquid crystal display device with excellent display characteristics can be realized.

[0188] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0189] (Embodiment 7) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device This will be explained with reference to Fig. 10. Fig. 10(A) shows a c-axis oriented film formed on a first substrate. The transistor and the light-emitting element including the oxide semiconductor layer are disposed between the second substrate and the first substrate using a sealing material. 10(B) is a plan view of the panel sealed by the HI in FIG. 10(A). This corresponds to a cross-sectional view.

[0190] A pixel portion 4502, a signal line driver circuit 4503a, a signal line driver circuit 4503b, a signal line driver circuit 4503c, a signal line driver circuit 4503d, a signal line driver circuit 4503e, a signal line driver circuit 4503f, a signal line driver circuit 4503g, a signal line driver circuit 4503h, a signal line driver circuit 4503m, a signal line driver circuit 4503 The driver circuit 4503b, the scanning line driver circuit 4504a, and the scanning line driver circuit 4504b are surrounded by a In this way, a sealing material 4505 is provided. 4503a, a signal line driver circuit 4503b, and a scanning line driver circuit 4504a. A second substrate 4506 is provided on the path 4504b. a signal line driver circuit 4503a, a signal line driver circuit 4503b, and a scanning line driver circuit 4504a. The scan line driver circuit 4504b is made up of a first substrate 4501, a sealant 4505, and a second substrate 450 6, and the filling material 4507 is sealed. The product is packaged (enclosed) in a protective film or covering material that is highly airtight and has little outgassing. It is preferable.

[0191] A pixel portion 4502, a signal line driver circuit 4503a, a signal line driver circuit 4503b, a signal line driver circuit 4503c, a signal line driver circuit 4503d, a signal line driver circuit 4503e, a signal line driver circuit 4503f, a signal line driver circuit 4503g, a signal line driver circuit 4503h, a signal line driver circuit 4503m, a signal line driver circuit 4503 The scanning line driver circuit 4503b, the scanning line driver circuit 4504a, and the scanning line driver circuit 4504b are 10B, the transistors included in the pixel portion 4502 are 4503a and a transistor 4510 included in the signal line driver circuit 4503a. is doing.

[0192] The transistors 4509 and 4510 are made of the c-axis oriented oxide semiconductor shown in Embodiment 2. A transistor having high mobility including a nitride semiconductor layer can be applied to this embodiment. In this case, the transistors 4509 and 4510 are n-channel transistors. do.

[0193] A region overlapping with a channel formation region of the oxide semiconductor layer of the transistor 4509 for the driver circuit is The conductive layer 4540 is provided over the insulating layer 4544. The gate electrode layer of the second gate electrode may be the same as or different from that of the transistor 4509. The conductive layer 4540 can also function as a ground electrode layer. V, or may be floating.

[0194] The transistor 4509 has an insulating layer in contact with a semiconductor layer including a channel formation region as a protective insulating layer. The insulating layer 4541 is the oxide insulating layer 4441 described in Embodiment 2. The protective insulating layer 45 may be formed using a material and a method similar to those of the insulating layer 4541. The protective insulating layer 4514 is formed in the same manner as the interlayer insulating layer 416 described in Embodiment 2. The protective insulating layer 4514 may be formed by a similar material and method. A silicon nitride layer is formed by the method.

[0195] Further, a planarization insulating layer for reducing surface unevenness of the transistor is formed over the protective insulating layer 4514. A functional insulating layer 4544 is formed. As the insulating layer 4544, the insulating layer shown in Embodiment 6 is used. The insulating layer 4544 may be formed using the same material and method as the insulating layer 4021. Acrylic is used.

[0196] The first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is formed by a transistor The light-emitting element is electrically connected to the source electrode layer or the drain electrode layer of 4510. The structure of 4511 is a first electrode layer 4517, an electroluminescent layer 4512, a second electrode layer 4513, and a The laminated structure is not limited to the structure shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately depending on the orientation and the like.

[0197] The partition wall 4520 is formed using an organic resin layer or an inorganic insulating layer. An opening is formed on the first electrode layer 4517 using the above-mentioned method, and the sidewall of the opening has a continuous curvature. It is preferable that the surface be an inclined surface.

[0198] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It may be possible to do so.

[0199] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective layer may be formed on the partition wall 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer, A silicon nitride oxide layer, a DLC layer, or the like can be formed.

[0200] In addition, a signal line driver circuit 4503a, a signal line driver circuit 4503b, a scanning line driver circuit 4504 a, various signals and potentials given to the scanning line driver circuit 4504b or the pixel portion 4502 , FPC4518a, FPC4518b are supplied.

[0201] The connection terminal electrode 4515 is formed on the same conductive layer as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the transistor 4509 and the transistor 4510. The source electrode layer and the drain electrode layer are formed from the same conductive layer as the source electrode layer and the drain electrode layer.

[0202] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive layer 4519. are electrically connected to each other.

[0203] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 is not light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0204] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and acrylic resin, epoxy resin, etc. For example, nitrogen can be used as a filler.

[0205] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. stomach.

[0206] Through the above steps, a light-emitting display device (display panel) can be manufactured.

[0207] The transistor using the c-axis aligned oxide semiconductor layer described in Embodiment 2 has excellent crystallinity. Since the oxide semiconductor layer has a large field-effect mobility, the By using this to manufacture a light-emitting display device, a light-emitting display device with excellent display characteristics can be realized. .

[0208] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0209] (Embodiment 8) An example of electronic paper will be shown as one mode of the semiconductor device.

[0210] A transistor including a c-axis aligned oxide semiconductor layer obtained by the method described in Embodiment 2 The electronic paper may be used for an electrophoretic display device (electrophoretic display Also known as a digital readable display, it is as easy to read as paper and consumes less power than other display devices. This has the advantage of enabling the device to be made smaller, thinner, and lighter.

[0211] Electrophoretic displays can be of various types, for example, those having a positive charge. Microcapsules containing first particles and second particles having a negative charge are dissolved in a solvent or is dispersed in a solute, and by applying an electric field to the microcapsules, The particles in the microcapsules are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is measured. The first particles or the second particles may contain a dye, In the absence of an electric field, the particles do not move. are different (including colorless).

[0212] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0213] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0214] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. For example, in the case of the c-axis oriented liquid crystal of the second embodiment, An active matrix substrate obtained by using a transistor including an oxide semiconductor layer is used. It is possible.

[0215] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof It can be formed using

[0216] FIG. 11 shows an active matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the semiconductor device is the same as the transistor shown in the second embodiment. The transistor can be fabricated and has high mobility, and includes a c-axis oriented oxide semiconductor layer. The insulating layer 584 is a nitride insulating layer containing hydrogen, and is formed by adding hydrogen to the c-axis aligned oxide semiconductor layer. It is provided to supply.

[0217] The electronic paper in Figure 11 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0218] The transistor 581 is a bottom-gate transistor, and an insulating layer in contact with a semiconductor layer The source electrode layer or the drain electrode layer of the transistor 581 is covered with the first In the openings formed in the electrode layer 587, the insulating layer 583, the insulating layer 584, and the insulating layer 585, Between the first electrode layer 587 and the second electrode layer 588, a cavity is provided. The cavity 594 includes a black area 590a and a white area 590b. The cavity 594 is filled with spherical particles having the above structure and a liquid. The first substrate 580 and the second substrate 596 are filled with a filler material 595. (See Figure 11.)

[0219] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential The conductive particles disposed between the pair of substrates are electrically connected to the wiring by using the common connection part. The second electrode layer 588 and a common potential line can be electrically connected via the wiring.

[0220] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, which can be used for electronic paper. .

[0221] Through the above steps, electronic paper can be produced.

[0222] In this embodiment, the transistor including the c-axis aligned oxide semiconductor layer described in Embodiment 2 is The transistor has excellent crystallinity and is used to produce so-called electronic paper. It has an oxide semiconductor layer and high field-effect mobility, so it can be used to make electronic paper. By manufacturing this, electronic paper with excellent display characteristics can be realized.

[0223] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0224] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras and digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0225] In this embodiment, a display device obtained in any one of the sixth to eighth embodiments is installed. An example of an electronic device equipped with the above-mentioned method will be described with reference to FIGS.

[0226] FIG. 12(A) shows a notebook-type personal computer manufactured by mounting at least a display device as a component. It is a personal computer, and it has a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, and a 004, etc. The liquid crystal display device shown in the sixth embodiment is a notebook type. The personal computer has

[0227] FIG. 12(B) shows a portable information terminal (P DA), and the main body 3021 includes a display unit 3023, an external interface 3025, Operation buttons 3024 and the like are provided. A stylus 3022 is also provided as an accessory for operation. Note that the portable information terminal includes the light-emitting display device described in Embodiment 7.

[0228] FIG. 12(C) shows an electronic book manufactured by mounting the electronic paper shown in the eighth embodiment as a component. The electronic book 2700 is composed of two housings, housing 2701 and housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft 2711. The opening and closing operation can be performed around the shaft portion 2711. It is possible to perform operations such as registration.

[0229] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 12C), and An image can be displayed on the display portion (the display portion 2707 in FIG. 12C).

[0230] FIG. 12C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The surface may be provided with a keyboard, a pointing device, etc. On the back and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), storage media insertion port, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. A similar configuration may also be used.

[0231] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0232] FIG. 12(D) shows a mobile phone manufactured by mounting at least a display device as a component. It consists of two housings, housing 2800 and housing 2801. Housing 2801 has a display Panel 2802, speaker 2803, microphone 2804, pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. The housing 2800 contains a solar cell 2810 for charging the portable information terminal, an external memory slot, The housing 2801 is provided with a built-in antenna.

[0233] The display panel 2802 has a touch panel function, and in FIG. 12(D) The multiple operation keys 2805 connected to the solar cell 2810 are shown by dotted lines. A boost circuit is also implemented to boost the output voltage to the voltage required for each circuit.

[0234] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 12(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0235] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0236] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0237] FIG. 12(E) shows a digital camera manufactured by mounting at least a display device as one component. It includes a main body 3051, a display unit (A) 3057, an eyepiece 3053, an operation switch 3054, and a display It is composed of a display unit (B) 3055, a battery 3056, etc.

[0238] 13 shows an example of a television device. The television device 9600 has a housing 9 The display unit 9603 is incorporated in the camera 601. The display unit 9603 can display images. In this example, the housing 9601 is supported by a stand 9605. This shows:

[0239] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0240] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0241] The display portion 9603 includes the transistor described in Embodiment 2 as a switching element of a pixel. A plurality of display portions 9603 are arranged, and a driver circuit formed on the same insulating substrate as the display portion 9603 is A transistor with high mobility shown in is arranged.

[0242] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 8. [Explanation of symbols]

[0243] 100 boards 102 Insulating layer 104 First oxide semiconductor layer 104a: Island-shaped first oxide semiconductor layer 105 Second oxide semiconductor layer 106 Second oxide semiconductor layer 106a Island-shaped second oxide semiconductor layer 108 Conductive layer 108a Source electrode layer 108b Drain electrode layer 112 Gate insulating layer 114 gate electrode layer 116 Interlayer insulating layer 118 Interlayer insulating layer 150 transistors 200 boards 206 Element isolation insulating layer 208a Gate insulating layer 210a gate electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulation layer 228 Interlayer Insulation Layer 230a Source electrode layer or drain electrode layer 230b Source electrode layer or drain electrode layer 230c electrode 234 Insulating Layer 236a Electrode 236b Electrode 236c electrode 250 transistors 254a electrode 254b electrode 254c electrode 254d electrode 254e electrode 256 insulating layer 258a electrode 258b Electrode 258c electrode 258d electrode 300 transistors 302 Transistor 400 boards 401 Gate electrode layer 402 Gate insulating layer 404 First oxide semiconductor layer 404a Island-shaped first oxide semiconductor layer 406 Second oxide semiconductor layer 406a Island-shaped second oxide semiconductor layer 408a Source electrode layer 408b Drain electrode layer 412 Oxide insulating layer 414 Electrode layer 416 Interlayer insulation layer 418 Interlayer Insulation Layer 450 transistors 451 Transistor 500 boards 501 gate electrode layer 502 Gate insulating layer 504a Island-shaped first oxide semiconductor layer 506a Island-shaped second oxide semiconductor layer 508a Source electrode layer 508b Drain electrode layer 516 Interlayer insulation layer 518 Interlayer insulation layer 520 Island-shaped oxide insulating layer 550 transistors 580 First Substrate 581 Transistor 583 Insulating Layer 584 Insulating Layer 585 Insulation Layer 587 First electrode layer 588 Second electrode layer 590a black area 590b White area 594 Cavity 595 Filling material 596 Second Board 2700 e-books 2701 Case 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 First substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Second board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4014 Insulation layer 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Conductive layer 4501 First board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Second board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Second electrode layer 4514 Protective insulation layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 First electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine

Claims

1. a first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, a first insulating layer having a region disposed above a gate electrode of the first transistor; a first conductive layer and a second conductive layer having a region disposed above the first insulating layer; an oxide semiconductor layer having a region disposed above the first insulating layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region disposed above the first insulating layer, a region disposed above the first conductive layer, a region disposed above the second conductive layer, and a region disposed above the third conductive layer; a fourth conductive layer and a fifth conductive layer having regions disposed above the second insulating layer; and one of a source and a drain of the first transistor is electrically connected to the fourth conductive layer via the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the second conductive layer via the fifth conductive layer; the second conductive layer is electrically connected to an impurity region of a silicon substrate in which a channel formation region of the first transistor is disposed.

2. a first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, a first insulating layer having a region disposed above a gate electrode of the first transistor; a first conductive layer and a second conductive layer having a region disposed above the first insulating layer; an oxide semiconductor layer having a region disposed above the first insulating layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region disposed above the first insulating layer, a region disposed above the first conductive layer, a region disposed above the second conductive layer, and a region disposed above the third conductive layer; a fourth conductive layer and a fifth conductive layer having regions disposed above the second insulating layer; and one of a source and a drain of the first transistor is electrically connected to the fourth conductive layer via the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the second conductive layer via the fifth conductive layer; the second conductive layer is electrically connected to an impurity region of a silicon substrate in which a channel formation region of the first transistor is disposed, via a sixth conductive layer disposed in a first opening of the first insulating layer.

3. a first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, a first insulating layer having a region disposed above a gate electrode of the first transistor; a first conductive layer and a second conductive layer having a region disposed above the first insulating layer; an oxide semiconductor layer having a region disposed above the first insulating layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region disposed above the first insulating layer, a region disposed above the first conductive layer, a region disposed above the second conductive layer, and a region disposed above the third conductive layer; a fourth conductive layer and a fifth conductive layer having regions disposed above the second insulating layer; and one of a source and a drain of the first transistor is electrically connected to the fourth conductive layer via the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the second conductive layer via the fifth conductive layer; the second conductive layer is electrically connected to an impurity region of a silicon substrate in which a channel formation region of the first transistor is disposed, via a sixth conductive layer disposed in a first opening of the first insulating layer; The second conductive layer is electrically connected to the fifth conductive layer via a seventh conductive layer disposed in a second opening of the second insulating layer.

4. a first transistor including silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region, a first insulating layer having a region disposed above a gate electrode of the first transistor; a first conductive layer and a second conductive layer having a region disposed above the first insulating layer; an oxide semiconductor layer having a region disposed above the first insulating layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region disposed above the first insulating layer, a region disposed above the first conductive layer, a region disposed above the second conductive layer, and a region disposed above the third conductive layer; a fourth conductive layer and a fifth conductive layer having regions disposed above the second insulating layer; and one of a source and a drain of the first transistor is electrically connected to the fourth conductive layer via the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the second conductive layer via the fifth conductive layer; the second conductive layer is electrically connected to an impurity region of a silicon substrate in which a channel formation region of the first transistor is disposed, via a sixth conductive layer disposed in a first opening of the first insulating layer; the second conductive layer is electrically connected to the fifth conductive layer via a seventh conductive layer disposed in a second opening of the second insulating layer; the fifth conductive layer is electrically connected to the oxide semiconductor layer via an eighth conductive layer disposed in a third opening of the second insulating layer.

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