Semiconductor device

Abstract

To provide a highly reliable trimming circuit. To provide a rewritable trimming circuit. To provide a method for driving a highly reliable trimming circuit. To provide a method for driving a rewritable trimming circuit.SOLUTION: A trimming circuit is formed using a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely small and a transistor whose gate electrode is connected to the storage node. Further, a trimming state of an element or a circuit which is connected in parallel to a source electrode and a drain electrode of a transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely small.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a trimming circuit and a method for driving a trimming circuit. [Background technology]

[0002] Integrated circuits that require highly accurate voltage and current values ​​(such as AD converters and DA converters) In the manufacturing process of the data, the variation in characteristics that cannot be suppressed by adjusting the manufacturing conditions is compensated for. A method is needed.

[0003] In addition, in the manufacturing process of integrated circuits (for example, large-capacity storage devices) that require high yields, Therefore, a method for switching connections to built-in redundant circuits is needed.

[0004] A circuit called a trimming circuit is used for such purposes. The elements or circuits connected in parallel to the trimming circuit are made available or unavailable. This is a circuit that selects whether the output is in a normal state (trimming state) or not. For example, a fuse or a Zener zap diode is used.

[0005] Further, a transistor using an oxide semiconductor in a channel formation region is known (see Patent Document 1). 1) The oxide semiconductor layer can be manufactured relatively easily using a sputtering method or the like. A transistor using an oxide semiconductor for a channel formation region has the advantage of being easy to manufacture. can. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A Summary of the Invention [Problem to be solved by the invention]

[0007] By the way, fuses and Zener zap diodes can sometimes cause reliability problems. For example, in the laser cutting method, which uses a laser to burn out a fuse, Residue may remain and the circuit may not be shut off properly.

[0008] In addition, conventional trimming using irreversible elements such as fuses and Zener zap diodes Once the circuit is cut, it cannot be restored to its original state, so re-trimming or There are problems such as the inability to rewrite the data.

[0009] One aspect of the present invention has been made under such technical background. It is an object of the present invention to provide a highly reliable trimming circuit. It is an object of the present invention to provide a trimming circuit that can be used for trimming with high reliability. It is an object of the present invention to provide a method for driving a circuit. One of the objectives is to provide a method for driving a path. [Means for solving the problem]

[0010] In order to achieve the above object, one aspect of the present invention is to provide a method for setting up a network without physically disconnecting a circuit. We focused on a structure that would maintain the selected switching state for a long period of time. a storage node connected to a source electrode or a drain electrode of the transistor; The inventors have come up with a configuration in which a transistor is provided with a gate electrode connected to the off-state leakage current. A transistor with an extremely small current is used, and a transistor with a gate electrode connected to the storage node is used. Trimming of an element or circuit connected in parallel to the source and drain electrodes of a transistor We came up with a method for controlling the switching state, which solved the above problem.

[0011] That is, one aspect of the present invention is a semiconductor memory device in which one electrode is connected to a storage node, the other electrode is connected to a ground potential line, The capacitor element and the gate electrode are electrically connected to the write terminal, and the source electrode or One of the drain electrodes is electrically connected to the storage node, and the other is electrically connected to the power supply potential line. a first transistor having a gate electrode connected to an erase terminal and a source electrode or a drain electrode connected to an erase terminal; a second transistor electrically connected to the storage node on one side and to the ground potential line on the other side; and a third transistor having a gate electrode electrically connected to the storage node. The first transistor and the second transistor have a band gap of 2.5 eV or more. The semiconductor material above is provided in a channel forming region, and the source electrode and drain electrode of the third transistor are formed of the semiconductor material above. This is a trimming circuit in which an in-electrode is connected in parallel to a resistance element.

[0012] The trimming circuit according to one aspect of the present invention is made of a semiconductor material having a band gap of 2.5 eV or more. in a channel formation region thereof, and one of the source electrode or drain electrode of the first transistor and the gate of the third transistor The memory node is connected to one electrode of the capacitor element and the other electrode of the capacitor element. The band gap is 2. A transistor with a semiconductor material of 5 eV or more in the channel formation region has an off-leak current of The storage node having such a structure has an excellent charge retention capability, and the storage node is The operating state of the third transistor to which the gate electrode is connected can be stably maintained. , without changing the structure of the component (for example, without destroying the element or wiring) This allows the transistors in the 3-phase series to maintain their operating state for a long period of time, resulting in a highly reliable trimming circuit. We can provide a path.

[0013] The trimming circuit according to the embodiment of the present invention involves irreversible structural changes in its components. This allows the operating state of the third transistor to be changed without any need for a As a result, a rewritable trimming circuit can be provided. Cut.

[0014] In addition, one aspect of the present invention is a semiconductor memory device in which one electrode is connected to a storage node and the other electrode is connected to a ground potential line. The gate electrode is electrically connected to the write terminal, and the source electrode or drain electrode is electrically connected to the write terminal. One of the drain electrodes is electrically connected to the storage node, and the other is electrically connected to the power supply potential line. The transistor of 1 has a gate electrode connected to the erase terminal and either the source or drain electrode connected to the a second transistor electrically connected to the storage node and the other to a ground potential line; a third transistor having a gate electrode electrically connected to the storage node; and The off-leak current of the first transistor and the second transistor is 1 x 10 -17 A or less, and the source electrode and the drain electrode of the third transistor A trimming circuit in which the poles are connected in parallel to a resistive element.

[0015] The trimming circuit according to one embodiment of the present invention includes a first transistor having an extremely small off-leakage current. Specifically, the first transistor has a channel formation region formed of an oxide semiconductor. The magnitude of the off-leak current is 1 μm per 1 μm of channel width. 1×10 -17 A or less. The source electrode or drain electrode of each transistor a memory cell in which one of the electrodes is connected to a gate electrode of a third transistor and one of the electrodes of a capacitor element; The memory node having such a configuration has an excellent charge retention capability. The operating state of the third transistor, the gate electrode of which is connected to the first transistor, can be stably maintained. This allows the structure of the components to be maintained without being altered (for example, without destroying the elements or wiring). This allows the third transistor to remain in operation for a long period of time (without the need for a separate transistor). A timing circuit can be provided.

[0016] The trimming circuit according to the embodiment of the present invention involves irreversible structural changes in its components. This allows the operating state of the third transistor to be changed without any need for a As a result, a rewritable trimming circuit can be provided. Cut.

[0017] In one embodiment of the present invention, the first transistor and the second transistor are both The trimming circuit further includes an oxide semiconductor layer in the panel formation region.

[0018] The trimming circuit according to one embodiment of the present invention includes a first transistor having an extremely small off-leakage current. Specifically, the first transistor has a channel formation region formed with an oxide semiconductor layer. The transistors are provided with a source electrode or a drain electrode of each transistor. One of the electrodes is connected to the gate electrode of the third transistor and one of the electrodes of the capacitor element. A transistor including an oxide semiconductor layer has an extremely small off-leakage current. In addition, the oxide semiconductor layer can be easily formed by a sputtering method or the like. Furthermore, it is possible to provide a highly reliable trimming circuit for other semiconductor devices (for example, silicon monolithic devices). A trimming circuit can be formed by stacking on a semiconductor device using a crystal. A high-value semiconductor device can be provided.

[0019] In addition, one aspect of the present invention is a semiconductor memory device in which one electrode is connected to a storage node and the other electrode is connected to a ground potential line. The gate electrode is electrically connected to the write terminal, and the source electrode or drain electrode is electrically connected to the write terminal. One of the drain electrodes is electrically connected to the storage node, and the other is electrically connected to the power supply potential line. The transistor of 1 has a gate electrode connected to the erase terminal and either the source or drain electrode connected to the a second transistor electrically connected to the storage node and the other to a ground potential line; and a third transistor having a gate electrode electrically connected to the storage node. In addition, the off-leak current of the first transistor and the second transistor is 1 x 10 per -17 A or less, and the source electrode and drain electrode of the third transistor This is a method for driving a trimming circuit for a resistor element, in which electrodes are connected in parallel to the resistor element. The write terminal is connected to a signal that turns on the first transistor, and the erase terminal is connected to a signal that turns on the second transistor. A signal that turns off the first transistor is input, and the potential of the memory node is set to the third transistor. The first step is to set the potential at which the capacitor is turned on, and the second step is to set the potential at which the write terminal and the erase terminal are turned on. In addition, a first transistor and a second transistor are turned off by inputting a signal. A method for driving a trimming circuit that sets a resistor element in a trimmed state, the method including the steps of It is the law.

[0020] The method for driving the trimming circuit according to the aspect of the present invention further comprises: a step of applying a potential to the memory node so that the memory node is turned on; turning off the first and second transistors whose poles are connected; This allows the trimming circuit to be configured without changing the structure of any of the elements that make up the trimming circuit. This allows the operation state of the third transistor to be changed reversibly without any problem. It is possible to provide a method for driving a timing circuit.

[0021] In addition, one aspect of the present invention is a semiconductor memory device in which one electrode is connected to a storage node and the other electrode is connected to a ground potential line. The gate electrode is electrically connected to the write terminal, and the source electrode or drain electrode is electrically connected to the write terminal. One of the drain electrodes is electrically connected to the storage node, and the other is electrically connected to the power supply potential line. The transistor of 1 has a gate electrode connected to the erase terminal and either the source or drain electrode connected to the a second transistor electrically connected to the storage node and the other to a ground potential line; and a third transistor having a gate electrode electrically connected to the storage node. The off-leak current of the first transistor and the second transistor is 1×10 -17 A or less, and the source electrode and the drain electrode of the third transistor This is a method for driving a trimming circuit for a resistor element, in which the resistor element is connected in parallel. This is done by applying a signal to the write terminal that turns off the first transistor and applying a signal to the erase terminal that turns off the second transistor. A signal that turns on the transistor is input, and the potential of the storage node is changed by the third transistor. The first step is to set the potential to the OFF state, and the second step is to set the potential to the write terminal and the erase terminal. a second input terminal for inputting a signal that turns off the first transistor and the second transistor; and a step of driving a trimming circuit to make the resistor element available.

[0022] The method for driving the trimming circuit according to the aspect of the present invention further comprises: a step of applying a potential to the memory node so that the memory node is in an off state; turning off the first and second transistors whose poles are connected; This allows the structure of any element constituting the trimming circuit to be unchanged. This allows the operation state of the third transistor to be changed reversibly without any problem. It is possible to provide a method for driving a timing circuit.

[0023] In addition, one aspect of the present invention is to provide a method for writing a first transfer signal to a write terminal after the second step. A signal that turns on the second transistor is input to the erase terminal, and a signal that turns off the second transistor is input to the erase terminal. A signal is input to set the potential of the storage node to a potential at which the third transistor is turned on, or A signal that turns off the first transistor is applied to the write terminal, and a signal that turns off the second transistor is applied to the erase terminal. A signal that turns on the third transistor is input, and the potential of the storage node is set to the value that turns off the third transistor. The third step is a step in which the potential of the storage node is set to a potential different from that of the second step. a first transistor and a second transistor are connected to a write terminal and an erase terminal, respectively; and a fourth step of inputting a signal that turns the transistor off. This is a method for driving a trimming circuit that changes the trimming state.

[0024] The method for driving the trimming circuit according to one embodiment of the present invention is a method for driving the trimming circuit according to one embodiment of the present invention. a step of setting a potential at a level corresponding to the storage node; The method further includes turning off the first transistor and the second transistor. This allows the third trimming circuit to be reversibly changed without changing the structure of any of the elements that make up the trimming circuit. The operating state of the transistor can be changed, resulting in the driving of a rewritable trimming circuit. We can provide a method. [Effects of the Invention]

[0025] According to one embodiment of the present invention, a highly reliable trimming circuit can be provided. A trimming circuit that can be driven with high reliability can be provided. Alternatively, a method for driving a rewritable trimming circuit can be provided. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 2 is a diagram illustrating a configuration of a trimming circuit according to an embodiment. [Figure 2] 5A to 5C are diagrams illustrating the operation of a trimming circuit according to an embodiment. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a trimming circuit according to an embodiment. [Figure 4] 1A to 1C illustrate a manufacturing method of a trimming circuit according to an embodiment. [Figure 5] 1A to 1C illustrate a manufacturing method of a trimming circuit according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating a structure of an oxide material according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a structure of an oxide material according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a structure of an oxide material according to an embodiment. [Figure 9]1A to 1C are diagrams illustrating a structure of an oxide material according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0028] (Embodiment 1) In this embodiment, the source electrode or drain of a transistor with an extremely small off-leak current is a memory node connected to an input electrode, and a transistor having a gate electrode connected to the memory node; The configuration of the trimming circuit including the capacitor will be described with reference to FIG.

[0029] The configuration of a trimming circuit according to one embodiment of the present invention is shown in FIG. 00 is a circuit including the capacitor 140, the first transistor 110, and the second transistor 120. and a third transistor 130. The transistor 120 has a channel forming region made of a semiconductor material having a band gap of 2.5 eV or more. This transistor has extremely low off-leak current. By reducing the size of the storage node 150, the charge written to the storage node 150 can be retained for a long period of time. The oxide semiconductor layer with a band gap of 3.15 eV is provided in the channel formation region, and the off-leak current The size of 1×10 per 1 μm of channel width -17 A or less transistor is used. This can be done.

[0030] The transistors that can be used for the first transistor 110 and the second transistor 120 are: A semiconductor material with a band gap larger than the 1.12 eV of silicon semiconductor is called a sintered material. A transistor having a band gap of 2.5 is suitable. A transistor having a semiconductor material with a refractive index of 3.0 eV or more, preferably 3.0 eV or more, in a channel forming region. Specifically, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, carbide semiconductors, semiconductors It is possible to use a transistor having a diamond thin film or the like that exhibits such characteristics in the channel forming region. A transistor having a semiconductor material with a band gap of 2.5 eV or more in the channel formation region can be used. The transistor has a silicon semiconductor with a band gap of 1.12 eV in the channel formation region. The off-leak current can be made smaller than that of a conventional transistor.

[0031] In order to reduce the off-leak current of the first transistor and the second transistor, various Various transistor configurations can be used, for example, two or more transistors connected in series. A multi-gate transistor including a semiconductor layer having a channel forming region may be used. In addition, the distance (also called offset) between the source electrode or drain electrode and the channel forming region is A transistor provided with a gate insulating film (referred to as a gate insulating film) may be used.

[0032] The capacitance element 140 has one electrode connected to the storage node 150 and the other electrode connected to the ground potential line. They are electrically connected to each other.

[0033] The storage node 150 has a channel forming region made of a semiconductor material having a band gap of 2.5 eV or more. In preparation for this, a first transistor 110 and a second transistor The capacitor 140 is connected to the capacitor 120 and the capacitor 140. This can suppress the occurrence of a phenomenon in which the potential of the storage node 150 becomes unstable due to current or the like, thereby improving reliability. This is preferable because it fits perfectly.

[0034] The first transistor 110 has a gate electrode connected to a write terminal 115 and a source electrode or One of the drain electrodes is electrically connected to the storage node 150, and the other is electrically connected to the power supply potential line. The power supply potential line is supplied with a power supply potential Vdd that is higher than the ground potential.

[0035] The second transistor 120 has a gate electrode connected to an erase terminal 125 and a source or drain electrode connected to an erase terminal 126. One of the electrodes is electrically connected to the storage node 150, and the other is electrically connected to the ground potential line. do.

[0036] The third transistor 130 has a gate electrode electrically connected to the storage node 150 and a source The source electrode and the drain electrode are connected in parallel to the resistor element 105 .

[0037] The storage node 150 is connected to one electrode of the capacitance element 140, and the off-leak current is extremely large. The small first transistor 110 electrically isolates the power supply line, and The second transistor 120, which has a very small current, is electrically isolated from the ground potential line. The storage node 150 configured in this way can stably store the written charge for a long period of time. Can be maintained.

[0038] The third transistor 1 is connected to the storage node 150, which can stably hold the written charge for a long period of time. The gate electrode of the third transistor 30 is connected to the The operating state of the controller 130 (specifically, either the ON state or the OFF state) is maintained for a long period of time. can.

[0039] Furthermore, according to this configuration, the third component can be produced without irreversible structural changes of any of the components. Since the transistor 130 can be maintained in an operating state for a long period of time, it is particularly reliable. The potential of the storage node 150 is rewritten without any adverse structural changes, and the third transistor The operating state of the controller 130 can be changed any number of times.

[0040] According to one embodiment of the present invention, a highly reliable trimming circuit can be provided. A possible trimming circuit can be provided.

[0041] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0042] (Embodiment 2) In this embodiment, the source electrode or drain of a transistor with an extremely small off-leak current is a memory node connected to an input electrode, and a transistor having a gate electrode connected to the memory node; A method for driving a trimming circuit including a capacitor will be described with reference to FIG. A method for driving the trimming circuit 100 exemplified in the first embodiment will be described.

[0043] <Driving method example 1.> First, the elements and circuits connected in parallel to the trimming circuit are in an unusable state (trimming). A method for achieving the sintered state will be described with reference to FIG. 2(A) and FIG. 2(C).

[0044] A signal that turns on the first transistor 110 is input to the write terminal 115, and a signal that turns on the first transistor 110 is input to the erase terminal 12. A signal that turns off the second transistor 120 is input to the storage node 5. 150 is connected to the power supply line via the first transistor 110, and the charge is transferred to the capacitor element 14 0. Also, when the gate voltage The third transistor, whose source and drain electrodes are connected to the A current flows through the third transistor. This is the first step (see Figure 2(A)).

[0045] Next, a signal that turns off the first transistor 110 is applied to the write terminal 115. A signal that turns off the second transistor 120 is input to the terminal 125. As a result, The memory node 150 is electrically isolated from either the power supply line or the ground line. The charge written to the node 150 is held. This is the step (see Figure 2(C)).

[0046] The method for driving the trimming circuit 100 according to the embodiment of the present invention is as follows: A first step of setting the potential at which the transistor 130 of the storage node 15 is turned on; A first transistor 110 and a second transistor 111 each having a source electrode or a drain electrode connected to the The second step is to turn off the transistor 120. The third transistor 13 is provided without changing the structure of any of the elements that make up the circuit 100. 0 allows more current to flow, resulting in a more reliable trimming circuit. It can provide a way to do this.

[0047] <Driving method example 2.> Next, we will discuss how to make the elements and circuits connected in parallel to the trimming circuit available. This will be explained with reference to FIG. 2(B) and FIG. 2(C).

[0048] A signal that turns off the first transistor 110 is input to the write terminal 115, and a signal that turns off the first transistor 110 is input to the erase terminal 12. A signal that turns on the second transistor 120 is input to the storage node 5. 150 is connected to the ground potential line via the second transistor 120, and the storage node 150 is The third transistor, whose gate electrode is connected to the storage node 150, is connected to the ground potential. The transistor is turned off, and the resistor element 1 connected in parallel to its source and drain electrodes The current flows through the transistor 05. This is the first step of the driving method example 2. (See Figure 2(B)).

[0049] Next, a signal that turns off the first transistor 110 is applied to the write terminal 115. A signal that turns off the second transistor 120 is input to the terminal 125. As a result, The memory node 150 is electrically isolated from either the power supply line or the ground line. The charge written to the node 150 is held. This is the step (see Figure 2(C)).

[0050] The method for driving the trimming circuit 100 according to the embodiment of the present invention is as follows: a first step of setting the potential at which the transistor 130 of the storage node 15 is turned off; A first transistor 110 and a second transistor 111 each having a source electrode or a drain electrode connected to the The second step is to turn off the transistor 120. The third transistor 13 is provided without changing the structure of any of the elements that make up the circuit 100. A large amount of current flows through the resistor element 105 connected in parallel to the source electrode and drain electrode of As a result, a highly reliable method for driving the trimming circuit 100 can be provided. do.

[0051] <Driving method example 3.> Next, the trimming state is set using the method described in Driving Method Example 1 or Driving Method Example 2. A method for changing the settings of the trimming circuit 100 will be described below.

[0052] A signal that turns on the first transistor 110 is input to the write terminal 115, and a signal that turns on the first transistor 110 is input to the erase terminal 12. 5, a signal that turns off the second transistor 120 is input, and the voltage of the storage node 150 is The potential is set to a potential at which the third transistor 130 is turned on (see FIG. 2A), or A signal that turns off the first transistor 110 is input to an input terminal 115 and a signal that turns off the first transistor 110 is input to an erase terminal 125. A signal that turns on the second transistor 120 is input, and the potential of the storage node 150 is After the third transistor 130 is set to a potential at which it is turned off (see FIG. 2B), A storage node whose trimming state has been set using the method described in Example 1 or Driving Method Example 2. The steps up to this point are referred to as Driving Method Example 1 or Driving Method After the first and second steps of either of the driving methods described in Example 2 This is the third step of the driving method example 3.

[0053] Next, a signal that turns off the first transistor 110 is applied to the write terminal 115. A signal that turns off the second transistor 120 is input to the terminal 125. As a result, The memory node 150 is electrically isolated from either the power supply line or the ground line. The charge written to the node 150 is held. This is the step (see Figure 2(C)).

[0054] The method for driving the trimming circuit 100 according to one aspect of the present invention is to drive the potential of the storage node 150 by: A third switch is used to set the potential of the trimming circuit 100 to a different potential from that before driving the trimming circuit 100 using the driving method example 3. and a first transistor having a source electrode or a drain electrode connected to the storage node 150. a fourth step of turning off the first transistor 110 and the second transistor 120; This allows the trimming circuit to be adjusted without changing the structure of any of the elements that make up the circuit. The operating state of the third transistor 130 can be changed. A method for driving the logic circuit 100 can be provided.

[0055] <Modification> In the driving method example 3, a method for changing the operating state of the third transistor 130 is described. However, the operation state of the third transistor 130 is not changed, and the write terminal 115 and the erase terminal A driving method in which a signal is input again to 125 and data is written is also an embodiment of the present invention. This can be done.

[0056] The trimming circuit according to one embodiment of the present invention includes a first transistor 110 and a second transistor 120 is provided with a transistor with extremely small off-leak current, and writes to the storage node 150. The charge stored in the storage node 150 can be held for a long period of time. By inputting signals to the write terminal 115 and the erase terminal 125 so as to maintain Furthermore, reliability can be improved.

[0057] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0058] (Embodiment 3) In this embodiment, a configuration of a trimming circuit according to one embodiment of the present invention will be described with reference to FIG. Specifically, a transistor using a semiconductor other than an oxide semiconductor and a channel formation region and a transistor having an oxide semiconductor layer in a region thereof. do.

[0059] The configuration of a trimming circuit according to one embodiment of the present invention is shown in FIG. 3. FIG. 3(A) shows the trimming circuit 3 3(A) is a cross-sectional view taken along the line C1-C2 in FIG. 3(A). 3(C) is a cross-sectional view taken along the line D1-D2 shown in FIG. 3(A).

[0060] The trimming circuit 300 illustrated in FIG. 3 includes a third transistor 330 and a resistive element 305. A first transistor 31 is provided on a substrate 301 having a first insulating layer 304 interposed therebetween. 0, a second transistor 320, and a capacitor 340.

[0061] <Configuration of the third transistor and resistor element> In this embodiment, a channel formation region of the third transistor 330 is formed using a material other than an oxide semiconductor. The case where a semiconductor material is used will be described. Specifically, a silicon single crystal is used as the substrate 301. A structure in which a substrate is used and a third transistor 330 is formed on the surface thereof will be described ( See Figure 3(B)).

[0062] Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, and silicon dioxide. Congenerium germanium, silicon carbide, gallium arsenide, or the like can be used. An organic semiconductor material may also be used.

[0063] In addition, any semiconductor material may include an amorphous state or a crystalline state. It is preferable to use a single crystal semiconductor substrate because a transistor that can operate at high speed can be manufactured using the single crystal semiconductor substrate. stomach.

[0064] Also, SOI substrates can be used. Generally, an "SOI substrate" is a substrate with a The term "substrate" refers to a substrate having a structure in which a silicon semiconductor film is provided, but in this specification, etc., it refers to a substrate having an insulating surface. This also includes a substrate with a semiconductor film made of a material other than silicon. The semiconductor film of the SOI substrate is not limited to a silicon semiconductor film. The semiconductor device includes a structure in which a semiconductor film is provided on an insulating substrate such as a glass substrate via an insulating layer. It shall be possible.

[0065] An element isolation insulating layer 302 is provided to surround the third transistor 330. The gate electrode 331 of the transistor 330 is wired through an opening provided in the insulating layer 303. 332 is electrically connected to the

[0066] The bent portion of the wiring 335 made of the same conductive layer as the wiring 332 is the resistor element 305. The resistor element 305 functions as a resistor connected to the source electrode of the third transistor 330. and is connected in parallel to the drain electrode (see FIG. 3(A)).

[0067] <Configuration of Capacitor Element, First Transistor, and Second Transistor> The capacitor element 340 is provided with an insulating layer sandwiched between a wiring 341 and a wiring 352, and is The wiring 352 is formed through an opening formed in the insulating layer 304. 332 (see FIG. 3(B)).

[0068] The first transistor 310 includes an oxide semiconductor layer 313 formed over an insulating layer 304 and a gate insulating layer 315. A gate insulating layer 312 is provided between the wirings 311 which function as gate electrodes. 1 has an insulating layer on its side wall, and wiring 3 functions as a source electrode or a drain electrode. 51 and the wiring 352 (see FIG. 3(C)).

[0069] The second transistor 320 includes an oxide semiconductor layer 323 formed over the insulating layer 304 and a gate insulating layer 325. A gate insulating layer 322 is provided between the wirings 321 which function as gate electrodes. 1 has an insulating layer on its side wall, and wiring 3 functions as a source electrode or a drain electrode. 52 and the wiring 353 (see FIG. 3(C)).

[0070] The trimming circuit exemplified in this embodiment is a first transistor having an extremely small off-leak current. Specifically, the first transistor 310 has a channel forming region. The magnitude of the off-leak current of a transistor including an oxide semiconductor layer is determined by the channel width. 1 x 10 per μm -17 A or less. The off-leak current is extremely small (for example, 1×10 per 1 μm of channel width -17 A) and the voltage written to the storage node Can hold loads for long periods of time.

[0071] The trimming circuit exemplified in this embodiment includes a transistor including an oxide semiconductor layer. a transistor including an oxide semiconductor layer, The semiconductor device is provided on a substrate on which a transistor having a capacitance of 1000 Ω or less is formed. For example, a transistor that operates at high speed and an oxide semiconductor are used. Transistors using oxide semiconductors with reduced leak current can be combined and used. As a result, the long-term use of oxide semiconductors with reduced off-leakage current compared with semiconductors other than oxide semiconductors has been achieved. and a semiconductor device equipped with the trimming circuit. Cut.

[0072] The trimming circuit exemplified in this embodiment has a stacked structure. In this case, a transistor including an oxide semiconductor layer and a resistor are overlapped with each other. The area occupied by the trimming circuit can be reduced. This allows the semiconductor device to be miniaturized.

[0073] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0074] (Fourth embodiment) In this embodiment, a transistor that can be used in a trimming circuit of one embodiment of the present invention is Specifically, the structure of the FET is a semiconductor material with a band gap of 2.5 eV or more. The structure of a transistor provided in a channel formation region will be described. A manufacturing method of the transistor will be described in Embodiment 5.

[0075] The structure of a transistor exemplified in this embodiment will be described with reference to FIG. ) represents the cross section of a transistor.

[0076] The transistor 710 described as an example in this embodiment has a base insulating layer 704 over a substrate 701. an oxide semiconductor layer 713; a gate insulating layer 712; a gate electrode 711; and a source electrode Alternatively, the electrodes 751 and 752 function as drain electrodes, and the transistor protection layer and an insulating layer 705.

[0077] <Configuration of the underlying insulating layer> The insulating layer 704 serving as the base has an insulating surface, and the oxide semiconductor layer 704 in which the channel is formed is It serves as the foundation for 13.

[0078] The insulating layer 704 that serves as the base is made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or nitride. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, oxynitride One or more materials selected from aluminum oxide, hafnium oxide, gallium oxide, etc. The structure may be a single layer containing a layer or a laminated structure of two or more layers.

[0079] <Oxide semiconductor layer> The oxide semiconductor layer 713 in which a channel is formed is connected to a gate electrode via a gate insulating layer 712. Electrodes 751 and 752 overlap with the gate electrode 711 and are provided on either side of the gate electrode 711. The electrodes 751 and 752 are electrically connected to each other. It functions as:

[0080] The thickness of the oxide semiconductor layer 713 in which a channel is formed is preferably 2 nm to 200 nm. Or, it should be 5 nm or more and 30 nm or less.

[0081] Note that the oxide semiconductor layer 713 does not necessarily have to be processed into an island shape.

[0082] The oxide semiconductor layer 713 may be single-crystalline, polycrystalline (also referred to as polycrystalline), amorphous, or the like. The state is as follows.

[0083] Preferably, the oxide semiconductor layer is made of CAAC-OS (C Axis Aligned Cr The layer is a crystalline oxide semiconductor (COS) layer.

[0084] An example of a crystalline oxide semiconductor layer is a c-axis oriented (CAAC) crystal. An example of such a layer is an oxide semiconductor layer having c The details of the oxide semiconductor layer having axially-oriented crystals will be described in Embodiment 7.

[0085] The oxide semiconductor layer 713 preferably contains excess oxygen relative to the stoichiometric ratio. By adding an excess of oxygen, the generation of carriers due to oxygen vacancies in the metal oxide layer is suppressed. It is possible.

[0086] The oxide semiconductor layer 713 contains at least indium (In) or zinc (Zn). It is particularly preferable that the alloy contains In and Zn.

[0087] In addition, a transistor using the oxide semiconductor layer can be manufactured by a starter for reducing variations in electrical characteristics of the transistor. It is preferable to have gallium (Ga) as a barrier in addition to these. It is preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf). Also, aluminum is used as a stabilizer. It is preferable to have (Al).

[0088] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0089] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0090] Here, for example, the In-Ga-Zn-O based material is a material containing indium (In), gallium (G a) means an oxide containing zinc (Zn), regardless of its composition ratio. Metal elements other than In, Ga, and Zn may be included. For example, even if SiO2 is included, good.

[0091] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0092] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0093] <Gate insulating layer> The gate insulating layer 712 is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. tantalum oxide, gallium oxide, aluminum oxide, aluminum oxynitride, etc. It is possible.

[0094] The gate insulating layer 712 may also be made of a high-k material. Materials include hafnium oxide, yttrium oxide, lanthanum oxide, and hafnium silicate. (HfSi x O y (x>0, y>0)), hafnium aluminate (HfAl x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x> 0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z Examples include (x>0, y>0, z>0).

[0095] The gate insulating layer 712 may have a single layer structure or a stacked layer structure. Layers containing -k materials and silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride Alternatively, the insulating film may have a laminated structure with a layer containing a material selected from the group consisting of silicon dioxide, aluminum oxide, and the like.

[0096] The gate insulating layer 712 can be thinned or made of the high-k material described above. This allows transistors to be miniaturized without sacrificing their operating characteristics.

[0097] For example, when silicon oxide is used, the thickness is 1 nm or more and 100 nm or less, preferably 10 nm or less. The thickness can be set to 50 nm or more.

[0098] On the other hand, when using high-k materials, the thickness is reduced to prevent gate capacitance due to the tunneling effect. Transistors can be miniaturized without becoming so thin that they cause leaks.

[0099] Note that an insulating material containing a Group 13 element and oxygen can be used for the gate insulating layer 712. The insulating material containing a Group 13 element is an insulating material containing one or more Group 13 elements. means.

[0100] For example, gallium oxide, aluminum oxide, aluminum gallium oxide, gallium oxide Aluminum is an example of an insulating material containing a Group 13 element and oxygen. Here, aluminum gallium oxide is a material that has a gallium content (atomic %) of aluminum. It indicates the content (atomic %) of gallium. (atomic %) indicates that the aluminum content (atomic %) is equal to or greater than that.

[0101] Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements are oxides. Therefore, insulating materials containing group 13 elements and oxygen are By using it in the insulating layer in contact with the oxide semiconductor layer, the state of the interface with the oxide semiconductor layer can be improved. It can be maintained.

[0102] For example, when a gate insulating layer is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide for the gate insulating layer, the boundary between the oxide semiconductor layer and the gate insulating layer can be The surface characteristics can be maintained well.

[0103] In addition, by providing the oxide semiconductor layer and the insulating layer containing gallium oxide in contact with each other, It is possible to reduce the pile-up of hydrogen at the interface between the semiconductor layer and the insulating layer.

[0104] For example, it is also effective to form the insulating layer using a material containing aluminum oxide. Aluminum oxide has the property of being difficult to permeate with water, so the use of this material This is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0105] In this way, when an element of the same group as the component element of the oxide semiconductor is used for the insulating layer, It is possible to obtain the effect.

[0106] <Gate electrode> The gate electrode 711 overlaps with the oxide semiconductor layer 713 with the gate insulating layer 712 interposed therebetween. It functions as the gate electrode of the resistor 710.

[0107] The gate electrode 711 may have a single layer structure containing a conductive material or a stacked structure of two or more layers. That's fine.

[0108] The conductive material may be any material that can withstand the heat treatment process, such as molybdenum, titanium, or titanium. One of the following metals is selected from the group consisting of aluminum, tungsten, aluminum, copper, neodymium, and scandium. metals or alloys containing one selected from these can be used.

[0109] In addition, semiconductor layers such as polycrystalline silicon layers doped with impurity elements such as phosphorus, A silicide layer such as nickel silicide may also be used.

[0110] <Insulating layer on gate electrode and sidewall> The insulating layer 714a on the gate electrode overlaps the gate electrode 711 and has insulating properties.

[0111] The sidewall 714b is formed by the gate insulating layer 712, the gate electrode 711, and the insulating layer on the gate electrode. It is in contact with the side surface of the laminated body of 714a and has an insulating layer.

[0112] <Source and drain electrodes> The electrode 751 and the electrode 752 are both electrically connected to the oxide semiconductor layer 713. They function as the source and drain electrodes of the transistor.

[0113] The electrode functioning as the source electrode or the drain electrode has a single layer structure containing a conductive material. Alternatively, it may have a laminated structure of two or more layers.

[0114] The conductive material may be any material that can withstand the heat treatment process, such as aluminum, chromium, or copper. a metal selected from titanium, tantalum, molybdenum and tungsten, or An alloy containing one selected from the group consisting of manganese, magnesium, and zinc can also be used. a metal selected from the group consisting of zinc, beryllium, neodymium and scandium, or An alloy containing one selected from these may also be used.

[0115] The conductive material may be a metal nitride, such as titanium nitride or molybdenum nitride. Examples include buten and tungsten nitride.

[0116] The conductive material may be a conductive metal oxide. Tin oxide, indium tin oxide (also known as ITO), indium zinc oxide, Zinc oxide, zinc oxide doped with gallium or aluminum, or these metal oxides A material containing silicon oxide can be used.

[0117] In addition, graphene or the like can be used as the conductive material.

[0118] For example, a single layer structure made of titanium or titanium nitride, or a single layer structure made of aluminum containing silicon , a two-layer structure with a titanium layer laminated on an aluminum layer, and a titanium layer laminated on a titanium nitride layer and a three-layer structure consisting of a titanium layer, an aluminum layer and another titanium layer. It can be obtained.

[0119] The channel length (L) of the transistor is determined by the distance between the edge of the source electrode in contact with the oxide semiconductor layer and the oxide semiconductor layer. The distance is determined by the distance between the ends of the drain electrode that contact the oxide semiconductor layer.

[0120] <Insulating layer to protect transistors> The insulating layer 705 for protecting the transistor prevents impurities such as moisture from entering from the outside. , a layer that protects the transistor.

[0121] The thickness of the insulating layer 705 is at least 1 nm or more.

[0122] The insulating layer 705 may have a single-layer structure including an insulator having a barrier property or a stack structure of two or more layers. It may be a structure.

[0123] In particular, a structure containing aluminum oxide is preferable, and a structure containing an aluminum oxide layer and other inorganic insulating materials Aluminum oxide can be used as a laminated structure with a layer containing a material. This is because it is difficult for objects to pass through.

[0124] The insulating layer 705 is a stack of an oxide insulating layer having an oxygen excess region and an aluminum oxide layer. an oxide insulating layer having an oxygen excess region on the oxide semiconductor layer side; Good too.

[0125] The oxide insulating layer having an oxygen excess region is, for example, a silicon oxide film, a silicon oxynitride film, or the like. can be used.

[0126] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0127] (Embodiment 5) In this embodiment, the semiconductor material having a band gap of 2.5 eV or more described in the fourth embodiment is A method for manufacturing a transistor 710 having a channel formation region made of a material will be described with reference to FIGS. Reveal.

[0128] <Formation of the insulating layer that serves as the base> First, an insulating layer 704 is formed as a base for an oxide semiconductor layer in which a channel is to be formed. The insulating layer 704 serving as the base is formed on the substrate 701 by plasma CVD or sputtering. Form more.

[0129] The substrate 701 is made of a material that can withstand the processes that follow the process of forming the insulating layer that serves as the base. There is no limitation on the size of the material as long as it has heat resistance.

[0130] The substrate 701 may have other semiconductor elements already provided thereon.

[0131] The substrate 701 may be made of, for example, barium borosilicate glass or aluminoborosilicate glass. A glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, silicon gate Compound semiconductor substrates such as ruthenium substrates, SOI substrates, etc. can also be used.

[0132] A flexible substrate may be used as the substrate 701. It may be fabricated directly, or the transistor may be fabricated on another fabrication substrate and then peeled off onto the flexible substrate. In the case of peeling or transferring from the formation substrate to a flexible substrate, A separation layer may be provided between the oxide semiconductor layer and the transistor including the oxide semiconductor layer.

[0133] <Formation of oxide semiconductor layer> Next, an oxide semiconductor layer 713 in which a channel is to be formed is formed over the insulating layer 704 serving as a base. do.

[0134] The oxide semiconductor layer can be formed by sputtering, molecular beam epitaxy, atomic layer deposition, or pulse deposition. The film can be formed by laser deposition.

[0135] For example, when an In-Ga-Zn-O-based material is used as the oxide semiconductor, the target is The target can be made using a variety of materials and their composition ratios. For example, In2O3, Ga2O3, and ZnO can be mixed in a molar ratio of 1:1:1. An oxide target containing In2O3:Ga2O3:ZnO can be used. For example, In2O3, Ga2O3, and ZnO can be mixed in a molar ratio of 1:1:2 (= An oxide target containing In2O3:Ga2O3:ZnO can also be used. .

[0136] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, The atomic ratio of metal elements is In:Zn=50:1 to 1:2 (converted to molar ratio, InO In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn= 15:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0137] In addition, for example, when an In-Sn-Zn-O-based material is used as the oxide semiconductor, The composition ratio of the target can be varied. For example, the atomic ratio of In, Sn, and Zn is 1:2:2 (=In:Sn:Zn). In addition, for example, an oxide target containing In, Sn, and Zn can be used. An oxide target containing In:Sn:Zn in an atomic ratio of 2:1:3 is used. For example, In, Sn, and Zn can be mixed in an atomic ratio of 1:1:1 (=In:Sn An oxide target containing In and S in a ratio of Zn can be used. Oxide ternary containing In and Zn in the atomic ratio of 20:45:35 (=In:Sn:Zn) A get can be used.

[0138] The relative density of the target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. % or less. By using a target with a high relative density, the oxide semiconductor layer formed can be a dense film.

[0139] In addition, the carrier density of the oxide semiconductor layer can be reduced to make the oxide semiconductor layer substantially i-type. The details of the method will be explained in the sixth embodiment.

[0140] Next, a resist mask is formed by a photolithography process. Then, the oxide semiconductor layer is selectively etched to form island-shaped regions (see FIG. 4A).

[0141] Note that when the resist mask is etched while being recessed, the oxide semiconductor layer is tapered. When the island-shaped oxide semiconductor layer is tapered, the cross section of the layer formed after this step can be reduced. It prevents breakage and improves coverage.

[0142] <Formation of gate insulating layer, gate electrode, and insulating layer on gate electrode> Next, the gate insulating layer 712, the gate electrode 711, and the insulating layer 714a on the gate electrode are The stack is formed over the oxide semiconductor layer 713 .

[0143] The insulating layer that will become the gate insulating layer and the insulating layer that will become the insulating layer on the gate electrode are formed by plasma CVD. The film is formed by a deposition method, a sputtering method, or the like.

[0144] The conductive layer that will become the gate electrode is formed by sputtering or the like.

[0145] Next, a resist mask is formed by a photolithography process. The insulating layer that will become the gate insulating layer, the conductive layer that will become the gate electrode, and the insulating layer on the gate electrode are The insulating layer is etched to form a gate insulating layer 712, a gate electrode 711, and a gate electrode An upper insulating layer 714a is formed as a laminate.

[0146] <Sidewall formation> Next, the sidewall 714b is formed by insulating the gate insulating layer 712, the gate electrode 711, and the insulating layer on the gate electrode. The edge layer 714a is formed adjacent to the side of the laminate.

[0147] The insulating layer that becomes the sidewall is formed by using a plasma CVD method, a sputtering method, or the like.

[0148] Next, anisotropic etching is performed to leave the insulating layer in contact with the side surface of the stacked body, forming a side wall. (See Figure 4(B)).

[0149] <Formation of an electrode that functions as a source electrode or a drain electrode> Next, an electrode 751 and an electrode 752 which function as a source electrode and a drain electrode are formed. .

[0150] The layer containing a conductive material to be the source electrode or the drain electrode is formed by sputtering or the like. The film is formed.

[0151] Next, a resist mask is formed by a photolithography process. Then, the layer containing the conductive material is selectively etched to form the electrodes 751 and 752 (see FIG. 4(C). Wiring (not shown) made of a layer containing the same conductive material is also formed in the same process. Formed by.

[0152] The channel length (L) is 10 nm or more and 1000 nm (1 μm) or less, especially less than 25 nm. When forming a transistor, extreme ultraviolet rays with a wavelength of several nanometers to several tens of nanometers are used. It is preferable to form a mask using ultraviolet light. This is because it has high resolution and a large depth of focus.

[0153] Note that the electrodes functioning as the source electrode or the drain electrode may be formed to have a tapered shape. If the electrodes that function as source electrodes or drain electrodes are tapered, the electrodes that are formed after this process can be used. This prevents the layer (for example, the gate insulating layer) from being broken and improves coverage. The angle is preferably, for example, between 30° and 60°.

[0154] When the layer containing the conductive material has a single layer structure of titanium layer or titanium nitride layer, the tapered It is easy to process the source and drain electrodes into a shaped electrode.

[0155] <Formation of insulating layer to protect transistors> Next, an insulating layer 705 is formed to protect the transistor.

[0156] The insulating layer that protects the transistor is formed using plasma CVD or sputtering. do.

[0157] Through the above steps, a transistor using an oxide semiconductor material in a channel formation region is obtained. 710 can be created.

[0158] Note that the resist mask used in this embodiment is formed by a photolithography process. In addition to the photolithography method, inkjet method, printing method, etc. The resist mask can be formed without using a photomask. This reduces the manufacturing cost of the semiconductor device.

[0159] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0160] (Embodiment 6) In this embodiment, an off-leak current that can be used in the trimming circuit of one embodiment of the present invention is The flow is extremely small (e.g., 1 × 10 per μm of channel width). -17 A and below) Trans Specifically, a method for forming an oxide semiconductor layer that can be applied to a semiconductor device will be described. A method for manufacturing an oxide semiconductor layer in which the resistance is reduced and which is substantially i-type will be described with reference to FIG. .

[0161] <Configuration of the underlying insulating layer and its manufacturing method> At least the oxide semiconductor of the insulating layer 504 that is the base of the oxide semiconductor layer in which the channel is formed is The region in contact with the insulating layer preferably includes an insulating layer from which oxygen is released by heat treatment. When the insulating layer 504 has an oxygen-excess region, oxygen is transferred from the oxide semiconductor layer to the insulating layer 504. The phenomenon of migration can be prevented, and by carrying out a heat treatment described later, the insulating layer 504 This is because oxygen can be supplied to the oxide semiconductor layer from the source.

[0162] When the base insulating layer has a stacked structure, the oxide insulating layer having an oxygen excess region is formed by It is more preferable that the conductive layer be provided thereon.

[0163] For example, the insulating layer serving as the base is formed from a silicon oxide layer having an oxygen excess region from the oxide semiconductor layer side. A laminated structure of a silicon layer and an aluminum oxide layer is preferable.

[0164] In this specification, the phrase "oxygen is released by heat treatment" refers to the TDS (Therm Thermal Desorption Spectroscopy (TDE) analysis The amount of oxygen released (or desorbed) converted to oxygen atoms is 1.0 x 10 18 cm -3 That's all, Preferably 3.0 x 10 20 cm -3 In addition, "heat treatment reduces the amount of oxygen "Does not desorb" refers to the amount of oxygen desorbed (or released) converted to oxygen atoms in TDS analysis. is 1.0×10 18 cm -3 It means that it is less than.

[0165] As a method for forming an insulating layer from which oxygen is released by heat treatment, a method for forming a film in an oxygen atmosphere is used. or a method for forming a film by using oxygen (at least oxygen radicals, oxygen atoms or oxygen ions) Examples of the method include a method of injecting a

[0166] Oxygen injection methods include ion implantation, ion doping, and plasma immersion. On-implantation methods, plasma treatment, etc. can be used.

[0167] <Method 1 for forming an oxide semiconductor layer with reduced impurity concentration: Film formation method> The oxide semiconductor layer 413a is formed over a base insulating layer 504 (see FIG. 5A). The oxide semiconductor layer 413a is an oxide semiconductor layer in which a channel is formed later. The impurities containing hydrogen atoms are formed to be excluded as much as possible. This is because donor levels are easily formed in the oxide semiconductor layer.

[0168] As a method for manufacturing an oxide semiconductor layer in which impurities including hydrogen atoms are reduced, sputtering It is preferable to form the film by using a coating method. In particular, it is preferable to form the film by using an insulating layer that is not exposed to the atmosphere as a base. In this case, a method of forming an oxide semiconductor layer continuously on the insulating layer is preferable.

[0169] For example, impurities including hydrogen attached to the substrate surface are removed by heat treatment or plasma treatment. After that, the insulating layer is formed without exposing it to the atmosphere. An oxide semiconductor layer may be formed on the surface of the insulating layer. The impurities, including the hydrogen adsorbed on the substrate, are reduced, and the interface between the substrate and the underlying insulating layer and the underlying insulating layer are also reduced. This can prevent atmospheric components from adhering to the interface between the insulating layer and the oxide semiconductor layer.

[0170] Note that before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced into a treatment chamber. Inverse sputtering is performed by introducing a gas to generate plasma, and a film is attached to the surface of the insulating layer. It is preferable to remove adhering powdery substances (also called particles or dust).

[0171] Reverse sputtering is a process in which no voltage is applied to the target side, but the target side is sputtered in an argon atmosphere. This is a method of modifying the surface by applying voltage using an RF power source to form plasma near the substrate. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0172] In addition, it is preferable to form the oxide semiconductor layer using a treatment chamber with a small leakage rate. Specifically, the leak rate of the sputtering equipment processing chamber is set to 1×10 -10 Pa·m 3 / sec or less, alkali metal and hydride are not introduced into the oxide semiconductor layer during the film formation. It is possible to reduce the inclusion of impurities such as

[0173] The oxide semiconductor layer is evacuated using an adsorption type vacuum pump (for example, a cryopump). It is preferable to form the film in the processing chamber of the sputtering equipment that is evacuated. Reducing backflow of impurities such as metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides can be done.

[0174] In addition, the oxide semiconductor layer is formed by supplying a high-purity atmospheric gas into a processing chamber of a sputtering apparatus. Specifically, a method of forming a film using water, a compound containing a hydroxyl group, or a hydride is preferred. High-purity rare gas (typically argon) from which impurities have been removed, oxygen, or rare gas and oxygen A mixed gas containing oxygen and nitrogen is used as appropriate.

[0175] For example, the purity of argon is 9N (99.9999999%) or more (H2O is 0.1p pb, H2 is 0.5ppb), and the dew point is -121°C. The purity of oxygen is 8N (99.999999%) or more (H2O is 1 ppb, H2 is 1 ppb), and dew point - Set the temperature to 112°C.

[0176] When a mixture of rare gas and oxygen is used, it is preferable to increase the flow rate of oxygen. I wish.

[0177] <<Example of film formation conditions for an oxide semiconductor layer>> As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film This is preferable because the thickness distribution is uniform.

[0178] <Method 2 for Forming Oxide Semiconductor Layer with Reduced Impurity Concentration: First Heat Treatment> The oxide semiconductor layer 413b is formed by removing impurities including hydrogen atoms as much as possible (FIG. 5B). reference).

[0179] As a method for manufacturing an oxide semiconductor layer in which impurities including hydrogen atoms are reduced, To reduce impurities such as water or hydrogen in the body layers (also called dehydration or dehydrogenation) In this case, a method in which the oxide semiconductor layer is subjected to a first heat treatment is preferable.

[0180] In the case where the first heat treatment is performed, oxygen is released from the insulating layer in contact with the oxide semiconductor layer by the heat treatment. It is preferable to use an insulating layer containing hydrogen atoms, because the first heat treatment can remove impurities containing hydrogen atoms. This is because oxygen is released from the oxide semiconductor layer together with the impurities. Some of the oxygen vacancies generated in the oxide semiconductor layer become donors, and carriers are transported to the oxide semiconductor layer. This may cause a problem that affects the characteristics of the transistor.

[0181] The temperature of the first heat treatment is, for example, 150° C. or higher and lower than the substrate strain point temperature, preferably 250° C. The temperature is preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower.

[0182] The time for the first heat treatment is 3 minutes to 24 hours. Heat treatment for more than 24 hours will decrease productivity. It is not desirable because it invites

[0183] The first heat treatment is carried out in an oxidizing atmosphere or an inert atmosphere. It refers to an atmosphere containing 10 ppm or more of oxidizing gases such as ozone or oxygen nitride. The inert atmosphere contains less than 10 ppm of the above-mentioned oxidizing gases, and the other gases are nitrogen or dilute. A gas-filled atmosphere.

[0184] For example, under a reduced pressure atmosphere, under an inert gas atmosphere such as nitrogen or a rare gas, under an oxygen gas atmosphere, The dew point was measured using an ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)) dew point meter. The moisture content measured by the method is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm Hereinafter, the atmosphere is more preferably 10 ppb or less (air).

[0185] In addition, nitrogen or rare gases such as helium, neon, and argon do not contain water or hydrogen. Alternatively, nitrogen, helium, neon, or aluminum may be introduced into the heat treatment device. The purity of rare gases such as argon is 6N (99.9999%) or more, preferably 7N (99.999%). 99%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is preferable that:

[0186] The heating device used in the first heat treatment is not particularly limited. The heating device may be a resistance heating element or the like. The apparatus may be provided with a device for heating the object to be treated by heat conduction or heat radiation from a heating element. .

[0187] For example, electric furnaces and LRTA (Lamp Rapid Thermal Annealing) ng) equipment, GRTA (Gas Rapid Thermal Annealing) equipment It is possible to use an RTA (Rapid Thermal Annealing) device such as a LRTA devices can be used with halogen lamps, metal halide lamps, and xenon arc lamps. The radiation emitted from lamps such as high-pressure sodium lamps, carbon arc lamps, and high-pressure mercury lamps The GRTA device heats the object to be treated by radiating light (electromagnetic waves) that This is an apparatus for performing heat treatment using gas.

[0188] By performing the first heat treatment, hydrogen (water, a compound containing a hydroxyl group) is released from the oxide semiconductor layer. The first heat treatment reduces impurities and produces i-type (intrinsic) Alternatively, a substantially i-type oxide semiconductor layer can be formed.

[0189] The first heat treatment causes hydrogen, which is a source of unstable carriers, to be desorbed from the oxide semiconductor layer. This makes it possible to suppress the phenomenon in which the threshold voltage of the transistor shifts in the negative direction. Furthermore, the reliability of the transistor can be improved.

[0190] <Modification> After the first heat treatment, oxygen (at least oxygen radicals, oxygen atoms, or ions) may be implanted.

[0191] Oxygen injection methods include ion implantation, ion doping, and plasma immersion. On-implantation methods, plasma treatment, etc. can be used.

[0192] <Configuration of gate insulating layer and method for manufacturing same> At least the oxide of the gate insulating layer 512 covering the oxide semiconductor layer 513 in which the channel is formed is The region in contact with the compound semiconductor layer preferably includes an insulating layer from which oxygen is released by heat treatment. This is because when the gate insulating layer 512 has an oxygen-excess region, the gate This can prevent the phenomenon of oxygen migration to the gate insulating layer 512, and the second heating step described later can be performed. By performing the treatment, oxygen can be supplied from the gate insulating layer 512 to the oxide semiconductor layer 513. That's why.

[0193] When the insulating layer covering the oxide semiconductor layer in which the channel is formed has a stacked structure, the oxygen excess region It is more preferable that the oxide insulating layer having the above structure be provided on the oxide semiconductor layer side.

[0194] For example, the insulating layer covering the oxide semiconductor layer in which the channel is formed is formed as follows from the oxide semiconductor layer side: A structure having a stacked structure of a silicon oxide layer having an oxygen excess region and an aluminum oxide layer. is preferred.

[0195] The aluminum oxide layer has the effect of preventing the permeation of both impurities such as hydrogen and moisture, and oxygen. In other words, the blocking effect is high, and after forming the aluminum oxide layer, a second treatment is performed. This is because the heat treatment can prevent oxygen from being released from the oxide semiconductor layer.

[0196] <Formation of gate insulating layer, gate electrode, and insulating layer on gate electrode> Next, the gate insulating layer 512, the gate electrode 511, and the insulating layer 514a on the gate electrode are The stack is formed over the oxide semiconductor layer 513 .

[0197] The insulating layer that will become the gate insulating layer and the insulating layer that will become the insulating layer on the gate electrode are formed by plasma CVD. The film is formed by a deposition method, a sputtering method, or the like.

[0198] The conductive layer that will become the gate electrode is formed by sputtering or the like.

[0199] Next, a resist mask is formed by a photolithography process. The insulating layer that will become the gate insulating layer, the conductive layer that will become the gate electrode, and the insulating layer on the gate electrode are The insulating layer is etched to form a gate insulating layer 512, a gate electrode 511, and a gate electrode An upper insulating layer 514a is formed as a laminate.

[0200] <Sidewall formation> Next, the insulating layer 514b is formed on the gate insulating layer 512, the gate electrode 511, and the The insulating layer 514a is formed in contact with the side wall of the laminate.

[0201] The insulating layer that becomes the sidewall is formed by using a plasma CVD method, a sputtering method, or the like.

[0202] Next, anisotropic etching is performed to leave the insulating layer in contact with the side surface of the stacked body, forming a side wall. .

[0203] <Method 1 for Manufacturing Oxygen-Supplied Oxide Semiconductor Layer: Second Heat Treatment> The oxide semiconductor layer 513 in which a channel is formed is preferably an oxide semiconductor layer to which oxygen is supplied. In particular, an oxide semiconductor layer in which oxygen vacancies are filled is preferable. The part acts as a donor, generating carriers in the oxide semiconductor layer, which affects the characteristics of the transistor. This is because there is a risk of this happening.

[0204] As a method for manufacturing an oxide semiconductor layer to which oxygen is supplied, a method for manufacturing an oxide semiconductor layer in which oxygen is released by heat treatment is used. A method in which a second heat treatment is performed in a state in which the insulating layer and the oxide semiconductor layer in which a channel is formed are in contact with each other. Specifically, an insulating layer from which oxygen is released by heat treatment is used to form an insulating substrate. An insulating layer is formed to cover the edge layer and / or the region where the channel is to be formed, and a second heat treatment is performed. This treatment may be performed to supply oxygen to the oxide semiconductor layer (see FIG. 5C).

[0205] Note that the second heat treatment is performed by applying an oxide film to a region of the oxide semiconductor layer where a channel is to be formed. After the insulating layer including the insulating layer from which the element is released is formed in contact with the insulating layer, Even if there is, it will be effective.

[0206] In particular, from the oxide semiconductor layer side, a silicon oxide layer having an oxygen excess region and a blocking effect (blocking effect) The aluminum oxide layer has a laminated structure with a high blocking effect. It is preferable to carry out the second heat treatment in this state.

[0207] The second heat treatment is carried out in an atmosphere of nitrogen, oxygen, or ultra-dry air (with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less of air), or rare gases (argon, helium The reaction may be carried out under an atmosphere of nitrogen, oxygen, ultra-dry air, or a rare gas. It is preferable that the atmosphere does not contain water, hydrogen, etc. Also, nitrogen, oxygen, etc. introduced into the heat treatment device The purity of the element or rare gas is 6N (99.9999%) or more, preferably 7N (99.99%). 999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is preferable.

[0208] <<Method for measuring the amount of oxygen released converted into oxygen atoms>> The following describes a method for quantifying the amount of released oxygen by converting it into oxygen atoms using TDS analysis.

[0209] The amount of gas desorbed during TDS analysis is proportional to the integral value of the spectrum. The amount of gas desorption is calculated from the ratio of the integral value of the spectrum of the layer to the reference value of the standard sample. The reference value of the standard sample is the integral of the spectrum of the sample containing the specified atom. is the ratio of the atomic density to the value.

[0210] For example, the TDS analysis results of a silicon wafer containing a specified density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating layer, the amount of oxygen molecules desorbed from the insulating layer (N O2 ) is calculated using Equation 1. Here, the entire spectrum detected at mass number 32 obtained by TDS analysis can be It is assumed that all of the atoms are derived from oxygen molecules. There is a molecule with a mass number of 32, CH3OH, but it may exist. The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is is not taken into consideration because it is an extremely small amount.

[0211] N O2 =N H2 / S H2 ×S O2 ×α (Equation 1)

[0212] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the material is subjected to TDS analysis is shown in Fig. 1. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the spectrum obtained by TDS analysis of the insulating layer. α is a coefficient that affects the spectral intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The standard test was carried out using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. 1 x 10 as a fee 16 cm -3 The values ​​were measured using a silicon wafer containing hydrogen atoms. be.

[0213] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0214] Note that NO2 is the amount of oxygen molecules released. In the insulating layer, when converted to oxygen atoms, The amount of oxygen released is twice the amount of oxygen molecules released.

[0215] An example of a layer from which oxygen is released by heat treatment is silicon oxide (SiOx(x >2)). Silicon oxide with excess oxygen (SiOx(x>2)) is a silicon atom It contains more than twice the number of oxygen atoms per unit volume. The numbers of carbon atoms and oxygen atoms are values ​​measured by Rutherford backscattering spectroscopy.

[0216] <Formation of an electrode that functions as a source electrode or a drain electrode> Next, an electrode 551 and an electrode 552 which function as a source electrode and a drain electrode are formed. .

[0217] The layer containing a conductive material to be the source electrode or the drain electrode is formed by sputtering or the like. The film is formed.

[0218] Next, a resist mask is formed by a photolithography process. Then, the layer containing the conductive material is selectively etched to form the electrodes 551 and 552. Wiring and the like (not shown) made of a layer containing the same conductive material are also formed in the same process.

[0219] The channel length (L) is 10 nm or more and 1000 nm (1 μm) or less, especially less than 25 nm. When forming a transistor, extreme ultraviolet rays with a wavelength of several nanometers to several tens of nanometers are used. It is preferable to form a mask using ultraviolet light. This is because it has high resolution and a large depth of focus.

[0220] Note that the electrodes functioning as the source electrode or the drain electrode may be formed to have a tapered shape. If the electrodes that function as source electrodes or drain electrodes are tapered, the electrodes that are formed after this process can be used. This prevents the layer (for example, the gate insulating layer) from being broken and improves coverage. The angle is preferably, for example, between 30° and 60°.

[0221] When the layer containing the conductive material has a single layer structure of titanium layer or titanium nitride layer, the tapered It is easy to process the source and drain electrodes into a shaped electrode.

[0222] <Formation of insulating layer to protect transistors> Next, an insulating layer 505 is formed to protect the transistor.

[0223] The insulating layer that protects the transistor is formed using plasma CVD or sputtering. (See Figure 5(D)).

[0224] As described above, the generation of carriers in the oxide semiconductor layer where the channel is formed can be suppressed. This can suppress fluctuations in the transistor characteristics.

[0225] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0226] (Embodiment 7) In this embodiment, an off-leak current that can be used in the trimming circuit of one embodiment of the present invention is The flow is extremely small (e.g., 1 × 10 per μm of channel width). -17 A and below) Trans Specifically, an oxide semiconductor layer having c-axis oriented crystals will be described. The compound semiconductor layer will now be described.

[0227] In this embodiment, the c-axis is oriented and the crystal is triangular or triangular when viewed from the ab-plane, surface, or interface direction. The metal atoms are arranged in layers or in a combination of metal atoms and oxygen atoms along the c-axis. The molecules are arranged in layers, and the orientation of the a-axis or b-axis is different in the ab plane (the c-axis is the center). C-Axis Aligned Crystal (CAAC) This section explains oxides containing .

[0228] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0229] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0230] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0231] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0232] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0233] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0234] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0235] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that constitutes the CAAC is in a certain direction (for example, the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface on which the CAAC is formed, It may be oriented in a direction perpendicular to the surface of the AC.

[0236] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Do it.

[0237] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0238] An example of the crystal structure contained in CAAC will be described in detail with reference to FIGS. 6 to 8, unless otherwise specified, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is The ab plane is the boundary. When we simply refer to the upper half and the lower half, we mean the upper half when the ab plane is used as the boundary. In Figure 6, the circled O atom indicates a tetrahedral O atom, and the double circle indicates a tetrahedral O atom. The O atom surrounded by indicates a three-coordinate O atom.

[0239] Figure 6(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms ( Here, we show a structure having a tetracoordinated O atom and a metal atom. The structure shown in Figure 6(A) is an octahedral structure. However, for simplicity, it is shown as a planar structure. Each group has three tetracoordinated O atoms. The small group shown in Figure 6(A) has a zero charge.

[0240] Figure 6(B) shows a structure of a Ga atom with five coordinates and three oxygen atoms ( The structure shown here has a tricoordinated O atom (hereinafter referred to as a Ga atom) and two tetracoordinated O atoms adjacent to the Ga atom. The three-coordinated O atoms are all located on the ab plane. Each of the has one tetrahedral O atom. In addition, the In atom also has five coordinates, so as shown in Figure 6( The small group shown in Figure 6(B) has a zero charge.

[0241] Figure 6(C) shows one tetrahedral Zn atom and four tetrahedral O atoms adjacent to the Zn atom. The upper half of Figure 6(C) shows a structure with one tetracoordinate O atom, and the lower half shows a structure with There are three tetracoordinated O atoms. Or, there are three tetracoordinated O atoms in the upper half of Figure 6(C). The small group shown in Figure 6(C) has a charge is 0.

[0242] Figure 6(D) shows one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 6(D) has three tetracoordinate O atoms, and the lower half has There are three tetracoordinate O atoms. The small group shown in Figure 6(D) has a charge of +1.

[0243] Figure 6(E) shows a small group containing two Zn atoms. The upper half of Figure 6(E) shows one Zn atom. The small group shown in Figure 6(E) has four-coordinated O atoms, and the lower half has one four-coordinated O atom. The loop has a charge of -1.

[0244] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0245] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the coordinated In atom each have three neighboring In atoms below. The three O atoms in the lower half each have three adjacent In atoms in the upper direction. One O atom in the upper half of the five-coordinate Ga atom shown in Fig. 1 has one neighboring Ga atom below it, One O atom in the lower half has one neighboring Ga atom in the upper direction. One O atom in the upper half of the Zn atom has one neighboring Zn atom downward, and three in the lower half Each O atom has three neighboring Zn atoms above it. The number of tetrahedral O atoms in the direction is equal to the number of adjacent metal atoms below the O atoms. Similarly, the number of tetrahedral O atoms below the metal atom and the number of neighboring metal atoms above the O atom are The number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of neighboring metal atoms is 4. Therefore, the number of tetrahedral O atoms above the metal atom is When the sum of the number of tetracoordinated O atoms below another metal atom is 4, the metal atom is Two small groups of the same kind can bond together. For example, a six-coordinate metal atom (In or When Sn or Sn is bonded via a tetracoordinated O atom in the lower half, there are three tetracoordinated O atoms. Therefore, it is possible to combine it with either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn). It will be combined.

[0246] Metal atoms with these coordination numbers are bonded via four-coordinated O atoms in the c-axis direction. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. This forms the medium group.

[0247] Figure 7(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 7(B) shows a large group consisting of three medium groups. 7(B) shows the atomic arrangement when the layer structure of FIG. 7(B) is observed from the c-axis direction.

[0248] In Fig. 7(A), for simplicity, the three-coordinate O atoms are omitted, and the four-coordinate O atoms are For example, the upper and lower halves of the Sn atom each contain three tetrahedral O atoms. Similarly, in Figure 7(A), the upper half of the In atom The two halves each contain one tetracoordinated O atom, indicated by the circle 1. Similarly, in Figure 7(A), there is one tetracoordinate O atom in the lower half and The Zn atom has three tetrahedral O atoms, and the upper half has one tetrahedral O atom, and the lower half has One half shows a Zn atom with three tetrahedral O atoms.

[0249] In Figure 7(A), the middle group, which is composed of an In-Sn-Zn-O layer structure, is The Sn atoms in the upper and lower halves each have three tetrahedral O atoms, and the four-coordinated O atoms One In atom is bonded to the upper half and one to the lower half, and the In atom is bonded to three In atoms in the upper half. A tetrahedral O atom is bonded to a Zn atom, and one tetrahedral O atom is bonded to the lower half of the Zn atom. Three tetrahedral O atoms are bonded to the In atoms in the upper and lower halves via the I n atom bonded to a small group of two Zn atoms with one tetracoordinated O atom in the top half In the lower half of this small group, three tetracoordinate O atoms are connected via one tetracoordinate O atom. The Sn atoms in the upper and lower halves are bonded together. Together they form a large group.

[0250] Here, for a three-coordinated O atom and a four-coordinated O atom, the charges per bond are For example, In (6-coordinate or 5-coordinate) atoms The charges of the Zn (four-coordinated) atom and the Sn (five- or six-coordinated) atom are +3 and + 2, +4. Therefore, the small group containing the Sn atom has a charge of +1. Therefore, S To form a layer structure containing n atoms, a charge of -1 is required to cancel out the charge of +1. As shown in Figure 6(E), a small group containing two Zn atoms takes charge-1. For example, there is one small group containing an Sn atom, and two small groups containing Zn atoms. If there is one group, the charges are cancelled out, so the total charge of the layer structure can be set to 0. can.

[0251] Specifically, by dividing the large group shown in Figure 7(B), the In-Sn-Zn-O system crystals The resulting In-Sn-Zn-O crystal (In2SnZn3O8) The layer structure of the system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed as the formula:

[0252] In addition, there are oxides of quaternary metals such as In-Sn-Ga-Zn-O oxides. In-Ga-Zn-O oxide (also written as IGZO), which is an oxide of a ternary metal. , In-Al-Zn-O oxide, Sn-Ga-Zn-O oxide, Al-Ga-Zn- O-based oxides, Sn-Al-Zn-O-based oxides, In-Hf-Zn-O-based oxides, In- La-Zn-O oxide, In-Ce-Zn-O oxide, In-Pr-Zn-O oxide In-Nd-Zn-O oxides, In-Sm-Zn-O oxides, In-Eu-Zn -O-based oxides, In-Gd-Zn-O-based oxides, In-Tb-Zn-O-based oxides, In- Dy-Zn-O oxide, In-Ho-Zn-O oxide, In-Er-Zn-O oxide In-Tm-Zn-O oxides, In-Yb-Zn-O oxides, In-Lu-Zn -O-based oxides, and binary metal oxides such as In-Zn-O-based oxides and Sn-Zn-O-based oxides. Oxides, Al-Zn-O oxides, Zn-Mg-O oxides, Sn-Mg-O oxides, The same applies to the case where an In-Mg-O based oxide or an In-Ga-O based oxide is used.

[0253] For example, Figure 8(A) shows a model of the middle group that consists of an In-Ga-Zn-O system layer structure. The figure is shown.

[0254] In Figure 8(A), the middle group, which is composed of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetrahedral O atoms, and in the lower half, there are three tetrahedral O atoms. It bonds to one Zn atom in the upper half and to three tetracoordinate O atoms in the lower half of that Zn atom. One tetrahedral O atom bonds to a Ga atom in the upper half and one to a Ga atom in the lower half. Three tetrahedral O atoms are connected to the upper half and the lower half via one tetrahedral O atom in the lower half. The structure is such that it is bonded to the In atom in the lower half. Configure a group.

[0255] Figure 8(B) shows a large group consisting of three medium groups. The atomic arrangement of the layer structure of 8(B) is shown when observed from the c-axis direction.

[0256] Here, the In (6-coordinate or 5-coordinate) atom, Zn (4-coordinate) atom, and Ga (5-coordinate) atom The charges are +3, +2, and +3, respectively, so the In, Zn, and Ga atoms A small group containing either of these has a charge of 0. Therefore, the combination of these small groups If so, the total charge of the middle group will always be 0.

[0257] The middle group, which is composed of an In-Ga-Zn-O-based layer structure, is shown in Figure 8(A). The arrangement of In atoms, Ga atoms, and Zn atoms is not limited to the group. Large combined groups are also possible.

[0258] Specifically, by dividing the large group shown in Figure 8(B), In-Ga-Zn-O system crystals The resulting In-Ga-Zn-O layer structure is InGaO 3(ZnO) n (n is a natural number.)

[0259] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 9(A) can be obtained. In the crystal structure shown in FIG. 9(A), as explained in FIG. 6(B), Ga atoms and Since the In atom has a five-coordinate system, a structure in which a Ga atom is replaced by an In atom is also possible.

[0260] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in Figure 9(B) is obtained. In the crystal structure shown in FIG. 9(B), as explained in FIG. 6(B), Ga Since the Ga atom and In atom have five-coordinated structures, a structure in which the Ga atom is replaced by an In atom is also possible. do.

[0261] The transistor used in one embodiment of the present invention is an oxide semiconductor containing CAAC in a channel formation region. By adopting a structure in which a body layer is applied, high reliability can be expected, which is preferable.

[0262] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0263] 100 Trimming circuit 105 Resistor element 110 Transistor 115 terminals 120 transistors 125 Erase terminal 130 transistors 140 Capacitive element 150 storage nodes 300 Trimming circuit 301 Substrate 302 Element isolation insulating layer 303 Insulation Layer 304 Insulation layer 305 Resistor element 310 Transistor 311 Wiring 312 Gate insulating layer 313 Oxide semiconductor layer 320 transistors 321 Wiring 322 Gate insulating layer 323 Oxide semiconductor layer 330 Transistor 331 Gate electrode 332 Wiring 335 Wiring 340 Capacitive element 341 Wiring 351 Wiring 352 Wiring 353 Wiring 413a Oxide semiconductor layer 413b Oxide semiconductor layer 504 Insulation layer 505 Insulation Layer 511 Gate electrode 512 Gate insulating layer 513 Oxide semiconductor layer 514a Insulating layer 514b Insulating layer 551 Electrode 552 Electrode 701 PCB 704 Insulation layer 705 Insulation Layer 710 Transistor 711 Gate electrode 712 Gate insulating layer 713 Oxide semiconductor layer 714a Insulating layer 714b side wall 751 Electrode 752 Electrode

Claims

1. a first conductive film; a first insulating film having a region disposed above the first conductive film; a first transistor having a channel formation region disposed above the first insulating film; a second transistor having a channel formation region disposed above the first insulating film; a second conductive film having a region disposed above the first insulating film; a third conductive film having a region disposed above the first insulating film; a fourth conductive film having a region disposed above the first insulating film; a fifth conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a sixth conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; the second conductive film functions as a first wiring that supplies a first power supply potential to one of a source and a drain of the first transistor; the fourth conductive film functions as a second wiring that supplies a second power supply potential to the other of the source and the drain of the second transistor, the semiconductor device has a function of controlling an operating state of an element in accordance with a potential of the third conductive film; the third conductive film functions as an electrode of a capacitor element; Semiconductor device.

2. a first conductive film; a first insulating film having a region disposed above the first conductive film; a first transistor having a channel formation region disposed above the first insulating film; a second transistor having a channel formation region disposed above the first insulating film; a second conductive film having a region disposed above the first insulating film; a third conductive film having a region disposed above the first insulating film; a fourth conductive film having a region disposed above the first insulating film; a fifth conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a sixth conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; the second conductive film functions as a first wiring that supplies a first power supply potential to one of a source and a drain of the first transistor; the fourth conductive film functions as a second wiring that supplies a second power supply potential to the other of the source and the drain of the second transistor; a first signal is input to a gate electrode of the first transistor; a second signal is input to a gate electrode of the second transistor; the semiconductor device has a function of controlling an operating state of an element in accordance with a potential of the third conductive film; the third conductive film functions as an electrode of a capacitor element; Semiconductor device.

3. a first conductive film; a first insulating film having a region disposed above the first conductive film; a first transistor having a channel formation region disposed above the first insulating film; a second transistor having a channel formation region disposed above the first insulating film; a second conductive film having a region disposed above the first insulating film; a third conductive film having a region disposed above the first insulating film; a fourth conductive film having a region disposed above the first insulating film; a fifth conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a sixth conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; the second conductive film functions as a first wiring that supplies a first power supply potential to one of a source and a drain of the first transistor; the fourth conductive film functions as a second wiring that supplies a second power supply potential to the other of the source and the drain of the second transistor, the semiconductor device has a function of controlling an operating state of an element in accordance with a potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; the third conductive film functions as an electrode of a capacitor element; Semiconductor device.

4. a first conductive film; a first insulating film having a region disposed above the first conductive film; a first transistor having a channel formation region disposed above the first insulating film; a second transistor having a channel formation region disposed above the first insulating film; a second conductive film having a region disposed above the first insulating film; a third conductive film having a region disposed above the first insulating film; a fourth conductive film having a region disposed above the first insulating film; a fifth conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a sixth conductive film having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; the second conductive film functions as a first wiring that supplies a first power supply potential to one of a source and a drain of the first transistor; the fourth conductive film functions as a second wiring that supplies a second power supply potential to the other of the source and the drain of the second transistor; a first signal is input to a gate electrode of the first transistor; a second signal is input to a gate electrode of the second transistor; the semiconductor device has a function of controlling an operating state of an element in accordance with a potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; the third conductive film functions as an electrode of a capacitor element; Semiconductor device.

5. In any one of claims 1 to 4, a channel formation region of the first transistor and a channel formation region of the second transistor each contain an oxide semiconductor; Semiconductor device.

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