Semiconductor device

Abstract

To provide a semiconductor element having high reliability, high speed, and multiple functions.SOLUTION: The semiconductor device includes an active pattern D1 spaced apart in a D2 direction and extending in the AP1 direction, a lower channel pattern and a lower source / drain pattern alternately disposed on the active pattern in the D2 direction, an upper channel pattern UCH1 on the lower channel pattern and an upper source / drain pattern USD1 on the lower source / drain pattern, a gate pattern GE located on the active pattern and on the lower channel pattern and the upper channel pattern, and a gate inner spacer GIS located between the gate pattern and the lower source / drain pattern and the upper source / drain pattern. The gate inner spacer has a side D1 with the upper channel pattern and the lower channel pattern, an overlapping portion side D2 overlapping in a side D3 direction perpendicular to the side IS1 direction, and a non-overlapping portion side D3 not overlapping in the side IS2 direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices, for example, three-dimensional semiconductor devices. [Background technology]

[0002] A semiconductor is a material that is intermediate between a conductor and a non-conductor and can conduct electricity under certain conditions. Various semiconductor devices, such as memory devices, can be manufactured using such semiconductor materials. These semiconductor devices can be used in a variety of electronic devices.

[0003] As the electronics industry advances, the demands placed on the properties of semiconductor devices are increasing, such as higher reliability, higher speed, and / or more functionality. To meet these demands, the structures within semiconductor devices are becoming increasingly complex and integrated. Summary of the Invention [Means for solving the problem]

[0004] According to an aspect of the present disclosure, a lower source / drain contact and a lower gate contact can be formed in a self-aligned manner without an additional structure such as a placeholder, damage to a gate pattern can be prevented when forming the lower source / drain contact, lateral growth of the lower source / drain pattern and the upper source / drain pattern can be controlled, the height of the lower surface of the gate pattern can be prevented from being recessed, thereby reducing parasitic capacitance, a cutting process of the gate pattern can be simplified, and a threshold voltage (V t ) between the lower gate structure and the upper gate structure of the gate pattern can be minimized. tThe object of the present invention is to provide a semiconductor device capable of minimizing variation by controlling the temperature.

[0005] According to one aspect, the semiconductor device includes active patterns spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns positioned on the active patterns and alternately arranged in the second direction; an upper channel pattern positioned on the lower channel pattern and an upper source / drain pattern positioned on the lower source / drain pattern; a gate pattern positioned on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer positioned between the gate pattern and the lower source / drain pattern and the upper source / drain pattern; wherein the gate inner spacer has an overlapping portion that overlaps with the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first and second directions and a non-overlapping portion that does not overlap with the third direction.

[0006] According to another aspect, the semiconductor device includes active patterns spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern positioned on the active patterns and alternately arranged in the second direction; an upper channel pattern positioned on the lower channel pattern and an upper source / drain pattern positioned on the lower source / drain pattern; a gate pattern positioned on the active patterns and above the lower channel pattern and the upper channel pattern; lower source / drain contacts positioned below the lower source / drain pattern and connected to the lower source / drain pattern; and barrier rib patterns spaced apart in the first direction, extending in a second direction across the gate patterns, and alternately arranged with the active patterns in the first direction; and the barrier rib patterns extend in a third direction perpendicular to the first and second directions from a level lower than an upper surface of the lower source / drain contacts to a level lower than an upper surface of the gate patterns.

[0007] According to yet another aspect, a semiconductor device includes: active patterns spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern located on the active patterns and alternately arranged in the second direction; an upper channel pattern located on the lower channel pattern and an upper source / drain pattern located on the lower source / drain pattern; a gate pattern located on the active patterns and above the lower channel pattern and the upper channel pattern; a gate inner spacer located between the gate pattern and the lower source / drain pattern and the upper source / drain pattern, the gate inner spacer having an overlapping portion that overlaps with the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first and second directions and a non-overlapping portion that does not overlap with the upper channel pattern and the lower channel pattern in the third direction; and partition patterns spaced apart in the first direction and extending in the second direction and alternately arranged with the active patterns in the first direction; both sides of the lower source / drain pattern and the upper source / drain pattern in the first direction are surrounded by the partition pattern, and both sides of the lower source / drain pattern and the upper source / drain pattern in the second direction are surrounded by the overlapping portion and the non-overlapping portion of the gate inner spacer.

[0008] In the semiconductor device according to the embodiment, the lower source / drain contacts and the lower gate contacts can be formed in a self-aligned manner without an additional structure such as a placeholder, the gate pattern can be prevented from being damaged when the lower source / drain contacts are formed, the lateral growth of the lower source / drain patterns and the upper source / drain patterns can be controlled, the height of the lower surface of the gate pattern can be prevented from being recessed, thereby reducing parasitic capacitance, the gate pattern cutting process can be simplified, and the threshold voltage (V t ) between the lower gate structure and the upper gate structure of the gate pattern can be minimized. t) can be controlled to minimize variation. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment. [Figure 2] 2 is a cross-sectional view taken along the lines X1-X1' and X2-X2' in FIG. 1. [Figure 3] 2 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in FIG. 1. [Figure 4] 2 is a cross-sectional view showing a semiconductor device according to an embodiment, taken along line X1-X1' in FIG. 1; FIG. [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 13] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 14] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 15] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 17] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 18] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 19] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 20] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 21] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 22] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 23] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 24] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 25] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 26] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 27] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 28] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 29] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; [Figure 30] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment in the order of steps; DETAILED DESCRIPTION OF THE INVENTION

[0010] The present disclosure may be embodied in various different forms and is not limited to the embodiments set forth herein.

[0011] To clearly explain this disclosure, parts not necessary for explanation will be omitted and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0012] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present disclosure is not necessarily limited to those shown. In the drawings, thicknesses are exaggerated to clearly show various layers and regions. In the drawings, the thicknesses of some layers and regions are exaggerated for the convenience of explanation.

[0013] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly above" that other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the side opposite to gravity.

[0014] Furthermore, throughout the specification, when a part "comprises" a certain element, this means that it may further include other elements, rather than excluding other elements, unless otherwise specified.

[0015] Furthermore, throughout the specification, "on a plane" means when the target part is viewed from above, and "on a cross section" means when the target part is cut vertically and viewed from the side.

[0016] Furthermore, throughout this specification, two directions parallel to and intersecting the upper surface of the substrate are defined as a first direction (D1) and a second direction (D2), respectively, and a direction perpendicular to the upper surface of the substrate is defined as a third direction (D3). For example, the first direction (D1) and the second direction (D2) may be perpendicular to each other.

[0017] Fig. 1 is a plan view showing a semiconductor device according to one embodiment. Fig. 2 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 3 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0018] For the sake of clarity and simplicity, Fig. 1 mainly illustrates a cell region where logic cells constituting a logic circuit are arranged, and does not illustrate a peripheral region arranged around the cell region. Fig. 1 also mainly illustrates an active pattern (AP1), a gate pattern (GE), a gate inner spacer (GIS), an upper source / drain pattern (USD1), and a partition pattern 150 in the cell region.

[0019] As an example, the semiconductor device may be a three-dimensional semiconductor device (e.g., stacked transistors). In other words, transistors may be stacked in the cell region in a third direction (D3). For example, a single height cell (SHC) may be located between the first power wiring and the second power wiring. The single height cell may include a first active region (AR1) as a bottom tier, and a second active region (AR2) may be stacked on top of the first active region (AR1) as a top tier.

[0020] For example, an NMOSFET may be located in a first active region (AR1), and a PMOSFET may be stacked on the NMOSFET in a second active region (AR2). The first active region (AR1) and the second active region (AR2) may be spaced apart from each other in a third direction (D3).

[0021] In other words, the three-dimensional semiconductor device allows the first active region (AR1) and the second active region (AR2) to overlap in the third direction (D3), thereby reducing the area of ​​the logic cell and improving the integration density of the device.

[0022] Meanwhile, although not shown in FIGS. 1 to 3, in some embodiments, a peripheral region in which transistors constituting a processor core or I / O terminals are arranged may be located around the cell region. In other words, the peripheral region may be a core / periphery region. As an example, the peripheral region may include long gate transistors (or long channel transistors) having a relatively long gate length (i.e., channel length). The transistors in the peripheral region may operate at higher power than the transistors in the cell region. As an example, the transistors in the cell region may be single gate (SG) devices, and the transistors in the peripheral region may be extra gate (EG) devices.

[0023] The active pattern (AP1) is defined by trenches located in the cell region. In other words, the active pattern (AP1) may be a portion protruding perpendicularly in the third direction (D3). On a planar surface (e.g., FIG. 1), the active pattern (AP1) may have a bar shape spaced apart in the first direction (D1) and extending in the second direction (D2). First and second active regions (AR1, AR2) may be sequentially stacked on the active pattern (AP1). For example, the active pattern (AP1) may include a semiconductor material such as silicon, germanium, or silicon germanium, e.g., silicon.

[0024] An isolation layer (ST) may fill the trenches between the active patterns (AP1). For example, the isolation layer (ST) may include silicon oxide. The upper surface of the isolation layer (ST) may be coplanar with or lower than the upper surface of the active patterns (AP1). The isolation layer (ST) may not cover the lower channel pattern (LCH1) and upper channel pattern (UCH1), which will be described later.

[0025] The barrier rib patterns 150 may be located between any one active pattern AP1 and another active pattern AP1 adjacent thereto in the first direction D1. The barrier rib patterns 150 may extend in the second direction D2 along the active pattern AP1. In a plan view (e.g., FIG. 1), the barrier rib patterns 150 may have a bar shape spaced apart from each other in the first direction D1 and extending in the second direction D2.

[0026] For example, the barrier rib patterns 150 may be alternately arranged with the active patterns AP1 in the first direction D1. The barrier rib patterns 150 may be spaced apart from the active patterns AP1 in the first direction D1, and an isolation layer ST may be located between the barrier rib patterns 150 and the active patterns AP1.

[0027] The partition pattern 150 may be a portion that protrudes perpendicularly in the third direction (D3). For example, the partition pattern 150 may extend in the third direction (D3) from a level lower than the top surface of a lower source / drain contact (bCA) to a level lower than the top surface of a main gate structure (MGE) of a gate pattern (GE).

[0028] Here, the level of the top surface of the lower source / drain contact (bCA) or the top surface of the gate pattern (GE) may refer to the shortest distance in the third direction (D3) from the bottom surface of the active pattern (AP1) to the top surface of the lower source / drain contact (bCA) or the top surface of the gate pattern (GE).

[0029] For example, the partition pattern 150 may extend from substantially the same level as the lower surface of the lower source / drain contact (bCA) or the lower surface of the lower gate contact (bCB) described below to substantially the same level as the upper surface of the upper gate structure (UGE) described below.

[0030] Accordingly, the partition pattern 150 may be located between any one lower source / drain pattern (LSD1) described below and another lower source / drain pattern (LSD1) adjacent thereto in the first direction (D1). The partition pattern 150 may be located between any one upper source / drain pattern (USD1) and the upper source / drain pattern (USD1). The partition pattern 150 may be located between any one lower gate structure (LGE) described below and another lower gate structure (LGE) adjacent thereto in the first direction (D1). The partition pattern 150 may be located between any one upper gate structure (UGE) described below and another upper gate structure (UGE) adjacent thereto in the first direction (D1). The partition pattern 150 may be located between a lower source / drain contact (bCA) and another lower source / drain contact (bCA) adjacent thereto in the first direction (D1). The partition pattern 150 may be located between a bottom gate contact bCB and another bottom gate contact bCB adjacent to the bottom gate contact bCB in the first direction D1.

[0031] In other words, since the lower source / drain contact (bCA) and the lower gate contact (bCB) are located between one partition pattern 150 and another partition pattern 150 adjacent to it in the first direction (D1), the lower source / drain contact (bCA) and the lower gate contact (bCB) can be formed in a self-aligned manner without any additional structure such as a placeholder, and damage to the gate pattern (GE) can be prevented when the lower source / drain contact (bCA) is formed.

[0032] In addition, since the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) are located between one partition pattern 150 and another partition pattern 150 adjacent to it in the first direction (D1), the partition pattern 150 can self-isolate the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) in the first direction (D1), thereby controlling the lateral growth of the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1).

[0033] In addition, any one lower gate structure (LGE) of the gate pattern (GE) and its upper gate structure (UGE) located thereon may be separated from another lower gate structure (LGE) adjacent thereto in the first direction (D1) and its upper gate structure (UGE) located thereon by a barrier rib pattern 150. In other words, the barrier rib pattern 150 may extend across the gate pattern (GE) in the second direction (D2), and the barrier rib pattern 150 may penetrate the lower gate structure (LGE) and the upper gate structure (UGE) of the gate pattern (GE).

[0034] In addition, the connection of the main gate structure (MGE) can be cut by a gate cutting pattern (CT) located on the barrier rib pattern 150, which will be described later, and only the main gate structure (MGE) can be connected by a main gate connecting portion (PO8) located on the barrier rib pattern 150, which will be described later. As a result, the gate pattern (GE) extends or is cut in the first direction (D1) only on the barrier rib pattern 150, preventing the height of the lower surface of the extension of the gate pattern (GE) from being recessed, thereby reducing parasitic capacitance, simplifying the cutting process of the gate pattern (GE), and protecting the metal of the gate pattern (GE) by the barrier rib pattern 150, thereby reducing the threshold voltage (V t ) can be minimized.

[0035] For example, the barrier rib pattern 150 may include an insulating material, which may include SiON, SiCN, SiOCN, SiN, or a combination thereof, for example, SiOCN.

[0036] A second hard mask (HM2) may be positioned on the partition pattern 150. Also, a gate cutting pattern (CT) may be positioned on the partition pattern 150. For example, the second hard mask (HM2) may be positioned between the partition pattern 150 and the gate cutting pattern (CT). In this case, the length of the second hard mask (HM2) and the gate cutting pattern (CT) in the first direction (D1) may be substantially the same as the length of the partition pattern 150 in the first direction (D1). The length of the second hard mask (HM2) and the gate cutting pattern (CT) in the second direction (D2) may be greater than the length of the main gate structure (MGE) in the second direction (D2) and may be substantially the same as the length of an upper channel pattern (UCH1) in the second direction (D2), which will be described later. Thus, the connection of the main gate structure (MGE) can be cut by the second hard mask (HM2) and the gate cutting pattern (CT) positioned on the partition pattern 150.

[0037] For example, the level of the lower surface of the second hard mask (HM2) may be lower than the level of the lower surface of the main gate structure (MGE). Alternatively, the level of the lower surface of the second hard mask (HM2) may be higher than the level of the lower surface of the main gate structure (MGE). Alternatively, the level of the lower surface of the second hard mask (HM2) may be substantially the same as the level of the lower surface of the main gate structure (MGE). For example, the level of the upper surface of the second hard mask (HM2) in the third direction (D3) may be lower than the level of the upper surface of the main gate structure (MGE) in the third direction (D3).

[0038] In addition, the level of the lower surface of the gate cut pattern (CT) may be higher than the level of the upper surface of the upper gate structure (UGE) and lower than the level of the upper surface of the main gate structure (MGE). For example, the level of the upper surface of the gate cut pattern (CT) may be higher than the level of the upper surface of the main gate structure (MGE).

[0039] Here, the level of the lower or upper surface of the second hard mask (HM2) may refer to the shortest distance in the third direction (D3) from the lower surface of the active pattern (AP1) to the lower or upper surface of the second hard mask (HM2).

[0040] In addition, the level of the lower or upper surface of the gate cut pattern (CT) may refer to the shortest distance in the third direction (D3) from the lower surface of the active pattern (AP1) to the lower or upper surface of the gate cut pattern (CT).

[0041] When the main gate connecting portion PO8 is located on the barrier rib pattern 150, the second hard mask HM2 may be located on both sides of the main gate connecting portion PO8 in the second direction D2. In this case, the length of the second hard mask HM2 in the second direction D2 may be substantially the same as the length of the gate spacer GS (described later) in the second direction D2.

[0042] For example, the second hard mask (HM2) may include an insulating material, which may include SiCN, SiOCN, SiN, or a combination thereof. The second hard mask (HM2) may include a multi-layer structure, each of which may include SiCN, SiOCN, SiN, or a combination thereof.

[0043] The gate cut pattern (CT) may include an insulating material, and the insulating material may include SiCN, SiOCN, SiN, or a combination thereof. The gate cut pattern (CT) may include a multi-layer including SiCN, SiOCN, SiN, or a combination thereof.

[0044] A first active region (AR1) including a lower channel pattern (LCH1) and a lower source / drain pattern (LSD1) may be located on the active pattern (AP1). The lower channel pattern (LCH1) may be interposed between one lower source / drain pattern (LSD1) and another lower source / drain pattern (LSD1) adjacent thereto in the second direction (D2). The lower channel pattern (LCH1) may connect a pair of lower source / drain patterns (LSD1) to each other. For example, the lower channel pattern (LCH1) and the lower source / drain pattern (LSD1) may be alternately arranged in the second direction (D2).

[0045] The lower channel pattern (LCH1) may include a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2) stacked and spaced apart from each other in the third direction (D3). However, without being limited thereto, the lower channel pattern (LCH1) may include three or more semiconductor patterns. Each of the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) may include crystalline silicon.

[0046] A lower insulating structure (BDI) may be located between the active pattern (AP1) and the lower channel pattern (LCH1).

[0047] For example, the lower insulating structure (BDI) may be located between the active pattern (AP1) and a first semiconductor pattern (SP1) located at the bottom of the lower channel pattern (LCH1). Also, the lower insulating structure (BDI) may be located between the active pattern (AP1) and a first sub-gate portion (PO1) located at the bottom of a lower gate structure (LGE) described below.

[0048] The lower insulating structure (BDI) may space the active pattern (AP1) and the lower channel pattern (LCH1) from each other in the third direction (D3). The lower insulating structure (BDI) may overlap the lower channel pattern (LCH1) and an upper channel pattern (UCH1) described later in the third direction (D3). The lower insulating structure (BDI) may also overlap the middle insulating structure (MDI) described later in the third direction (D3). The lower insulating structure (BDI) may also overlap the upper gate structure (UGE) and the lower gate structure (LGE) of the gate pattern (GE) and an overlapping portion (IS1) of the gate inner spacer (GIS) described later in the third direction (D3). Meanwhile, the lower insulating structure (BDI) may not overlap the sub-gate connecting portion (PO7) of the gate pattern (GE) and a non-overlapping portion (IS2) of the gate inner spacer (GIS) described later in the third direction (D3).

[0049] As an example, the BDI may include an insulating material, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0050] The bottom insulating structure (BDI) can prevent damage to the gate pattern (GE) during the formation of the bottom source / drain contact (bCA), and the work function metal of the gate pattern (GE) is protected, resulting in a low threshold voltage (V t ) can be minimized.

[0051] At least one dummy channel pattern may be interposed between the lower insulating structure (BDI) and the lower channel pattern (LCH1), and the lower insulating structure (BDI) may be interposed between the dummy channel patterns. For example, a first dummy channel pattern (not shown) may be located between the lower insulating structure (BDI) and the lower channel pattern (LCH1).

[0052] For example, the first dummy channel pattern may be located between the lower insulating structure (BDI) and the first semiconductor pattern (SP1) located at the bottom of the lower channel pattern (LCH1), and the first dummy channel pattern may be located between the active pattern (AP1) and the first sub-gate portion (PO1) located at the bottom of the lower gate structure (LGE).

[0053] In other words, the active pattern (AP1), the lower insulating structure (BDI), the first dummy channel pattern, the first sub-gate portion (PO1) of the lower gate structure (LGE), and the first semiconductor pattern (SP1) of the lower channel pattern (LCH1) may be sequentially stacked in the third direction (D3).

[0054] The first dummy channel pattern may include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), or may include a silicon-based insulating material such as a silicon oxide film or a silicon nitride film. For example, the first dummy channel pattern may include a silicon-based insulating material.

[0055] The lower source / drain pattern (LSD1) may be located on an upper surface of the active pattern (AP1). The lower source / drain pattern (LSD1) may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper surface of the lower source / drain pattern (LSD1) may be higher than the upper surface of the second semiconductor pattern (SP2) of the lower channel pattern (LCH1).

[0056] The lower source / drain pattern (LSD1) may be doped with impurities and have a first conductivity type. The first conductivity type may be N-type or P-type. As an example, the first conductivity type may be N-type. The lower source / drain pattern (LSD1) may include silicon (Si) or silicon germanium (SiGe).

[0057] Although not shown, in some embodiments, the semiconductor device may further include a first interlayer insulating layer.

[0058] The first interlayer insulating layer may be located on the side of the lower gate structure (LGE) and the top surface of the lower source / drain pattern (LSD1). For example, the first interlayer insulating layer may be located between the partition wall pattern 150 and the side of the lower gate structure (LGE).

[0059] As an example, the first interlayer insulating layer may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0060] Although not shown, in some embodiments, a first interlayer stop layer may be further disposed between the lower gate structure (LGE) and the first interlayer insulating layer and between the lower source / drain pattern (LSD1) and the first interlayer insulating layer. The first interlayer stop layer may include a material having an etching selectivity with respect to the first interlayer insulating layer.

[0061] The first interlayer stop film can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonate nitride (SiOCN), silicon boron oxynitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0062] A second active region (AR2) may be located on the first active region (AR1), and the second active region (AR2) may include an upper channel pattern (UCH1) and an upper source / drain pattern (USD1).

[0063] The upper channel pattern (UCH1) may be positioned above the lower channel pattern (LCH1). The upper source / drain pattern (USD1) may be positioned above the lower source / drain pattern (LSD1). In other words, the upper channel pattern (UCH1) may overlap the lower channel pattern (LCH1) in the third direction (D3). The upper source / drain pattern (USD1) may overlap the lower source / drain pattern (LSD1) in the third direction (D3). The upper channel pattern (UCH1) may be interposed between any one upper source / drain pattern (USD1) and another upper source / drain pattern (USD1) adjacent to it in the second direction (D2). The upper channel pattern (UCH1) may connect a pair of upper source / drain patterns (USD1) to each other. For example, the upper channel pattern (UCH1) and the upper source / drain pattern (USD1) may be alternately arranged in the second direction (D2).

[0064] The upper channel pattern (UCH1) may include a third semiconductor pattern (SP3) and a fourth semiconductor pattern (SP4) stacked and spaced apart from each other in the third direction (D3). However, without being limited thereto, the upper channel pattern (UCH1) may include three or more semiconductor patterns. The third semiconductor pattern (SP3) and the fourth semiconductor pattern (SP4) of the upper channel pattern (UCH1) may include the same semiconductor material as the first and second semiconductor patterns (SP1, SP2) of the lower channel pattern (LCH1) described above.

[0065] An intermediate insulating structure (MDI) may be located between the lower channel pattern (LCH1) and the upper channel pattern (UCH1) thereon.

[0066] For example, the intermediate insulating structure (MDI) may be located between the second semiconductor pattern (SP2) located at the top of the lower channel pattern (LCH1) and the third semiconductor pattern (SP3) located at the bottom of the upper channel pattern (UCH1). Also, the intermediate insulating structure (MDI) may be located between the third sub-gate portion (PO3) located at the top of the lower gate structure (LGE) described below and the fourth sub-gate portion (PO4) located at the bottom of the upper gate structure (UGE) described below.

[0067] The intermediate insulating structure (MDI) may space the lower channel pattern (LCH1) and the upper channel pattern (UCH1) from each other in the third direction (D3). The intermediate insulating structure (MDI) may overlap the lower channel pattern (LCH1) and the upper channel pattern (UCH1) in the third direction (D3). Also, the intermediate insulating structure (MDI) may overlap the lower insulating structure (BDI) in the third direction (D3).

[0068] In addition, the intermediate insulating structure (MDI) may overlap the upper gate structure (UGE) and the lower gate structure (LGE) of the gate pattern (GE) and the overlapping portion (IS1) of the gate inner spacer (GIS) in the third direction (D3). On the other hand, the intermediate insulating structure (MDI) may not overlap the sub-gate connecting portion (PO7) of the gate pattern (GE) and the non-overlapping portion (IS2) of the gate inner spacer (GIS) in the third direction (D3).

[0069] As an example, the intermediate insulating structure (MDI) may include an insulating material, for example, the intermediate insulating structure (MDI) may include silicon oxide, silicon nitride, or silicon oxynitride.

[0070] At least one dummy channel pattern may be interposed between the lower channel pattern (LCH1) and the upper channel pattern (UCH1) thereon, and an intermediate insulating structure (MDI) may be interposed between the dummy channel patterns. For example, a second dummy channel pattern (DS2) and a third dummy channel pattern (DS3) may be located between the lower channel pattern (LCH1) and the upper channel pattern (UCH1), and an intermediate insulating structure (MDI) may be interposed between the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3).

[0071] For example, the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3) may be located between the uppermost second semiconductor pattern (SP2) of the lower channel pattern (LCH1) and the lowermost third semiconductor pattern (SP3) of the upper channel pattern (UCH1). Also, the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3) may be located between the uppermost third sub-gate portion (PO3) of the lower gate structure (LGE) and the lowermost fourth sub-gate portion (PO4) of the upper gate structure (UGE).

[0072] In other words, the second semiconductor pattern (SP2) of the lower channel pattern (LCH1), the third sub-gate portion (PO3) of the lower gate structure (LGE), the second dummy channel pattern (DS2), the intermediate insulating structure (MDI), the third dummy channel pattern (DS3), the fourth sub-gate portion (PO4) of the upper gate structure (UGE), and the third semiconductor pattern (SP3) of the upper channel pattern (UCH1) can be sequentially stacked in the third direction (D3).

[0073] The second dummy channel pattern (DS2) and the third dummy channel pattern (DS3) may be spaced apart from the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1). For example, a buried insulating layer (SDI) (described later) may be located on the second direction (D2) side of the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3), so that the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) may not be located. As a result, the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3) are not connected to any source / drain patterns.

[0074] The intermediate insulating structure (MDI) and the second dummy channel pattern (DS2) and the third dummy channel pattern (DS3) located above and below the intermediate insulating structure (MDI) control the threshold voltage (V) between the lower gate structure (LGE) and the upper gate structure (UGE) of the gate pattern (GE). t ) can be controlled to minimize variation.

[0075] At least one dummy channel pattern may be located on the upper channel pattern (UCH1). For example, a fourth dummy channel pattern (DS4) may be located on the upper channel pattern (UCH1).

[0076] For example, the fourth dummy channel pattern DS4 may be located on the fourth semiconductor pattern SP4 located at the top of the upper channel pattern UCH1. Also, the fourth dummy channel pattern DS4 may be located on a sixth sub-gate portion PO6 (described later) located at the top of the upper gate structure UGE.

[0077] In other words, the fourth semiconductor pattern (SP4) of the upper channel pattern (UCH1), the sixth sub-gate portion (PO6) of the upper gate structure (UGE), and the fourth dummy channel pattern (DS4) can be sequentially stacked in the third direction (D3).

[0078] The second dummy channel pattern (DS2), the third dummy channel pattern (DS3), and the fourth dummy channel pattern (DS4) may include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), or may include a silicon-based insulating material such as a silicon oxide film or a silicon nitride film. For example, the second dummy channel pattern (DS2), the third dummy channel pattern (DS3), and the fourth dummy channel pattern (DS4) may include a silicon-based insulating material.

[0079] A first hard mask HM1 may be positioned on the fourth dummy channel pattern DS4. For example, the first hard mask HM1 may be positioned on both sides of the main gate structure MGE in the second direction D2.

[0080] For example, the level of the lower surface of the first hard mask (HM1) may be lower than the level of the lower surface of the main gate structure (MGE). Alternatively, the level of the lower surface of the first hard mask (HM1) may be higher than the level of the lower surface of the main gate structure (MGE). Alternatively, the level of the lower surface of the first hard mask (HM1) may be substantially the same as the level of the lower surface of the main gate structure (MGE). For example, the level of the upper surface of the first hard mask (HM1) may be lower than the level of the upper surface of the main gate structure (MGE).

[0081] Here, the level of the lower or upper surface of the first hard mask (HM1) may refer to the shortest distance in the third direction (D3) from the lower surface of the active pattern (AP1) to the lower or upper surface of the first hard mask (HM1).

[0082] For example, the first hard mask (HM1) may include an insulating material, which may include SiCN, SiOCN, SiN, or a combination thereof. The first hard mask (HM1) may include a multi-layer structure, each of which may include SiCN, SiOCN, SiN, or a combination thereof.

[0083] A first etch stop layer (ESL1) may be located on the first hard mask (HM1) and the second hard mask (HM2).

[0084] However, the first etch stop layer (ESL1) may not be located on the main gate structure (MGE), and the first etch stop layer (ESL1) may not be located between the second hard mask (HM2) and the gate cut pattern (CT).

[0085] For example, the first etch stop layer (ESL1) may be located on both sides of the main gate structure (MGE) in the second direction (D2), and the first etch stop layer (ESL1) may be located on the non-overlapping portion (IS2) of the gate inner spacer (GIS).

[0086] The first etch stop layer (ESL1) can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), or silicon oxycarbide (SiOC).

[0087] The upper source / drain pattern (USD1) may be located on an upper surface of the buried insulating layer (SDI). The upper source / drain pattern (USD1) may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper surface of the upper source / drain pattern (USD1) may be higher than the upper surface of the fourth semiconductor pattern (SP4) of the upper channel pattern (UCH1).

[0088] The upper source / drain pattern (USD1) may be doped with impurities and have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern (LSD1). For example, the second conductivity type may be P-type. The upper source / drain pattern (USD1) may include silicon germanium (SiGe) or silicon (Si).

[0089] A buried insulating layer (SDI) may be interposed between the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) thereon. For example, the buried insulating layer (SDI) may be located between an upper surface of the lower source / drain pattern (LSD1) and a lower surface of the upper source / drain pattern (USD1).

[0090] The buried insulating layer (SDI) may separate the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) from each other in the third direction (D3). The buried insulating layer (SDI) may overlap the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1) in the third direction (D3).

[0091] The buried insulating layer (SDI) can include an insulating material. For example, the buried insulating layer (SDI) can include silicon nitride, silicon oxynitride, or a combination thereof.

[0092] The semiconductor device may further include a second interlayer insulating layer 120.

[0093] The second interlayer insulating layer 120 may be located on an upper surface of the upper source / drain pattern (USD1). The second interlayer insulating layer 120 may be located on an upper surface of the partition wall pattern 150. The second interlayer insulating layer 120 may be located on a side of the main gate structure (MGE). The second interlayer insulating layer 120 may be located on a side of the gate capping pattern (GP) and a side of the gate cutting pattern (CT), which will be described later.

[0094] For example, the second interlayer insulating layer 120 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0095] Although not shown, in some embodiments, a second interlayer stop film may further be located between the upper gate structure (UGE) and the second interlayer insulating layer, and between the upper source / drain pattern (USD1) and the second interlayer insulating layer.

[0096] The second interlayer stop film may include a material having an etch selectivity with respect to the second interlayer insulating layer, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0097] The gate pattern (GE) may be located on the lower channel pattern (LCH1) and the upper channel pattern (UCH1). The gate pattern (GE) may overlap the stacked lower channel pattern (LCH1) and upper channel pattern (UCH1) in a third direction (D3).

[0098] The gate pattern (GE) may extend in a third direction (D3) from an upper surface of the isolation layer (ST) or an upper surface of the active pattern (AP1) to the gate capping pattern (GP). The gate pattern (GE) may extend in the third direction (D3) from the lower channel pattern (LCH1) of the first active region (AR1) to the upper channel pattern (UCH1) of the second active region (AR2). In other words, the gate pattern (GE) may extend in the third direction (D3) from the lowermost first semiconductor pattern (SP1) to the uppermost fourth semiconductor pattern (SP4).

[0099] The gate pattern (GE) may be located on the top surface, bottom surface, and both side surfaces of each of the first semiconductor pattern (SP1), the second semiconductor pattern (SP2), the third semiconductor pattern (SP3), and the fourth semiconductor pattern (SP4). In other words, the logic cell may include a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate pattern (GE) three-dimensionally surrounds the channel.

[0100] The gate pattern (GE) may have a lower gate structure (LGE) located in the first active region (AR1), an upper gate structure (UGE) located in the second active region (AR2), and a main gate structure (MGE) located on the upper gate structure (UGE). The lower gate structure (LGE), upper gate structure (UGE), and main gate structure (MGE) may overlap each other in the third direction (D3). The lower gate structure (LGE), upper gate structure (UGE), and main gate structure (MGE) may be connected to each other. In other words, the gate pattern (GE) may be a common gate electrode in which the lower gate structure (LGE) on the lower channel pattern (LCH1), the upper gate structure (UGE) on the upper channel pattern (UCH1), and the main gate structure (MGE) are connected to each other.

[0101] The lower gate structure (LGE) may have a first sub-gate portion (PO1) interposed between the active pattern (AP1) and the first semiconductor pattern (SP1), a second sub-gate portion (PO2) interposed between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2), and a third sub-gate portion (PO3) interposed between the second semiconductor pattern (SP2) and the second dummy channel pattern (DS2).

[0102] The upper gate structure (UGE) may have a fourth sub-gate portion (PO4) interposed between the third dummy channel pattern (DS3) and the third semiconductor pattern (SP3), a fifth sub-gate portion (PO5) interposed between the third semiconductor pattern (SP3) and the fourth semiconductor pattern (SP4), and a sixth sub-gate portion (PO6) located between the fourth semiconductor pattern (SP4) and the fourth dummy channel pattern (DS4).

[0103] The main gate structure (MGE) may be located on the sixth sub-gate portion (PO6) of the upper gate structure (UGE). For example, the main gate structure (MGE) may be located on the upper channel pattern (UCH1) and on the fourth semiconductor pattern (SP4) located on the top of the upper channel pattern (UCH1). For example, the main gate structure (MGE) may be located on the fourth dummy channel pattern (DS4).

[0104] For example, the lower gate structure (LGE) may include a first work function metal pattern located on the first and second semiconductor patterns (SP1, SP2). The upper gate structure (UGE) and the main gate structure (MGE) may include a second work function metal pattern located on the third and fourth semiconductor patterns (SP3, SP4). Each of the first and second work function metal patterns may include a metal, such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), or a combination thereof, and nitrogen (N). The first and second work function metal patterns may have different work functions. The gate pattern (GE) may include a low-resistivity metal, such as tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), or a combination thereof, on the first and second work function metal patterns. For example, the main gate structure (MGE) may include a low-resistivity metal.

[0105] The gate pattern (GE) may further include sub-gate connecting portions (PO7) located on both sides of the lower channel pattern (LCH1) and the upper channel pattern (UCH1) in the first direction (D1). As an example, the sub-gate connecting portions (PO7) may be located on both sides of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) in the first direction (D1). For example, the sub-gate connecting portions (PO7) may contact both sides of the first to fourth semiconductor patterns (SP1 to SP4) in the first direction (D1).

[0106] The sub-gate connection portion (PO7) may be located on both side surfaces of the first to sixth sub-gate portions (PO1 to PO6) in the first direction (D1), and the sub-gate connection portion (PO7) may contact both side surfaces of the first to sixth sub-gate portions (PO1 to PO6) in the first direction (D1). The sub-gate connection portion (PO7) may extend in the third direction (D3) from the lowermost first sub-gate portion (PO1) to the uppermost sixth sub-gate portion (PO6) and connect the first to sixth sub-gate portions (PO1 to PO6) by passing through the side surfaces of the first to sixth sub-gate portions (PO1 to PO6). For example, the sub-gate connection portion (PO7) may extend in the third direction (D3) from an upper surface of the isolation layer (ST) to a lower surface of the main gate structure (MGE).

[0107] The sub-gate connecting portion PO7 may not overlap with the lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3. For example, the sub-gate connecting portion PO7 may not overlap with the first to fourth semiconductor patterns SP1 to SP4 in the third direction D3.

[0108] Meanwhile, the first to sixth sub-gate portions (PO1 to PO6) may overlap with the first to fourth semiconductor patterns (SP1 to SP4) in the third direction (D3). Therefore, the sub-gate connection portion (PO7) does not need to overlap with the first to sixth sub-gate portions (PO1 to PO6) in the third direction (D3).

[0109] The first to sixth sub-gate portions PO1 to PO6 may be located on the active pattern AP1, while the sub-gate connection portion PO7 may be located on the isolation layer ST.

[0110] As described above, any one lower gate structure (LGE) and the upper gate structure (UGE) located thereon of the gate pattern (GE) may be separated from another lower gate structure (LGE) and the upper gate structure (UGE) located thereon adjacent thereto in the second direction (D2) by a barrier rib pattern 150.

[0111] The first to sixth sub-gate portions (PO1 to PO6) of the gate pattern (GE) are located between the partition patterns 150 in the first direction (D1), and the first to sixth sub-gate portions (PO1 to PO6) do not contact the partition pattern 150, but the sub-gate connection portion (PO7) is located between the first to sixth sub-gate portions (PO1 to PO6) and the partition pattern 150, and can contact the first to sixth sub-gate portions (PO1 to PO6) and the partition pattern 150.

[0112] Thus, the gate pattern (GE) may extend in the first direction (D1) from one partition wall pattern 150 to another partition wall pattern 150 adjacent thereto in the first direction (D1). For example, the gate pattern (GE) may contact one partition wall pattern 150 and another partition wall pattern 150 adjacent thereto in the first direction (D1).

[0113] The gate pattern (GE) may further include a main gate connection portion (PO8) located on the barrier rib pattern 150.

[0114] The main gate connecting portion (PO8) may be located between any one of the main gate structures (MGE) arranged in the first direction (D1) with any one of the barrier rib patterns 150 therebetween. Any one of the main gate structures (MGE) arranged in the first direction (D1) with any one of the barrier rib patterns 150 therebetween may be connected to another main gate structure (MGE) by the main gate connecting portion (PO8). As a result, the gate patterns (GE) may extend in the first direction (D1).

[0115] The gate pattern (GE) extends in the first direction (D1) only on the barrier rib pattern 150, thereby preventing the height of the lower surface of the gate pattern (GE) from being recessed, thereby reducing parasitic capacitance. In addition, the metal of the gate pattern (GE) is protected by the barrier rib pattern 150, thereby reducing the threshold voltage (V t ) can be minimized.

[0116] For example, the level of the lower surface of the main gate connecting portion (PO8) may be lower than the level of the lower surface of the main gate structure (MGE), or the level of the lower surface of the main gate connecting portion (PO8) may be higher than the level of the lower surface of the main gate structure (MGE), or the level of the lower surface of the main gate connecting portion (PO8) may be substantially the same as the level of the lower surface of the main gate structure (MGE).

[0117] Here, the level of the lower surface of the main gate connecting portion (PO8) or the lower surface of the main gate structure (MGE) may refer to the shortest distance in the third direction (D3) from the lower surface of the active pattern (AP1) to the lower surface of the main gate connecting portion (PO8) or the lower surface of the main gate structure (MGE).

[0118] Gate inner spacers (GIS) may be positioned between the gate pattern (GE) and the lower source / drain pattern (LSD1) and upper source / drain pattern (USD1). For example, the gate inner spacers (GIS) may be positioned between the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) and the lower source / drain pattern (LSD1), and between the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE) and the upper source / drain pattern (USD1). The gate inner spacers (GIS) may extend in a first direction (D1) along the gate pattern (GE).

[0119] For example, in a cross section (eg, FIG. 2), the gate inner spacers (GIS) may be located on both sides of the first to sixth sub-gate portions (PO1 to PO6) in the second direction (D2).

[0120] The gate inner spacer (GIS) may have an overlapping portion (IS1) that overlaps the upper channel pattern (UCH1) and the lower channel pattern (LCH1) in the third direction (D3) and a non-overlapping portion (IS2) that does not overlap the upper channel pattern (UCH1) and the lower channel pattern (LCH1) in the third direction (D3).

[0121] For example, the overlapping portion (IS1) may be located between the first to fourth semiconductor patterns (SP1 to SP4) in the third direction (D3). For example, the overlapping portion (IS1) may be located between the active pattern (AP1) and the first semiconductor pattern (SP1), between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2), between the second semiconductor pattern (SP2) and the second dummy channel pattern (DS2), between the third dummy channel pattern (DS3) and the third semiconductor pattern (SP3), between the third semiconductor pattern (SP3) and the fourth semiconductor pattern (SP4), and between the fourth semiconductor pattern (SP4) and the fourth dummy channel pattern (DS4).

[0122] As an example, the non-overlapping portions (IS2) may be located on both sides of the first to fourth semiconductor patterns (SP1, SP2, SP3, SP4) in the first direction (D1). For example, the non-overlapping portions (IS2) may contact both sides of the first to fourth semiconductor patterns (SP1 to SP4) in the first direction (D1). Furthermore, the non-overlapping portions (IS2) may be located on both sides of the overlapping portion (IS1) in the first direction (D1), and the non-overlapping portions (IS2) may contact both sides of the overlapping portion (IS1) in the first direction (D1).

[0123] The non-overlapping portion (IS2) may extend in the third direction (D3) from the lowermost first semiconductor pattern (SP1) to the uppermost fourth semiconductor pattern (SP4). The non-overlapping portion (IS2) may extend in the third direction (D3) from the lowermost overlapping portion (IS1) to the uppermost overlapping portion (IS1) and connect the overlapping portions (IS1) by passing along the side surfaces of the overlapping portions (IS1). For example, the non-overlapping portion (IS2) may extend in the third direction from the upper surface of the isolation layer (ST) to the lower surface of the first etch stop layer (ESL1). The non-overlapping portion (IS2) may contact the upper surface of the isolation layer (ST) and the lower surface of the first etch stop layer (ESL1).

[0124] Meanwhile, the overlapping portion (IS1) may be located on the active pattern (AP1), and the non-overlapping portion (IS2) may be located on the isolation layer (ST).

[0125] For example, any one gate inner spacer (GIS) may be separated from another gate inner spacer (GIS) adjacent thereto in the first direction (D1) by a barrier rib pattern 150.

[0126] The overlapping portion (IS1) of the gate inner spacer (GIS) is located between the partition patterns 150 in the first direction (D1), and the overlapping portion (IS1) does not contact the partition pattern 150, but the non-overlapping portion (IS2) is located between the overlapping portion (IS1) and the partition pattern 150 and can contact the overlapping portion (IS1) and the partition pattern 150.

[0127] Thus, the gate inner spacer (GIS) may extend in the first direction (D1) from one partition pattern 150 to another partition pattern 150 adjacent thereto in the first direction (D1). For example, the gate inner spacer (GIS) may contact one partition pattern 150 and another partition pattern 150 adjacent thereto in the first direction (D1).

[0128] For example, the thicknesses of the overlapping portion (IS1) and the non-overlapping portion (IS2) of the gate inner spacer (GIS) in the second direction (D2) may be substantially the same. For example, the thicknesses of the overlapping portion (IS1) and the non-overlapping portion (IS2) in the second direction (D2) may be 4 nm or more, 5 nm or more, 6 nm or more, or 7 nm or more, or 8 nm or less, 7 nm or less, 6 nm or less, or 5 nm or less, for example, 4 nm to 8 nm.

[0129] The length of the non-overlapping portion (IS2) in the first direction (D1) may be 4 nm or more, 5 nm or more, 6 nm or more, 7 nm or more, 8 nm or more, 9 nm or more, 10 nm or more, 11 nm or more, 12 nm or more, 13 nm or more, or 14 nm or more, or may be 15 nm or less, 14 nm or less, 13 nm or less, 12 nm or less, 11 nm or less, 10 nm or less, 9 nm or less, 8 nm or less, 7 nm or less, or 6 nm or less, for example, 5 nm to 15 nm.

[0130] As an example, the gate inner spacer (GIS) may include a low-k material. The low-k material may include silicon oxide or a material with a dielectric constant lower than that of silicon oxide. For example, the low-k material may include silicon oxide, fluorine- or carbon-doped silicon oxide, porous silicon oxide, or an organic polymeric dielectric. Without being limited thereto, the gate inner spacer (GIS) may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0131] In this manner, the gate inner spacer (GIS) has an overlapping portion (IS1) that overlaps with the lower channel pattern (LCH1) and the upper channel pattern (UCH1) in the third direction (D3) and a non-overlapping portion (IS2) that does not overlap with the third direction (D3), and the gate inner spacer (GIS) extends in the first direction (D1) from one partition pattern 150 to another partition pattern 150 adjacent to it in the first direction (D1).Since the gate inner spacer (GIS) is located on the entire surface of the gate pattern (GE) that contacts the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1), damage to the gate pattern (GE) can be prevented when forming the lower source / drain contact (bCA).

[0132] A pair of gate spacers (GS) may be disposed on both side surfaces of the sixth sub-gate portion (PO6) of the gate pattern (GE), and the gate spacers (GS) may extend in the first direction (D1) along the gate pattern (GE).

[0133] The top surface of the gate spacer (GS) may be higher than the top surface of the gate pattern (GE) and may be coplanar with the top surface of the second interlayer insulating layer 120.

[0134] The gate spacer (GS) may include SiCN, SiOCN, SiN, or a combination thereof. As an example, the gate spacer (GS) may include a multi-layer each including SiCN, SiOCN, SiN, or a combination thereof.

[0135] A gate capping pattern (GP) may be positioned on an upper surface of the gate pattern (GE). The gate capping pattern (GP) may extend in a first direction (D1) along the gate pattern (GE). For example, the gate capping pattern (GP) may include SiON, SiCN, SiOCN, SiN, or a combination thereof.

[0136] Although not shown, in some embodiments, a gate insulating film may be interposed between the gate pattern (GE) and the first to fourth semiconductor patterns (SP1 to SP4). The gate insulating film may include a silicon oxide film, a silicon oxynitride film, a high-k film, or a combination thereof. As an example, the gate insulating film may include a silicon oxide film directly covering the surfaces of the first to fourth semiconductor patterns (SP1 to SP4) and a high-k film located on the silicon oxide film. In other words, the gate insulating film may include a multi-layer structure of a silicon oxide film and a high-k film.

[0137] The high-k dielectric film may include a high-k material having a higher dielectric constant than a silicon oxide film. For example, the high-k material may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0138] An upper source / drain contact (aCA) may be electrically connected to the upper source / drain pattern (USD1) through the second interlayer insulating layer 120. Also, an upper gate contact (aCB) may be electrically connected to the main gate structure (MGE) through the second interlayer insulating layer 120 and the gate capping pattern (GP).

[0139] Although not shown, in some embodiments, each of the upper source / drain contacts (aCA) and the upper gate contact (aCB) may include a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the conductive pattern may include aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern may cover the side and bottom surfaces of the conductive pattern. The barrier pattern may include a metal film or a metal nitride film. The metal film may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride film may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or a combination thereof.

[0140] Although not shown, in some embodiments, a silicide pattern may be interposed between the upper source / drain contact (aCA) and the upper source / drain pattern (USD1) and between the upper gate contact (aCB) and the main gate structure (MGE). The upper source / drain contact (aCA) may be electrically connected to the upper source / drain contact (aCA) through the silicide pattern, and the upper gate contact (aCB) may be electrically connected to the main gate structure (MGE) through the silicide pattern. The silicide pattern may include a metal-silicide, such as titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, cobalt-silicide, or a combination thereof.

[0141] Although not shown, in some embodiments, a first upper interlayer insulating film may be located on and cover the upper source / drain contacts (aCA) and the upper gate contact (aCB).

[0142] A first upper metal layer may be disposed in the first upper interlayer insulating film. The first upper metal layer may include a first upper power wiring, a first upper wiring, and a first upper via. The first upper via may be disposed below the first upper power wiring and the first upper wiring. The first upper via may be interposed between the upper source / drain contact (aCA) and the first upper power wiring and between the upper source / drain contact (aCA) and the first upper power wiring and the first upper wiring. The first upper via may be interposed between the upper gate contact (aCB) and the first upper wiring.

[0143] The first upper power wiring and the first upper wiring of the first upper metal layer can include the same or different conductive materials, such as aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0144] Although not shown, in some embodiments, an upper metal layer may be additionally disposed on the first upper interlayer insulating film, and each of the upper metal layers may include routing wiring.

[0145] The lower source / drain contact (bCA) may be located under the lower source / drain pattern (LSD1) and may be electrically connected to the lower source / drain pattern (LSD1). For example, the lower source / drain contact (bCA) may be electrically connected to the lower source / drain pattern (LSD1) through the active pattern (AP1).

[0146] In addition, a bottom gate contact (bCB) may be located below the bottom gate structure (LGE) and electrically connected to the bottom gate structure (LGE). For example, the bottom gate contact (bCB) may be electrically connected to the bottom gate structure (LGE) through the active pattern (AP1).

[0147] An insulating liner (CBL) may be further positioned between the lower source / drain contact (bCA) and the adjacent lower gate contact (bCB), and may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonate nitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0148] Although not shown, in some embodiments, each of the lower source / drain contacts (bCA) and the lower gate contact (bCB) may include a conductive pattern and a barrier pattern enveloping the conductive pattern. For example, the conductive pattern may include a metal such as aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern may cover the side and bottom surfaces of the conductive pattern. The barrier pattern may include a metal film or a metal nitride film. The metal film may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride film may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or a combination thereof.

[0149] Although not shown, in some embodiments, a silicide pattern may be interposed between the lower source / drain contact (bCA) and the lower source / drain pattern (LSD1) and between the lower gate contact (bCB) and the lower gate structure (LGE). The lower source / drain contact (bCA) may be electrically connected to the lower source / drain pattern (LSD1) through the silicide pattern, and the lower gate contact (bCB) may be electrically connected to the lower gate structure (LGE) through the silicide pattern. The silicide pattern may include a metal silicide, such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or a combination thereof.

[0150] Although not shown, in some embodiments, a first lower interlayer insulating film may be located below the lower source / drain contacts (bCA) and the lower gate contact (bCB) and may cover the lower source / drain contacts (bCA) and the lower gate contact (bCB).

[0151] A first lower metal layer may be disposed in the first lower interlayer insulating film. The first lower metal layer may include a first lower power wiring, a first lower wiring, and a first lower via. The first lower via may be disposed on the first lower power wiring and the first lower wiring. The first lower via may be interposed between the lower source / drain contact (bCA) and the first lower power wiring and between the lower source / drain contact (bCA) and the first lower power wiring and the first lower wiring. The first lower via may be interposed between the lower gate contact (bCB) and the first lower wiring.

[0152] The first lower power wiring and the first lower wiring of the first lower metal layer may include the same or different conductive materials, such as aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0153] Although not shown, in some embodiments, a lower metal layer may be additionally disposed below the first lower interlayer insulating film, and each of the lower metal layers may include a routing line.

[0154] FIG. 4 is a cross-sectional view showing a semiconductor device according to an embodiment, taken along line X1-X1' in FIG.

[0155] The embodiment shown in Fig. 4 has many similarities to the embodiment shown in Fig. 2, so a description thereof will be omitted and the differences will be focused on. Also, the same reference numerals will be used for the same components as those in the previous embodiment.

[0156] Figure 2 shows that the length of the lower insulating structure (BDI) in the second direction (D2) is substantially the same as the length of the intermediate insulating structure (MDI) in the second direction (D2), and the length of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) in the second direction (D2) is substantially the same as the length of the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE) in the second direction (D2).

[0157] Referring to FIG. 4, the length of the lower insulating structure (BDI) in the second direction (D2) may be greater than the length of the middle insulating structure (MDI) in the second direction (D2).

[0158] In addition, the length in the second direction (D2) of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) may be greater than the length in the second direction (D2) of the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE).

[0159] As a result, the bottom source / drain contact (bCA) and bottom gate contact (bCB) can be formed more easily by self-alignment without additional structures such as place holders, and damage to the gate pattern (GE) can be prevented when forming the bottom source / drain contact (bCA). The work function metal of the gate pattern (GE) is protected, and the threshold voltage (V t ) changes can be minimized.

[0160] For example, the length of the lower insulating structure (BDI) in the second direction (D2) may be greater than the length of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) in the second direction (D2).

[0161] The lengths of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) in the second direction (D2) become smaller as they go up in the third direction (D3). For example, the length of the first sub-gate portion (PO1) in the second direction (D2) may be greater than the length of the second sub-gate portion (PO2) in the second direction (D2). The length of the second sub-gate portion (PO2) in the second direction (D2) may be greater than the length of the third sub-gate portion (PO3) in the second direction (D2).

[0162] The lengths of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) in the second direction (D2) may be greater than the length of the intermediate insulating structure (MDI) in the second direction (D2). For example, the length of the third sub-gate portion (PO3) of the lower gate structure (LGE) in the second direction (D2) may be greater than the length of the intermediate insulating structure (MDI) in the second direction (D2).

[0163] The length of the intermediate insulating structure (MDI) in the second direction (D2) may be greater than the length of the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE) in the second direction (D2). For example, the length of the intermediate insulating structure (MDI) in the second direction (D2) may be greater than the length of the fourth sub-gate portion (PO4) of the upper gate structure (UGE) in the second direction (D2).

[0164] The lengths of the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE) in the second direction (D2) become smaller as they go up in the third direction (D3). For example, the length of the fourth sub-gate portion (PO4) in the second direction (D2) may be greater than the length of the fifth sub-gate portion (PO5) in the second direction (D2). The length of the fifth sub-gate portion (PO5) in the second direction (D2) may be greater than the length of the sixth sub-gate portion (PO6) in the second direction (D2).

[0165] As an example, the length of the lower insulating structure (BDI) in the second direction (D2) may be 1 nm or more greater than the length of the intermediate insulating structure (MDI) in the second direction (D2), for example, 2 nm or more, 3 nm or more, 4 nm or more, or 5 nm or more greater.

[0166] Furthermore, the length in the second direction (D2) of the first to third sub-gate portions (PO1 to PO3) of the lower gate structure (LGE) may be 1 nm or more longer than the length in the second direction (D2) of the fourth to sixth sub-gate portions (PO4 to PO6) of the upper gate structure (UGE), for example, 2 nm or more, 3 nm or more, 4 nm or more, or 5 nm or more longer.

[0167] Next, a method for manufacturing a semiconductor device according to one embodiment will be described with reference to Figures 5 to 30. Note that Figures 1 to 3 described above can also be referenced.

[0168] 5 to 30 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment in the order of steps.

[0169] Fig. 5 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 6 is a cross-sectional view taken along line Y1-Y1' in Fig. 1. At this time, cross-sectional views taken along lines Y2-Y2' and Y3-Y3' in Fig. 1 are omitted because they are similar to Fig. 6.

[0170] 5 and 6, a first high-concentration sacrificial layer (SCL1) is stacked on the lower substrate 101, and first to third low-concentration sacrificial layers (SAL1 to SAL3) and first and second active layers (ACL1, ACL2) are alternately stacked on the first high-concentration sacrificial layer (SCL1). In other words, the first high-concentration sacrificial layer (SCL1), the first low-concentration sacrificial layer (SAL1), the first active layer (ACL1), the second low-concentration sacrificial layer (SAL2), the second active layer (ACL2), and the third low-concentration sacrificial layer (SAL3) are stacked in order.

[0171] Moreover, a second dummy layer (DSL2), a second high-concentration sacrificial layer (SCL2), and a third dummy layer (DSL3) can be laminated in this order on the third low-concentration sacrificial layer (SAL3).

[0172] Furthermore, the fourth to sixth low-concentration sacrificial layers (SAL4 to SAL6) and the third and fourth active layers (ACL3, ACL4) can be alternately stacked on the third dummy layer (DSL3). In other words, the third dummy layer (DSL3), the fourth low-concentration sacrificial layer (SAL4), the third active layer (ACL3), the fifth low-concentration sacrificial layer (SAL5), the fourth active layer (ACL4), and the sixth low-concentration sacrificial layer (SAL6) can be stacked in this order.

[0173] Moreover, a fourth dummy layer (DSL4) can be laminated on the sixth low-concentration sacrificial layer (SAL6).

[0174] The lower substrate 101 may be a semiconductor substrate containing silicon, germanium, silicon germanium, etc., or a compound semiconductor substrate. For example, the lower substrate 101 may be a silicon substrate.

[0175] The first to sixth low-concentration sacrificial layers (SAL1 to SAL6) may contain one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) may contain silicon germanium (SiGe), and the concentration of germanium (Ge) in each of the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) may be 10 at % to 30 at %.

[0176] The first and second high-concentration sacrificial layers (SCL1 and SCL2) may contain silicon (Si) or silicon germanium (SiGe). When the first and second high-concentration sacrificial layers (SCL1 and SCL2) contain silicon germanium (SiGe), the germanium (Ge) concentration of the first and second high-concentration sacrificial layers (SCL1 and SCL2) may be higher than the germanium (Ge) concentration of the first to sixth low-concentration sacrificial layers (SAL1 to SAL6). For example, the germanium (Ge) concentration of the first and second high-concentration sacrificial layers (SCL1 and SCL2) may be 40 at% to 90 at%.

[0177] The first to fourth active layers (ACL1 to ACL4) may contain one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first to fourth active layers (ACL1 to ACL4) may contain silicon (Si).

[0178] The first to fourth dummy layers (DSL1 to DSL4) may contain one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first to fourth dummy layers (DSL1 to DSL4) may contain silicon (Si).

[0179] The stacked first high-concentration sacrificial layer (SCL1), first low-concentration sacrificial layer (SAL1), first active layer (ACL1), second low-concentration sacrificial layer (SAL2), second active layer (ACL2), third low-concentration sacrificial layer (SAL3), second dummy layer (DSL2), second high-concentration sacrificial layer (SCL2), third dummy layer (DSL3), fourth low-concentration sacrificial layer (SAL4), third active layer (ACL3), fifth low-concentration sacrificial layer (SAL5), fourth active layer (ACL4), sixth low-concentration sacrificial layer (SAL6), and fourth dummy layer (DSL4) can be patterned to form a stacked pattern (STP).

[0180] For example, the stack pattern (STP) may be formed by forming a first hard mask layer (HML1) on the uppermost fourth dummy layer (DSL4) and etching the stacked layers on the lower substrate 101 using the first hard mask layer (HML1) as an etching mask. During the formation of the stack pattern (STP), the upper portion of the lower substrate 101 may be patterned to form trenches that define the active pattern (AP1). The stack pattern (STP) may have a bar shape extending in the second direction (D2).

[0181] The first hard mask layer (HML1) may include SiCN, SiOCN, SiN, or a combination thereof. For example, the first hard mask layer (HML1) may include a multi-layer including SiCN, SiOCN, SiN, or a combination thereof.

[0182] The laminated pattern (STP) may include a lower laminated pattern (STP1) on the active pattern (AP1) and an upper laminated pattern (STP2) on the lower laminated pattern (STP1). The lower laminated pattern (STP1) may include first to third low-concentration sacrificial layers (SAL1 to SAL3) and first and second active layers (ACL1, ACL2) that are alternately stacked. The upper laminated pattern (STP2) may include fourth to sixth low-concentration sacrificial layers (SAL4 to SAL6) and third and fourth active layers (ACL3, ACL4) that are alternately stacked.

[0183] An isolation layer (ST) filling the trench may be formed on the lower substrate 101. For example, an insulating layer covering the active pattern (AP1) and the stack pattern (STP) may be formed on the entire surface of the lower substrate 101. The isolation layer (ST) may be formed by recessing the insulating layer until the stack pattern (STP) is exposed. For example, the isolation layer (ST) may expose up to the first low-concentration sacrificial layer (SAL1) of the stack pattern (STP) and cover the first high-concentration sacrificial layer (SCL1).

[0184] A seventh low-concentration sacrificial layer (SAL7) covering the stack pattern (STP) may be formed on the isolation layer (ST). For example, the seventh low-concentration sacrificial layer (SAL7) may be formed by depositing a low-concentration sacrificial layer material on the stack pattern (STP). The seventh low-concentration sacrificial layer (SAL7) may cover the top surface and both side surfaces in the first direction (D1) of the stack pattern (STP). The seventh low-concentration sacrificial layer (SAL7) may be formed conformally. In other words, the thickness in the third direction (D3) of the portion of the seventh low-concentration sacrificial layer (SAL7) located on the top surface of the stack pattern (STP) may be similar to the thickness in the first direction (D1) of the portion of the seventh low-concentration sacrificial layer (SAL7) located on the side surfaces of the stack pattern (STP).

[0185] The seventh low-concentration sacrificial layer (SAL7) may include one of silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the seventh low-concentration sacrificial layer (SAL7) may include silicon germanium (SiGe), and the concentration of germanium (Ge) in the seventh low-concentration sacrificial layer (SAL7) may be 10 at% to 30 at%.

[0186] Fig. 7 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 8 is a cross-sectional view taken along line Y1-Y1' in Fig. 1. At this time, cross-sectional views taken along lines Y2-Y2' and Y3-Y3' in Fig. 1 are omitted because they are similar to Fig. 8.

[0187] 7 and 8, the isolation layer (ST) is etched back until the lower substrate 101 is exposed, and then a barrier rib pattern 150 is formed in the space between the stack patterns (STP).

[0188] For example, the partition wall pattern 150 may be formed by filling spaces between the stacked patterns (STP) with an insulating material and planarizing the insulating material until the first hard mask layer (HML1) is exposed. The planarization of the insulating material may be performed using an etch back or chemical mechanical polishing (CMP) process.

[0189] During the planarization process, the seventh lightly doped sacrificial layer (SAL7) located on the top surface of the stack pattern (STP) may be removed, leaving only the seventh lightly doped sacrificial layer (SAL7) located on the side of the stack pattern (STP). Also, during the planarization process, the first hard mask layer (HML1) may be completely removed or partially left.

[0190] As a result, the partition pattern 150 may extend in the third direction D3 from a level lower than the top surface of the active pattern AP1 to a level higher than the top surface of the sixth low-concentration sacrificial layer SAL6 of the upper stack pattern STP2. For example, the bottom surface of the partition pattern 150 may be coplanar with the top surface of the lower substrate 101, and the top surface of the partition pattern 150 may be coplanar with the top surface of the fourth dummy layer DSL4 and the bottom surface of the first hard mask layer HML1.

[0191] A second hard mask layer (HML2) may be formed on the top surface of the partition wall pattern 150 and in the space between the stack pattern (STP). As an example, the second hard mask layer (HML2) may be formed on the top surface of the partition wall pattern 150 and the top surface of the stack pattern (STP), and the second hard mask layer (HML2) may be planarized until the first hard mask layer (HML1) is exposed. The planarization of the second hard mask layer (HML2) may be performed using an etch back or chemical mechanical polishing (CMP) process.

[0192] The second hard mask layer (HML2) may include SiCN, SiOCN, SiN, or a combination thereof. For example, the second hard mask layer (HML2) may include a multi-layer each including SiCN, SiOCN, SiN, or a combination thereof.

[0193] A first etch stop layer (ESL1) may be conformally formed on the first and second hard mask layers (HML1, HML2). The first etch stop layer (ESL1) may cover the top surfaces of the barrier rib pattern 150 and the stack pattern (STP).

[0194] Fig. 9 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 10 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0195] 9 and 10, a plurality of sacrificial patterns (PP) may be formed across the stack pattern (STP). Each sacrificial pattern (PP) may be formed in the form of a line extending in a first direction (D1). For example, the sacrificial patterns (PP) may be formed by forming a sacrificial layer on a first etch stop layer (ESL1), forming a hard mask pattern on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern as an etching mask. The sacrificial layer may include amorphous silicon or polysilicon.

[0196] A pair of gate spacers (GS) may be formed on both sides of the sacrificial pattern (PP) in the second direction (D2). For example, a spacer layer may be conformally formed on the entire surface of the first etch stop layer (ESL1) and the sacrificial pattern (PP). The spacer layer may cover the first etch stop layer (ESL1) and the sacrificial pattern (PP). For example, the spacer layer may include SiCN, SiOCN, SiN, or a combination thereof.

[0197] Fig. 11 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 12 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0198] 11 and 12, an etching process can be performed on the stack pattern (STP) using the gate spacer (GS) and the sacrificial pattern (PP) as an etching mask.

[0199] For example, the stacked first high-concentration sacrificial layer (SCL1), first low-concentration sacrificial layer (SAL1), first active layer (ACL1), second low-concentration sacrificial layer (SAL2), second active layer (ACL2), third low-concentration sacrificial layer (SAL3), second dummy layer (DSL2), second high-concentration sacrificial layer (SCL2), third dummy layer (DSL3), fourth low-concentration sacrificial layer (SAL4), third active layer (ACL3), fifth low-concentration sacrificial layer (SAL5), fourth active layer (ACL4), sixth low-concentration sacrificial layer (SAL6), and fourth dummy layer (DSL4) may be patterned by an etching process to form a lower channel pattern (LCH1) and an upper channel pattern (UCH1).

[0200] The lower channel pattern (LCH1) may include a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2) stacked and spaced apart from each other in the third direction (D3), and the upper channel pattern (UCH1) may include a third semiconductor pattern (SP3) and a fourth semiconductor pattern (SP4) stacked and spaced apart from each other in the third direction (D3).

[0201] Meanwhile, first to third low-concentration sacrificial layers (SAL1 to SAL3) can be alternately stacked between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2) of the lower channel pattern (LCH1), and fourth to sixth low-concentration sacrificial layers (SAL4 to SAL6) can be alternately stacked between the third semiconductor pattern (SP3) and the fourth semiconductor pattern (SP4) of the upper channel pattern (UCH1).

[0202] In addition, the second dummy layer (DSL2), the third dummy layer (DSL3), and the fourth dummy layer (DSL4) are also patterned to form a second dummy channel pattern (DS2), a third dummy channel pattern (DS3), and a fourth dummy channel pattern (DS4), respectively.

[0203] The first and second hard mask layers (HML1, HML2) are also patterned to form first and second hard masks (HM1, HM2), respectively.

[0204] As a result, a first recess ET1 can be formed between the lower channel pattern LCH1 and the upper channel pattern UCH1.

[0205] Fig. 13 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 14 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0206] Referring to Figures 13 and 14, portions of both sides of the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) exposed by the first recess (ET1) in the second direction (D2) can be removed, and gate inner spacers (GIS) can be formed in the removed spaces.

[0207] For example, an indentation process is performed on the first to sixth low-concentration sacrificial layers (SAL1 to SAL6). In the indentation process, the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) are etched using a wet etching or dry etching method, thereby reducing the lengths of the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) in the second direction (D2).

[0208] At this time, the etching agent used in the indentation process has a selectivity for the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) compared to the first and second high-concentration sacrificial layers (SCL1, SCL2), and can etch only the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) without etching the first and second high-concentration sacrificial layers (SCL1, SCL2).

[0209] Meanwhile, the seventh low-concentration sacrificial layer (SAL7), which covers both sides of the lower channel pattern (LCH1) and the upper channel pattern (UCH1) in the first direction (D1), also has portions of both sides removed in the second direction (D2) by the indentation process, reducing its length in the second direction (D2).

[0210] Next, a low-dielectric material is filled into the spaces where the first to seventh low-concentration sacrificial layers (SAL1 to SAL7) have been partially removed by an indentation process to form gate inner spacers (GIS). For example, an overlapping portion (IS1) of the gate inner spacer (GIS) may be formed in the spaces where the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) have been partially removed, and a non-overlapping portion (IS2) of the gate inner spacer (GIS) may be formed in the spaces where the seventh low-concentration sacrificial layer (SAL7) has been partially removed.

[0211] The low dielectric material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or the like.

[0212] Fig. 15 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 16 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0213] Referring to Figures 15 and 16, the first and second high-concentration sacrificial layers (SCL1, SCL2) exposed by the first recess (ET1) can be selectively removed to form a lower insulating structure (BDI) and a middle insulating structure (MDI), respectively, in the removed space.

[0214] For example, the first and second high-concentration sacrificial layers (SCL1, SCL2) can be removed by wet etching or dry etching. At this time, the etchant used to etch the first and second high-concentration sacrificial layers (SCL1, SCL2) has a selectivity to the first and second high-concentration sacrificial layers (SCL1, SCL2) compared to the first to sixth low-concentration sacrificial layers (SAL1 to SAL6), so that the first to sixth low-concentration sacrificial layers (SAL1 to SAL6) are not etched, and only the first and second high-concentration sacrificial layers (SCL1, SCL2) are etched.

[0215] Next, an insulating material can be filled into the spaces where the first and second highly-doped sacrificial layers (SCL1, SCL2) have been removed to form a bottom insulating structure (BDI) and a middle insulating structure (MDI), respectively.

[0216] The insulating material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or the like.

[0217] Fig. 17 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 18 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0218] Referring to FIGS. 17 and 18, a lower source / drain pattern (LSD1), a buried insulating layer (SDI), and an upper source / drain pattern (USD1) may be formed in the first recess (ET1).

[0219] First, a lower source / drain pattern (LSD1) may be formed in the first recess (ET1). For example, the lower source / drain pattern (LSD1) may be formed by performing a selective epitaxial growth (SEG) process using the exposed side surfaces of the lower channel pattern (LCH1) and the top surface of the active pattern (AP1) as a seed layer. The lower source / drain pattern (LSD1) may be grown using the first and second semiconductor patterns (SP1, SP2) and the active pattern (AP1) exposed by the first recess (ET1) as a seed. For example, the selective epitaxial growth (SEG) process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0220] During the selective epitaxial growth (SEG) process, impurities may be implanted in-situ into the lower source / drain pattern (LSD1). As another example, after the lower source / drain pattern (LSD1) is formed, impurities may be implanted into the lower source / drain pattern (LSD1). The lower source / drain pattern (LSD1) may be doped to have a first conductivity type (e.g., N-type).

[0221] Although not shown, in some embodiments, the side surfaces of the upper stack pattern (STP2) may be covered by a liner film. In other words, the third and fourth semiconductor patterns (SP3, SP4) of the upper stack pattern (STP2) may not be exposed by the liner film during the selective epitaxial growth (SEG) process of the lower source / drain pattern (LSD1). Therefore, no additional semiconductor layer is grown on the upper channel pattern (UCH1) during the selective epitaxial growth (SEG) process.

[0222] The first and second semiconductor patterns (SP1, SP2) interposed between a pair of lower source / drain patterns (LSD1) may form a lower channel pattern (LCH1). The lower channel pattern (LCH1) and the lower source / drain pattern (LSD1) may form a first active region (AR1), which is a lower tier of the three-dimensional device.

[0223] A buried insulating layer (SDI) may be formed in the first recess (ET1). For example, the buried insulating layer (SDI) may fill the first recess (ET1) to a level covering the third dummy channel pattern (DS3). Next, the liner film is removed, and both side surfaces of the upper channel pattern (UCH1) can be exposed by the first recess (ET1).

[0224] The upper source / drain pattern (USD1) may be formed between the upper channel pattern (UCH1) in the first recess (ET1). For example, the upper source / drain pattern (USD1) may be formed by performing a selective epitaxial growth (SEG) process using the exposed side surfaces of the upper stack pattern (STP2) as a seed layer. The upper source / drain pattern (USD1) may be grown using the third and fourth semiconductor patterns (SP3, SP4) exposed by the first recess (ET1) as a seed. For example, the selective epitaxial growth (SEG) process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0225] During the selective epitaxial growth (SEG) process, impurities can be implanted in-situ into the upper source / drain pattern (USD1). As another example, after the upper source / drain pattern (USD1) is formed, impurities can be implanted into the upper source / drain pattern (USD1). The upper source / drain pattern (USD1) can be doped to have a second conductivity type (e.g., P-type) that is different from the first conductivity type (e.g., P-type) of the lower source / drain pattern (LSD1).

[0226] The third and fourth semiconductor patterns (SP3, SP4) interposed between the pair of upper source / drain patterns (USD1) may form an upper channel pattern (UCH1). The upper channel pattern (UCH1) and the upper source / drain pattern (USD1) may form a second active region (AR2) of an upper tier of the three-dimensional device.

[0227] A second interlayer insulating layer 120 may be formed on the upper source / drain pattern USD1 and the partition wall pattern 150.

[0228] As an example, an insulating material may be deposited on the upper source / drain pattern (USD1) and the partition wall pattern 150 to form the second interlayer insulating layer 120, and the second interlayer insulating layer 120 may be planarized until the top surface of the sacrificial pattern (PP) is exposed.

[0229] The insulating material may be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or the like. Planarization of the second interlayer insulating layer 120 may be performed using an etch back or chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern may be completely removed. As a result, the top surface of the second interlayer insulating layer 120 may be coplanar with the top surfaces of the sacrificial pattern (PP) and the gate spacer (GS).

[0230] Fig. 19 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 20 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0231] Referring to Figures 19 and 20, a gate cut pattern (CT) can be formed through the sacrificial pattern (PP).

[0232] For example, the exposed sacrificial pattern (PP) is selectively removed using a hard mask, for example, a portion of the sacrificial pattern (PP) located on the barrier rib pattern 150 is removed.

[0233] The length of the removed sacrificial pattern (PP) in the first direction (D1) may be substantially the same as the length of the partition pattern 150 in the first direction (D1). The length of the removed sacrificial pattern (PP) in the second direction (D2) may be substantially the same as the length of the first hard mask (HM1) in the second direction (D2). As a result, the connection of the main gate structure (MGE) is cut by the gate cutting pattern (CT) on the partition pattern 150.

[0234] The sacrificial pattern (PP) may be removed by wet etching using an etchant that selectively etches polysilicon. By removing the sacrificial pattern (PP), the second hard mask (HM2) located on the partition wall pattern 150 may be exposed.

[0235] The space where the sacrificial pattern (PP) has been removed can be filled with an insulating material to form a gate cut pattern (CT). The insulating material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

[0236] Fig. 21 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 22 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0237] 21 and 22, the exposed sacrificial pattern (PP) and the first and second hard masks (HM1, HM2) may be selectively removed to form a second recess (ET2). The sacrificial pattern (PP) may be removed by wet etching using an etchant that selectively etches polysilicon. By removing the sacrificial pattern (PP) and the first and second hard masks (HM1, HM2), the first to seventh sacrificial layers (SAL1 to SAL7) may be exposed.

[0238] An etching process is performed to selectively etch the first to seventh sacrificial layers (SAL1 to SAL7) exposed by the second recess (ET2), thereby removing only the first to seventh sacrificial layers (SAL1 to SAL7) while leaving the first to fourth semiconductor patterns (SP1 to SP4) and the second to fourth dummy channel patterns (DS2 to DS4) intact. The etching process may have a high etching rate for silicon germanium. For example, the etching process may have a high etching rate for silicon germanium having a germanium concentration greater than 10 at%.

[0239] Fig. 23 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 24 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0240] Referring to FIGS. 23 and 24, a gate pattern (GE) may be formed in the region where the sacrificial pattern (PP) and the first to seventh sacrificial layers (SAL1 to SAL7) have been removed.

[0241] First, although not shown, in some embodiments, a gate insulating film can be conformally formed in the region where the sacrificial pattern (PP) and the first to seventh sacrificial layers (SAL1 to SAL7) have been removed.

[0242] A gate pattern (GE) may be formed on the gate insulating film by forming a lower gate structure (LGE) including first to third sub-gate portions (PO1 to PO3) between the first and second semiconductor patterns (SP1, SP2), forming an upper gate structure (UGE) including fourth to sixth sub-gate portions (PO4 to PO6) between the third and fourth semiconductor patterns (SP3, SP4), and forming a main gate structure (MGE) in a region where the sacrificial pattern (PP) has been removed.

[0243] The gate pattern (GE) may be recessed to reduce its height. A gate capping pattern (GP) may be formed on the recessed gate pattern (GE). A planarization process may be performed on the gate capping pattern (GP) so that the top surface of the gate capping pattern (GP) is coplanar with the top surface of the second interlayer insulating layer 120.

[0244] Fig. 25 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 26 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0245] Referring to Figures 25 and 26, an upper source / drain contact (aCA) is formed to connect to the upper source / drain pattern (USD1), and an upper gate contact (aCB) is formed to connect to the main gate structure (MGE) of the gate pattern (GE).

[0246] For example, a hard mask pattern is formed on the second interlayer insulating layer 120, and the second interlayer insulating layer 120 is patterned using the hard mask pattern as an etching mask to form a first contact hole in the upper surface of the upper source / drain pattern USD1 by penetrating the second interlayer insulating layer 120 in the third direction D3. For example, the patterning may be performed using dry etching.

[0247] Also, a second contact hole is formed through the gate capping pattern GP in the third direction D3 to expose the top surface of the main gate structure MGE of the gate pattern GE.

[0248] The first and second contact holes are filled with metal, and an upper source / drain contact (aCA) connected to the upper source / drain pattern (USD1) is formed in the first contact hole, and an upper gate contact (aCB) connected to the main gate structure (MGE) of the gate pattern (GE) is formed in the second contact hole.

[0249] Although the above description has been given of the case where the upper source / drain contact (aCA) and the upper gate contact (aCB) are formed in separate processes, the present disclosure is not limited thereto, and the upper source / drain contact (aCA) and the upper gate contact (aCB) can be formed simultaneously, or the upper gate contact (aCB) can be formed first and then the upper source / drain contact (aCA) can be formed.

[0250] Although not shown, in some embodiments, a first upper interlayer insulating film including a first upper metal layer electrically connected to the upper source / drain contacts (aCA) and the upper gate contact (aCB) can be formed on the upper surface of the second interlayer insulating layer 120 and the gate capping pattern (GP).

[0251] Fig. 27 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 28 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0252] Referring to Figures 27 and 28, the lower substrate 101 is removed.

[0253] First, the semiconductor element can be rotated.

[0254] For example, although not shown, in some embodiments, the rotated semiconductor device may be positioned on a carrier substrate. In this case, the semiconductor device may be attached to the carrier substrate after being positioned so that the top surface of the semiconductor device faces the carrier substrate. That is, a first upper interlayer insulating film positioned on the top surface of the semiconductor device may be attached to the carrier substrate. An adhesive member may be disposed between the first upper interlayer insulating film and the carrier substrate.

[0255] The carrier substrate may have an area substantially the same as or larger than that of the semiconductor device. The carrier substrate may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The adhesive member may be in the form of a film.

[0256] The adhesive member may include a base film and adhesive layers attached to both sides of the base film. The base film may be a polyethylene-based film such as polyethylene terephthalate (PET) or polyethylene-2,6-naphthalenedicarboxylate (PEN), or a polyolefin-based film. The base film may be formed by coating a polyethylene-based film or a polyolefin-based film with silicone or Teflon. The adhesive layer may be made of, for example, an acrylic polymer resin, an epoxy resin, or a mixture thereof.

[0257] Next, an etching process may be performed to remove the lower substrate 101. The etching process may be performed by, for example, wet etching, but is not limited thereto.

[0258] By removing the lower substrate 101, the lower surface of the partition wall pattern 150 can be exposed. Thus, by using the exposed partition wall pattern 150, the lower source / drain contacts (bCA) and the lower gate contacts (bCB) can be formed in a self-aligned manner without an additional structure such as a placeholder.

[0259] In addition, the gate inner spacer (GIS) extends in the first direction (D1) from one partition pattern 150 to another partition pattern 150 adjacent to it in the first direction (D1), the gate inner spacer (GIS) is positioned on the entire surface of the gate pattern (GE) that contacts the lower source / drain pattern (LSD1) and the upper source / drain pattern (USD1), and the lower part of the gate pattern (GE) is protected by the lower insulating structure (BDI), thereby preventing the gate pattern (GE) from being damaged when forming the lower source / drain contact (bCA).

[0260] Fig. 29 is a cross-sectional view taken along lines X1-X1' and X2-X2' in Fig. 1. Fig. 30 is a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' in Fig. 1.

[0261] Referring to Figures 29 and 30, a lower source / drain contact (bCA) is formed to connect to the lower source / drain pattern (LSD1), and a lower gate contact (bCB) is formed to connect to the lower gate structure (LGE) of the gate pattern (GE).

[0262] For example, a patterning process may be performed to remove a portion of the active pattern AP1 to form a third contact hole exposing the lower source / drain pattern LSD1. At this time, the third contact hole may penetrate the active pattern AP1. In other words, the side of the third contact hole may be surrounded by the active pattern AP1.

[0263] Subsequently, the third contact hole is filled and a lower source / drain contact (bCA) is formed to be electrically connected to the lower source / drain pattern (LSD1).

[0264] Next, a patterning process may be performed to remove a portion of the active pattern AP1 to form a fourth contact hole exposing the first sub-gate portion PO1 of the gate pattern GE. At this time, the fourth contact hole may penetrate the active pattern AP1. In other words, the side of the fourth contact hole may be surrounded by the active pattern AP1.

[0265] Subsequently, an insulating liner (CBL) is conformally coated on the side surface of the fourth contact hole, and then the fourth contact hole is filled to form a bottom gate contact (bCB) that is electrically connected to the first sub-gate portion (PO1) of the gate pattern (GE).

[0266] Although the above describes the case where the lower source / drain contact (bCA) and the lower gate contact (bCB) are formed in separate processes, the present disclosure is not limited thereto, and the lower source / drain contact (bCA) and the lower gate contact (bCB) can be formed simultaneously, or the lower gate contact (bCB) can be formed first and then the lower source / drain contact (bCA) can be formed.

[0267] Although not shown, in some embodiments, a first lower interlayer insulating film including an isolation layer (ST) and a first lower metal layer electrically connecting the lower source / drain contacts (bCA) and the lower gate contacts (bCB) to the lower surface of the active pattern (AP1) may be formed.

[0268] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of the present disclosure as defined in the claims below also fall within the scope of the present disclosure. [Explanation of symbols]

[0269] AP1 activity pattern ST element separation membrane AR1 1st active region AR2 second active region LCH1 Lower Channel Pattern UCH1 Upper Channel Pattern LSD1 bottom source / drain pattern USD1 top source / drain pattern GE Gate Pattern LGE lower gate structure UGE upper gate structure MGE Main Gate Structure PO1~PO6 1st to 6th sub-gate parts PO7 subgate connection part PO8 Main gate connection part aCA top source / drain contact aCB upper gate contact bCA bottom source / drain contact bCB bottom gate contact GIS Gate Inner Spacer IS1 overlapping part IS2 Non-overlapping part 120 Second interlayer insulating layer 150 bulkhead pattern BDI Lower Insulation Structure MDI Intermediate Insulation Structure SDI buried insulating layer CT gate cutting pattern

Claims

1. active patterns spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns positioned on the active patterns and alternately arranged in the second direction; an upper channel pattern located above the lower channel pattern; and an upper source / drain pattern located above the lower source / drain pattern; a gate pattern positioned on the active pattern and on the lower channel pattern and the upper channel pattern; and a gate inner spacer located between the gate pattern and the lower source / drain pattern and the upper source / drain pattern; the gate inner spacer has an overlapping portion overlapping the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first and second directions and a non-overlapping portion not overlapping the upper channel pattern and the lower channel pattern in the third direction; Semiconductor element.

2. the lower channel pattern and the upper channel pattern include a plurality of semiconductor patterns stacked and spaced apart from each other in the third direction, the overlapping portion of the gate inner spacer is located between the semiconductor patterns, the non-overlapping portions of the gate inner spacers are located on both sides of the semiconductor patterns in the first direction and extend in the third direction from the semiconductor patterns located at the bottom to the semiconductor patterns located at the top. The semiconductor device according to claim 1 .

3. The semiconductor element is an isolation layer disposed on both sides of the active pattern in the first direction; and a first hard mask disposed on the upper channel pattern; and an etch stop layer disposed on the first hard mask; the non-overlapping portion of the gate inner spacer extends in the third direction from an upper surface of the isolation layer to a lower surface of the etch stop layer. The semiconductor device according to claim 2 .

4. the semiconductor device further includes barrier rib patterns spaced apart in the first direction, extending in the second direction, and alternately arranged with the active patterns in the first direction; The gate inner spacer extends in the first direction from one of the barrier rib patterns to another of the barrier rib patterns adjacent to the barrier rib pattern in the first direction. The semiconductor device according to claim 2 .

5. the overlapping portion of the gate inner spacer is located between one of the barrier rib patterns and another of the barrier rib patterns adjacent thereto in the first direction, the non-overlapping portion of the gate inner spacer is located between the overlapping portion and the barrier rib pattern, the overlapping portion does not contact the partition pattern, and the non-overlapping portion contacts the partition pattern. The semiconductor device according to claim 2 .

6. The gate pattern is a lower gate structure overlying the active pattern and including a plurality of sub-gate portions positioned between the semiconductor patterns; an upper gate structure overlying the lower gate structure and including a plurality of sub-gate portions positioned between the semiconductor patterns; a main gate structure overlying the upper gate structure; and a sub-gate connection portion located on both sides of the sub-gate portion in the first direction, extending in the third direction from the sub-gate portion located at the lowermost end to the sub-gate portion located at the uppermost end, and not overlapping with the upper channel pattern and the lower channel pattern in the third direction; The semiconductor device according to claim 2 .

7. the semiconductor device further includes barrier rib patterns spaced apart in the first direction, extending in the second direction, and alternately arranged with the active patterns in the first direction; the gate pattern extends in the first direction from one of the barrier rib patterns to another of the barrier rib patterns adjacent to the barrier rib pattern in the first direction; The semiconductor device according to claim 6 .

8. the sub-gate portion of the gate pattern is located between the barrier rib patterns, and the sub-gate connection portion is located between the sub-gate portion and the barrier rib pattern; the sub-gate portion does not contact the partition pattern, and the sub-gate connecting portion contacts the partition pattern. The semiconductor device according to claim 7 .

9. The semiconductor element is a lower insulating structure located between the active pattern and the lower gate structure; and further comprising an intermediate insulating structure located between the lower gate structure and the upper gate structure. The semiconductor device according to claim 6 .

10. The lower insulating structure and the intermediate insulating structure are overlapping the upper channel pattern, the lower channel pattern, the upper gate structure and the lower gate structure of the gate pattern, and the overlapping portion of the gate inner spacer in the third direction; the sub-gate connecting portion of the gate pattern and the non-overlapping portion of the gate inner spacer do not overlap in the third direction; The semiconductor device according to claim 9 .

11. a length of the lower insulating structure in the second direction being greater than a length of the intermediate insulating structure in the second direction; a length of the sub-gate portion of the lower gate structure in the second direction is greater than a length of the sub-gate portion of the upper gate structure in the second direction; The semiconductor device according to claim 9 .

12. active patterns spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns positioned on the active patterns and alternately arranged in the second direction; an upper channel pattern located above the lower channel pattern; and an upper source / drain pattern located above the lower source / drain pattern; a gate pattern disposed on the active pattern and disposed on the lower channel pattern and the upper channel pattern; a lower source / drain contact positioned below the lower source / drain pattern and connected to the lower source / drain pattern; and barrier rib patterns that are spaced apart in the first direction, extend in the second direction across the gate patterns, and are alternately arranged with the active patterns in the first direction; the partition pattern extends in a third direction perpendicular to the first and second directions from a level lower than an upper surface of the lower source / drain contact to a level lower than an upper surface of the gate pattern; Semiconductor element.

13. the lower channel pattern and the upper channel pattern include a plurality of semiconductor patterns stacked and spaced apart from each other in the third direction, The gate pattern is a lower gate structure overlying the active pattern and including a plurality of sub-gate portions positioned between the semiconductor patterns; an upper gate structure overlying the lower gate structure and including a plurality of sub-gate portions positioned between the semiconductor patterns; and a main gate structure positioned above the upper gate structure; The semiconductor device according to claim 12.

14. the barrier rib pattern is located between any one of the lower gate structure and the upper gate structure and another of the lower gate structure and the upper gate structure adjacent thereto in the first direction, Any one of the sub-gate portion and the sub-gate connection portion, and another adjacent sub-gate portion and sub-gate connection portion are separated from the other adjacent sub-gate portion and sub-gate connection portion by the barrier rib pattern. The semiconductor device of claim 13.

15. The gate pattern is a main gate connection portion located on any one of the barrier rib patterns, any one of the main gate structures disposed apart in the first direction with any one of the barrier rib patterns therebetween is connected to another of the main gate structures by the main gate connecting portion; The semiconductor device of claim 14.

16. The semiconductor element is a second hard mask disposed on any one of the partition patterns; and a gate cutting pattern disposed on the second hard mask, any one of the main gate structures disposed apart in the first direction with any one of the barrier rib patterns therebetween is separated from another one of the main gate structures by the gate cutting pattern; The semiconductor device of claim 14.

17. the barrier rib pattern is located between any one of the lower source / drain patterns and another of the lower source / drain patterns adjacent thereto in the first direction, the barrier rib pattern is located between any one of the upper source / drain patterns and another of the upper source / drain patterns adjacent thereto in the first direction, the barrier rib pattern is located between any one of the lower gate structures and another of the lower gate structures adjacent thereto in the first direction, the barrier rib pattern is located between any one of the upper gate structures and another of the upper gate structures adjacent thereto in the first direction; The semiconductor device of claim 14.

18. The semiconductor element is a lower gate contact positioned below the gate pattern and connected to the gate pattern; the barrier rib pattern is located between any one of the lower source / drain contacts and another of the lower source / drain contacts adjacent thereto in the first direction; the barrier rib pattern is positioned between any one of the lower gate contacts and another of the lower gate contacts adjacent thereto in the first direction; The semiconductor device of claim 14.

19. active patterns spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns positioned on the active patterns and alternately arranged in the second direction; an upper channel pattern located above the lower channel pattern; and an upper source / drain pattern located above the lower source / drain pattern; a gate pattern disposed on the active pattern and disposed on the lower channel pattern and the upper channel pattern; a gate inner spacer positioned between the gate pattern and the lower source / drain pattern and the upper source / drain pattern, the gate inner spacer having an overlapping portion overlapping the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first direction and the second direction and a non-overlapping portion not overlapping the upper channel pattern and the lower channel pattern in the third direction; and barrier rib patterns spaced apart in the first direction, extending in the second direction, and alternately arranged with the active patterns in the first direction; both side surfaces of the lower source / drain pattern and the upper source / drain pattern in the first direction are surrounded by the partition wall pattern; both side surfaces of the lower source / drain pattern and the upper source / drain pattern in the second direction are surrounded by the overlapping portion and the non-overlapping portion of the gate inner spacer; Semiconductor element.

20. The semiconductor element is a lower source / drain contact positioned below the lower source / drain pattern and connected to the lower source / drain pattern; and a lower insulating structure disposed between the active pattern and the lower gate structure; the lower insulating structure is located between the lower source / drain contact and the gate pattern in the third direction, and the overlapping portion and the non-overlapping portion of the gate inner spacer are located in the second direction, and the gate pattern does not contact the lower source / drain contact; 20. The semiconductor device of claim 19.

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