Semiconductor memory device

Abstract

To provide a semiconductor memory in which row hammer refresh operation can be performed without deteriorating performance of normal refresh operation.SOLUTION: A semiconductor memory device includes a control unit 10 which performs control so as to perform normal refresh operation for simultaneously refreshing memory cells connected to each of a plurality of word lines in response to a refresh request, and performs control so as to perform row hammer refresh operation each time the normal refresh operation is performed at least once.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device, is a volatile memory that stores information by storing electric charge in a capacitor and loses the stored information when power is cut off. Because the electric charge stored in the capacitor is discharged after a certain period of time, DRAM requires a memory retention operation called refresh, in which the electric charge is periodically charged (for example, Patent Documents 1 to 3).

[0003] However, if many read and / or write requests are concentrated on the same row address during a refresh, a row hammer problem may occur. The row hammer problem is a problem in which, when many accesses are concentrated on the same row address within a certain period of time, the charges of data bits corresponding to row addresses physically adjacent to the row address are discharged, causing data corruption.

[0004] To solve the row hammer problem, a semiconductor memory device is also known that is configured to perform a row hammer refresh (RH) operation. In the row hammer refresh operation, for example, a frequently accessed row address (hammer address) is detected, and an additional refresh operation is performed on a row address physically adjacent to the detected hammer address. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] China Patent Publication No. 107924697 [Patent Document 2] U.S. Patent Publication No. 9,741,421 [Patent Document 3] Taiwan Patent Publication No. 201535366 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to perform a row hammer refresh operation in a conventional semiconductor memory device, for example, as shown in Figure 1(a), a row hammer refresh operation RH ref is performed after a normal refresh operation (Reg ref) is performed in response to one refresh request (refresh command) REF. In the example shown in Figure 1(a), two refresh operations (Reg ref) are performed on a row address corresponding to one of the word lines WL in response to one refresh request REF, followed by one row hammer refresh operation RH ref on row addresses physically adjacent to the detected hammer address (row addresses ±1 of the hammer address). However, in this case, there is a risk that the time required for the refresh operations (Reg ref) and the row hammer refresh operation RH ref to be completed in response to one refresh request REF may exceed the refresh cycle period tRFC, which is the time required for the refresh operation (Reg ref) corresponding to one refresh request REF to be completed and is determined by specifications.

[0007] Furthermore, in the specifications of conventional semiconductor memory devices, the refresh cycle period tRFC is set to be shorter as the storage capacity becomes smaller, such as 1 GB or 500 MB, etc. In this case, as shown in Fig. 1(b), only one refresh operation Reg ref can be performed in the refresh cycle period tRFC corresponding to one refresh request REF, and it may become difficult to perform a row hammer refresh operation RH ref in addition to the refresh operation Reg ref in the refresh cycle period tRFC.

[0008] 1(c), it is also possible to perform a row hammer refresh operation RH ref instead of performing a refresh operation Reg ref in response to one refresh request REF. However, in this case, the period for performing the row hammer refresh operation RH ref is added to the period until the refresh operations Reg ref for all row addresses are completed, so there is a risk that the period (interval) for performing the refresh operation Reg ref for the same row address ("A" in the example shown in the figure) will exceed the refresh period t REF, which is the period (interval) defined by the specifications.

[0009] Therefore, in conventional semiconductor memory devices, it has been difficult to perform a row hammer refresh operation without degrading the performance of the refresh operation, such as the refresh cycle period tRFC and the refresh period tREF.

[0010] The present invention has been made in view of the above-mentioned problems, and aims to provide a semiconductor memory device and a control method thereof that are capable of performing row hammer refresh operations without degrading the performance of the refresh operations. [Means for solving the problem]

[0011] In order to solve the above problem, the present invention provides a semiconductor memory device including a control unit that controls a refresh operation to simultaneously refresh memory cells connected to each of a plurality of word lines in response to a refresh request, and that controls a row hammer refresh operation to be performed each time the refresh operation is performed at least once.

[0012] According to this invention, refresh operations for multiple word lines (row addresses) are performed simultaneously in response to one refresh request. This reduces the number of refresh requests required to perform refresh operations for all word lines, compared to when a refresh operation is performed for a single word line in response to one refresh request. In this case, row hammer refresh operations can be performed in response to the reduced number of refresh requests, allowing refresh operations for all row addresses and at least one row hammer refresh operation to be performed within a refresh period (e.g., refresh period tREF). This allows row hammer refresh operations to be performed without degrading refresh performance.

[0013] The present invention also provides a method for controlling a semiconductor memory device, which includes a step of controlling a control unit of the semiconductor memory device to perform a refresh operation in response to a refresh request, which simultaneously refreshes memory cells connected to each of a plurality of word lines, and a step of controlling to perform a row hammer refresh operation each time the refresh operation is performed at least once. [Effects of the Invention]

[0014] According to the semiconductor memory device and the control method thereof of the present invention, the row hammer refresh operation can be performed without degrading the performance of the refresh operation. [Brief explanation of the drawings]

[0015] [Figure 1] 10(a) to 10(c) are diagrams showing an example of changes in signal voltages when a refresh operation and a row hammer refresh operation are performed in a semiconductor memory device according to the prior art. [Figure 2] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 3]FIG. 1A is a diagram showing an example of a change in the voltage of a signal when a refresh operation is performed in a semiconductor memory device of the prior art, and FIG. 1B is a diagram showing an example of a change in the voltage of each signal when a refresh operation and a row hammer refresh operation are performed in a semiconductor memory device of this embodiment. [Figure 4] FIG. 1A is a diagram showing an example of a change in the voltage of a signal when a refresh operation is performed in a semiconductor memory device of the prior art, and FIG. 1B is a diagram showing an example of a change in the voltage of each signal when a refresh operation and a row hammer refresh operation are performed in a semiconductor memory device according to a modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] FIG. 2 is a diagram showing an example of the configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 2, the semiconductor memory device according to this embodiment includes a control unit 10. The control unit 10 also includes a command decoder 11, a refresh (REF) control unit 12, a refresh counter 13, a row hammer (RH) control unit 14, a REF address counter 15, a first multiplexer 16, an RH address generation unit 17, a second multiplexer 18, and a row decoder 19. Each of the units 11 to 19 in the control unit 10 may be configured by a dedicated hardware device or logic circuit. Note that, in this embodiment, other well-known components such as a memory cell array, a power supply circuit, and a clock generator are not shown for the sake of simplicity.

[0017] Furthermore, the semiconductor memory device according to this embodiment may be, for example, a DRAM, or a pSRAM (pseudo-static random access memory) configured to internally control refresh operations.

[0018] In this embodiment, as shown in Figures 3 and 4 (described later), the control unit 10 performs control to perform a refresh operation Reg ref in response to a refresh request REF, which simultaneously refreshes memory cells (not shown) connected to multiple (two in this embodiment) word lines WL1 and WL2. The control unit 10 also performs control to perform a row hammer refresh operation RH ref every time a refresh operation Reg ref is performed at least once. Note that it is assumed here that, in one row hammer refresh operation RH ref, an additional refresh operation is performed on row addresses physically adjacent to a detected hammer address (row addresses ±1 from the hammer address).

[0019] Furthermore, the control unit 10 may be configured to perform a row hammer refresh operation RH ref in response to the refresh request REF, thereby making it possible to perform the row hammer refresh operation RH ref in response to the refresh request REF.

[0020] Furthermore, the control unit 10 may be configured to perform the row hammer refresh operation RH ref multiple times within the refresh cycle period tRFC (predetermined period) in response to the refresh request REF, thereby improving the refresh rate of the row hammer refresh operation RH ref.

[0021] Furthermore, the control unit 10 may be configured to determine whether to perform the refresh operation Reg ref or the row hammer refresh operation RH ref each time a refresh request REF is received, thereby making it possible to perform either the refresh operation Reg ref or the row hammer refresh operation RH ref in accordance with the refresh request REF.

[0022] Furthermore, the control unit 10 may be configured not to perform the refresh operation Reg ref when the refresh request REF is acquired after the number of times the refresh operation Reg ref has been executed reaches a predetermined value. This makes it possible to perform a row hammer refresh operation RH ref instead of the refresh operation Reg ref, for example, when the cumulative number of times the refresh operation Reg ref has been executed reaches a predetermined value, or every time the cumulative number of times the refresh operation Reg ref has been executed reaches a predetermined value.

[0023] Furthermore, the control unit 10 may be configured not to perform the refresh operation when a refresh request REF is acquired after the refresh operation Reg ref has been performed a predetermined number of times in succession. This makes it possible to perform a row hammer refresh operation RH ref instead of the refresh operation Reg ref, for example, when the refresh operation Reg ref has been performed a predetermined number of times in succession (for example, twice).

[0024] Furthermore, the control unit 10 may be configured to perform the refresh operation Reg ref multiple times within a refresh cycle period tRFC (a predetermined period) in response to the refresh request REF, thereby making it possible to improve the refresh rate of the refresh operation Reg ref.

[0025] The detailed configuration of each of the units 11 to 19 in the control unit 10 will be described with reference to FIG.

[0026] The command decoder 11 decodes a command signal input from the outside and generates an internal command. Here, the generated internal commands include, for example, a refresh request REF, active, read, write, precharge, etc. When the command decoder 11 generates (acquires) a refresh request based on a command signal input from the outside, it outputs the refresh request REF to the REF control unit 12. Note that, if the semiconductor memory device is a pSRAM, the command decoder 11 may generate (acquire) a refresh request REF and output it to the REF control unit 12, for example, every time a predetermined period has elapsed.

[0027] When a refresh request REF is input, the REF control unit 12 asserts (high level) a signal Refresh_state indicating the refresh state until a predetermined period (for example, a refresh cycle period tRFC) has elapsed since the timing at which the refresh request REF was input, and outputs the signal to the refresh counter 13 and the first multiplexer 16. The REF control unit 12 also receives as input a value counted by the refresh counter 13. Here, the REF control unit 12 asserts or negates (low level) a signal Bank_select for selecting a bank on which a refresh operation Reg ref or a row hammer refresh operation RH ref is to be performed, according to the counted value, and outputs the signal to the row decoder 19.

[0028] The refresh counter 13 is configured to count the number of times a refresh operation Reg ref is performed in response to a refresh request REF. Specifically, the refresh counter 13 increments its count value by one each time the signal Refresh_state changes from asserted to negated. The refresh counter 13 then outputs a signal indicating the count value to the REF control unit 12 and the RH control unit 14. Note that this count value may be set to circulate within a predetermined range (e.g., 0 to 3). The refresh counter 13 is an example of the "counter" of the present invention.

[0029] When the count value is input from the refresh counter 13, the RH control unit 14 outputs a signal RH_state indicating the row hammer state to the second multiplexer 18. In this embodiment, when the count value reaches a predetermined value (for example, 3), the RH control unit 14 asserts the signal RH_state and outputs it to the second multiplexer 18.

[0030] The REF address counter 15 is configured to count the row address that is the target of the refresh operation (Reg ref). For example, the REF address counter 15 may increment the value of the row address that is the target of the refresh operation (Reg ref) by a predetermined value (for example, 1) every time the refresh operation (Reg ref) is normally completed, and output this value to the first multiplexer 16. The REF address counter 15 may have a well-known configuration.

[0031] The first multiplexer 16 is configured to select, based on the signal Refresh_state, either a first row address, which is a row address included in an address signal input from the outside, or a second row address (i.e., a row address subject to the refresh operation Reg ref) input from the REF address counter 15, and output the selected row address to the second multiplexer 18. Specifically, when an asserted signal Refresh_state is input (i.e., when a refresh operation Reg ref is performed), the first multiplexer 16 selects the second row address and outputs it to the second multiplexer 18. On the other hand, when a negated signal Refresh_state is input (i.e., when a refresh operation Reg ref is not performed), the first multiplexer 16 selects the first row address and outputs it to the second multiplexer 18. The first multiplexer 16 is an example of a "first selection unit" in the present invention.

[0032] When the RH address generation unit 17 detects a frequently accessed row address (hammer address), it is configured to output a row address that is the target of the row hammer refresh operation RH ref (for example, a row address that is ±1 of the hammer address) to the second multiplexer 18. The hammer address detection method may be a well-known method.

[0033] The second multiplexer 18 is configured to select either the row address input from the first multiplexer 16 or the third row address input from the RH address generation unit 17 (i.e., the row address that is the target of the row hammer refresh operation RH_ref) based on the signal RH_state, and output the selected row address to the row decoder 19. Specifically, when an asserted signal RH_state is input (i.e., when the row hammer refresh operation RH_ref is to be performed), the second multiplexer 18 selects the third row address and outputs it to the row decoder 19. On the other hand, when a negated signal RH_state is input (i.e., when the row hammer refresh operation RH_ref is not to be performed), the second multiplexer 18 selects the row address input from the first multiplexer 16 and outputs it to the row decoder 19. The second multiplexer 18 is an example of a "second selection unit" in the present invention.

[0034] The row decoder 19 is configured to select a word line corresponding to the first row address when a first row address is input from the second multiplexer 18 (for example, when both the signal Refresh_state and the signal RH_state are invalid (negated)). Furthermore, the row decoder 19 is configured to select a plurality of (two in this embodiment) word lines WL1 and WL2 corresponding to the second row address (i.e., select a word line corresponding to a row address that is the target of a normal refresh operation) when a second row address is input from the second multiplexer 18 (for example, when the signal Refresh_state is valid (asserted) and the signal RH_state is invalid (negated)). In one embodiment, the row decoder 19 may store information (for example, table information) indicating the correspondence between the second row address and the plurality of word lines WL1 and WL2. Furthermore, the row decoder 19 is configured to select a word line corresponding to the third row address (i.e., a word line corresponding to a row address that is the target of the row hammer refresh operation RH ref) when the third row address is input from the second multiplexer 18 (for example, when both the signals Refresh_state and RH_state are valid (asserted)). Note that, although not shown in FIG. 2, in one embodiment, the row decoder 19 may be configured to receive both the signals Refresh_state and RH_state.

[0035] In particular, in this embodiment, each time the control unit 10 receives a refresh request (refresh command) REF, the row decoder 19 receives only one row address as the row address to be subjected to either the normal refresh operation (Reg ref) or the row hammer refresh operation (RH ref) based on a combination of the signal Refresh_state output from the REF control unit 12 and the signal RH_state output from the RH control unit 14, and selects a word line corresponding to the row address to be refreshed. Furthermore, in this embodiment, the address of the selected word line can be easily changed to selectively perform either the normal refresh operation or the row hammer refresh operation, eliminating the need to separately generate complex commands to adjust the normal refresh operation and the row hammer refresh operation. Furthermore, this embodiment makes it possible to avoid the problem of the refresh cycle period tRFC possibly being exceeded when a row hammer refresh operation RH ref is performed after a normal refresh operation (Reg ref) is performed in response to the refresh request (refresh command) REF (as shown in FIG. 1(b)).

[0036] An example of the operation of the control unit 10 when performing a refresh operation Reg ref and a row hammer refresh operation RH ref will be described with reference to Fig. 3. Here, Fig. 3(a) shows an example of a change in the voltage of the word line WL when two refresh operations Reg ref are performed for every four refresh requests REF in a semiconductor memory device of the prior art (i.e., when refresh operations Reg ref are performed for a total of eight row addresses A to H with four refresh requests REF). Also, Fig. 3(b) shows an example of a change in the voltage of each signal when a refresh operation Reg ref and a row hammer refresh operation RH ref are performed in this embodiment.

[0037] First, at time t1, when a refresh request REF generated (acquired) by the command decoder 11 is input to the REF control unit 12, the REF control unit 12 asserts a signal Refresh_state and outputs it to the refresh counter 13 and the first multiplexer 16. Furthermore, when the REF control unit 12 determines that the count value input from the refresh counter 13 is a value other than a first predetermined value (here, 2), it outputs two pulse signals Bank_select to the row decoder 19 to select a bank on which the refresh operation Reg ref is to be performed.

[0038] Here, the row decoder 19 receives the second row address (i.e., the row address to be subjected to the refresh operation Reg ref) output from the REF address counter 15 via the first multiplexer 16 and the second multiplexer 18. When the first high-level signal Bank_select is input, the row decoder 19 selects multiple (here, two) word lines WL1 and WL2 corresponding to the input second row address. In the example shown in FIG. 3(b), the word line WL1 corresponding to row address A and the word line WL2 corresponding to row address C are selected in response to the first high-level signal Bank_select. Then, the control unit 10 simultaneously performs the refresh operation Reg ref on row addresses A and C.

[0039] Furthermore, when the second high-level signal Bank_select is input, the row decoder 19 selects multiple (here, two) word lines WL1 and WL2 corresponding to the newly input second row address. In the example shown in FIG. 3(b), the word line WL1 corresponding to row address B and the word line WL2 corresponding to row address D are selected in response to the second high-level signal Bank_select. Then, the control unit 10 simultaneously performs a refresh operation Reg ref on row addresses B and D.

[0040] In this way, the control unit 10 can perform the refresh operation Reg ref multiple times (here, twice for each of the multiple word lines WL1 and WL2) within the refresh cycle period tRFC (predetermined period) in response to one refresh request REF.

[0041] Next, when the signal Refresh_state changes from asserted to negated at time t2, the refresh counter 13 increments its count value by 1. When a refresh request REF is input to the REF control unit 12 at time t3, the control unit 10 performs a refresh operation Reg ref on the row addresses corresponding to the selected word lines WL1 and WL2, similar to the operation at time t1. In this case, the refresh operation Reg ref is performed on row addresses E, F, G, and H between times t3 and t4.

[0042] As described above, the control unit 10 outputs multiple (two in this example) pulse signals Bank_select for selecting a memory bank for performing the normal refresh operation Reg ref in response to one refresh request REF, thereby making it possible to perform the normal refresh operation Reg ref multiple times (two in this example) within the refresh cycle period tRFC (predetermined period).

[0043] Furthermore, the control unit 10 selects multiple (two in this example) word lines in response to one refresh request REF and simultaneously performs the normal refresh operation Reg ref. Therefore, compared to the case where one word line is selected in response to one refresh request RFC and the normal refresh operation Reg ref is performed, the normal refresh operation Reg ref can be performed on twice the number of word lines (twice in this example) in the same refresh cycle period tRFC (predetermined period).

[0044] In this manner, in this embodiment, the refresh operation Reg ref can be performed on a total of eight row addresses A to H by two refresh requests REF.

[0045] Next, at time t4, when the signal Refresh_state changes from asserted to negated, the refresh counter 13 increments its count value by 1. Also, at time t5, when the refresh request REF generated (acquired) by the command decoder 11 is input to the REF control unit 12, the REF control unit 12 asserts the signal Refresh_state and outputs it to the refresh counter 13 and the first multiplexer 16. Also, when the REF control unit 12 determines that the count value input from the refresh counter 13 is a first predetermined value (here, 2) (that is, determines that the refresh operation Reg ref for the eight row addresses A to H has been completed), it does not need to output the pulse signal Bank_select to the row decoder 19 (that is, it does not need to perform the refresh operation Reg ref).

[0046] In this way, the control unit 10 can control so that the refresh operation Reg ref is not performed when a refresh request REF is acquired after the number of times the refresh operation Reg ref has been performed reaches a predetermined value (here, four times: the first refresh operation Reg ref for row addresses A and C, the second refresh operation Reg ref for row addresses B and D, the third refresh operation Reg ref for row addresses E and G, and the fourth refresh operation Reg ref for row addresses F and H).

[0047] Furthermore, the control unit 10 can control so that the refresh operation Reg ref is not performed when it acquires a refresh request REF after the refresh operation Reg ref has been performed a predetermined number of times in succession (here, four times: the first refresh operation Reg ref for row addresses A and C, the second refresh operation Reg ref for row addresses B and D, the third refresh operation Reg ref for row addresses E and G, and the fourth refresh operation Reg ref for row addresses F and H).

[0048] Next, at time t6, when the signal Refresh_state changes from asserted to negated, the refresh counter 13 increments its count value by 1. Here, when the RH control unit 14 determines that the count value input from the refresh counter 13 has reached a second predetermined value (here, 3), it asserts the signal RH_state and outputs it to the second multiplexer 18.

[0049] Furthermore, at time t7, when the refresh request REF generated (acquired) by the command decoder 11 is input to the REF control unit 12, the REF control unit 12 asserts the signal Refresh_state and outputs it to the refresh counter 13 and the first multiplexer 16. Furthermore, when the REF control unit 12 determines that the count value input from the refresh counter 13 is a value other than a first predetermined value (here, 2), it outputs two pulse signals Bank_select to the row decoder 19 to select a bank on which the row hammer refresh operation RH ref is to be performed.

[0050] Here, the row decoder 19 receives the third row address output from the RH address generation unit 17 (i.e., the row address that is the target of the row hammer refresh operation RH ref) via the second multiplexer 18. When the first high-level signal Bank_select is input, the row decoder 19 selects the word line WL1 corresponding to the input third row address (here, the row address of hammer address +1). The control unit 10 then performs the row hammer refresh operation RH ref on the row address of hammer address +1. When the second high-level signal Bank_select is input, the row decoder 19 selects the word line WL1 corresponding to the input third row address (here, the row address of hammer address -1). The control unit 10 then performs the row hammer refresh operation RH ref on the row address of hammer address -1.

[0051] In this way, the control unit 10 can perform control so that the row hammer refresh operation RH ref is performed in response to the refresh request REF.

[0052] Furthermore, in this embodiment, the control unit 10 is able to determine whether to perform the refresh operation Reg ref or the row hammer refresh operation RH ref each time it receives a refresh request REF, based on the operations of the REF control unit 12, the refresh counter 13, and the RH control unit 14.

[0053] In the example shown in FIG. 3(b), a case is described in which one row hammer refresh operation RH ref is performed within the refresh cycle period tRFC, but the row hammer refresh operation RH ref may be performed two or more times within the refresh cycle period tRFC.

[0054] 3(b) illustrates an example in which a row hammer refresh operation RH ref is performed using one word line WL1 in response to one refresh request REF. However, for example, a row hammer refresh operation RH ref may be performed using multiple word lines WL1 and WL2 in response to one refresh request REF. In this case, for example, in response to a single high-level signal Bank_select, word line WL1 corresponding to a row address of hammer address +1 may be selected, and word line WL2 corresponding to a row address of hammer address -1 may be selected. Then, row hammer refresh operations RH ref may be performed simultaneously for row addresses of hammer addresses ±1.

[0055] In this way, for four refresh requests REF, it is possible to perform the refresh operation Reg ref for eight row addresses A to H and one row hammer refresh operation RH ref within the refresh period tREF.

[0056] As described above, according to the semiconductor memory device and control method of this embodiment, refresh operations are simultaneously performed on multiple word lines (row addresses) WL1 and WL2 in response to one refresh request REF. This makes it possible to reduce the number of refresh requests REF required to perform the refresh operation (Reg ref) on all word lines, compared to when a refresh operation (Reg ref) is performed on one word line in response to one refresh request REF. In this case, for example, a row hammer refresh operation (RH ref) can be performed in response to this reduced number of refresh requests REF. This makes it possible to perform the refresh operation (Reg ref) on all row addresses and at least one row hammer refresh operation (RH ref) within the refresh period tREF. This allows the row hammer refresh operation (RH ref) to be performed without degrading the performance of the refresh operation (Reg ref).

[0057] In the above-described embodiment, a case where the refresh operation (Reg ref) is not performed between times t5 and t6 has been described as an example, but the present invention is not limited to this case. For example, the control unit 10 may perform control so that the refresh operation (Reg ref) is performed between times t5 and t6, as shown in FIG. 4. In this case, the refresh operation (Reg ref) can be performed for a total of 12 row addresses A to L using three refresh requests REF. This makes it possible to further improve the refresh rate of the refresh operation (Reg ref). Furthermore, the control unit 10 may perform control so that a row hammer refresh operation (RH ref) is performed instead of the refresh operation (Reg ref) between times t5 and t6.

[0058] In the above-described embodiment and modified examples, the control unit 10 is described as including the units 11 to 19. However, the present invention is not limited to this. For example, the control unit 10 may be configured with other circuits that provide the same effects as those of the above-described embodiment and modified examples. [Explanation of symbols]

[0059] 10...Control unit 11...Command decoder 12...REF control section 13...Refresh counter 14...RH control section 15...REF address counter 16...First multiplexer 17...RH address generation unit 18...Second multiplexer 19...Row decoder REF...Refresh request Reg ref...Refresh operation RH ref...Row hammer refresh operation tREF: Refresh period tRFC...Refresh cycle period

Claims

1. A semiconductor memory device, a control unit configured to receive a refresh command and selectively output a plurality of normal refresh addresses and a plurality of row hammer refresh addresses in response to the refresh command; The control unit a refresh controller configured to receive the refresh command and, upon receiving the refresh command, enable a refresh state signal for a predetermined period of time; a counter configured to increment a count value each time the refresh state signal changes from valid to invalid; a row hammer control unit configured to enable a row hammer refresh state signal when the count value reaches a predetermined value; The control unit outputs the plurality of normal refresh addresses when the refresh state signal is valid and the row hammer refresh state signal is invalid, and outputs the plurality of row hammer refresh addresses when the refresh state signal is valid and the row hammer refresh state signal is valid. Semiconductor memory device.

2. The count value corresponds to the number of refresh commands received by the control unit.

2. The semiconductor memory device according to claim 1.

3. the plurality of normal refresh addresses are generated by a refresh address counter; 2. The semiconductor memory device according to claim 1.

4. The plurality of row hammer refresh addresses are generated by a row hammer address generation unit.

2. The semiconductor memory device according to claim 1.

5. The count value is configured to cycle within a predetermined range.

2. The semiconductor memory device according to claim 1.

6. The control unit a first selection unit connected to an externally input row address and the normal refresh address, the first selection unit outputting the normal refresh address when the refresh state signal is valid; a second selector connected to the normal refresh address and the row hammer refresh address, the second selector outputting the row hammer refresh address when the row hammer refresh state signal is valid, and the second selector outputting the normal refresh address when the row hammer refresh state signal is invalid; 2. The semiconductor memory device according to claim 1.

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