Liquid crystal display device

Abstract

To solve the problem that power consumption required for refreshing is large in a conventional memory display type liquid crystal display device.SOLUTION: A display device includes a pixel including a first memory circuit, a second memory circuit, and a display circuit that includes a liquid crystal capacitor and is connected to the first memory circuit and the second memory circuit, a first power supply line and a second power supply line that are connected to the display circuit, a refresh circuit that reads memory data stored in the first memory circuit and writes back the memory data to the first memory circuit in accordance with a result of the reading, and a control circuit that controls the refresh circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal display device. [Background technology]

[0002] Patent Document 1 discloses a liquid crystal display device including a DRAM type memory in each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2012-93436 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional memory display type liquid crystal display devices have a problem in that they require a large amount of power for refreshing. [Means for solving the problem]

[0005] A liquid crystal display device according to one embodiment of the present disclosure includes pixels each having a first memory circuit and a second memory circuit, a display circuit including a liquid crystal capacitor and connected to the first memory circuit and the second memory circuit, a first power supply line and a second power supply line connected to the display circuit, a refresh circuit that reads memory data stored in the first memory circuit and writes it back to the first memory circuit depending on the results of the read, and a control circuit that controls the refresh circuit. [Effects of the Invention]

[0006] In a liquid crystal display device capable of displaying data in a memory, the power consumption required for refreshing is reduced. [Brief explanation of the drawings]

[0007] [Figure 1]1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram showing an example of a pixel configuration of a liquid crystal display device. [Figure 3] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 4] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 5] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 6] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 7] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 8] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 9] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 10] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 11] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 12] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 13] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 14] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 15] 4 is a timing chart showing an example of signal waveforms on first and second data lines and first and second control lines. [Figure 16] 4 is a timing chart showing an example of signal waveforms of first and second control lines. [Figure 17] FIG. 1 is a schematic diagram showing a stable state of a liquid crystal display device. [Figure 18] FIG. 2 is a schematic diagram showing a transition state 1 in a liquid crystal display device. [Figure 19]FIG. 2 is a schematic diagram showing a transition state 2 in a liquid crystal display device. [Figure 20] FIG. 10 is a schematic diagram showing a transition state 3 in a liquid crystal display device. [Figure 21] FIG. 10 is a schematic diagram showing a transition state 4 in a liquid crystal display device. [Figure 22] FIG. 1 is a schematic diagram showing a transition state 5 in a liquid crystal display device. [Figure 23] FIG. 1 is a schematic diagram showing a transition state 6 in a liquid crystal display device. [Figure 24] FIG. 2 is a schematic diagram showing a stable state Y1 in a liquid crystal display device. [Figure 25] FIG. 1 is a schematic diagram showing a transition state 7 in a liquid crystal display device. [Figure 26] FIG. 10 is a schematic diagram showing a stable state Y2 in the liquid crystal display device. [Figure 27] FIG. 10 is a schematic diagram showing a transition state 6Z in a liquid crystal display device. [Figure 28] 1 is a schematic diagram showing a stable state Z in a liquid crystal display device. [Figure 29] 1A and 1B are schematic diagrams showing the state of a liquid crystal display device during a rewriting period. [Figure 30] FIG. 10 is a schematic diagram showing a state in which rewriting of the liquid crystal display device is completed. [Figure 31] FIG. 2 is a schematic diagram showing the configuration of a refresh circuit; [Figure 32] FIG. 1 is a circuit diagram showing a conventional memory-type liquid crystal display device. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 is a block diagram showing the configuration of a liquid crystal display device according to this embodiment. FIG. 2 is a circuit diagram showing an example of a pixel configuration of a liquid crystal display device. As shown in FIGS. 1 and 2, a liquid crystal display device 10 includes a pixel PX having a first memory circuit M1, a second memory circuit M2, and a display circuit DS including a liquid crystal capacitor LC and connected to the first memory circuit M1 and the second memory circuit M2; a first power line 11 and a second power line 12 connected to the display circuit DS; a refresh circuit RE that reads memory data stored in the first memory circuit M1 and writes it back to the first memory circuit M1 based on the results of the read; and a control circuit 5 that controls the refresh circuit RE. The pixel PX(m,n) in FIGS. 1 and 2 is, for example, one pixel (a pixel in m columns and n rows) arranged in a matrix. As shown in FIG. 2, the liquid crystal display device 10 may have a display area DA in which a pixel group including the pixel PX(m,n) is provided, and a non-display area NA in which the refresh circuit RE is provided.

[0009] In the liquid crystal display device 10, the refresh circuit RE reads memory data from the first memory circuit M1 and writes it back to the first memory circuit M1, for example, at a predetermined cycle, thereby reducing the load on the control circuit 5 and reducing the power consumption required for refreshing (reading and writing back). The memory data may be binary data.

[0010] The control circuit 5 may include a timer TM, a low-frequency oscillator LO, a high-frequency oscillator HO, a timing controller TC, a low-frequency power supply circuit PF, and a high-frequency power supply circuit PS. The timing controller TC may output various signals (including video signals, control signals, and clock signals) to the first to third driver circuits D1 to D3. The power supply circuit PF may be connected to the third driver circuit D3. Refreshing may be performed by activating the high-frequency oscillator HO and the power supply circuit PS using a timer TM (low-power consumption type) that operates with a low-frequency signal from the low-frequency oscillator LO.

[0011] The refresh circuit RE may write back to the first memory circuit M1 the inverted data of the memory data read from the first memory circuit M1. If the memory data read from the first memory circuit M1 is "1 (voltage VH)", the inverted data "0 (voltage VL)" may be written back to the first memory circuit M1. If the memory data read from the first memory circuit M1 is "0 (voltage VL)", the inverted data "1 (voltage VH)" may be written back to the first memory circuit M1.

[0012] The refresh circuit RE may write back to the second memory circuit M2 the same data as the memory data read from the first memory circuit M1. If the memory data read from the first memory circuit M1 is "1 (voltage VH)", the refresh circuit RE may write back the same data "1 (voltage VH)" to the second memory circuit M2. If the memory data read from the first memory circuit M1 is "0 (voltage VL)", the refresh circuit RE may write back the same data "0 (voltage VL)" to the second memory circuit M2.

[0013] The refresh circuit RE may perform the write-back within the memory retention period of the first memory circuit M1 in response to an instruction from the control circuit 5. The memory retention period is a period depending on the characteristics of the first memory circuit M1, including the transistors and capacitance, and may be, for example, several hundred seconds.

[0014] The write-back may switch the potentials of the first power supply line 11 and the second power supply line 12. For example, if the first power supply line 11 is at potential V1 and the second power supply line 12 is at potential V2 before the write-back, the first power supply line 11 may be switched to potential V2 and the second power supply line 12 may be switched to potential V1 after the write-back.

[0015] The control circuit 5 may include a timer TM and a timing controller TC, and the timing controller TC activated by the timer TM may control the refresh circuit RE. After the write-back by the refresh circuit RE, the refresh circuit RE may be stopped, and after the write-back, the timing controller TC may be stopped.

[0016] The liquid crystal display device 10 may include a first data line Fm connected to a first memory circuit M1 and a second data line Sm connected to a second memory circuit M2. The display circuit DS may include a first transistor T1 connected to the first memory circuit M1 and a second transistor T2 connected to the second memory circuit M2, and the liquid crystal capacitance LC of the display circuit DS may include a pixel electrode PE and a counter electrode CE. The pixel electrode PE may be connected to a first power line 11 via the first transistor T1 and to a second power line 12 via the second transistor T2.

[0017] The liquid crystal display device 10 may be provided with a refresh period during which the refresh circuit RE reads and writes back data, and a hold period during which the memory data in each of the first and second memory circuits M1 and M2 is maintained. Furthermore, a rewrite period during which the memory data in each of the first and second memory circuits M1 and M2 is rewritten may be provided. The rewrite interval may include multiple refresh periods and multiple hold periods.

[0018] The liquid crystal display device 10 includes a first control line An that controls the first memory circuit M1 and a second control line Bn that controls the second memory circuit M2. During the hold period, the drive signals output to the first and second control lines An and Bn may be inverted. For example, the second control line Bn may be inverted from "L" to "H" in response to the first control line An inverting from "H" to "L." This reduces the shift in the threshold voltage of the transistors in each of the first and second memory circuits M1 and M2. The first control line An may also transition from "L" to "L" to "H" in synchronization with the transition of the first control line An from "H" to "L" to "L." This prevents the first and second control lines An and Bn from unintentionally going "H" simultaneously, causing a change in memory voltage.

[0019] The potential supplied to the counter electrode CE may be switched in association with the write-back. For example, if the potential (counter potential) supplied to the counter electrode CE before the write-back is potential V2, the counter potential may be switched to potential V1 in association with the write-back.

[0020] The refresh circuit RE may include a read circuit YC that reads memory data and a latch circuit 26 that latches the read memory data. The read circuit YC may include a comparison circuit (e.g., an amplifier circuit) and a capacitance element. The latch circuit 26 may include a D-flip-flop. During a refresh period, the refresh circuit RE may latch the memory data read from the first memory circuit M1 by the read circuit YC in the latch circuit 26 and output inverted data of the latched memory data to the first memory circuit M1.

[0021] The liquid crystal display device 10 may be provided with a first driver circuit D1 that includes a refresh circuit RE and drives the first data line Fm and the second data line Sm. The first driver circuit D1 may be stopped during a hold period in which the memory data in the first and second memory circuits M1 and M2 are maintained.

[0022] The liquid crystal display device 10 may be provided with a second driver circuit D2 that drives the first control line An and the second control line Bn, and a third driver circuit D3 that drives the first power supply line 11 and the second power supply line 12. The third driver circuit D3 may drive the counter electrode CE of the liquid crystal capacitor LC.

[0023] The refresh circuit RE may read the memory data stored in the second memory circuit M2, and if the memory data stored in the first and second memory circuits M1 and M2 are not in an inverted relationship, may notify the timing controller TC. Upon receiving the notification, the timing controller TC may write the original data (most recently rewritten data) to the first and second memory circuits M1 and M2.

[0024] 1 and 2, the first memory circuit M1 may include a first capacitor C1 and a third transistor T3 and a fourth transistor T4, and the second memory circuit M2 may include a second capacitor C2 and a fifth transistor T5 and a sixth transistor T6. The gate terminals of the third and fifth transistors T3 and T5 may be connected to a first control line An, and the gate terminals of the fourth and sixth transistors T4 and T6 may be connected to a second control line Bn.

[0025] The first data line Fm may be connected to the gate terminal of the first transistor T1 via the third and fourth transistors T3 and T4, and the second data line Sm may be connected to the gate terminal of the second transistor T2 via the fifth and sixth transistors T and T6. The gate terminal of the first transistor T1 may be connected to the first capacitor C1, and the gate terminal of the second transistor T2 may be connected to the second capacitor C2.

[0026] According to the liquid crystal display device 10, the first transistor T1 is controlled by the voltage held by the first memory circuit M1, and the second transistor T2 is controlled by the voltage (memory voltage) held by the second memory circuit M2, so that a display voltage can be written to the pixel electrode PE from the first power line 11 or the second power line 12. This makes it possible to reduce the refresh frequency (lengthen the refresh interval) while maintaining the quality of the memory display (for example, low flicker).

[0027] In the conventional technology disclosed in Patent Document 1 (Figure 32) (a memory-type liquid crystal pixel 98 connected to a refresh line 82, a data line 89, a gate line 88, a sampling line 83, and a CS line 84, and including a sampling capacitor 93, a storage capacitor 92, and a liquid crystal capacitor 96), the storage capacitor 92 and the liquid crystal capacitor 96 are connected in parallel, and the voltage of the storage capacitor 92 and the voltage of the liquid crystal capacitor 96 are maintained in the same configuration, resulting in a large change in brightness during refreshing and easy-to-see flicker.

[0028] On the other hand, in the present liquid crystal display device 10, the memory voltages (e.g., binary data) of the first and second memory circuits M1 and M2 and the voltage of the liquid crystal capacitance LC are held in separate configurations, so there is little change in brightness during refreshing and flicker is less visible.

[0029] During the hold period (display period), one of the first and second transistors T1 and T2 may be turned ON and the other OFF, thereby supplying the pixel electrode PE with a first potential V1 or a second potential V2 lower than the first potential V1.

[0030] The pixel PX may display two values, black and white. The black display means black display in the pixel PX. The white display may mean primary color display in the pixel PX (for example, red, green, or blue) or white display in the pixel PX. When primary colors are displayed in the pixel PX, eight colors can be displayed.

[0031] In the liquid crystal display device 10, during the write period, the first and second control lines An and Bn are set to an active potential and the third to sixth transistors T3 to T6 are turned on, thereby writing one of a positive logic voltage (e.g., VH) and a negative logic voltage (e.g., VL) from the first data line Fm to the first capacitor C1, and writing the other of the positive logic voltage (e.g., VH) and the negative logic voltage (e.g., VL) from the second data line Sm to the second capacitor C2. The write period refers to a period during which the potential of the output U1 of the first memory circuit M1 and the potential of the output U2 of the second memory circuit M2 are refreshed (no change in frame data) or rewritten (change in frame data).

[0032] When the pixel PX is of a normally black type, it may display white gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the second potential V2, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the first potential V1, and may display black gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the first potential V1, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the second potential V2.

[0033] When the pixel PX is of a normally white type, it may display white gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the first potential V1, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the second potential V2, and may display black gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the second potential V2, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the first potential V1.

[0034] The first and second transistors T1 and T2 may have the same type of channel, and a positive logic potential may be stored in the first memory circuit M1 and a negative logic potential may be stored in the second memory circuit M2, thereby turning the first transistor T1 ON and the second transistor T2 OFF, and a negative logic potential may be stored in the first memory circuit M1 and a positive logic potential may be stored in the second memory circuit M2, thereby turning the first transistor T1 OFF and the second transistor T2 ON.

[0035] When the first and second transistors T1 and T2 have N-type channels, the positive logic potential may be VH (high-side memory potential) and the negative logic potential may be VL (low-side memory potential), and when the first and second transistors T1 and T2 have P-type channels, the positive logic potential may be VL (low-side memory potential) and the negative logic potential may be VH (high-side memory potential).

[0036] In the pixel PX, the first and second transistors T1 and T2 may be alternately turned on during the display period of the white gradation. This prevents the first and second transistors T1 and T2 from changing in characteristics (shifting in the IV characteristics) that may occur when the transistors are turned on for a long period of time. As the first and second transistors T1 and T2 are alternately turned on, the potentials (power supply potentials) of the first and second power lines 11 and 12 may be swapped, or the potential of the counter electrode CE may be swapped.

[0037] 3 to 5 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 3 to 5, a display period for white gradation in a normally black mode includes a first hold period during which the first transistor T1 is turned ON (T2 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the first power supply line 11, and a second potential V2 is supplied to the counter electrode CE, and a second hold period during which the second transistor is turned ON (T1 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the second power supply line 12, and a second potential V2 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0038] 6 to 8 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 6 to 8, a display period for white gradation in a normally black mode includes a first hold period during which the first transistor T1 is turned ON (T2 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the first power supply line 11, and a second potential V2 is supplied to the counter electrode CE, and a second hold period during which the second transistor T2 is turned ON (T1 is OFF) and a second potential V2 is supplied to the pixel electrode PE from the second power supply line 12, and the first potential V1 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0039] In the pixel PX, the first and second transistors T1 and T2 may be alternately turned on during a period in which a black gradation is displayed. This prevents the first and second transistors T1 and T2 from changing in characteristics (shifting in the IV characteristics) that may occur when the transistors are turned on and off for a long period of time. As the first and second transistors T1 and T2 are alternately turned on, the potentials of the first and second power supply lines 11 and 12 (power supply potentials) may be switched, or the potential of the counter electrode CE may be switched.

[0040] 9 to 11 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 9 to 11, a display period for black gradation in a normally black mode includes a first hold period during which the second transistor T2 is turned ON (T1 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the second power supply line 12 and the second potential V2 is supplied to the counter electrode CE, and a second hold period during which the first transistor T1 is turned ON (T2 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the first power supply line 11 and the second potential V2 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0041] 12 to 14 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 12 to 14, a display period for black gradation in a normally black mode includes a first hold period during which the second transistor T2 is turned ON (T1 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the second power supply line 12 and the second potential V2 is supplied to the counter electrode CE, and a second hold period during which the first transistor T1 is turned ON (T2 is OFF) and the first potential V1 is supplied to the pixel electrode PE from the first power supply line 11 and the first potential V1 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0042] 15 is a timing chart showing an example of signal waveforms of the first and second data lines and the first and second control lines. As shown in FIG. 15, a period may be included in which the first transistor T1 is ON (U1 is VH) and the second transistor T2 is OFF (U2 is VL), followed by a period in which the first and second transistors T1 and T2 are both OFF (U1 and U2 are VL), and then a period in which the first transistor T1 is OFF (U1 is VL) and the second transistor T2 is ON (U2 is VH). By providing a period TM (U1 and U2 are VL) in which both transistors are simultaneously OFF before each of the first and second transistors T1 and T2 transitions between their states, it is possible to avoid a short circuit between the first and second power supply lines 11 and 12, which would otherwise occur if the first and second transistors T1 and T2 were both ON.

[0043] 16 is a timing chart showing an example of signal waveforms of the first and second control lines. In the liquid crystal display device 10, during the hold period (the period during which the outputs U1 and U2 of the first and second memory circuits M1 and M2 are maintained), one of the first and second control lines An and Bn may be at an active potential and the other at an inactive potential. This allows the third and fifth transistors T3 and T5 to be turned ON (T4 and T6 to be turned OFF) and the fourth and sixth transistors T4 and T6 to be turned ON (T3 and T5 to be turned OFF) while maintaining the potential (memory potential) of the output node U1 of the first memory circuit M1 and the potential (memory potential) of the output node U2 of the second memory circuit M2. As a result, characteristic changes (shifts in the IV characteristics) that may occur when the third through sixth transistors T3 through T6 are turned ON or OFF for a long period of time can be reduced.

[0044] During the hold period, the first and second control lines An and Bn may alternately be at the active potential, which allows the third to sixth transistors T3 to T6 to be periodically turned on and off, thereby more effectively reducing changes in the characteristics of each transistor.

[0045] As shown in FIG. 16, during the hold period, in order to prevent the third to sixth transistors from being turned ON simultaneously, it is desirable to shift the timing of the pulse shift (e.g., fall) of the first control line An from the timing of the potential shift (e.g., rise) of the pulse of the second control line Bn.

[0046] In the liquid crystal display device 10, the first to sixth transistors T1 to T6 may have channels of the same type, and the first to sixth transistors T1 to T6 may have a channel containing an oxide semiconductor. At least one of the first to sixth transistors T1 to T6 may have an N-type channel containing an oxide semiconductor. The oxide semiconductor may be indium gallium zinc oxide.

[0047] In the liquid crystal display device 10, a pixel row PL consisting of a plurality of pixels PX arranged in the row direction may share the first and second power supply lines 11 and 12, and may share the counter electrode CE. Alternatively, the pixel row PL may share the first and second power supply lines 11 and 12 and the counter electrode CE.

[0048] The liquid crystal display device 10 is suitable for so-called digital signage. In signage displays, sample-and-hold transistors may remain OFF for long periods of time, potentially changing the transistor characteristics. However, the liquid crystal display device 10 can periodically transition the states (ON → OFF, OFF → ON) of not only the first and second transistors T1 and T2 but also the third to sixth transistors T3 to T6 while maintaining the display state (memory display), thereby reducing the risk of changes in the transistor characteristics.

[0049] For example, in the case of a transistor with an N-type channel, if the OFF period (gate voltage = OFF voltage) continues for a long period of time, the VI characteristics shift to the low-voltage side, and eventually, even if the gate voltage is the OFF voltage, the current flows, and the transistor no longer functions as a current control element. Conversely, if the ON period (gate voltage = ON voltage) continues for a long period of time, the VI characteristics shift to the high-voltage side, and eventually, even if the gate voltage is the ON voltage, the current decreases, and the transistor no longer functions as a current control element. This tendency for characteristic changes is also observed in transistors whose channels are oxide semiconductors. Therefore, as in the liquid crystal display device 10, by periodically switching the gate potential of not only the first and second transistors T1 and T2 but also the third to sixth transistors T3 to T6 between the OFF voltage and the ON voltage, the VI characteristics are fixed and the transistors can function properly as current control elements. This allows for reduced power consumption while maintaining the quality of the memory display, such as low flicker.

[0050] In this way, the liquid crystal display device 10 can display still images (memory display) for a long period of time with low power consumption and high quality, but can also display moving images by increasing the writing frequency.

[0051] FIG. 17 is a schematic diagram showing a stable state of a liquid crystal display device. FIGS. 18 to 23 are schematic diagrams showing transition states. FIG. 24 is a schematic diagram showing a stable state of a liquid crystal display device. As shown in FIGS. 17 to 24, the first driver circuit D1 includes a shift register SR, a D flip-flop 25, and a refresh circuit RE. A signal S31 is input to the shift register SR, and the output of the shift register SR is input to the CK terminal of the D flip-flop 25. A signal S32 is input to the D terminal of the D flip-flop 25. The refresh circuit RE includes a D flip-flop 26, AND circuits 13 and 14, switch circuits (selection circuits) J1 to J4, amplifier circuits 71 and 72, and a capacitance element CL.

[0052] The amplifier circuits 71 and 72, the capacitance element CL, and the switch circuit J2 constitute a read circuit. The switch circuits J1 and J2 are controlled by a signal S34, and the switch circuits J3 and J4 are controlled by a signal S36. The CK terminal of the D flip-flop 26 receives a signal S33.

[0053] In the refresh circuit RE, the first input terminals of amplifier circuits 71 and 72 are connected to each other via a capacitance element CL, and a switch circuit J2 is arranged in parallel with the capacitance element CL. The second input of amplifier circuit 71 is a reference potential Vt, and the second input of amplifier circuit 72 is a reference potential Vr. The switch circuit J1 selectively connects the D terminal of D flip-flop 26 to the Q terminal of D flip-flop 25 or the output terminal of amplifier circuit 71. The first input of AND circuit 13 is the xQ signal of D flip-flop 26, the first input of AND circuit 14 is the Q signal of D flip-flop 26, and the second input of each of AND circuits 13 and 14 is signal S35. The switch circuit J3 selectively connects the first data line Fm to the output terminal of AND circuit 14 or the first input terminal of amplifier circuit 72. The switch circuit J4 connects or disconnects the second data line Sm from the output terminal of AND circuit 14.

[0054] The second driver circuit D2 includes a D flip-flop 29, AND circuits 18, 23, and 24, a NAND circuit 19, and OR circuits 21 and 22. A signal S51 is input to the CK terminal of the D flip-flop 29. The first input of the AND circuit 18 is the Q signal of the D flip-flop 29, the first input of the NAND circuit 19 is the inverted signal of the xQ signal of the D flip-flop 29, and the second inputs of the AND circuit 18 and the NAND circuit 19 are signal S52. A first input of the OR circuit 21 is the output of the AND circuit 18, a first input of the OR circuit 22 is the inverted output of the AND circuit 19, a second input of the OR circuit 21 is the signal S53, and a second input of the OR circuit 22 is the inverted signal of the signal S53. A first input of the AND circuit 23 is the output of the OR circuit 21, a first input of the AND circuit 24 is the output of the OR circuit 22, and a second input of each of the AND circuits 23 and 24 is the signal S54.

[0055] The third driver circuit D3 includes switch circuits J10 to J16, D flip-flops 27 and 28, an XNOR circuit 15, AND circuits 16 and 17, a first voltage source (V1 source), and a second voltage source (V2 source). Signals S41 and S42 are input to the XNOR circuit 15. The switch circuits J10 and J12 are controlled by the signal S42. The first input of the XNOR circuit 15 is the signal S41, the second input is the signal S42, and the switch circuit J11 is controlled by the output of the XNOR circuit 15. The switch circuits J13 and J16 are controlled by the output of the AND circuit 16. The switch circuits J14 and J15 are controlled by the output of the AND circuit 17. A signal S44 is input to the CK terminal of the D flip-flop 27. A signal S45 is input to the D terminal of the D flip-flop 28, and a signal S46 is input to the CK terminal of the D flip-flop 28. The first input of the AND circuits 16 and 17 is the xQ signal of the D flip-flop 27, the second input of the AND circuit 16 is the Q signal of the D flip-flop 28, and the second input of the AND circuit 17 is the xQ signal of the D flip-flop 28.

[0056] The switch circuit J10 selectively connects the counter electrode CE to a first voltage source (V1 source) or a second voltage source (V2 source). The first power supply line 11 is connected to the first voltage source (V1 source) via switch circuits J11 and J14, and is connected to the second voltage source (V2 source) via switch circuits J12 and J13. The second power supply line 12 is connected to the first voltage source (V1 source) via switch circuits J11 and J16, and is connected to the second voltage source (V2 source) via switch circuits J12 and J15.

[0057] 17 shows the stable state X (FIG. 3), in which the first driver circuit D1 (including the refresh circuit RE) is stopped, the first and second data lines Fm and Sm are in the floating state FZ (high impedance state), the first memory circuit M1 (T3, T4, C1) stores "1 (voltage VH)," the second memory circuit M2 (T5, T6, C2) stores "0 (voltage VL)," the first transistor T1 is ON, and the second transistor T2 is OFF.

[0058] The second driver circuit D2 sets the first control line An to "H (High)" and the second control line Bn to "L (Low)," turning the third and fifth transistors T3 and T5 ON and the fourth and sixth transistors T4 and T6 OFF. In the third driver circuit D3, the switch circuit J11 is connected to the first voltage source (V1 source) and the switch circuit J12 is connected to the second voltage source (V2 source). Furthermore, the switch circuits J14 and J15 are turned ON and the switch circuits J13 and J16 are turned OFF, setting (driving) the first power supply line 11 to V1, the second power supply line 12 to V2, and the counter electrode CE to V2. As a result, the potential of the pixel electrode PE is maintained at V1, and the liquid crystal capacitor LC displays white.

[0059] FIG. 18 is a schematic diagram showing transition state 1. In FIG. 18, the first driver circuit D1 (including the refresh circuit RE) is activated, the switch circuit J1 connects the D terminal of the D flip-flop 26 to the Q terminal of the D flip-flop 25, the switch circuit J2 is turned ON, and the switch circuit J3 connects the first data line Fm to the first input terminal of the amplifier circuit 72. The first data line Fm is precharged to the reference potential Vr. In the second driver, the Q signal of the D flip-flop 29 becomes active, but the signal 52 (strobe signal) is inactive, so the potential states of the first and second control lines An and Bn do not change. In the third driver, the outputs (Q signal and xQ signal) of the D flip-flop 27 become active, and the switch circuits J14 and J15 are turned OFF. As a result, the first and second power supply lines 11 and 12 enter a floating state FZ (high impedance state).

[0060] 19 is a schematic diagram showing transition state 2. In FIG. 19, the switch circuit J1 connects the D terminal of the D flip-flop 26 to the output terminal of the amplifier circuit 71, and the switch circuit J2 is turned OFF. In the third driver, the outputs (Q signal and xQ signal) of the D flip-flop 28 are made active. This completes preparations for reading.

[0061] FIG. 20 is a schematic diagram showing transition state 3. In FIG. 20, signal 52 (strobe signal) becomes active, the first and second control lines An and Bn both become "H," and the third to sixth transistors T3 to T6 are turned ON. As a result, memory data "1 (voltage VH)" in the first memory circuit M1 is read out to the refresh circuit RE via transistors T3 and T4, the first data line Fm, and the switch circuit J13. That is, after the charge in the first capacitor C1 is converted into an IV signal, the amplifier circuit 71 determines whether it is "0" or "1," and the result is latched in the D flip-flop 26 (latch circuit).

[0062] FIG. 21 is a schematic diagram showing transition state 4. In FIG. 21, the switch circuit J1 connects the D terminal of the D flip-flop 26 to the Q terminal of the D flip-flop 25, the switch circuit J3 connects the first data line Fm to the output terminal of the AND circuit 13, and the switch circuit J4 connects the second data line Sm to the output terminal of the AND circuit 14. As a result, the inverted data "0" of the latch data "1" of the D flip-flop 26 is written back to the first memory circuit M1 (first capacitor C1) via the switch circuit J3, the first data line Fm, and the transistors T3 and T4, and the same data "1" of the latch data "1" of the D flip-flop 26 is written back to the second memory circuit M2 (first capacitor C2) via the switch circuit J4, the second data line Sm, and the transistors T5 and T6. As a result, the first transistor T1 is turned OFF and the second transistor T2 is turned ON.

[0063] FIG. 22 is a schematic diagram showing transition state 5. In FIG. 22, the switch circuit J3 connects the first data line Fm to the first input terminal of the amplifier circuit 72, and the switch circuit J4 is turned OFF. In the second driver D2, the second control line Bn goes to "L," and the fourth and sixth transistors T4 and T6 are turned OFF. This inhibits reading and writing back of the pixel PX(m,n).

[0064] 23 is a schematic diagram showing transition state 6. In FIG. 23, the outputs (Q signal and xQ signal) of the D flip-flop 27 become inactive, and the switch circuits J13 and J16 are turned ON. As a result, the first power supply line 11 is charged to V2, and the second power supply line 12 is charged to V1, completing the refresh of pixel PX(m,n).

[0065] Figure 24 is a schematic diagram showing a stable state Y1. In Figure 24, the first driver circuit D1 (including the refresh circuit RE) is stopped, and the first and second data lines Fm and Sm are in a floating state FZ (high impedance state). The first memory circuit M1 (T3, T4, and C1) stores "0 (voltage VH)," the second memory circuit M2 (T5, T6, and C2) stores "1 (voltage VL)," the first transistor T1 is OFF, and the second transistor T2 is ON.

[0066] The second driver circuit D2 sets the first control line An to "H (High)" and the second control line Bn to "L (Low)," turning the third and fifth transistors T3 and T5 ON and the fourth and sixth transistors T4 and T6 OFF. In the third driver circuit D3, the switch circuit J11 is connected to the first voltage source (V1 source) and the switch circuit J12 is connected to the second voltage source (V2 source). Furthermore, the switch circuits J14 and J15 are turned OFF and the switch circuits J13 and J16 are turned ON, setting (driving) the first power supply line 11 to V2, the second power supply line 12 to V1, and the counter electrode CE to V2. As a result, the potential of the pixel electrode PE is maintained at V1, and the liquid crystal capacitor LC displays white.

[0067] 25 is a schematic diagram showing a transition state 7 after the stable state Y1. In FIG. 25, the first driver circuit D1 (including the refresh circuit RE) is stopped, and the first and second data lines Fm and Sm are in a floating state FZ (high impedance state). The second driver circuit D2 sets both the first control line An and the second control line Bn to "L (Low)," and the third to sixth transistors T3 to T6 are turned off.

[0068] FIG. 26 is a schematic diagram showing a stable state Y2 after transition state 7. In FIG. 26, the first driver circuit D1 (including the refresh circuit RE) is stopped, and the first and second data lines Fm and Sm are in a floating state FZ (high impedance state). The second driver circuit D2 sets the first control line An to "L" and the second control line Bn to "H," turning on the fourth and sixth transistors T4 and T6. By transitioning from the stable state Y1 to the stable state Y2, it is possible to reduce the threshold voltage shift of the third to sixth transistors T3 to T6.

[0069] FIG. 27 is a schematic diagram showing a transition state 6Z after transition state 5 (FIG. 22). FIG. 28 is a schematic diagram showing a stable state Z after transition state 6Z. In FIGS. 27 and 28, switch circuit J11 is connected to the second voltage source (V2 source), switch circuit J12 is connected to the first voltage source (V1 source), switch circuits J13 and J16 are ON, switch circuits J14 and J15 are OFF, and the first power supply line 11 is set (driven) to V1, the second power supply line 12 is set to V2, and the counter electrode CE is set (driven) to V2. As a result, the potential of the pixel electrode PE is maintained at V1, and the liquid crystal capacitor LC displays white. By achieving stable state Z, burn-in of the liquid crystal layer of the liquid crystal capacitor LC (caused by application of a DC voltage to the liquid crystal layer) can be avoided, improving the reliability of the display device.

[0070] The intervals between the transition from stable state X to stable state Y1, the transition from stable state Y1 to stable state Y2, and the transition from stable state X to stable state Z can be individually set according to the characteristics of the first and second memory circuits M1 and M2 (T3 to T6, C1 and C2), the display circuit DS (T1 and T2, LC), etc.

[0071] FIG. 29 is a schematic diagram showing the state during the rewrite period. FIG. 30 is a schematic diagram showing the state after rewrite is completed. As shown in FIGS. 29 and 30, by starting the first driver circuit D1 (including the refresh circuit RE) and setting both the first control line An and the second control line Bn to "H (High)" by the second driver circuit D2, a signal S32, which is video data, can be written to the first and second memory circuits M1 and M2 via D flip-flops 25 and 26, switch circuits J3 and J4, the first and second data lines Fm and Sm, and the third through sixth transistors T3 and T6. That is, "0 (VL)" is written to the first memory circuit M1 and "1 (VH)" is written to the second memory circuit M2, turning the first transistor T1 OFF and the second transistor T2 ON.

[0072] 29 and 30, the switch circuit J11 is connected to the first voltage source (V1 source), the switch circuit J12 is connected to the second voltage source (V2 source), and further, the switch circuits J13 and J16 are turned OFF and the switch circuits J14 and J15 are turned ON, so that the first power supply line 11 is set (driven) to V1, the second power supply line 12 is set to V2, and the counter electrode CE is set to V2. As a result, the potential of the pixel electrode PE is maintained at V2, and the liquid crystal capacitor LC displays black.

[0073] FIG. 31 is a schematic diagram showing the configuration of a refresh circuit. In FIG. 31, the refresh circuit RE includes a read circuit (amplifier circuits 73 and 74, capacitor CL, and switch circuit J22) connected to switch circuit J4, and an XNOR circuit 77 to which the outputs of amplifier circuits 71 and 74 are input. This allows the refresh circuit RE to read the memory data of the first and second memory circuits M1 and M2, and if the data are not inverted, notify the timing controller TC (FIG. 1) (by output ER of XNOR circuit 77). Upon receiving the notification, the timing controller TC may write the original data (the most recently rewritten data) to the first and second memory circuits M1 and M2.

[0074] The above-described embodiment is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, it will be apparent to those skilled in the art that many modifications are possible. The gist of this embodiment will be described below. "Above" in the following description includes the configurations disclosed in FIGS. 1 to 30.

[0075] a pixel having a first memory circuit, a second memory circuit, and a display circuit including a liquid crystal capacitor and connected to the first memory circuit and the second memory circuit; a first power line and a second power line connected to the display circuit; a refresh circuit that reads memory data stored in the first memory circuit and writes back to the first memory circuit according to the result of the read; a control circuit for controlling the refresh circuit.

[0076] The liquid crystal display device described above, wherein the refresh circuit writes back to the first memory circuit inverted data of the memory data read from the first memory circuit.

[0077] The liquid crystal display device described above, wherein the refresh circuit writes back to the second memory circuit the same data as the memory data read from the first memory circuit.

[0078] The liquid crystal display device described above, wherein the potentials of the first power supply line and the second power supply line are switched in association with the write-back.

[0079] The liquid crystal display device described above, wherein the refresh circuit performs the write-back within a storage retention period of the first memory circuit in response to an instruction from the control circuit.

[0080] the control circuit includes a timer and a timing controller; The liquid crystal display device described above, wherein a timing controller activated by the timer controls the refresh circuit.

[0081] The liquid crystal display device as described above, wherein the refresh circuit is stopped after the write-back.

[0082] The liquid crystal display device described above, wherein the timing controller stops after the write-back.

[0083] In the liquid crystal display device described above, the refresh circuit includes a read circuit that reads out memory data and a latch circuit that latches the read memory data.

[0084] a first data line connected to the first memory circuit and a second data line connected to the second memory circuit; the display circuit includes a first transistor connected to the first memory circuit and a second transistor connected to the second memory circuit; the liquid crystal capacitor includes a pixel electrode and a counter electrode; The liquid crystal display device described above, wherein the pixel electrode is connected to the first power supply line via the first transistor and is connected to the second power supply line via the second transistor.

[0085] The liquid crystal display device as described above, including a refresh period in which the reading and the writing back are performed, and a hold period in which the memory data of the first memory circuit and the second memory circuit are maintained.

[0086] a first control line for controlling the first memory circuit and a second control line for controlling the second memory circuit; The above liquid crystal display device, wherein the drive signals output to the first and second control lines are inverted during the hold period.

[0087] The liquid crystal display device described above, wherein the potentials supplied to the counter electrodes are switched in association with the write-back.

[0088] The liquid crystal display device described above, wherein the refresh circuit latches the memory data read from the first memory circuit during the refresh period, and outputs inverted data of the latched memory data to the first memory circuit.

[0089] The above-mentioned liquid crystal display device further comprises a first driver circuit including the refresh circuit and driving the first data lines and the second data lines.

[0090] The above-mentioned liquid crystal display device, wherein the first driver circuit is stopped during the hold period.

[0091] a second driver circuit that drives the first control line and the second control line; the liquid crystal display device described above, further comprising a third driver circuit that drives the first power supply line and the second power supply line.

[0092] The liquid crystal display device described above, wherein the third driver circuit drives the counter electrode.

[0093] The liquid crystal display device as described above, further comprising a rewrite period for rewriting memory data in the first memory circuit and the second memory circuit.

[0094] the refresh circuit reads out the memory data stored in the second memory circuit; The liquid crystal display device as described above, wherein when the memory data stored in the first and second memory circuits are not in an inverted relationship, a notification is given to the timing controller.

[0095] The timing controller that has received the notification writes the original data into the first and second memory circuits.

[0096] the first memory circuit includes a first capacitor, a third transistor, and a fourth transistor; the second memory circuit includes a second capacitor, a fifth transistor, and a sixth transistor; the gate terminals of the third and fifth transistors are connected to the first control line; the gate terminals of the fourth and sixth transistors are connected to the second control line; the first data line is connected to a gate terminal of the first transistor via the third and fourth transistors; the second data line is connected to the gate terminal of the second transistor via the fifth and sixth transistors; a gate terminal of the first transistor is connected to the first capacitor; The liquid crystal display device described above, wherein the gate terminal of the second transistor is connected to the second capacitor.

[0097] The liquid crystal display device described above has a display area in which a pixel group including the pixel is provided, and a non-display area in which the refresh circuit is provided. [Explanation of symbols]

[0098] 10 LCD display device 11 1st power line 12 2nd power line M1 First memory circuit M2 Second memory circuit T1 First transistor T2 Second transistor T3 Third transistor T4 Fourth transistor T5 Fifth transistor T6 6th transistor PX pixels PE pixel electrode LC liquid crystal capacity CE counter electrode

Claims

1. a pixel having a first memory circuit, a second memory circuit, and a display circuit including a liquid crystal capacitor and connected to the first memory circuit and the second memory circuit; a first power supply line and a second power supply line connected to the display circuit; a refresh circuit that reads memory data stored in the first memory circuit and writes back the memory data to the first memory circuit according to the results of the read; a control circuit for controlling the refresh circuit.

2. 2. The liquid crystal display device according to claim 1, wherein said refresh circuit writes back to said first memory circuit inverted data of memory data read from said first memory circuit.

3. 3. The liquid crystal display device according to claim 2, wherein said refresh circuit writes back to said second memory circuit the same data as the memory data read from said first memory circuit.

4. The liquid crystal display device according to claim 1 , wherein the potentials of the first power supply line and the second power supply line are switched in association with the write-back.

5. 2. The liquid crystal display device according to claim 1, wherein the refresh circuit performs the write-back within a storage retention period of the first memory circuit in response to an instruction from the control circuit.

6. the control circuit includes a timer and a timing controller; 2. The liquid crystal display device according to claim 1, wherein a timing controller activated by the timer controls the refresh circuit.

7. 2. The liquid crystal display device according to claim 1, wherein the refresh circuit is stopped after the write-back.

8. The liquid crystal display device according to claim 6 , wherein the timing controller stops after the write-back.

9. 2. The liquid crystal display device according to claim 1, wherein said refresh circuit includes a read circuit for reading memory data and a latch circuit for latching the read memory data.

10. a first data line connected to the first memory circuit and a second data line connected to the second memory circuit; the display circuit includes a first transistor connected to the first memory circuit and a second transistor connected to the second memory circuit; the liquid crystal capacitor includes a pixel electrode and a counter electrode; 10. The liquid crystal display device according to claim 1, wherein the pixel electrode is connected to the first power supply line via the first transistor and to the second power supply line via the second transistor.

11. 11. The liquid crystal display device according to claim 10, further comprising: a refresh period during which the reading and the writing back are performed; and a hold period during which memory data in each of the first memory circuit and the second memory circuit is maintained.

12. a first control line for controlling the first memory circuit and a second control line for controlling the second memory circuit; The liquid crystal display device according to claim 11 , wherein the drive signals output to the first and second control lines are inverted during the hold period.

13. The liquid crystal display device according to claim 10 , wherein the potentials supplied to the counter electrodes are switched in association with the write-back.

14. 12. The liquid crystal display device according to claim 11, wherein the refresh circuit latches the memory data read from the first memory circuit during the refresh period, and outputs inverted data of the latched memory data to the first memory circuit.

15. 12. The liquid crystal display device according to claim 11, further comprising a first driver circuit including the refresh circuit and driving the first data lines and the second data lines.

16. The liquid crystal display device according to claim 15 , wherein the first driver circuit is stopped during the hold period.

17. a second driver circuit that drives the first control line and the second control line; 13. The liquid crystal display device according to claim 12, further comprising: a third driver circuit that drives the first power supply line and the second power supply line.

18. 18. The liquid crystal display device according to claim 17, wherein the third driver circuit drives the counter electrode.

19. 13. The liquid crystal display device according to claim 12, further comprising a rewrite period for rewriting memory data in each of the first memory circuit and the second memory circuit.

20. The refresh circuit reads out the memory data stored in the second memory circuit, 7. The liquid crystal display device according to claim 6, wherein when the memory data stored in said first and second memory circuits are not in an inverted relationship, a notification is given to said timing controller.

21. 20. The liquid crystal display device according to claim 19, wherein the timing controller, upon receiving the notification, writes the original data into the first and second memory circuits.

22. the first memory circuit includes a first capacitor, a third transistor, and a fourth transistor; the second memory circuit includes a second capacitor, a fifth transistor, and a sixth transistor; the gate terminals of the third and fifth transistors are connected to the first control line; the gate terminals of the fourth and sixth transistors are connected to the second control line; the first data line is connected to a gate terminal of the first transistor via the third and fourth transistors; the second data line is connected to a gate terminal of the second transistor via the fifth and sixth transistors; a gate terminal of the first transistor is connected to the first capacitor; The liquid crystal display device according to claim 10 , wherein a gate terminal of the second transistor is connected to the second capacitor.

23. 2. The liquid crystal display device according to claim 1, further comprising: a display area in which a pixel group including said pixel is provided; and a non-display area in which said refresh circuit is provided.

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