Processor and operation control method of processor

Abstract

To suppress a reduction in an operating voltage margin of a processor by suppressing the occurrence of a gradient in a power supply voltage in an internal circuit.SOLUTION: The processor includes a plurality of power supply switch circuits that are distributed in an internal circuit and supply a power supply voltage to the internal circuit, and first and second control circuits. The first control circuit compares a power supply voltage at a detection position in the internal circuit with a target voltage and controls the plurality of power supply switch circuits to bring the power supply voltage in the internal circuit closer to the target voltage. The second control circuit increases the power supply capability of the power supply switch circuit near the deficient region compared to the power supply capability of the power supply switch circuit away from the deficient region when there is a deficient region of the power supply capability in the internal circuit. Accordingly, it is possible to suppress the occurrence of a gradient in the power supply voltage in the internal circuit, and to suppress a decrease in the operating voltage margin of the processor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processor and a method for controlling the operation of a processor. [Background technology]

[0002] A known technique is to independently adjust the power supply voltages supplied to multiple cores included in a processor using a power switch circuit provided for each core. This type of power switch circuit has multiple p-channel metal oxide semiconductor (pMOS) transistors arranged between an external power line and the power line of each core. A power control circuit that controls the power switch circuit compares the power supply voltage measured within the core with a target voltage and generates a digital control signal with a bit value to be output to the gate of each pMOS transistor. Then, by applying the bit value of the digital control signal to the gate of each pMOS transistor in the power switch circuit, the power supply voltage measured at one location within the core can be made to approach the target voltage (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-019152 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, by placing multiple power switch circuits in a core, it is possible to prevent a power supply voltage gradient from occurring within the core. However, in processor layout design, power switch circuits may be placed in an empty area after circuits such as arithmetic units have been laid out. As a result, the multiple power switch circuits placed within the core may not be evenly distributed. In this case, the power supply voltage in areas within the core that are far from the power switch circuits may be lower than the target voltage, resulting in a power supply voltage gradient within the core.

[0005] Furthermore, a core may contain multiple circuits with different current consumptions. In this case, even if multiple power switch circuits are evenly distributed within the core, the power supply voltage in the area where the circuit with the larger current consumption is mounted will be lower than the target voltage, resulting in a power supply voltage gradient within the core.

[0006] In one aspect, the present invention aims to suppress a decrease in the operating voltage margin of a processor by suppressing the occurrence of a gradient in the power supply voltage within an internal circuit. [Means for solving the problem]

[0007] According to one aspect, a processor has an internal circuit, a plurality of power switch circuits that are distributed within the internal circuit and supply a power supply voltage to each of the internal circuits, a first control circuit that controls the plurality of power switch circuits based on a comparison result between a power supply voltage at a detection position provided within the internal circuit and a target voltage, thereby bringing the power supply voltage within the internal circuit closer to the target voltage, and a second control circuit that, when there is a shortage area within the internal circuit where power supply capacity is insufficient, increases the power supply capacity of the power switch circuit that is located near the shortage area compared to the power supply capacity of the power switch circuit that is located at a position away from the shortage area. [Effects of the Invention]

[0008] By suppressing the occurrence of a gradient in the power supply voltage within the internal circuit, it is possible to suppress a decrease in the operating voltage margin of the processor. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor according to one embodiment. [Figure 2] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 3] 3 is an explanatory diagram showing an example in which a gradient of the power supply voltage occurs in the core circuit of FIG. 2. FIG. [Figure 4] FIG. 3 is a block diagram showing an example of a setting register in FIG. 2. [Figure 5] 3 is a circuit diagram showing an example of a power supply control circuit and a power supply switch circuit included in the LDO of FIG. 2. [Figure 6] 6 is a circuit diagram showing an example of the power switch circuit of FIG. 5. [Figure 7] 3 is an explanatory diagram showing another example in which a gradient of the power supply voltage occurs in the core circuit of FIG. 2. FIG. [Figure 8] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 9] 9 is an explanatory diagram showing an example in which a gradient of the power supply voltage occurs in the core circuit of FIG. 8. FIG. [Figure 10] FIG. 10 is a block diagram illustrating an example of another processor. [Figure 11] 11 is a circuit diagram showing an example of a power supply control circuit and a power supply switch circuit included in the LDO of FIG. 10. [Figure 12] 12 is a circuit diagram showing an example of the power switch circuit of FIG. 11. [Figure 13] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 14] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for signal lines through which signals are transmitted, and the same reference numerals as the voltage names are used for voltage lines through which voltages are supplied.

[0011] 1 shows an example of a processor according to an embodiment. The processor 100 shown in FIG. 1 includes a core 200 and peripheral circuits (not shown). For example, the peripheral circuits include an I / O circuit that inputs and outputs signals to and from the outside of the processor 100, and an operation control circuit that controls the operation of the core 200. The operation of the processor 100 described below may be realized by an operation control method for the processor 100.

[0012] The core 200 has a core circuit 210, a plurality of power switch circuits 220 distributed within the core circuit 210, and a first control circuit 230 and a second control circuit 240 that control the plurality of power switch circuits 220. The core circuit 210 is an example of an internal circuit, and may include various circuits such as various arithmetic units such as a floating-point arithmetic unit, a cache, a scheduler, a register file, and the like.

[0013] The multiple power switch circuits 220 step down the power supply voltage VDD0 supplied from outside the core circuit 210 to generate the power supply voltage VDD used for operating the circuits in the core circuit 210. For example, the multiple power switch circuits 220, the first control circuit 230, and the second control circuit 240 function as regulators that use the power supply voltage VDD0 supplied from outside the core circuit 210 to generate the power supply voltage VDD used in the core circuit 210.

[0014] The power supply voltage VDD0 is an example of an external power supply voltage, and the power supply line VDD0 to which the power supply voltage VDD0 is supplied is an example of an external power supply line. The power supply voltage VDD0 may be generated within the processor 100 or may be supplied from outside the processor 100. The power supply line VDD to which the power supply voltage VDD is supplied is an example of an internal power supply line. In FIG. 1, areas AR(11), AR(12), AR(21), and AR(22) in which each power switch circuit 220 is arranged are shown divided by dashed lines.

[0015] In the following description, when the areas AR(11), AR(12), AR(21), and AR(22) are not to be distinguished from one another, they are also referred to as areas AR or areas AR(xy). The area AR is an example of a circuit area in which circuits are arranged. In FIG. 1, the power switch circuit 220 arranged in each area AR(xy), the power supply voltage VDD generated by the power switch circuit 220, and the code xCODE supplied to the power switch circuit 220 are suffixed with the same symbol (xy) as the area AR. Note that, for ease of explanation, FIG. 1 shows an example in which the core circuit 210 has four areas AR, but the number of areas AR and power switch circuits 220 is not limited to four as long as there are multiple areas.

[0016] The divisions indicated by dashed lines do not indicate separation of power supplies. The power supply voltage VDD generated by the multiple power switch circuits 220 is used in common by the circuits in the core circuit 210. However, there is a risk that a gradient will occur in the power supply voltage VDD within the core circuit 210 due to the current consumption of the circuits mounted in each area AR within the core circuit 210. For this reason, in this embodiment, the power supply capacity of each power switch circuit 220 is adjusted using the code xCODE output from the second control circuit 240, thereby suppressing the occurrence of a gradient in the power supply voltage VDD within the core circuit 210.

[0017] Each power switch circuit 220 has a plurality of power switches (not shown) that, when turned on, connect the power line VDD0 to the power line VDD within the core circuit 210, and, when turned off, cut off the connection between the power line VDD0 and the power line VDD within the core circuit 210. Each power switch circuit 220 adjusts the supply capacity of the power supply voltage VDD to the core circuit 210 by changing the number of power switches to be turned on in accordance with the value of a common code CODE indicated by a control signal received from the first control circuit 230.

[0018] Furthermore, each power switch circuit 220 individually adjusts the supply capacity of the power supply voltage VDD to the core circuit 210 by adjusting the number of power switches to be turned on in accordance with the value of the individual code xCODE indicated by a control signal received from the second control circuit 240. The control signal indicating the value of the common code CODE is an example of a first control signal, and the control signal indicating the value of the individual code xCODE is an example of a second control signal.

[0019] For example, the first control circuit 230 has a voltage comparator (not shown) that compares the power supply voltage VDD with the target voltage VTG at a predetermined detection position SNS in the core circuit 210. The first control circuit 230 generates a common code CODE of multiple bits based on the comparison result between the power supply voltage VDD and the target voltage VTG, and outputs the generated code CODE to the multiple power switch circuits 220.

[0020] When the power supply voltage VDD at the detection position SNS is lower than the target voltage VTG, the first control circuit 230 generates code CODE to increase the number of on-state power switches in each power switch circuit 220. When the power supply voltage VDD at the detection position SNS is higher than the target voltage VTG, the first control circuit 230 generates code CODE to decrease the number of on-state power switches in each power switch circuit 220. Then, the first control circuit 230 controls the multiple power switch circuits 220 based on the generated code CODE to bring the power supply voltage VDD in the core circuit 210 closer to the target voltage VTG.

[0021] The power supply voltage VDD at the detection position SNS may be detected by a voltage detection circuit provided at the detection position SNS. In this case, a signal indicating the value of the power supply voltage VDD is transmitted from the detection position SNS to the first control circuit 230. The power supply voltage VDD at the detection position SNS may also be detected by a voltage detection circuit provided in the first control circuit 230. In this case, a power supply line VDD is wired from the detection position SNS to the first control circuit 230. The power supply voltage VDD at the detection position SNS may also be detected by a voltage detection circuit provided between the detection position SNS and the first control circuit 230.

[0022] The second control circuit 240 generates a code xCODE to be output to each power switch circuit 220 arranged in each area AR. For example, the second control circuit 240 has a setting register (not shown) that holds the value of each code xCODE in an externally rewritable manner, and outputs the value set in the setting register as the code xCODE. The setting register may be provided using a storage area of ​​an electrically rewritable nonvolatile memory.

[0023] For example, if there is a shortage area in the core circuit 210 where the power supply capacity of the power switch circuit 220 is insufficient, the power supply voltage VDD in the shortage area may become lower than the target voltage VTG even when the power supply capacity is controlled by the first control circuit 230. For this reason, the code xCODE supplied to the power switch circuit 220 arranged in the area AR including the shortage area is set to a value that allows the power supply capacity to be increased individually.

[0024] The power switch circuit 220 that receives the code xCODE indicating a value for increasing the power supply capacity increases the number of power switches that are turned on by the code CODE, thereby increasing the power supply capacity. That is, the second control circuit 240 increases the power supply capacity of the power switch circuit 220 that is located near the shortage area compared to the power supply capacity of the power switch circuit 220 that is located farther from the shortage area. This makes it possible to equalize the value of the power supply voltage VDD within the core circuit 210 and prevent the occurrence of a gradient in the power supply voltage VDD. As a result, it is possible to prevent a decrease in the operating voltage margin of the processor 100.

[0025] For example, due to the layout of the circuits mounted in the core circuit 210, the power switch circuits 220 may not be evenly distributed within the core circuit 210. In this case, one or more areas AR may include circuits that are far from the power switch circuits 220 and therefore have insufficient power supply capacity.

[0026] In addition, an area AR in which a circuit consuming a larger current than the circuits in other areas AR is placed may become an area with insufficient power supply capacity. Whether the current consumption of a circuit placed in the area AR is large can be determined during the design of the processor 100 (during the circuit design or layout design, etc.).

[0027] For example, if a shortage area of ​​power supply capacity is identified at the time of designing the processor 100, the code xCODE may be set in a setting register in the second control circuit 240 at the time of starting up the processor 100. Note that if the setting register is provided using a non-volatile memory and the code xCODE can be set in the setting register in advance, the setting process of the setting register at the time of starting up the processor 100 does not need to be performed.

[0028] Furthermore, for example, if one of the areas AR includes a floating-point arithmetic unit or other arithmetic unit whose current consumption during operation is greater than that of other arithmetic units, the second control circuit 240 may have an operation monitoring circuit that monitors the operation of the arithmetic unit such as the floating-point arithmetic unit.

[0029] When a computing unit consuming a large amount of current during operation is operating, the operation monitoring circuit in the second control circuit 240 sets the code xCODE supplied to the power switch circuit 220 included in the area AR in which the computing unit consuming a large amount of current during operation is located to a value that increases the power supply capability. For example, the operation monitoring circuit may detect the execution of an operation instruction consuming a large amount of current based on the decoded result of an instruction decoder mounted in the core circuit 210. Alternatively, if the core circuit 210 has a scheduler that temporarily holds information on the decoded instruction until it is issued to the computing unit, the operation monitoring circuit may detect the execution of an operation instruction consuming a large amount of current based on the instruction issued from the scheduler to the computing unit.

[0030] 1 includes a first control circuit 230 that commonly controls the power supply capacity of a plurality of power switch circuits 220 that are distributed within the core circuit 210, and a second control circuit 240 that individually controls the power supply capacity of the plurality of power switch circuits 220. This allows the power supply voltage VDD within the core circuit 210 to approach the target voltage VTG through control by the first control circuit 230. Furthermore, the power supply capacity of the power switch circuits 220 near a power supply capacity shortage area within the core circuit 210 can be increased through control by the second control circuit 240.

[0031] This makes it possible to make the value of the power supply voltage VDD in the core circuit 210 uniform, regardless of the position of the power switch circuit 220, differences in current consumption of the circuits in the core circuit 210, or differences in current consumption due to operation / non-operation of the circuits in the core circuit 210. As a result, it is possible to prevent a gradient from occurring in the power supply voltage VDD, and to prevent a decrease in the operating voltage margin of the processor 100.

[0032] FIG. 2 illustrates an example of a processor according to another embodiment. Elements similar to those in FIG. 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The processor 100A illustrated in FIG. 2 includes multiple cores 200A, an I / O (Input / Output) circuit 120, a common circuit 121, and a configuration register 122. In the example illustrated in FIG. 2, the processor 100A includes four cores 200A, identified by the identification symbols (00), (10), (01), and (11). However, the number of cores 200A may be one or more. The processor 100A operates by receiving a power supply line VDD0 generated by a power supply circuit 300, such as a POL (Point of Load) power supply, external to the processor 100A. The operation of the processor 100A described below may be achieved by an operation control method for the processor 100A.

[0033] Each core 200A includes a core circuit 210A and an LDO (Low Drop Out) 220A. The LDO 220A generates multiple power supply voltages VDD by multiple power switch circuits 222A (FIG. 3) that step down the power supply voltage VDD0 supplied from the power supply circuit 300 and supply the voltages to multiple circuit regions of the core circuit 210, respectively.

[0034] 2 shows an example in which each LDO 220A is arranged outside the core circuit 210A for ease of explanation, but in reality, some circuits of the LDO 220A are arranged inside the core circuit 210A. The core circuit 210A may include various circuits such as various arithmetic units such as a floating-point arithmetic unit, a cache, a scheduler, a register file, etc. The core circuit 210A is an example of an internal circuit.

[0035] The I / O circuit 120 has an input buffer that receives a signal from outside the processor 100 and an output buffer that outputs a signal to outside the processor 100. The common circuit 121 includes, for example, a control circuit that is shared by the multiple cores 200A. The setting register 122 holds the value of a code xCODE that individually controls the LDO 220A of each core 200A, and outputs multiple control signals indicating the held code xCODE value to each LDO 220A.

[0036] The setting register 122 is an example of a storage unit that stores an increase in the power supply capacity of the power switch circuit 222A that is located near an area in the core circuit 210A where the power supply capacity is insufficient. The setting register 122 may be provided using a storage area of ​​an electrically rewritable nonvolatile memory, or may be provided using a ROM (Read Only Memory), a fuse, or a wiring pattern in which a voltage value is fixed. Note that while FIG. 2 shows the setting register 122 corresponding to the core circuit 210A of one core 200A, a setting register 122 is provided for each core 200A.

[0037] 2 does not show the clock that operates the processor 100A and the circuit that controls the clock frequency. For example, the processor 100A has a DVFS (Dynamic Voltage and Frequency Scaling) control function that dynamically controls the power supply voltage VDD and the clock frequency for each core 200A according to the processing load assigned to each core 200A.

[0038] 3 shows an example in which a gradient of the power supply voltage VDD occurs within the core circuit 210A of FIG. 2. The core 200A shown in FIG. 3 is one of the four cores 200A shown in FIG. 2. The core 200A has a power supply control circuit 221A and a core circuit 210A including multiple power switch circuits 222A arranged in each area AR. The multiple power switch circuits 222A are arranged in each area AR, and are disposed between the power supply line VDD0 and the power supply line VDD. The power supply control circuit 221A and the power switch circuit 222A are included in the LDO 220A of FIG. 2.

[0039] 3, the core circuit 210 is partitioned into nine regions AR(xy) of three rows and three columns. The symbol x indicates the column number of the region AR, and the symbol y indicates the row number of the region AR. For example, the detection position SNS for detecting the power supply voltage VDD in the core circuit 210A is provided in the region AR(22) located in the center of the core circuit 210A. In this embodiment, the current consumption of the circuits arranged in each region AR is assumed to be approximately the same.

[0040] The power supply control circuit 221A generates a common multi-bit code CODE based on the comparison result between the power supply voltage VDD at the detection position SNS and the target voltage VTG, and outputs the generated code CODE to the nine power supply switch circuits 222A. The power supply switch circuit 222A generates the power supply voltage VDD by stepping down the power supply voltage VDD0 based on the common multi-bit code CODE and the multi-bit code xCODE for each area AR.

[0041] For example, in the layout design of the processor 100A, circuits that realize the functions of the processor 100 are laid out first, and the power switch circuit 222A is laid out using an empty area where no circuit is laid out. In the example shown in Figure 3, one or more circuits are laid out in an area spanning the areas AR(21), AR(31), AR(22), and AR(32). The power switch circuits 222A in the areas AR(21), AR(31), and AR(32) are laid out at positions offset from the center of each area AR. Therefore, the placement density of the power switch circuits 222A varies within the core circuit 210A.

[0042] 3 indicates an area where the power supply voltage VDD is likely to become lower than the target voltage VTG due to an increase in the distance from the power switch circuit 222A. That is, the circle indicated by the dashed line in Fig. 3 indicates an insufficient area where the power supply capacity becomes lower than other areas due to a decrease in the placement density of the power switch circuit 222A.

[0043] The position of each power switch circuit 222A within each area AR is known at the completion of the layout design of the processor 100. Then, for example, the code xCODE to be set in the setting register 122 in FIG. 2 is determined for each power switch circuit 222A according to the amount of deviation of each power switch circuit 222A from the center of each area AR.

[0044] In the example shown in Figure 3, the power switch circuit 222A(21) in the area AR(21) is the most displaced from the center of the area AR(21). The power control circuit 221A(31) in the area AR(31) is the second most displaced from the center of the area AR(21). The power control circuit 221A(32) in the area AR(22) is the third most displaced from the center of the area AR(32). The power switch circuits 222A in the other areas AR are located at the centers of the areas AR.

[0045] Therefore, the code xCODE supplied to the power switch circuit 222A(21) is set to a value that maximizes the rate of increase in the power supply capacity relative to the power supply capacity set by the code CODE. The code xCODE supplied to the power switch circuit 222A(31) is set to a value that maximizes the rate of increase in the power supply capacity relative to the power supply capacity set by the code CODE. The code xCODE supplied to the power switch circuit 222A(32) is set to a value that maximizes the rate of increase in the power supply capacity relative to the power supply capacity set by the code CODE. The codes xCODE supplied to the other power switch circuits 222A are set to values ​​that maintain the power supply capacity set by the code CODE.

[0046] 2 holds an increase amount of power supply capacity according to the amount of deviation from the position of the power switch circuits 222A (i.e., the center of each area RA) when the power switch circuits 222A are evenly distributed and arranged within the core circuit 210A. The increase amount of power supply capacity held in the setting register 122 is set to a value that increases the current supply capacity as the amount of deviation increases.

[0047] Fig. 4 shows an example of the setting register 122 of Fig. 2. The setting register 122 outputs nine codes xCODE for each core 200A. As shown in Fig. 3, each core 200A includes nine areas AR(xy), and the setting register 122 outputs nine codes xCODE(xy) corresponding to the nine areas AR of each core 200A, respectively.

[0048] Fig. 5 shows an example of a power supply control circuit 221A and a power supply switch circuit 222A included in the LDO 220A of Fig. 2. The power supply control circuit 221A has a voltage comparator VCMP and a filter FLT. The power supply control circuit 221A is an example of a first control circuit.

[0049] The voltage comparator VCMP compares the power supply voltage VDD at the detection position SNS in the core circuit 210A with the target voltage VTG, and outputs an error value ERR corresponding to the difference between the power supply voltage VDD and the target voltage VTG. The error value ERR is an example of the comparison result between the power supply voltage VDD and the target voltage VTG.

[0050] The filter FLT generates a 10-bit code CODE[9:0] by filtering the error value ERR. For example, the filter FLT performs feedback control using PID (Proportional Integral Differential). The binary number represented by the code CODE[9:0] indicates the number of power switches PSW provided in the power switch circuit 222A that are turned on.

[0051] The power switch circuit 222A has multiple power switches PSW, each including a different number of pMOS transistors. The power switch circuit 222A increases the number of pMOS transistors that are turned on as the power supply voltage VDD becomes lower than the target voltage VTG, thereby increasing the power supply capability. This reduces the amount of voltage drop and increases the power supply voltage VDD.

[0052] The higher the power supply voltage VDD is, the more the power switch circuit 222A reduces the number of pMOS transistors that are turned on, thereby reducing the power supply capacity. Through the above operations, the power supply voltage VDD is maintained at the target voltage VTG. That is, the power supply control circuit 221A controls the multiple power switch circuits 222A based on the generated code CODE[9:0], and brings the power supply voltage VDD in the core circuit 210A closer to the target voltage VTG.

[0053] Furthermore, in this embodiment, the power switch circuit 222A(xy) arranged in each area AR(xy) in Fig. 3 has a multiplier MUL. The multiplier MUL and the setting register 122 shown in Fig. 2 are an example of a second control circuit.

[0054] The multiplier MUL multiplies the binary number indicated by the code CODE[9:0] output from the power supply control circuit 221A by the value indicated by the code xCODE, and outputs the value of each bit of the binary number code CODE+[9:0] obtained by the multiplication to the power supply switch PSW.

[0055] Each power switch circuit 222A arranged in each area AR in Fig. 3 turns on pMOS transistors PT in the number indicated by the binary code CODE+[9:0] output from the multiplier MUL. This allows the power supply voltage VDD generated based on the code CODE[9:0] for each area AR in Fig. 3 to be adjusted by the code xCODE. The multiplier MUL is an example of an adjustment circuit that adjusts the value indicated by the code CODE[9:0] in accordance with the value indicated by the code xCODE to generate the code CODE+[9:0], and outputs each bit of the code CODE+[9:0] to the corresponding power switch PSW.

[0056] The power supply voltage VDD(xy) output from each power switch circuit 222A is supplied as a common power supply voltage VDD for the core circuit 210A to a circuit which is a current load LD(xy) arranged between the power supply line VDD(xy) and the ground line GND of each area AR.

[0057] Fig. 6 shows an example of the power switch circuit 222A shown in Fig. 5. Fig. 6 shows an example of the power switch circuit 222A arranged in one of the nine areas AR shown in Fig. 3. The power switch circuit 222A has ten inverters IV in addition to the multiplier MUL and power switch PSW shown in Fig. 5. The multiplier MUL multiplies the binary value indicated by the code CODE[9:0] by the value of the code xCODE, and outputs the result to the power switch PSW as a 10-bit code CODE+[9:0].

[0058] For example, when the value of code xCODE indicates 1.5 times, the multiplier MUL outputs code CODE+[9:0], which is 1.5 times the value of code CODE[9:0]. When the value of code xCODE indicates 1.8 times, the multiplier MUL outputs code CODE+[9:0], which is 1.8 times the value of code CODE[9:0]. Note that code CODE+[9:0], which is the multiplication result of the multiplier MUL, is rounded to a value that can be expressed in binary.

[0059] The power switch circuit 222A has ten power switches PSW each including 2 n (n is an integer from 0 to 9) pMOS transistors PT. The numbers (512, 4, 2, 1) added after the symbol PSW of each power switch PSW indicate the number of pMOS transistors included in the power switch PSW. The ten power switches PSW have current supply capacities to the area AR that differ by two times.

[0060] The power switch circuit 222A, which has 10 power switches PSW, has a total of 1023 pMOS transistors PT. The pMOS transistors PT in each power switch PSW (except PSW1) are connected in parallel between the power supply line VDD0 and the power supply line VDD. The pMOS transistor PT of the power switch PSW1 is connected between the power supply line VDD0 and the power supply line VDD.

[0061] Each bit of the code CODE+[9:0] is connected to the power switch PSW having the greatest number of pMOS transistors PT via an inverter IV, starting from the most significant bit. The pMOS transistors PT included in each power switch PSW are all turned on or all turned off according to the value of the corresponding bit of the code CODE+.

[0062] For example, when the value of code CODE+[9] is "1", all 512 pMOS transistors PT of the power switch PSW512 are turned on. When the value of code CODE+[9] is "0", all 512 pMOS transistors PT of the power switch PSW512 are turned off. Similarly, when the value of code CODE+[2] is "1", all four pMOS transistors PT of the power switch PSW4 are turned on. When the value of code CODE+[2] is "0", all four pMOS transistors PT of the power switch PSW4 are turned off.

[0063] By turning on or off the pMOS transistors PT for each power switch PSW, the number of pMOS transistors PT indicated by the value of the code CODE+[9:0] can be turned on. This allows the power supply voltage VDD to be supplied to the area AR with a current supply capacity according to the value of the code CODE+[9:0].

[0064] Figure 7 shows another example in which a gradient of the power supply voltage VDD occurs within the core circuit 210A of Figure 2. Elements similar to those in Figure 3 are given the same reference numerals, and detailed descriptions will be omitted. In the example shown in Figure 7, it is known in advance at the time of designing the processor 100A that the current consumption of the circuits mounted in the area AR(33) is greater than the current consumption of the circuits mounted in the other areas AR.

[0065] In this case, if the power supply voltage VDD is generated in all the power switch circuits 222A using only the code CODE common to all the areas AR, the power supply voltage VDD in the area AR (33) will be lower than the target voltage VTG, which will result in a gradient of the power supply voltage VDD within the core circuit 210A.

[0066] Therefore, the value of the code xCODE(33) corresponding to the area AR(33) including circuits with large current consumption is set larger than the values ​​of the other codes xCODE, and the current supply capacity of the power supply voltage VDD for the area AR(33) is increased. By increasing the current supply capacity of the area AR(33) including circuits with large current consumption compared to the current supply capacity of the other areas AR, it is possible to suppress the occurrence of a gradient in the power supply voltage VDD in the core circuit 210A.

[0067] 2 to 7 can also achieve the same effects as the embodiment shown in Fig. 1. For example, the setting register 122 and the multiplier MUL can increase the power supply capacity of the power switch circuit 222A near the area where the power supply capacity is insufficient within the core circuit 210A.

[0068] For example, even when the power switch circuit 222A is laid out at a position shifted from the center of each area AR, it is possible to prevent a gradient in the power supply voltage VDD from occurring in the core circuit 510. Also, even when there is an area AR whose current consumption is larger than that of the other areas AR, it is possible to prevent a gradient in the power supply voltage VDD from occurring in the core circuit 510. As a result, it is possible to prevent a decrease in the operating voltage margin of the processor 100.

[0069] 3, an example has been described in which the power supply capacity is increased by increasing the value of the code xCODE supplied to the power switch circuits 222A arranged in an area AR where the arrangement density of the power switch circuits 222A is lower than in other areas. However, the power supply capacity may be reduced by decreasing the value of the code xCODE supplied to the power switch circuits 222A arranged in an area AR where the arrangement density of the power switch circuits 222A is higher than in other areas.

[0070] 7 illustrates an example in which the power supply capacity is increased by increasing the value of the code xCODE supplied to the power switch circuit 222A arranged in the area AR where the current consumption is higher than others. However, the power supply capacity may be reduced by decreasing the value of the code xCODE supplied to the power switch circuit 222A arranged in the area AR where the current consumption is higher than others.

[0071] By reducing the value of the code xCODE, it is possible to suppress unnecessary power consumption while suppressing the occurrence of a gradient in the power supply voltage VDD in the core circuit 510. In this case, however, the value of the code CODE[9:0] in the standard state of the current supply capability of the power switch circuit 222A is set to, for example, the median value (for example, 511), and the magnification indicated by the value of the code xCODE can be set to a value smaller than 1.

[0072] FIG. 8 shows an example of a processor according to another embodiment. Elements similar to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 100B shown in FIG. 8 has a circuit configuration similar to that of the processor 100A of FIG. 2, except that it has a core operation monitoring circuit 123 instead of the setting register 122 of FIG. 2. Note that FIG. 8 shows the core operation monitoring circuit 123 corresponding to the core circuit 210A of one core 200A. A core operation monitoring circuit 123 is provided for each core 200A. The operation of the processor 100B described below may be realized by an operation control method for the processor 100B.

[0073] The core operation monitoring circuit 123 monitors the operation of a specific circuit, among the circuits mounted in the core circuit 210A, that consumes more current during operation than the other circuits. The core operation monitoring circuit 123 is an example of an operation monitoring circuit that monitors the operation of a circuit included in a circuit area, among multiple circuit areas in the core circuit 210A, that becomes a shortage area due to a lack of power supply capacity during operation. The specific circuit whose operation is monitored by the core operation monitoring circuit 123 is an example of a first circuit, and when it operates, it generates a shortage area where the power supply capacity is insufficient.

[0074] For example, the specific circuit is a floating-point arithmetic unit. The core operation monitoring circuit 123 determines whether the floating-point arithmetic unit is operating based on floating-point arithmetic instruction information from an instruction decoder or scheduler (not shown). If the core operation monitoring circuit 123 determines that the floating-point arithmetic unit is operating, it increases the value of the code xCODE corresponding to the area AR including the floating-point arithmetic unit until the operation of the floating-point arithmetic unit stops. Note that the specific circuit may also be a circuit including multiple multiply-accumulate units, such as an engine for inference processing in deep learning. In this case, the multiply-accumulate units may be floating-point type or integer type.

[0075] The specific circuit consuming a large amount of current during operation may be a SIMD (Single Instruction Multiple Data) arithmetic unit. In this case, when a SIMD arithmetic unit executes a SIMD arithmetic instruction, the core operation monitoring circuit 123 increases the value of the code xCODE corresponding to the area AR including the SIMD arithmetic unit. When a SISD (Single Instruction Single Data) arithmetic instruction is executed by the SIMD arithmetic unit, the core operation monitoring circuit 123 does not need to increase the value of the code xCODE corresponding to the area AR including the SIMD arithmetic unit.

[0076] Furthermore, the core operation monitoring circuit 123 does not increase the value of the code xCODE corresponding to an area AR that does not include a SIMD arithmetic unit. In this way, when the core operation monitoring circuit 123 detects that processing of a specific pattern that increases current consumption is being performed, it increases the value of the code xCODE corresponding only to the area AR that performs processing of the specific pattern while the processing of the specific pattern is being performed. This makes it possible to suppress the occurrence of a gradient in the power supply voltage VDD within the core circuit 210A even when one or more areas AR include a specific circuit that consumes a large amount of current during operation.

[0077] In addition, the core operation monitoring circuit 123 may monitor the operation of a floating-point arithmetic circuit including multiple floating-point arithmetic units or a SIMD arithmetic circuit including multiple SIMD arithmetic units, and increase the value of the code xCODE of a specific area AR based on the monitoring results.

[0078] 9 shows an example of a power supply voltage VDD gradient occurring within the core circuit 210A of FIG. 8. The same elements as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the example shown in FIG. 9, it is known in advance at the time of designing the processor 100A that a circuit consuming a larger current during operation than other circuits will be mounted in the area AR(11). For example, the current consumption during non-operation of a circuit consuming a larger current during operation than other circuits may be lower than the current consumption during operation of the other circuits, or may be equal to the current consumption of the other circuits during non-operation.

[0079] 8 monitors the operation of a specific circuit mounted in area AR(11) that consumes more current during operation than other circuits. When the specific circuit operates, core operation monitoring circuit 123 increases the value of code xCODE corresponding to power switch circuit 222A(11) included in area AR(11) until the operation stops.

[0080] Assume that a specific circuit that consumes more current during operation than other circuits is mounted in the area AR(22) that includes the detection position SNS of the power supply voltage VDD. In this case, the power supply voltage VDD of the area AR(22) can be brought closer to the target voltage VTG by controlling only the code CODE[9:0]. However, when the circuit mounted in the area AR(22) is operating, the power supply capacity of the other areas AR becomes excessive, resulting in unnecessary power consumption.

[0081] In such a case, the core operation monitoring circuit 123 may set the values ​​of the codes xCODE other than the code xCODE(22) to be smaller than the value of the code xCODE(22) when the circuits mounted in the area AR(22) are operating. For example, the core operation monitoring circuit 123 sets the values ​​of the codes xCODE other than the code xCODE(22) to be smaller as the value of the code CODE[9:0] increases due to the operation of the circuits mounted in the area AR(22). This makes it possible to prevent the power supply capacity of the other areas AR from becoming excessive when the circuits mounted in the area AR(22) are operating, and to suppress an increase in current consumption of the processor 100A.

[0082] Furthermore, it may take some time for the value of code CODE[9:0] to increase after the circuits mounted in area AR(22) start operating. In this case, the core operation monitoring circuit 123 may temporarily increase the value of code xCODE(22) until the value of code CODE[9:0] increases. After the value of code CODE[9:0] increases, the value of code xCODE(22) may be restored and the values ​​of codes xCODE other than code xCODE(22) may be set to smaller values. In this case, the value of code CODE[9:0] when the current supply capacity of the power switch circuit 222A is standard is set to, for example, a median value (e.g., 511), and the scaling factor indicated by the value of code xCODE can be set to a value smaller than 1.

[0083] Note that a specific circuit that consumes less current during operation than other circuits may be included in an area AR other than the area AR (22) including the detection position SNS. In this case, the core operation monitoring circuit 123 may output a code xCODE that reduces the current supply capacity of the power switch circuit 222A included in the area AR where the specific circuit is installed during operation of the specific circuit. This can suppress an increase in current consumption of the processor 100A.

[0084] As described above, the embodiments shown in Figures 8 and 9 can also achieve the same effects as the embodiment shown in Figure 1. For example, the core operation monitoring circuit 123 and the multiplier MUL can increase the power supply capacity of the power switch circuit 222A near the power supply capacity shortage area in the core circuit 210A.

[0085] Furthermore, in the embodiments shown in Figures 8 and 9, even if the current consumption during operation of a circuit mounted in a certain area AR is greater than the current consumption during operation of a circuit mounted in another area AR, it is possible to suppress the occurrence of a gradient in the power supply voltage VDD in the core circuit 510.

[0086] 9 illustrates an example in which the power supply capacity is increased by increasing the value of the code xCODE during circuit operation, which is supplied to the power switch circuit 222A arranged in the area AR where the current consumption during circuit operation is larger than in the other areas AR. However, the power supply capacity may be decreased by decreasing the value of the code xCODE during circuit operation, which is supplied to the power switch circuit 222A arranged in the area AR where the current consumption during circuit operation is smaller than in the other areas AR. By decreasing the value of the code xCODE, it is possible to suppress unnecessary power consumption while suppressing the occurrence of a gradient in the power supply voltage VDD in the core circuit 510.

[0087] 10 shows an example of another processor. Elements similar to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 400 shown in FIG. 10 has multiple cores 500, an I / O circuit 120, and a common circuit 121. As in FIG. 2, the processor 400 has four cores 500 identified by the identification symbols (00), (10), (01), and (11), and operates by receiving a power supply voltage VDD0 generated by a power supply circuit 300.

[0088] Each core 500 includes a core circuit 510 and an LDO 520. The LDO 520 steps down the power supply voltage VDD0 to generate multiple power supply voltages VDD that are respectively supplied to multiple circuit areas of the core circuit 510. Some circuits of the LDO 520 are arranged within the core circuit 510. The core circuit 510 may include various circuits such as various arithmetic units such as a floating-point arithmetic unit, a cache, a scheduler, and a register file.

[0089] Figure 11 shows an example of a power supply control circuit 521 and a power supply switch circuit 522 included in the LDO of Figure 10. Elements similar to those in Figure 5 are assigned the same reference numerals and detailed description will be omitted. Note that the core circuit 510 is partitioned into nine areas AR(xy) of three rows and three columns, similar to the core circuit 210A of Figure 3, and power supply switch circuits 522(xy) are arranged in each of the nine areas AR(xy) of the core circuit 510.

[0090] The power supply control circuit 521 has the same circuit configuration as the power supply control circuit 221A in Figure 5. Each power switch circuit 522(xy) has a circuit configuration that excludes the multiplier MUL from the power switch circuit 222A(xy) in Figure 5. Therefore, the power switch PSW of each power switch circuit 522(xy) operates by directly receiving the code CODE[9:0]. The detection position SNS for detecting the power supply voltage VDD is provided in an area AR(22) located in the center of the core circuit 510.

[0091] 12 shows an example of the power switch circuit 522 of FIG. 11. Elements similar to those in FIG. 6 are assigned the same reference numerals, and detailed description thereof will be omitted. The power switch circuit 522 has a circuit configuration similar to that of the power switch circuit 222A of FIG. 6, except that it does not have the multiplier MUL. Therefore, the power switch circuit 522 turns on the number of pMOS transistors PT indicated by the value of the code CODE[9:0], and supplies the power supply voltage VDD to the area AR with a current supply capacity according to the value of the code CODE[9:0].

[0092] 10, the power switch circuit 522 may be laid out at a position shifted from the center of each area AR, as shown in Fig. 3. In this case, the power supply capacity of the power switch circuit 522 may be insufficient, and a gradient in the power supply voltage VDD may occur in the core circuit 510.

[0093] 7, if there is an area AR in which the current consumption is larger than that of other areas AR, the power supply capacity may be insufficient in the area AR in which the current consumption is large, and a gradient in the power supply voltage VDD may occur in the core circuit 510. Furthermore, as shown in FIG. 9, the current consumption during operation of a circuit mounted in a certain area AR may be larger than the current consumption during operation of a circuit mounted in another area AR. In this case, the power supply capacity may be insufficient in the area AR in which the circuit with the large current consumption is operating, and a gradient in the power supply voltage VDD may occur in the core circuit 510.

[0094] FIG. 13 shows an example of a processor according to another embodiment. Elements similar to those in FIGS. 2 and 8 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 100B shown in FIG. 13 has the same circuit configuration as the processor 100A shown in FIG. 2, except that a core operation monitoring circuit 123 and a selector 124 are added to FIG. 2. Note that FIG. 13 shows the setting register 122, the core operation monitoring circuit 123, and the selector 124 corresponding to the core circuit 210A of one core 200A. The setting register 122, the core operation monitoring circuit 123, and the selector 124 are provided for each core 200A. The operation of the processor 100B described below may be realized by an operation control method for the processor 100B.

[0095] 2, the setting register 122 increases the value of the code xCODEa corresponding to an area AR including an area where power supply capacity is likely to be insufficient because the position of the power switch circuit 222A is shifted from the center of the area AR. Alternatively, if the current consumption of a circuit mounted in a certain area AR is greater than the current consumption of a circuit mounted in another area AR, the setting register 122 increases the value of the code xCODEa corresponding to the area AR in which the circuit with higher power consumption is mounted.

[0096] When a specific circuit operates, consuming a larger current than other circuits, the core operation monitoring circuit 123 increases the value of the code xCODEb corresponding to the area AR including the specific circuit until the operation of the specific circuit stops. Note that the codes xCODEa and xCODEb are the same as the code xCODE output from the setting register 122 in Fig. 2 and the code xCODE output from the core operation monitoring circuit 123 in Fig. 8, respectively.

[0097] Furthermore, when a specific circuit that consumes more current during operation than the other circuits is operating, the core operation monitoring circuit 123 outputs a selection signal SEL that causes the selector 124 to select the code xCODEb. When a specific circuit that consumes more current during operation than the other circuits is not operating, the core operation monitoring circuit 123 outputs a selection signal SEL that causes the selector 124 to select the code xCODEa.

[0098] The selector 124 selects one of the codes xCODEa and xCODEb in response to the selection signal SEL from the core operation monitoring circuit 123 and outputs it as the code xCODE to the core circuit 210A of each core 200A. That is, the selector 124 selects whether to adjust the power supply capacity based on the monitoring by the core operation monitoring circuit 123 or to increase the power supply capacity based on the increase amount of the power supply capacity held in the setting register 122.

[0099] This makes it possible to selectively resolve a local power supply capacity shortage in the core circuit 210A caused by the circuit layout and a local power supply capacity shortage in the core circuit 210A caused by the circuit operation, thereby preventing a gradient from occurring in the power supply voltage VDD within the core circuit 210A and preventing a reduction in the operating voltage margin of the processor 100B.

[0100] As described above, the embodiment shown in Fig. 13 can also achieve the same effects as the embodiments shown in Fig. 1 to Fig. 9. Furthermore, the embodiment shown in Fig. 13 can resolve localized power supply capacity shortages in the core circuit 210A caused by the circuit layout and localized power supply capacity shortages in the core circuit 210A caused by the circuit operation. As a result, it is possible to prevent a gradient from occurring in the power supply voltage VDD within the core circuit 210A, and to prevent a reduction in the operating voltage margin of the processor 100B.

[0101] FIG. 14 shows an example of a processor according to another embodiment. Elements similar to those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 100C shown in FIG. 14 has the same circuit configuration as the processor 100B shown in FIG. 13, except that a multiplication circuit 125 is provided instead of the selector 124 in FIG. 13. Note that FIG. 14 shows the setting register 122, core operation monitoring circuit 123, and multiplication circuit 125 corresponding to the core circuit 210A of one core 200A. The setting register 122, core operation monitoring circuit 123, and multiplication circuit 125 are provided for each core 200A. The operation of the processor 100C described below may be realized by an operation control method for the processor 100C.

[0102] The multiplication circuit 125 multiplies the areas AR of the core circuit 210A by the codes xCODEa and xCODEb corresponding to the areas AR, and outputs the multiplication result as the code xCODE to the power switch circuit 222A arranged in the corresponding areas AR. That is, the multiplication circuit 125 multiplies the code xCODEa, which indicates the amount of increase in the power supply capacity held in the setting register 122, by the code xCODEb, which indicates the amount of adjustment in the power supply capacity output from the core operation monitoring circuit 123.

[0103] For example, suppose that an area AR(31) including the area surrounded by the dashed circle in Fig. 3 contains a circuit whose current consumption during operation is greater than the current consumption during operation of circuits mounted in other areas AR. In this case, in the setting register 122, the value of the code xCODEa corresponding to the areas AR(21), AR(31), and AR(32) including the area surrounded by the dashed circle in Fig. 3 is set to be greater than the value of the code xCODEa of the other areas AR. Furthermore, when a circuit with high power consumption mounted in the area AR(31) is operating, the core operation monitoring circuit 123 sets the value of the code xCODEb corresponding to the area AR(31) to be greater than the value of the code xCODEb of the other areas AR.

[0104] As a result, the code xCODE output from the multiplication circuit 125 has the largest value (magnification factor) of the code xCODE corresponding to the area AR(31), for example, followed by the values ​​(magnification factors) of the code xCODE corresponding to the areas AR(21) and AR(32). The values ​​of the code xCODE corresponding to the other areas AR are set to a value indicating 1x, in order to maintain the value of the code CODE[9:0] output by the power supply control circuit 221A in FIG.

[0105] Then, the power supply capacity of the power switch circuit 222A arranged near the power supply capacity shortage area is adjusted based on the multiplication result by the multiplication circuit 125. As a result, it is possible to eliminate a local shortage of power supply capacity in the core circuit 210A that occurs in one or more areas AR due to both circuit layout and circuit operation.

[0106] As described above, the embodiment shown in Fig. 14 can also achieve the same effects as the embodiments shown in Fig. 1 to Fig. 9. Furthermore, the embodiment shown in Fig. 13 can eliminate a local shortage of power supply capability in the core circuit 210A that occurs in one or more areas AR due to both circuit layout and circuit operation.

[0107] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0108] 100, 100A, 100B, 100C processors 120 I / O circuits 121 Common Circuit 122 Configuration Registers 123 Core operation monitoring circuit 124 Selectors 125 Multiplication Circuit 200, 200A core 210, 210A core circuit 220 Power switch circuit 221A Power Control Circuit 222A power switch circuit 230 First control circuit 240 Second control circuit 300 Power circuit 400 processors 500 cores 510 Core Circuit 520 LDO 521 Power supply control circuit 522 Power Switch Circuit AR area CODE[9:0] Code ERR Error value FLT filter GND ground wire IV Inverter LD current load MUL multiplier PSW Power switch PT pMOS transistor SEL selection signal SNS detection location VCMP voltage comparator VDD, VDD0 power supply voltage VTG Target Voltage xCODE, xCODEa, xCODEb codes

Claims

1. An internal circuit, a plurality of power switch circuits that are distributed within the internal circuit and supply power supply voltages to the internal circuit respectively; a first control circuit that controls the plurality of power switch circuits based on a comparison result between a power supply voltage at a detection position provided in the internal circuit and a target voltage, and brings the power supply voltage in the internal circuit closer to the target voltage; a second control circuit that, when there is a shortage area in the internal circuit where the power supply capacity is insufficient, increases the power supply capacity of the power switch circuit that is arranged near the shortage area compared to the power supply capacity of the power switch circuit that is arranged at a position away from the shortage area; A processor having:

2. the first control circuit outputs a first control signal for changing the power supply capabilities of the plurality of power switch circuits based on the comparison result; the second control circuit outputs, among a plurality of second control signals respectively corresponding to the plurality of power switch circuits, a second control signal that increases the power supply capability of the power switch circuit that is arranged near the shortage area; each of the plurality of power supply switch circuits has a plurality of power supply switches arranged between an external power supply line and an internal power supply line to which the power supply voltage is supplied within the internal circuit; The power supply capacity of each of the plurality of power switch circuits is adjusted by turning on or off the plurality of power switches based on the first control signal common to the plurality of power switch circuits and the second control signal individual to each of the plurality of power switch circuits. The processor of claim 1 .

3. the first control circuit outputs the first control signal of n bits (n is an integer equal to or greater than 1) based on the comparison result; Each of the plurality of power switch circuits n power switches provided corresponding to each bit of the first control signal, each having a current supply capacity to the internal circuit that differs by two times; an adjustment circuit that adjusts a value indicated by the n bits of the first control signal according to a value indicated by the second control signal, and outputs each bit of the adjusted value to a corresponding one of the power switches. The processor of claim 2 .

4. The adjustment circuit includes a multiplier that multiplies the value indicated by the first control signal by the value indicated by the second control signal to generate the adjusted value. The processor of claim 3 .

5. the insufficient area occurs because the layout density of the power switch circuits in the internal circuit is lower than that of other areas in the internal circuit, The second control circuit has a holding unit that holds an increase amount of the power supply capacity of the power switch circuit that is placed near the shortage area, and increases the power supply capacity of the power switch circuit that is placed near the shortage area in accordance with the increase amount held in the holding unit. A processor according to any one of claims 1 to 4.

6. the holding unit holds the increase amount of the power supply capacity corresponding to the amount of deviation of the power switch circuits from a position where the plurality of power switch circuits are evenly distributed within the internal circuit; The increase amount held in the holding unit is set to a value that increases the current supply capacity as the deviation amount increases. The processor of claim 5 .

7. the insufficient region occurs when a circuit consuming a higher current than other regions in the internal circuit is arranged in the internal circuit, The second control circuit has a holding unit that holds an increase amount of the power supply capacity of the power switch circuit that is placed near the shortage area, and increases the power supply capacity of the power switch circuit that is placed near the shortage area in accordance with the increase amount held in the holding unit. A processor according to any one of claims 1 to 4.

8. the second control circuit has an operation monitoring circuit that monitors the operation of a first circuit included in a circuit area that becomes a shortage area due to a shortage of power supply capacity during operation, among a plurality of circuit areas in the internal circuit; When the shortage area occurs due to the operation of the first circuit, the operation monitoring circuit increases the power supply capacity of the power switch circuit arranged near the first circuit, and when the shortage area disappears due to the stop of the operation of the first circuit, restores the power supply capacity of the power switch circuit arranged near the first circuit to its original state. A processor according to any one of claims 1 to 4.

9. The second control circuit further includes: a holding unit that holds an increase in the power supply capacity of the power switch circuit that is arranged near the shortage area that occurs when the arrangement density of the power switch circuits in the internal circuit is lower than that of other areas in the internal circuit, or when a circuit that consumes more current than other areas in the internal circuit is arranged in the internal circuit; a selector that selects whether to adjust the power supply capacity based on the monitoring by the operation monitoring circuit or to increase the power supply capacity based on the increase amount held in the holding unit. The processor of claim 8 .

10. The second control circuit further includes: a holding unit that holds an increase in the power supply capacity of the power switch circuit that is arranged near the shortage area that occurs when the arrangement density of the power switch circuits in the internal circuit is lower than that of other areas in the internal circuit, or when a circuit that consumes more current than other areas in the internal circuit is arranged in the internal circuit; a multiplication circuit that multiplies the amount of adjustment of the power supply capacity by the operation monitoring circuit by the amount of increase held in the holding unit, The power supply capacity of the power switch circuit arranged near the shortage area is adjusted based on the multiplication result of the multiplication circuit. The processor of claim 8 .

11. 1. A method for controlling the operation of a processor having an internal circuit and a plurality of power switch circuits that are distributed within the internal circuit and supply power supply voltages to the internal circuit, the method comprising: a first control circuit included in the processor controls the plurality of power switch circuits based on a comparison result between a power supply voltage at a detection position provided in the internal circuit and a target voltage, and makes the power supply voltage in the internal circuit approach the target voltage; When there is a shortage area in the internal circuit where the power supply capacity is insufficient, a second control circuit included in the processor increases the power supply capacity of the power switch circuit arranged near the shortage area compared to the power supply capacity of the power switch circuit arranged at a position away from the shortage area. A method for controlling the operation of a processor.

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