Converter Circuit

Abstract

A converter circuit that can easily achieve zero voltage switching while suppressing losses is provided. [Solution] A converter circuit 100 includes an inductor L1, a first switch element S1, a second switch element S2, a control circuit 2, a main detection circuit 5, and a main OR circuit 8. The control circuit 2 boosts the input voltage by alternately turning on the first switch element S1 and the second switch element S2. When the main detection circuit 5 detects that the voltage applied to one of the main switch elements, the first switch element S1 or the second switch element S2, becomes zero, it outputs an interrupt ON signal for turning on the main switch element. When an ON signal for turning on the main switch element via the control circuit 2 or an interrupt ON signal for the main switch element is input, the main OR circuit 8 turns on the main switch element.

Description

[Technical Field]

[0001] The present invention relates to a converter circuit that steps up or steps down an input voltage and outputs the stepped-up voltage. [Background technology]

[0002] Patent Document 1 discloses a switching power supply circuit that supplies DC power to a load by controlling a switching element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-261039 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a converter circuit that can easily achieve zero voltage switching while suppressing losses. [Means for solving the problem]

[0005] A converter circuit according to one aspect of the present invention includes an inductor, a first switch element, a second switch element, a control circuit, a main detection circuit, and a main OR circuit. A first end of the inductor is connected to a high-potential input terminal. The first switch element is connected between a second end of the inductor and a high-potential output terminal. The second switch element is connected between the second end of the inductor and a low-potential output terminal. The control circuit boosts the input voltage by alternately turning on the first switch element and the second switch element. When the main detection circuit detects that the voltage applied to a main switch element, which is either the first switch element or the second switch element, becomes zero, it outputs an interrupt-on signal for turning on the main switch element. When the main OR circuit receives an on signal for turning on the main switch element via the control circuit or the interrupt-on signal for the main switch element, it turns on the main switch element. The on signal for the main switching element is a signal output by a drive circuit that receives a control signal from the control circuit and drives the main switching element, and the drive circuit has a first terminal that outputs the on signal to the main OR circuit and a second terminal for discharging the charge accumulated in the main switching element.

[0006] A converter circuit according to one aspect of the present invention includes an inductor, a first switch element, a second switch element, a control circuit, a main detection circuit, and a main OR circuit. The inductor has a first end connected to a high-potential output terminal. The first switch element is connected between a second end of the inductor and a high-potential input terminal. The second switch element is connected between the second end of the inductor and a low-potential input terminal. The control circuit steps down the input voltage by alternately turning on the first switch element and the second switch element. When the main detection circuit detects that the voltage applied to a main switch element, which is either the first switch element or the second switch element, becomes zero, it outputs an interrupt-on signal for turning on the main switch element. The main OR circuit turns on the main switch element when it receives an on signal for turning on the main switch element via the control circuit or the interrupt-on signal for the main switch element. The on signal for the main switching element is a signal output by a drive circuit that receives a control signal from the control circuit and drives the main switching element, and the drive circuit has a first terminal that outputs the on signal to the main OR circuit and a second terminal for discharging the charge accumulated in the main switching element. [Effects of the Invention]

[0007] The converter circuit of the present invention has the advantage that it is easy to achieve zero voltage switching while suppressing losses. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a basic converter circuit. [Figure 2] FIG. 2 is a waveform diagram when the basic converter circuit operates as a boost chopper. [Figure 3] FIG. 3 is a waveform diagram when the basic converter circuit operates as a step-down chopper. [Figure 4]FIG. 4 is a diagram showing an example of an inductor current waveform in zero voltage switching. [Figure 5] FIG. 5 is a circuit diagram showing a configuration of the converter circuit according to the embodiment when it operates as a boost chopper. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of the converter circuit according to the embodiment when it operates as a step-down chopper. [Figure 7] FIG. 7 is a circuit diagram showing a specific configuration of the second detection circuit. [Figure 8] FIG. 8 is a circuit diagram showing a specific configuration of the second OR circuit. [Figure 9] FIG. 9 is a timing chart of each of the second drive signal and the second interrupt-on signal. [Figure 10] FIG. 10 is a diagram illustrating the operation of the converter circuit according to the embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a configuration of a converter circuit according to a first modified example of the embodiment. [Figure 12] FIG. 12 is a circuit diagram showing a configuration of a converter circuit according to a second modification of the embodiment. [Figure 13] FIG. 13 is a circuit diagram showing a configuration of a converter circuit according to a third modification of the embodiment. [Figure 14] FIG. 14 is a circuit diagram showing a configuration of a converter circuit according to a fourth modification of the embodiment. [Figure 15] FIG. 15 is a circuit diagram showing a configuration of a converter circuit according to a fifth modification of the embodiment. [Figure 16] FIG. 16 is a circuit diagram showing a configuration of a converter circuit according to a sixth modification of the embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a configuration of a converter circuit according to a seventh modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Embodiment) [1.Technical background] First, the technical background that led to the invention of the converter circuit according to the embodiment will be described using a basic converter circuit 200 shown in Fig. 1. Fig. 1 is a circuit diagram showing the configuration of the basic converter circuit 200.

[0010] The basic converter circuit 200 is a synchronous rectification bidirectional converter circuit. As shown in FIG. 1 , when a power supply 3 is connected between a first high potential terminal P11 and a first low potential terminal P12 and a load 4 is connected between a second high potential terminal P21 and a second low potential terminal P22, the basic converter circuit 200 performs a boost chopper operation to boost the input voltage supplied from the power supply 3 and output it to the load 4, thereby functioning as a boost converter circuit. When a load 4 is connected between the first high potential terminal P11 and a first low potential terminal P12 and a power supply 3 is connected between the second high potential terminal P21 and a second low potential terminal P22, the basic converter circuit 200 performs a buck chopper operation to buck the input voltage supplied from the power supply 3 and output it to the load 4, thereby functioning as a buck converter circuit.

[0011] The potential of the first low potential terminal P12 is lower than the potential of the first high potential terminal P11, and the potential of the second low potential terminal P22 is lower than the potential of the second high potential terminal P21. The first low potential terminal P12 and the second low potential terminal P22 are connected and have the same potential.

[0012] The basic converter circuit 200 includes a first capacitor C1, a second capacitor C2, an inductor L1, a first switch element S1, a second switch element S2, a first gate resistor Rg1, a second gate resistor Rg2, a first drive circuit 11, a second drive circuit 12, and a control circuit 2.

[0013] The first capacitor C1 is connected between the first high potential terminal P11 and the first low potential terminal P12. The second capacitor C2 is connected between the second high potential terminal P21 and the second low potential terminal P22. The first capacitor C1 and the second capacitor C2 are both aluminum electrolytic capacitors, for example.

[0014] The inductor L1 has a first end (left end in FIG. 1) connected to the first high potential terminal P11, and a second end (right end in FIG. 1) connected to the connection point of the first switch element S1 and the second switch element S2.

[0015] The first switch element S1 and the second switch element S2 are both field-effect transistors (FETs) such as normally-off N-channel metal oxide semiconductor field-effect transistors (MOSFETs), and are connected in series. The drain of the first switch element S1 is connected to a second high potential terminal P21, and the source of the second switch element S2 is connected to a first low potential terminal P12 and a second low potential terminal P22. The source of the first switch element S1 and the drain of the second switch element S2 are connected to a second end of the inductor L1. The gate of the first switch element S1 is connected to a first drive circuit 11 via a first gate resistor Rg1, and the gate of the second switch element S2 is connected to a second drive circuit 12 via a second gate resistor Rg2.

[0016] The first drive circuit 11 is an integrated circuit (IC) that receives a first control signal Sig10 from the control circuit 2 and outputs a first drive signal Sig11 for applying a drive voltage between the gate of the first switch element S1 and the source of the first switch element S2 via a first gate resistor Rg1. The first control signal Sig10 is a signal that instructs the first switch element S1 to be turned on or off. In other words, the first drive circuit 11 receives the first control signal Sig10 from the control circuit 2 and outputs the first drive signal Sig11 to drive the first switch element S1.

[0017] Specifically, when the first drive signal Sig11 is at a high level, the gate capacitance (input capacitance) of the first switch element S1 is charged, turning the first switch element S1 on. On the other hand, when the first drive signal Sig11 is at a low level, the charge accumulated in the gate capacitance of the first switch element S1 is discharged, turning the first switch element S1 off.

[0018] The second drive circuit 12 is an IC that receives a second control signal Sig20 from the control circuit 2 and outputs a second drive signal Sig21 for applying a drive voltage between the gate of the second switch element S2 and the source of the second switch element S2 via the second gate resistor Rg2. The second control signal Sig20 is a signal that instructs the second switch element S2 to be turned on or off. In other words, the second drive circuit 12 receives the second control signal Sig20 from the control circuit 2 and drives the second switch element S2.

[0019] Specifically, when the second drive signal Sig21 is at a high level, the gate capacitance (input capacitance) of the second switch element S2 is charged, turning the second switch element S2 on. On the other hand, when the second drive signal Sig21 is at a low level, the charge accumulated in the gate capacitance of the second switch element S2 is discharged, turning the second switch element S2 off.

[0020] The control circuit 2 is realized by, for example, a microcomputer, but may also be realized by a processor or a dedicated circuit. The functions of the control circuit 2 are realized by hardware such as a microcomputer or processor that constitutes the control circuit 2 executing a computer program (software) stored in memory.

[0021] When the basic converter circuit 200 operates as a step-up chopper, the control circuit 2 alternately turns on the first switch element S1 and the second switch element S2 to boost the input voltage. When the basic converter circuit 200 operates as a step-down chopper, the control circuit 2 alternately turns on the first switch element S1 and the second switch element S2 to step down the input voltage. In either case, the control circuit 2 controls the first switch element S1 and the second switch element S2 by PWM (Pulse Width Modulation) control. Specifically, the control circuit 2 adjusts the duty ratio of each of the first control signal Sig10 output to the first drive circuit 11 and the second control signal Sig20 output to the second drive circuit 12, thereby boosting or lowering the input voltage to a desired output voltage.

[0022] Next, a zero voltage switching technique for reducing switching loss of a switching element will be described with reference to Fig. 2 and Fig. 3. Fig. 2 is a waveform diagram when the basic converter circuit 200 operates as a step-up chopper. Fig. 3 is a waveform diagram when the basic converter circuit 200 operates as a step-down chopper.

[0023] 2 and 3, "IL" indicates the inductor current flowing through inductor L1. The inductor current IL is shown as a positive current when it flows from the first terminal to the second terminal of inductor L1. Also, in each of FIGS. 2 and 3, "S1" indicates the drive voltage applied to the gate of the first switch element S1, and "S2" indicates the drive voltage applied to the gate of the second switch element S2. In each of "S1" and "S2," "H" indicates that the drive voltage is at a high level and the switch element is in an on state, and "L" indicates that the drive voltage is at a low level and the switch element is in an off state. Also, in FIG. 2, "Vds2" indicates the drain-source voltage of the second switch element S2, and "IS2" indicates the second current IS2 flowing through the second switch element S2. Also, in FIG. 3, "Vds1" indicates the drain-source voltage of the first switch element S1, and "IS1" indicates the first current IS1 flowing through the first switch element S1. In each of the first current IS1 and the second current IS2, the current flowing from the first switch element S1 to the second switch element S2 is shown as a positive current.

[0024] First, we will explain the boost chopper operation of the basic converter circuit 200. As shown in Fig. 2, during the off period of the first switch element S1 and the on period of the second switch element S2, a closed circuit is formed passing through the power supply 3, inductor L1, and second switch element S2, and the inductor current IL rises. During this period, the second current IS2 flowing through the second switch element S2 also rises.

[0025] Next, when the second switch element S2 is turned off, current stops flowing through the second switch element S2 and the drain-source voltage Vds2 of the second switch element S2 rises. After that, current flows from the source to the drain of the first switch element S1, including the period of the dead time DT1, and is supplied to the load 4. This causes the inductor current IL to start decreasing.

[0026] Next, when the inductor current IL flows from the second terminal to the first terminal, that is, when it becomes a negative current, the first switch element S1 is turned off. Then, during the dead time DT2, the drain-source voltage Vds2 of the second switch element S2 drops due to the charging of the parasitic capacitance (output capacitance) of the first switch element S1 and the discharging of the charge accumulated in the parasitic capacitance (output capacitance) of the second switch element S2.

[0027] After that, after the drain-source voltage Vds2 of the second switch element S2 reaches zero voltage due to the passage of dead time DT2, a current flows from the source to the drain of the second switch element S2, and the inductor current IL starts to rise. At this timing, the second switch element S2 is turned on. This achieves zero-voltage switching, and switching loss is reduced compared to when the second switch element S2 is turned on while the drain-source voltage Vds2 of the second switch element S2 is greater than zero voltage.

[0028] Next, a description will be given of the step-down chopper operation of the basic converter circuit 200. As shown in Fig. 3, during the on period of the first switch element S1 and the off period of the second switch element S2, a closed circuit is formed through the power source 3, the first switch element S1, the inductor L1, and the load 4, and the inductor current IL rises. During this period, the first current IS1 flowing through the first switch element S1 also rises. Note that, since a current flowing from the first terminal to the second terminal of the inductor L1 is considered positive, in Fig. 3 the rise in the inductor current IL is represented by a fall in the current.

[0029] Next, when the first switch element S1 is turned off, current stops flowing through the first switch element S1, and the drain-source voltage Vds1 of the first switch element S1 rises. After that, current flows from the source to the drain of the second switch element S2, including the dead time DT2, and is supplied to the load 4. This causes the inductor current IL to start decreasing. Note that in FIG. 3, the decrease in the inductor current IL is represented by an increase in current.

[0030] Next, when the inductor current IL flows from the first terminal to the second terminal, that is, when it becomes a positive current, the second switch element S2 is turned off. Then, during the dead time DT1, the charge accumulated in the parasitic capacitance (output capacitance) of the first switch element S1 is discharged and the charge is charged to the parasitic capacitance (output capacitance) of the second switch element S2, causing the drain-source voltage Vds1 of the first switch element S1 to drop.

[0031] After that, after the dead time DT1 has elapsed and the drain-source voltage Vds1 of the first switch element S1 reaches zero voltage, current flows from the source to the drain of the first switch element S1, and the inductor current IL begins to rise. At this timing, the first switch element S1 is turned on. This achieves zero-voltage switching, and switching loss is reduced compared to when the first switch element S1 is turned on when the drain-source voltage Vds1 of the first switch element S1 is greater than zero voltage.

[0032] Here, in the step-up chopper operation, the magnitude of the drain-source voltage that drops during the dead time DT2 is expressed by the following formula (1): In formula (1), "ΔV" represents the magnitude of the drain-source voltage that drops, "Coss1" represents the output capacitance of the first switch element S1, "Coss2" represents the output capacitance of the second switch element S2, "IL" represents the magnitude of the inductor current IL, and "t" represents time.

[0033]

number

[0034] Therefore, the condition for zero voltage switching to occur during the dead time DT2 is expressed by the following equation (2): In equation (2), "Vbus" represents the voltage between the second high potential terminal P21 and the second low potential terminal P22 of the basic converter circuit 200, and "tdead" represents the length of the dead time DT2.

[0035]

number

[0036] Here, the following two methods can be considered to realize zero voltage switching.

[0037] The first method theoretically calculates the drive frequency of the basic converter circuit 200 based on the waveform of the inductor current IL that satisfies the above formula (2) while changing the magnitude of the input voltage (or output voltage) and input power (or output power) of the basic converter circuit 200. The second method experimentally determines the drive frequency of the basic converter circuit 200 based on the waveforms of the inductor current IL, the drain-source voltage Vds1 of the first switch element S1, and the drain-source voltage Vds2 of the second switch element S2 that are actually measured while changing the magnitude of the input voltage (or output voltage) and input power (or output power) of the basic converter circuit 200. Either method obtains correlation data between various operating conditions of the basic converter circuit 200 and the drive frequency, making it possible to achieve zero voltage switching by determining the drive frequency with reference to the correlation data according to the desired operating conditions of the basic converter circuit 200.

[0038] The two above-mentioned means are both ideal zero voltage switching, and when either means is used, the inductor current IL has a waveform such as that shown in FIG. 4(a). FIG. 4 is a diagram showing an example of the waveform of the inductor current IL in zero voltage switching. FIG. 4(a) shows an example of the waveform of the inductor current IL when ideal zero voltage switching is performed during boost chopper operation of the basic converter circuit 200. In FIG. 4(a), the solid line shows the waveform of the inductor current IL when the output power is relatively small, and the dashed line shows the waveform of the inductor current IL when the output power is relatively large. The same is true for FIG. 4(b).

[0039] 4(a), the second switch element S2 is turned on when the inductor current IL reaches a threshold value (-1 [A] in this case) regardless of the magnitude of the output power, thereby realizing zero voltage switching. However, in an actual converter circuit, due to variations in the characteristics of the components that make up the converter circuit or variations due to the temperature of the converter circuit (hereinafter also referred to as "variations in the converter circuit"), the drain-source voltage Vds2 of the second switch element S2 may not become zero even when the inductor current IL reaches the threshold value, and zero voltage switching may not be realized.

[0040] To avoid such a situation, for example, as shown in Fig. 4(b), by increasing the threshold of the inductor current IL, it becomes possible to more reliably achieve zero voltage switching regardless of variations in the converter circuit. Fig. 4(b) shows an example of the waveform of the inductor current IL when the threshold of the inductor current IL is increased during boost chopper operation of the basic converter circuit 200. In the example shown in Fig. 4(b), the threshold of the inductor current IL is set to -3 [A].

[0041] However, while increasing the threshold of the inductor current IL makes it easier to achieve zero voltage switching, a new problem arises: the increase in the negative current of the inductor current IL increases losses during synchronous rectification and losses when the switch element is turned off.

[0042] In view of the above, the inventors have come up with the present disclosure.

[0043] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection forms, steps, step order, etc. shown in the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components.

[0044] It should be noted that the drawings are schematic diagrams and are not necessarily strict illustrations. In addition, in the drawings, substantially the same components are denoted by the same reference numerals, and overlapping descriptions may be omitted or simplified.

[0045] [2. Configuration] A converter circuit 100 according to an embodiment will be described below with reference to Fig. 5 and Fig. 6. Fig. 5 is a circuit diagram showing the configuration of the converter circuit 100 according to an embodiment when it operates as a step-up chopper. Fig. 6 is a circuit diagram showing the configuration of the converter circuit 100 according to an embodiment when it operates as a step-down chopper. In the following, a description of the configuration common to the basic converter circuit 200 will be omitted.

[0046] The converter circuit 100 according to the embodiment is a synchronous rectification bidirectional converter circuit. As shown in FIG. 5 , when a power supply 3 is connected between a first high potential terminal P11 and a first low potential terminal P12 and a load 4 is connected between a second high potential terminal P21 and a second low potential terminal P22, the converter circuit 100 performs a boost chopper operation to boost the input voltage supplied from the power supply 3 and output it to the load 4, thereby functioning as a boost converter circuit. On the other hand, as shown in FIG. 6 , when a load 4 is connected between the first high potential terminal P11 and a first low potential terminal P12 and a power supply 3 is connected between the second high potential terminal P21 and a second low potential terminal P22, the converter circuit 100 performs a buck chopper operation to buck the input voltage supplied from the power supply 3 and output it to the load 4, thereby functioning as a buck converter circuit.

[0047] In addition to the configuration of the basic converter circuit 200, the converter circuit 100 further includes a first detection circuit 51, a second detection circuit 52, a first OR circuit 71, a second OR circuit 72, a first detection resistor Rd1, and a second detection resistor Rd2.

[0048] The first detection resistor Rd1 is connected between the second end of the inductor L1 and the source of the first switch element S1 and is used to detect the current flowing through the first switch element S1. The second detection resistor Rd2 is connected between the source of the second switch element S2 and the connection point of the first low potential terminal P12 and the second low potential terminal P22 and is used to detect the current flowing through the second switch element S2.

[0049] The first detection circuit 51 is a circuit for detecting a reverse current flowing through the first detection resistor Rd1, in other words, a current flowing through the first switch element S1 in a direction from the second switch element S2 to the first switch element S1. When a reverse current flows through the first detection resistor Rd1, the first detection circuit 51 outputs a first interrupt on signal Sig1 for turning on the first switch element S1.

[0050] The second detection circuit 52 is a circuit for detecting a reverse current flowing through the second detection resistor Rd2, in other words, a current flowing through the second switch element S2 in a direction from the second switch element S2 to the first switch element S1. When a reverse current flows through the second detection resistor Rd2, the second detection circuit 52 outputs a second interrupt on signal Sig2 for turning on the second switch element S2.

[0051] In the following, when the converter circuit 100 performs a boost chopper operation as shown in FIG.

[0052] In this case, when the main detection circuit 5 (second detection circuit 52) ​​detects that the voltage (drain-source voltage of the second switch element S2) applied to the main switch element (second switch element S2), which is either the first switch element S1 or the second switch element S2, becomes zero, the main detection circuit 5 (second detection circuit 52) ​​outputs an interrupt-on signal (second interrupt-on signal Sig2) for turning on the main switch element. In the embodiment, the main detection circuit 5 (second detection circuit 52) ​​detects that the voltage applied to the main switch element (drain-source voltage of the second switch element S2) becomes zero by detecting the current flowing through the main switch element (second switch element S2) in the direction from the second switch element S2 to the first switch element S1.

[0053] In this case, when the sub-detection circuit 6 (first detection circuit 51) detects a current flowing in a direction from the second switch element S2 to the first switch element S1 through a sub-switch element (first switch element S1) that is different from the main switch element of the first switch element S1 and the second switch element S2, the sub-detection circuit 6 (first detection circuit 51) outputs an interrupt-on signal (first interrupt-on signal Sig1) for turning on the sub-switch element.

[0054] On the other hand, when the converter circuit 100 performs a step-down chopper operation as shown in FIG. 6, the first detection circuit 51 functions as the main detection circuit 5, and the second detection circuit 52 functions as the sub-detection circuit 6.

[0055] In this case, when the main detection circuit 5 (first detection circuit 51) detects that the voltage applied to the main switching element (first switching element S1) (the drain-source voltage of the first switching element S1) becomes zero, it outputs an interrupt-on signal (first interrupt-on signal Sig1) for turning on the main switching element. In the embodiment, the main detection circuit 5 (first detection circuit 51) detects that the voltage applied to the main switching element (the drain-source voltage of the first switching element S1) becomes zero by detecting the current flowing through the main switching element (first switching element S1) in the direction from the second switching element S2 to the first switching element S1.

[0056] In this case, when the sub-detection circuit 6 (second detection circuit 52) ​​detects a current flowing through the sub-switching element (second switching element S2) in a direction from the second switching element S2 to the first switching element S1, it outputs an interrupt-on signal (second interrupt-on signal Sig2) to turn on the sub-switching element.

[0057] Here, a specific configuration example of the second detection circuit 52 will be described with reference to FIG. 7. FIG. 7 is a circuit diagram showing a specific configuration of the second detection circuit 52. Note that, regarding the configuration of the first detection circuit 51, in the following description and FIG. 7, the "second detection circuit 52" can be read as the "first detection circuit 51," the "second switch element S2" as the "first switch element S1," the "second current IS2" as the "first current IS1," the "second detection resistor Rd2" as the "first detection resistor Rd1," the "second gate resistor Rg2" as the "first gate resistor Rg1," the "second OR circuit 72" as the "first OR circuit 71," the "second interrupt-on signal Sig2" as the "first interrupt-on signal Sig1," and the "second drive signal Sig21" as the "first drive signal Sig11."

[0058] FIG. 7A shows a circuit diagram of the second detection circuit 52 including a comparator circuit 5A that compares the voltage drop across the second detection resistor Rd2 with a predetermined value. In other words, in the example shown in FIG. 7A, the main detection circuit 5 (second detection circuit 52) ​​includes a comparator circuit 5A that compares the voltage drop across the detection resistor (second detection resistor Rd2) through which the current to be detected flows with a predetermined value. The comparator circuit 5A compares the voltage drop across the first end (the lower end in FIG. 7A) of the second detection resistor Rd2 with a voltage value set arbitrarily by a voltage divider circuit. When the voltage drop across the first end exceeds the predetermined voltage, i.e., when the reverse current flowing through the second detection resistor Rd2 exceeds the predetermined value, the comparator circuit 5A outputs a second interrupt on signal Sig2.

[0059] FIG. 7B shows a circuit diagram of the second detection circuit 52 including a non-inverting amplifier circuit 5B that amplifies the voltage drop across the second detection resistor Rd2 by a predetermined factor. In other words, in the example shown in FIG. 7B, the main detection circuit 5 (second detection circuit 52) ​​includes a non-inverting amplifier circuit 5B that amplifies the voltage drop across the detection resistor (second detection resistor Rd2) through which the current to be detected flows by a predetermined factor. The non-inverting input terminal of the non-inverting amplifier circuit 5B is connected to the first end (the lower end in FIG. 7A) of the second detection resistor Rd2, and the inverting input terminal is connected to the second end (the upper end in FIG. 7A) of the second detection resistor Rd2 via a resistor that determines the amplification factor. Therefore, when a reverse current flows through the second detection resistor Rd2, the non-inverting amplifier circuit 5B amplifies the potential difference (positive potential difference) across the second detection resistor Rd2, thereby outputting a second interrupt-on signal Sig2.

[0060] FIG. 7C shows a circuit diagram of the second detection circuit 52 including an inverting amplifier circuit 5C that amplifies the voltage drop across the second detection resistor Rd2 by a predetermined factor. In other words, in the example shown in FIG. 7C, the main detection circuit 5 (second detection circuit 52) ​​includes an inverting amplifier circuit 5C that amplifies the voltage drop across the detection resistor (second detection resistor Rd2) through which the current to be detected flows by a predetermined factor. The non-inverting input terminal of the inverting amplifier circuit 5C is connected to the first end (the lower end in FIG. 7A) of the second detection resistor Rd2, and the inverting input terminal is connected to the second end (the upper end in FIG. 7A) of the second detection resistor Rd2 via a resistor that determines the amplification factor. Therefore, when a reverse current flows through the second detection resistor Rd2, the inverting amplifier circuit 5C inverts and amplifies the potential difference (negative potential difference) across the second detection resistor Rd2, thereby outputting a second interrupt on signal Sig2.

[0061] As shown in FIG. 5, when the first drive signal Sig11 or the first interrupt-on signal Sig1 is input, the first OR circuit 71 applies a drive voltage to the gate of the first switch element S1 via the first gate resistor Rg1, thereby turning on the first switch element S1.

[0062] That is, the on / off of the first switch element S1 is basically controlled by the first drive signal Sig11 output from the first drive circuit 11 in accordance with the duty ratio of the first control signal Sig10 output from the control circuit 2. When the first interrupt on signal Sig1 is input to the first OR circuit 71, the first switch element S1 turns on regardless of the first drive signal Sig11.

[0063] As shown in FIG. 5, when the second drive signal Sig21 or the second interrupt-on signal Sig2 is input, the second OR circuit 72 applies a drive voltage to the gate of the second switch element S2 via the second gate resistor Rg2, thereby turning on the second switch element S2.

[0064] That is, the second switch element S2 is basically controlled to be turned on / off by the second drive signal Sig21 output from the second drive circuit 12 in accordance with the duty ratio of the second control signal Sig20 output from the control circuit 2. When the second interrupt-on signal Sig2 is input to the second OR circuit 72, the second switch element S2 is turned on regardless of the second drive signal Sig21.

[0065] In the following, when the converter circuit 100 performs a step-up chopper operation as shown in FIG. 5, the second OR circuit 72 functions as the main OR circuit 8, and the first OR circuit 71 functions as the sub-OR circuit 9.

[0066] In this case, when an ON signal (second drive signal Sig21) for turning on the main switch element (second switch element S2) via the control circuit 2 or an interrupt ON signal (second interrupt ON signal Sig2) for the main switch element is input, the main OR circuit 8 (second OR circuit 72) turns on the main switch element.

[0067] In this case, when an ON signal (first drive signal Sig11) for turning on the sub-switch element (first switch element S1) via the control circuit 2 or an interrupt ON signal (first interrupt ON signal Sig1) for the sub-switch element is input, the sub-OR circuit 9 (first OR circuit 71) turns on the sub-switch element.

[0068] On the other hand, when the converter circuit 100 performs a step-down chopper operation as shown in FIG. 6, the first OR circuit 71 functions as the main OR circuit 8, and the second OR circuit 72 functions as the sub-OR circuit 9.

[0069] In this case, when an ON signal (first drive signal Sig11) for turning on the main switch element (first switch element S1) via the control circuit 2 or an interrupt ON signal (first interrupt ON signal Sig1) for the main switch element is input, the main OR circuit 8 (first OR circuit 71) turns on the main switch element.

[0070] In this case, when an ON signal (second drive signal Sig21) for turning on the sub-switch element (second switch element S2) via the control circuit 2 or an interrupt ON signal (second interrupt ON signal Sig2) for the sub-switch element is input, the sub-OR circuit 9 (second OR circuit 72) turns on the sub-switch element.

[0071] Here, a specific configuration example of the second OR circuit 72 will be described with reference to FIGS. 8 and 9. FIG. 8 is a circuit diagram showing a specific configuration of the second OR circuit 72. FIG. 9 is a timing chart of the second drive signal Sig21 and the second interrupt-on signal Sig2. Note that, in the following description and FIGS. 8 and 9, the configuration of the first OR circuit 71 can be understood by replacing "second OR circuit 72" with "first OR circuit 71," "second drive circuit 12" with "first drive circuit 11," "second switch element S2" with "first switch element S1," "second gate resistor Rg2" with "first gate resistor Rg1," "second drive signal Sig21" with "first drive signal Sig11," and "second interrupt-on signal Sig2" with "first interrupt-on signal Sig1."

[0072] 8(a) is a diagram showing the configuration of the second OR circuit 72. As shown in FIG. 8(a), the second OR circuit 72 has a first diode D1 and a second diode D2. A second interrupt-on signal Sig2 is input to the anode of the first diode D1, and one end of a second gate resistor Rg2 is connected to the cathode of the first diode D1. Furthermore, a second drive signal Sig21 is input to the anode of the second diode D2, and one end of the second gate resistor Rg2 is connected to the cathode of the second diode D2.

[0073] That is, the second diode D2 has an anode to which an on signal (second drive signal Sig21) for the main switching element (second switching element S2) is input. Also, the first diode D1 has an anode to which an interrupt on signal (second interrupt on signal Sig2) for the main switching element (second switching element S2) is input. The cathodes of the first diode D1 and the second diode D2 are connected to the same output terminal (one terminal of the second gate resistor Rg2).

[0074] 8(b) is a diagram showing the configuration of the second OR circuit 72 and the configuration of the second drive circuit 12. The configuration of the second OR circuit 72 is the same as the configuration shown in FIG. 8(a). As shown in FIG. 8(b), the second drive circuit 12 has a first terminal A1 and a second terminal A2. The first terminal A1 is connected to the anode of the second diode D2 of the second OR circuit 72 and outputs a high-level second drive signal Sig21. The second terminal A2 is connected to the output terminal of the second OR circuit 72 and one end of the second gate resistor Rg2 and forms a path for discharging the charge accumulated in the gate capacitance of the second switch element S2 in synchronization with the low-level second drive signal Sig21.

[0075] That is, the second drive circuit 12 has a first terminal A1 that outputs an ON signal (high-level second drive signal Sig21) and a second terminal A2 that discharges the charge accumulated in the main switch element (second switch element S2) in synchronization with an OFF signal (low-level second drive signal Sig21). As a result, the charge accumulated in the gate capacitance of the second switch element S2 is discharged via the second terminal A2 of the second drive circuit 12 and the second gate resistor Rg2, making it possible to quickly turn off the second switch element S2.

[0076] 9, the second interrupt ON signal Sig2 is input to the second OR circuit 72 before the second drive signal Sig21 is input. That is, in the main OR circuit 8 (second OR circuit 72), the ON signal (second drive signal Sig21) is input later than the interrupt ON signal (second interrupt ON signal Sig2).

[0077] In the embodiment, the on signal (second drive signal Sig21) delays the timing of turning on the main switching element (second switching element S2) to increase the threshold value of the inductor current IL described in [1. Technical Background]. Therefore, if no measures are taken, while it becomes easier to achieve zero voltage switching of the main switching element, there is a problem that an increase in unnecessary inductor current IL increases losses. Therefore, in the embodiment, by turning on the main switching element earlier than the above timing using an interrupt on signal (second interrupt on signal Sig2), it is possible to suppress the increase in unnecessary inductor current IL and reduce losses.

[0078] [Operation] The operation of the converter circuit 100 according to the embodiment will be described below mainly with reference to Fig. 10 and Fig. 2. Fig. 10 is an explanatory diagram of the operation of the converter circuit 100 according to the embodiment. (a) of Fig. 10 is an explanatory diagram of the step-up chopper operation of the converter circuit 100 according to the embodiment, and (b) of Fig. 10 is an explanatory diagram of the step-down chopper operation of the converter circuit 100 according to the embodiment.

[0079] First, the boost chopper operation of the converter circuit 100 according to the embodiment will be described. As shown in (a) of Fig. 10, during the on period TS1 of the first switch element S1 (in other words, the off period of the second switch element S2), the inductor current IL drops and the drain-source voltage Vds2 of the second switch element S2 rises (see Fig. 2). When the inductor current IL becomes negative, the first switch element S1 is turned off. Then, due to the accumulation of charge in the parasitic capacitance (output capacitance) of the first switch element S1 and the discharge of the charge accumulated in the parasitic capacitance (output capacitance) of the second switch element S2, the drain-source voltage Vds2 of the second switch element S2 drops (see Fig. 2).

[0080] Thereafter, during dead time DT2 (see FIG. 2), charging of the parasitic capacitance of the first switch element S1 and discharging of the charge accumulated in the parasitic capacitance of the second switch element S2 are completed, and when the drain-source voltage Vds2 of the second switch element S2 reaches zero voltage, the second current IS2 flowing through the second switch element S2 becomes a reverse current, that is, a current flowing from the second switch element S2 to the first switch element S1 (see FIG. 2). The period during which this reverse current is detected corresponds to "TA2" in FIG. 10(a).

[0081] Then, the main detection circuit 5 (second detection circuit 52) ​​detects the reverse current flowing through the second detection resistor Rd2 and outputs a second interrupt-on signal Sig2 for the main switch element (second switch element S2) to the main OR circuit 8 (second OR circuit 72). When the second interrupt-on signal Sig2 is input, the main OR circuit 8 turns on the main switch element. This achieves zero-voltage switching of the main switch element.

[0082] On the other hand, as shown in (a) of Figure 10, during the on period TS2 of the second switch element S2 (in other words, the off period of the first switch element S1), the inductor current IL rises. Then, when the second switch element S2 is turned off, during the dead time DT1 (see Figure 2), a reverse current begins to flow through the body diode of the first switch element S1, that is, a current in the direction from the second switch element S2 to the first switch element S1. The period during which this reverse current is detected corresponds to "TA1" in (a) of Figure 10.

[0083] Then, the sub-detection circuit 6 (first detection circuit 51) detects the reverse current flowing through the first detection resistor Rd1 and outputs a first interrupt-on signal Sig1 for the sub-switching element (first switch element S1) to the sub-OR circuit 9 (first OR circuit 71). When the first interrupt-on signal Sig1 is input, the sub-OR circuit 9 turns on the sub-switching element. This achieves synchronous rectification.

[0084] Next, a description will be given of the step-down chopper operation of the converter circuit 100 according to the embodiment. As shown in (b) of Fig. 10, during the on period TS2 of the second switch element S2 (in other words, the off period of the first switch element S1), the inductor current IL drops and the drain-source voltage Vds1 of the first switch element S1 rises (see Fig. 3). Note that, since a current flowing from the first terminal to the second terminal of the inductor L1 is defined as a positive current, in (b) of Fig. 10, the drop in the inductor current IL is represented by a rise in current.

[0085] When the inductor current IL becomes positive, the second switch element S2 is turned off, and the drain-source voltage Vds1 of the first switch element S1 drops due to the discharge of the charge stored in the parasitic capacitance (output capacitance) of the first switch element S1 and the charging of the parasitic capacitance (output capacitance) of the second switch element S2 (see FIG. 3).

[0086] Thereafter, during dead time DT1 (see FIG. 3), charging of the parasitic capacitance of the first switch element S1 and discharging of the charge accumulated in the parasitic capacitance of the second switch element S2 are completed, and when the drain-source voltage Vds1 of the first switch element S1 reaches zero voltage, the first current IS1 flowing through the first switch element S1 becomes a reverse current, that is, a current flowing from the second switch element S2 to the first switch element S1 (see FIG. 3). The period during which this reverse current is detected corresponds to "TA1" in FIG. 10(b).

[0087] Then, the main detection circuit 5 (first detection circuit 51) detects the reverse current flowing through the first detection resistor Rd1 and outputs a first interrupt-on signal Sig1 for the main switch element (first switch element S1) to the main OR circuit 8 (first OR circuit 71). When the first interrupt-on signal Sig1 is input, the main OR circuit 8 turns on the main switch element. This achieves zero-voltage switching of the main switch element.

[0088] On the other hand, as shown in FIG. 10(b), during the on period TS1 of the first switch element S1 (in other words, during the off period of the second switch element S2), the inductor current IL rises. Note that, since the current flowing from the first terminal to the second terminal of the inductor L1 is considered positive, in FIG. 10(b), the rise of the inductor current IL is represented by a drop in the current. Then, when the first switch element S1 is turned off, during the dead time DT2 (see FIG. 3), a reverse current begins to flow through the body diode of the second switch element S2, that is, a current flowing from the second switch element S2 to the first switch element S1. The period during which this reverse current is detected corresponds to "TA2" in FIG. 10(b).

[0089] Then, the sub-detection circuit 6 (second detection circuit 52) ​​detects the reverse current flowing through the second detection resistor Rd2 and outputs a second interrupt-on signal Sig2 for the sub-switching element (second switch element S2) to the sub-OR circuit 9 (second OR circuit 72). When the second interrupt-on signal Sig2 is input, the sub-OR circuit 9 turns on the sub-switching element. This achieves synchronous rectification.

[0090] [advantage] As described above, in the converter circuit 100 according to the embodiment, when the main detection circuit 5 detects that a reverse current (a current flowing from the second switch element S2 to the first switch element S1) flows through the main switch element and that the voltage (drain-source voltage) applied to the main switch element becomes zero, the main OR circuit 8 turns on the main switch element. Therefore, the converter circuit 100 according to the embodiment can achieve zero-voltage switching of the main switch element regardless of variations in the converter circuit. Furthermore, the converter circuit 100 according to the embodiment can suppress an unnecessary increase in the inductor current IL and reduce losses, compared to when the threshold value of the inductor current IL is increased. In other words, the converter circuit 100 according to the embodiment has the advantage of easily achieving zero-voltage switching while suppressing switching losses.

[0091] Furthermore, in the converter circuit 100 according to the embodiment, the interrupt-on signal output from the main detection circuit 5 is input to the main OR circuit 8 without passing through the control circuit 2. Therefore, in the converter circuit 100 according to the embodiment, the main switching element can be turned on without passing through the control circuit 2, which has the advantage that the main switching element can be turned on more quickly than when the signal passes through the control circuit 2.

[0092] Furthermore, in the converter circuit 100 according to the embodiment, when the sub-detection circuit 6 detects that a reverse current (a current flowing in a direction from the second switch element S2 to the first switch element S1) flows through the sub-switching element, the sub-OR circuit 9 turns on the sub-switching element. Therefore, in the converter circuit 100 according to the embodiment, the sub-switching element can be turned on at an appropriate timing without waiting for the dead time to elapse, thereby achieving synchronous rectification, which has the advantage of reducing loss due to the current flowing through the body diode during the dead time.

[0093] (Variation) Although the embodiment has been described above, the present invention is not limited to the above embodiment. Modifications of the embodiment will be listed below.

[0094] (First Modification) Fig. 11 is a circuit diagram showing the configuration of a converter circuit 100A according to a first modified example of the embodiment. As shown in Fig. 11, the converter circuit 100A according to this modified example is a boost converter circuit that performs boost chopper operation, and differs from the converter circuit 100 according to the embodiment (see Fig. 5) in that it does not include the sub-detection circuit 6 (first detection circuit 51), the first detection resistor Rd1, and the sub-OR circuit 9 (first OR circuit 71).

[0095] (Second Modification) Fig. 12 is a circuit diagram showing the configuration of a converter circuit 100B according to a second modification of the embodiment. As shown in Fig. 12, the converter circuit 100B according to this modification is a step-down converter circuit that performs step-down chopper operation, and differs from the converter circuit 100 according to the embodiment (see Fig. 6) in that it does not include the sub-detection circuit 6 (second detection circuit 52), the second detection resistor Rd2, and the sub-OR circuit 9 (second OR circuit 72).

[0096] As in the first and second modifications, the converter circuit only needs to include the main detection circuit 5, the detection resistor, and the main OR circuit 8.

[0097] (Third Modification) Fig. 13 is a circuit diagram showing the configuration of a converter circuit 100C according to a third modification of the embodiment. As shown in Fig. 13, the converter circuit 100C according to this modification differs from the converter circuit 100 according to the embodiment in that a capacitor C3 is connected to the main detection circuit 5 (here, the second detection circuit 52) ​​as a noise removal element for removing noise.

[0098] The capacitor C3 is inserted between the detection resistor (here, the second detection resistor Rd2) and the main detection circuit 5 (here, the second detection circuit 52). This has the advantage that the converter circuit 100C according to this modification can reduce erroneous detection by the main detection circuit 5 due to noise. Note that the configuration of this modification can also be applied to the sub-detection circuit 6 in the same way.

[0099] (Fourth Modification) Fig. 14 is a circuit diagram showing the configuration of a converter circuit 100D according to a fourth modification of the embodiment. As shown in Fig. 14, the converter circuit 100D according to this modification differs from the converter circuit 100 according to the embodiment in that a limiting element 101 is connected to a main detection circuit 5 (here, the second detection circuit 52) ​​to limit the voltage applied to a detection resistor (here, the second detection resistor Rd2) through which a current to be detected flows.

[0100] The limiting element 101 is configured by a Zener diode and has the function of clamping the voltage applied to the main detection circuit 5 to a predetermined voltage when an excessive current flows through the detection resistor and a voltage higher than a predetermined voltage is applied to the detection resistor. This has the advantage that the converter circuit 100D according to this modification can easily prevent an excessive voltage from being applied to the main detection circuit 5. Note that the configuration of this modification can also be applied to the sub-detection circuit 6 in the same way.

[0101] (Fifth Modification) 15 is a circuit diagram showing a configuration of a converter circuit 100E according to a fifth modification of the embodiment. As shown in FIG. 15, the converter circuit 100E according to this modification differs from the converter circuit 100 according to the embodiment in that it further includes a buffer circuit 102.

[0102] The buffer circuit 102 has an auxiliary isolated power supply 102A, which is a DC power supply, an emitter follower circuit composed of an NPN transistor 102B, and a resistor 102C, the first terminal of which is connected to the source of a main switching element (the second switching element S2 in this case). The collector of the NPN transistor 102B is connected to the auxiliary isolated power supply 102A, and the emitter of the NPN transistor 102B is connected to the second terminal of the resistor 102C and an input terminal of a main OR circuit 8 (the second OR circuit 72 in this case). An interrupt-on signal (the second interrupt-on signal Sig2 in this case) output from the main detection circuit 5 (the second detection circuit 52 in this case) is input to the base of the NPN transistor 102B.

[0103] In the buffer circuit 102, when an interrupt-on signal is input to the base of the NPN transistor 102B, a signal is input from the auxiliary insulated power supply 102A to the main OR circuit 8. That is, the buffer circuit 102 current-amplifies the interrupt-on signal (here, the second interrupt-on signal Sig2) for the main switching element (here, the second switching element S2), and outputs the amplified signal to the main OR circuit 8. This has the advantage that it is easy to ensure a drive current for driving the main switching element. The configuration of this modification can also be applied to the sub-OR circuit 9 in the same way.

[0104] (Sixth Modification) 16 is a circuit diagram showing a configuration of a converter circuit 100F according to a sixth modified example of the embodiment. As shown in FIG. 16, the converter circuit 100F according to this modified example differs from the converter circuit 100 according to the embodiment in that it further includes an isolator 103.

[0105] The isolator 103 is a circuit that electrically insulates the input terminal on the high voltage side from the output terminal on the low voltage side. An interrupt-on signal (here, the second interrupt-on signal Sig2) from the main detection circuit 5 (here, the second detection circuit 52) ​​to the main switch element (here, the second switch element S2) is input to the main OR circuit 8 (here, the second OR circuit 72) via the isolator 103. Therefore, in this modification, it is possible to realize a configuration in which the main OR circuit 8 is disposed in the preceding stage of the drive circuit (here, the second drive circuit 12).

[0106] When the main OR circuit 8 receives a control signal (here, the second control signal Sig20) or an interrupt-on signal (here, the second interrupt-on signal Sig2) output as an on signal from the control circuit 2, it outputs a signal to a drive circuit (here, the second drive circuit 12). In response, the drive circuit outputs a drive signal (here, the second drive signal Sig21) to the main switch element (here, the second switch element S2), thereby turning on the main switch element.

[0107] In this way, in this modification, the main OR circuit 8 (here, the second OR circuit 72) can be arranged in front of the drive circuit (here, the second drive circuit 12), which has the advantage that the drive circuit does not need to have a second terminal A2 for discharging the charge accumulated in the main switch element (here, the second switch element S2). Note that the configuration of this modification can also be applied to the sub-detection circuit 6 and the sub-OR circuit 9 in the same way.

[0108] (Seventh Modification) 17 is a circuit diagram showing the configuration of a converter circuit 100G according to a seventh modification of the embodiment. As shown in Fig. 17, the converter circuit 100G according to this modification differs from the converter circuit 100 according to the embodiment in that it includes a switching circuit 104 that switches on / off the input of an interrupt-on signal (here, the first interrupt-on signal) to the sub-OR circuit 9 (here, the first OR circuit 71).

[0109] The switching circuit 104 is a switch inserted in an input path of an interrupt-on signal to the sub-OR circuit 9, and is configured to be switched on / off by, for example, the control circuit 2. When the switching circuit 104 is on, the sub-OR circuit 9 turns on the sub-switching element (here, the first switching element S1) when an on signal (here, the first drive signal Sig11) or an interrupt-on signal is input. In this case, the sub-OR circuit 9 turns on the sub-switching element without waiting for the dead time to elapse, thereby achieving synchronous rectification while reducing loss during the dead time.

[0110] On the other hand, when the switching circuit 104 is off, only an on signal is input to the sub-OR circuit 9. In this case, the sub-OR circuit 9 waits for the dead time to elapse before turning on the sub-switching element, thereby realizing synchronous rectification while reliably avoiding a situation in which both the first switching element S1 and the second switching element S2 are on.

[0111] As described above, in this modification, the switching circuit 104 can switch whether or not to input the interrupt-on signal to the sub-OR circuit 9, which has the advantage of making it easier to achieve desired synchronous rectification.

[0112] (Other variations) In the above-described embodiment, the main OR circuit 8 and the sub-OR circuit 9 are not limited to circuits having the first diode D1 and the second diode D2 as described above. For example, the main OR circuit 8 and the sub-OR circuit 9 may be realized by a general-purpose logic integrated circuit (IC) that implements an OR gate.

[0113] In the above-described embodiment, the main detection circuit 5 and the auxiliary detection circuit 6 are not limited to circuits that detect when a reverse current flows through the switch element to be detected and the voltage applied to the switch element to be detected becomes zero. For example, the main detection circuit 5 and the auxiliary detection circuit 6 may be configured to detect when the voltage (drain-source voltage) applied to the switch element to be detected becomes zero by monitoring the voltage.

[0114] In addition, the present invention also includes forms obtained by applying various modifications to each embodiment that a person skilled in the art would think of, or forms realized by arbitrarily combining the components and functions of each embodiment within the scope that does not deviate from the spirit of the present invention.

[0115] (summary) As described above, the converter circuits 100, 100A, 100C to 100G according to the first aspect include an inductor L1, a first switch element S1, a second switch element S2, a control circuit 2, a main detection circuit 5, and a main OR circuit 8. The inductor L1 has a first end connected to a high-potential input terminal (first high-potential terminal P11). The first switch element S1 is connected between a second end of the inductor L1 and a high-potential output terminal (second high-potential terminal P21). The second switch element S2 is connected between the second end of the inductor L1 and a low-potential output terminal (second low-potential terminal P22). The control circuit 2 boosts the input voltage by alternately turning on the first switch element S1 and the second switch element S2. When the main detection circuit 5 detects that the voltage applied to one of the first switch element S1 and the second switch element S2 becomes zero, it outputs an interrupt-on signal to turn on the main switch element. When an ON signal for turning on the main switching element via the control circuit 2 or an interrupt ON signal for the main switching element is input, the main OR circuit 8 turns on the main switching element.

[0116] This has the advantage that it is easy to achieve zero voltage switching while suppressing switching losses.

[0117] Furthermore, converter circuits 100, 100B to 100G according to a second aspect include an inductor L1, a first switch element S1, a second switch element S2, a control circuit 2, a main detection circuit 5, and a main OR circuit 8. The inductor L1 has a first end connected to a high-potential output terminal (first high-potential terminal P11). The first switch element S1 is connected between a second end of the inductor L1 and a high-potential input terminal (second high-potential terminal P21). The second switch element S2 is connected between the second end of the inductor L1 and a low-potential input terminal (second low-potential terminal P22). The control circuit 2 drops the input voltage by alternately turning on the first switch element S1 and the second switch element S2. When the main detection circuit 5 detects that the voltage applied to one of the first switch element S1 and the second switch element S2 becomes zero, it outputs an interrupt-on signal to turn on the main switch element. When an ON signal for turning on the main switching element via the control circuit 2 or an interrupt ON signal for the main switching element is input, the main OR circuit 8 turns on the main switching element.

[0118] This has the advantage that it is easy to achieve zero voltage switching while suppressing switching losses.

[0119] In the converter circuits 100 to 100G according to the third aspect, in the first or second aspect, the main detection circuit 5 detects that the voltage applied to the main switching element becomes zero by detecting the current flowing through the main switching element in the direction from the second switching element S2 to the first switching element S1.

[0120] This has the advantage that it is easy to detect by simple means that the voltage applied to the main switching element has become zero.

[0121] In addition, in converter circuits 100 to 100G according to the fourth aspect, in the third aspect, the main detection circuit 5 has a comparator circuit 5A that compares the voltage drop value of a detection resistor (first detection resistor Rd1 or second detection resistor Rd2) through which the current to be detected flows with a predetermined value.

[0122] This has the advantage that a current flowing through the main switch element in a direction from the second switch element S2 to the first switch element S1 can be detected with a simple configuration.

[0123] In addition, in converter circuits 100 to 100G according to the fifth aspect, in the third aspect, the main detection circuit 5 has a non-inverting amplifier circuit 5B that amplifies the voltage drop value of a detection resistor (first detection resistor Rd1 or second detection resistor Rd2) through which the current to be detected flows by a predetermined factor.

[0124] This has the advantage that a current flowing through the main switch element in a direction from the second switch element S2 to the first switch element S1 can be detected with a simple configuration.

[0125] In the converter circuits 100 to 100G according to the sixth aspect, in any one of the first to fifth aspects, the ON signal is input to the main OR circuit 8 with a delay from the interrupt ON signal.

[0126] This has the advantage that it is easy to realize zero voltage switching of the main switching element while suppressing switching loss.

[0127] In the converter circuit 100C according to the seventh aspect, in the third aspect, a noise removal element (capacitor C3) for removing noise is connected to the main detection circuit 5.

[0128] This has the advantage that it is possible to reduce false detections by the main detection circuit 5 due to noise.

[0129] In addition, in the converter circuit 100D according to the eighth aspect, in the third aspect, a limiting element 101 is connected to the main detection circuit 5 to limit the voltage applied to a detection resistor (first detection resistor Rd1 or second detection resistor Rd2) through which the current to be detected flows.

[0130] This has the advantage that it is easy to prevent an excessive voltage from being applied to the main detection circuit 5.

[0131] Moreover, the converter circuit 100E according to a ninth aspect is the converter circuit 100E of any one of the first to eighth aspects, further including a buffer circuit 102 that current-amplifies an interrupt ON signal for the main switch element and outputs the amplified signal to the main OR circuit 8.

[0132] This has the advantage that it is easy to ensure a drive current for driving the main switching element.

[0133] In converter circuits 100 to 100G according to a tenth aspect, in any one of the first to ninth aspects, the main OR circuit 8 has a first diode D1 and a second diode D2. An interrupt ON signal for the main switching element is input to the anode of the first diode D1. An ON signal for the main switching element is input to the anode of the second diode D2. The cathodes of the first diode D1 and the second diode D2 are connected to the same output terminal.

[0134] This has the advantage that the main OR circuit 8 can be realized with a simple configuration.

[0135] In converter circuits 100 to 100G according to an eleventh aspect, in any one of the first to tenth aspects, the on signal for the main switching element is a signal output by a drive circuit (first drive circuit 11 or second drive circuit 12) that drives the main switching element in response to a control signal from the control circuit 2. The drive circuit has a first terminal A1 that outputs the on signal and a second terminal A2 that releases charge accumulated in the main switching element.

[0136] This has the advantage that the main switching element can be turned off more quickly than when the drive circuit does not have the second terminal A2.

[0137] In addition, in a converter circuit 100F according to a twelfth aspect, in any one of the first to eleventh aspects, an interruption ON signal to the main switch element from the main detection circuit 5 is input to the main OR circuit 8 via the isolator 103.

[0138] This has the advantage that the main OR circuit 8 can be placed in the preceding stage of the drive circuit, so the drive circuit does not need to have a terminal (second terminal A2) for discharging the charge accumulated in the main switch element.

[0139] Furthermore, the converter circuits 100, 100C to 100G according to a thirteenth aspect are the same as those of any one of the first to twelfth aspects, and further include a sub-detection circuit 6 and a sub-OR circuit 9. When the sub-detection circuit 6 detects a current flowing through a sub-switching element other than the main switching element, either the first switching element S1 or the second switching element S2, in a direction from the second switching element S2 to the first switching element S1, the sub-detection circuit 6 outputs an interrupt-ON signal for turning on the sub-switching element. When an ON signal for turning on the sub-switching element via the control circuit 2 or an interrupt-ON signal for the sub-switching element is input, the sub-OR circuit 9 turns on the sub-switching element.

[0140] This has the advantage that synchronous rectification can be achieved by turning on the secondary switching element at an appropriate timing without waiting for the dead time to elapse, thereby reducing loss due to current flowing through the body diode during the dead time.

[0141] Moreover, the converter circuit 100G according to the fourteenth aspect is the converter circuit 100G of the thirteenth aspect, further including a switching circuit 104 that switches on / off the input of the interrupt-on signal to the sub-OR circuit 9.

[0142] This has the advantage that the switching circuit 104 can switch whether or not the interrupt-on signal is input to the sub-OR circuit 9, making it easier to achieve desired synchronous rectification. [Explanation of symbols]

[0143] 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G converter circuit 101 Limiting element 102 Buffer circuit 103 Isolator 104 Switching circuit 11 First drive circuit (drive circuit) 12 Second drive circuit (drive circuit) 2. Control circuit 200 Basic converter circuit 5 Main detection circuit 5A comparator circuit 5B Non-inverting amplifier circuit 6 Sub-detection circuit 8 Main OR circuit 9 Sub-OR circuit A1 First terminal A2 2nd terminal C3 Capacitor (noise elimination element) D1 First diode D2 Second diode L1 inductor P11 First high potential terminal (high potential input terminal, high potential output terminal) P12 First low potential terminal (low potential input terminal, low potential output terminal) P21 Second high potential terminal (high potential input terminal, high potential output terminal) P22 Second low potential terminal (low potential input terminal, low potential output terminal) Rd1 1st detection resistor (detection resistor) Rd2 Second detection resistor (detection resistor) S1 First switch element (main switch element, secondary switch element) S2 Second switch element (main switch element, sub switch element) Sig1, Sig2 Interrupt on signal Sig10, Sig11, Sig20, Sig21 On signal

Claims

1. an inductor having a first end connected to a high potential input terminal; a first switch element connected between the second end of the inductor and a high potential output terminal; a second switch element connected between the second end of the inductor and a low-potential output terminal; a control circuit that boosts an input voltage by alternately turning on the first switch element and the second switch element; a main detection circuit that detects that a voltage applied to a main switch element, which is either the first switch element or the second switch element, becomes zero voltage and outputs an interrupt-on signal for turning on the main switch element; a main OR circuit that turns on the main switching element when an ON signal for turning on the main switching element via the control circuit or an interrupt ON signal for the main switching element is input, The on signal for the main switching element is a signal output by a drive circuit that receives a control signal from the control circuit and drives the main switching element, The drive circuit has a first terminal that outputs the on signal to the main OR circuit, and a second terminal that releases charge accumulated in the main switch element. Converter circuit.

2. an inductor having a first end connected to a high potential output terminal; a first switch element connected between the second end of the inductor and a high potential input terminal; a second switch element connected between the second end of the inductor and a low potential input terminal; a control circuit that drops an input voltage by alternately turning on the first switch element and the second switch element; a main detection circuit that detects that a voltage applied to a main switch element, which is either the first switch element or the second switch element, becomes zero voltage and outputs an interrupt-on signal for turning on the main switch element; a main OR circuit that turns on the main switching element when an ON signal for turning on the main switching element via the control circuit or an interrupt ON signal for the main switching element is input, The on signal for the main switching element is a signal output by a drive circuit that receives a control signal from the control circuit and drives the main switching element, The drive circuit has a first terminal that outputs the on signal to the main OR circuit, and a second terminal that releases charge accumulated in the main switch element. Converter circuit.

3. the main detection circuit detects that the voltage applied to the main switching element becomes zero by detecting a current flowing through the main switching element in a direction from the second switching element to the first switching element.

3. A converter circuit according to claim 1 or 2.

4. The main detection circuit has a comparator circuit that compares a voltage drop value of a detection resistor through which a current to be detected flows with a predetermined value.

4. The converter circuit of claim 3.

5. The main detection circuit has a non-inverting amplifier circuit that amplifies a voltage drop value of a detection resistor through which a current to be detected flows by a predetermined factor.

4. The converter circuit of claim 3.

6. In the main OR circuit, the ON signal is input later than the interrupt ON signal.

3. A converter circuit according to claim 1 or 2.

7. a noise elimination element for eliminating noise is connected to the main detection circuit; 4. The converter circuit of claim 3.

8. a limiting element that limits a voltage applied to a detection resistor through which a current to be detected flows is connected to the main detection circuit; 4. The converter circuit of claim 3.

9. a buffer circuit that amplifies the current of the interrupt ON signal for the main switch element and outputs the amplified signal to the main OR circuit; 3. A converter circuit according to claim 1 or 2.

10. The main OR circuit is a first diode to whose anode the interrupt ON signal for the main switching element is input; a second diode to whose anode the on signal for the main switching element is input; The cathodes of the first diode and the second diode are connected to the same output terminal.

3. A converter circuit according to claim 1 or 2.

11. The interrupt-on signal for the main switch element from the main detection circuit is input to the main OR circuit via an isolator.

3. A converter circuit according to claim 1 or 2.

12. a sub-detection circuit that detects a current flowing through a sub-switching element, which is one of the first switch element and the second switch element and is different from the main switch element, in a direction from the second switch element to the first switch element, and outputs an interrupt-on signal for turning on the sub-switching element; a sub-OR circuit that turns on the sub-switching element when an ON signal for turning on the sub-switching element via the control circuit or an interrupt ON signal for the sub-switching element is input.

3. A converter circuit according to claim 1 or 2.

13. a switching circuit that switches on / off the input of the interrupt-on signal to the sub-OR circuit; 13. A converter circuit as claimed in claim 12.

Images