Power Supply Control Device

Abstract

The occurrence of an abnormality or unusual situation within the power supply control device is communicated to the outside. In a power supply control device provided in a switching power supply device that converts an input voltage (Vin) to an output voltage (Vout) through switching of an output transistor, a switching control circuit stabilizes the output voltage by controlling the switching of the output transistor based on a feedback voltage corresponding to the output voltage. A signal output circuit outputs a signal from a signal output terminal based on the feedback voltage, indicating whether the output voltage is normal or not. The switching control circuit limits the current flowing through the output transistor to a limit current (I LIM When the current flowing through the output transistor reaches the limit current, the signal output circuit outputs a specific signal (Sa) from the signal output terminal, which indicates that the overcurrent protection operation is being performed.

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] Switching power supplies that generate an output voltage from an input voltage are widely used. A power supply control device (power supply IC) is provided in a switching power supply to control its operation, and the power supply control device is often configured in the form of a semiconductor integrated circuit. Patent Document 1 below is an example of a document that discloses a power supply control device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 166389

[0004] [overview] While the power supply control device is performing an output voltage generation operation, some abnormality or peculiar situation may occur inside the power supply control device. It would be beneficial if the occurrence of an abnormality or peculiar situation could be communicated to the outside without requiring an additional terminal or the like.

[0005] A power supply control device according to one aspect of the present disclosure is a power supply control device provided in a switching power supply device configured to convert an input voltage into an output voltage through switching of an output transistor, and includes: a switching control circuit configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage corresponding to the output voltage; a signal output terminal; and a signal output circuit configured to be able to output a signal from the signal output terminal based on the feedback voltage, the signal output circuit indicating whether the output voltage is normal or not. The switching control circuit is configured to be able to perform an overcurrent protection operation to limit the current flowing through the output transistor to a limit current or less, and when the current flowing through the output transistor reaches the limit current, the signal output circuit outputs a specific signal from the signal output terminal indicating the execution of the overcurrent protection operation.

[0006] A power supply control device according to another aspect of the present disclosure is a power supply control device provided in a switching power supply device configured to convert an input voltage into an output voltage through switching of an output transistor, and includes: a switching control circuit configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage corresponding to the output voltage; a signal output terminal; a signal output circuit configured to be able to output a signal from the signal output terminal based on the feedback voltage indicating whether the output voltage is normal; and a temperature detection circuit configured to detect whether a target temperature within the power supply control device falls within a specific temperature range, and when the target temperature falls within the specific temperature range, the signal output circuit outputs a specific signal indicating that the target temperature falls within the specific temperature range from the signal output terminal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an overall configuration diagram of a power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of the power supply control device according to the embodiment of the present disclosure. [Figure 3] FIG. 3 is an explanatory diagram of basic switching control according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is an explanatory diagram of an overcurrent protection operation according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating two comparators provided in a power management circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is an explanatory diagram of multiple temperature ranges defined by a temperature detection circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a timing chart of a power supply control device according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is a timing chart of a power supply control device according to a second example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing chart of a power supply control device according to a third example of an embodiment of the present disclosure. [Figure 10] FIG. 10 is an overall configuration diagram of a power supply device according to a fourth example of an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing an example of a specific signal output from a power-good terminal according to a fifth example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing an example of two types of specific signals output from a power-good terminal according to a fifth example of the embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing a modified connection method between a power-good terminal and a processor according to a fifth example of the embodiment of the present disclosure. [Figure 14] FIG. 14 is a partial modified configuration diagram of a power supply device according to a sixth example of the embodiment of the present disclosure.

[0008] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0009] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having an electric potential of 0 V (zero volts) as a reference, or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0010] A level refers to the level (height) of the electric potential, and for any given signal or voltage, a high level has a higher electric potential than a low level. For any given signal or voltage, a rising edge refers to the transition from a low level to a high level, and a falling edge refers to the transition from a high level to a low level.

[0011] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0012] Hereinafter, for any transistor, the on state and the off state may also be simply expressed as on and off, respectively. Also, for any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period.

[0013] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0014] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0015] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0016] FIG. 1 is an overall configuration diagram of a power supply device 1 according to an embodiment of the present disclosure. The power supply device 1 of FIG. 1 includes a power supply control device 2 that controls the operation of the power supply device 1, and also includes a coil L1, an output capacitor C1, feedback resistors R1 and R2, and a pull-up resistor R3 as discrete components provided external to the power supply control device 2. The processor 3 and load LD shown in FIG. 1 are not components of the power supply device 1, but are provided external to the power supply device 1. The processor 3 is an example of an external device provided external to the power supply control device 2. The processor 3 is connected to the power supply control device 2. The processor 3 is, for example, an MCU (Micro Controller Unit) or an SOC (System on a Chip). Although not clear from FIG. 1, the power supply control device 2 and the processor 3 may be connected in a manner that allows bidirectional communication with each other. For example, an SPI (Serial Peripheral Interface) may be used as an interface for bidirectional communication, or an I / O 2 An interface using C (Inter-Integrated Circuit) or Microwire may also be used.

[0017] Figure 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component (semiconductor device) that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing CS to the outside of the power supply control device 2. The power supply control device 2 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 2 and the type of housing CS of the power supply control device 2 shown in Figure 2 are merely examples, and can be designed as desired.

[0018] The power supply 1 in FIG. 1 is configured as a step-down switching power supply (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from a DC voltage source (not shown). The output voltage Vout is generated at an output terminal OUT. That is, the output terminal OUT is the application terminal (terminal to which the output voltage Vout is applied) of the output voltage Vout. The output voltage Vout is supplied to a load LD connected to the output terminal OUT. Except in a transient state, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12V, the output voltage Vout can be stabilized at a desired positive voltage value (e.g., 3.3V or 5V) less than 12V by adjusting the resistance values ​​of the feedback resistors R1 and R2. The current supplied from the output terminal OUT to the load LD is referred to as the load current Iout. The load current Iout is the output current of the power supply 1. Note that the power supply 1 may be a switching power supply other than a step-down type, such as a step-up or step-down-boost type.

[0019] 1 shows an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, a power-good terminal PG, and an external synchronization terminal CIN as some of the external terminals provided in the power supply control device 2. The power-good terminal PG is an example of a signal output terminal.

[0020] The external configuration of the power supply control device 2 will now be described. An input voltage Vin is supplied to an input terminal IN from a DC voltage source (not shown) provided external to the power supply control device 2. A coil L1 is connected in series between a switch terminal SW and an output terminal OUT. That is, a first terminal of the coil L1 is connected to the switch terminal SW, and a second terminal of the coil L1 is connected to the output terminal OUT. The output terminal OUT is also connected to ground via an output capacitor C1. That is, a first terminal of the output capacitor C1 is connected to the output terminal OUT, and a second terminal of the output capacitor C1 is connected to ground. Furthermore, the output terminal OUT is connected to a first terminal of a feedback resistor R1, a second terminal of the feedback resistor R1 is connected to a first terminal of a feedback resistor R2, and a second terminal of the feedback resistor R2 is connected to ground. A feedback voltage Vfb is generated at a connection node between the feedback resistors R1 and R2. The connection node between the feedback resistors R1 and R2 is connected to a feedback terminal FB, thereby inputting the feedback voltage Vfb to the feedback terminal FB. The ground terminal GND is connected to ground. A current flowing through the coil L1 is referred to as a coil current IL. The coil current IL flowing from the switch terminal SW to the output terminal OUT has a positive polarity.

[0021] The wiring WRpg is a wiring provided outside the power supply control device 2. A first end of the wiring WRpg is connected to the power-good terminal PG, and a second end of the wiring WRpg is connected to the input terminal of the processor 3. The signal on the wiring WRpg is referred to as the signal Spg. The wiring WRpg is a wiring for transmitting the signal Spg to the processor 3. A first end of the pull-up resistor R3 is connected to the application terminal of the power supply voltage VDD (the terminal to which the power supply voltage VDD is applied), and a second end of the pull-up resistor R3 is connected to the wiring WRpg. The power supply voltage VDD is a positive DC voltage. The processor 3 is connected to the application terminal of the power supply voltage VDD and ground and is driven based on the power supply voltage VDD. The power supply voltage VDD may be an output voltage Vout, in which case the first end of the pull-up resistor R3 is connected to the output terminal OUT. In FIG. 1, the external synchronization terminal CIN is open, but the use of the external synchronization terminal CIN will be described later. The power supply control device 2 may not be provided with the external synchronization terminal CIN.

[0022] The following describes the internal configuration of the power supply control device 2. The power supply control device 2 includes an output stage circuit MM, a switching control circuit 10, an oscillator 20, a signal output circuit 30, and a temperature detection circuit 40. In addition to these, the power supply control device 2 is provided with circuits that realize various functions (such as an undervoltage protection circuit, an overvoltage protection circuit, and a reverse current protection circuit), but here we will focus on the circuits MM, 10, 20, 30, and 40.

[0023] The output stage circuit MM includes transistors MH and ML. In the configuration example of FIG. 1, the transistors MH and ML are configured by N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). The transistor MH is provided on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and receives the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore to ground). However, a resistor for current detection may be inserted between the source of the transistor ML and the ground terminal GND.

[0024] The switching of the output stage circuit MM is controlled by a switching control circuit 10. In the switching control of the output stage circuit MM, the transistors MH and ML are switched so that they are alternately turned on and off. The switching control of the output stage circuit MM causes a square-wave switch voltage Vsw to appear at the switch terminal SW. The coil L1 and the output capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw that appears at the switch terminal SW to generate the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generating circuit that divides the output voltage Vout to generate a feedback voltage Vfb that corresponds to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls.

[0025] Alternatively, the output voltage Vout itself may be used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout. The feedback voltage generating circuit (R1, R2) may be provided within the power supply control device 2. In this case, the feedback terminal FB is connected to the output terminal OUT.

[0026] The gates of the transistors MH and ML are supplied with gate signals GH and GL as drive signals from the switching control circuit 10, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. The transistor MH is on when the gate signal GH is at a high level, and is off when the gate signal GH is at a low level. Similarly, the transistor ML is on when the gate signal GL is at a high level, and is off when the gate signal GL is at a low level.

[0027] Basically, the transistors MH and ML are alternately turned on and off, but sometimes both transistors MH and ML are maintained in the off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a both-off state. In the output high state, the transistor MH is on and the transistor ML is off. In the output low state, the transistor MH is off and the transistor ML is on. In the both-off state, both transistors MH and ML are off. The transistors MH and ML are never on at the same time. In the switching control by the switching control circuit 10, alternately turning the transistors M1 and M2 on and off refers to the concept of both-off states being present between the output low state and the output high state, taking into account dead time, etc. Note that at least one of the transistors MH and ML may be provided external to the power supply control device 2. The entire output stage circuit MM may also be provided external to the power supply control device 2 and connected to the power supply control device 2.

[0028] The switching control circuit 10 is connected to the feedback terminal FB and receives a feedback voltage Vfb. Based on the feedback voltage Vfb, the switching control circuit 10 controls the on / off states of the transistors MH and ML by controlling the levels of the gate signals GH and GL, thereby generating a desired output voltage Vout at the output terminal OUT. A reference voltage Vref having a predetermined positive DC voltage value is generated within the power supply control device 2, and the switching control circuit 10 controls the switching of the output stage circuit MM so that the feedback voltage Vfb matches the reference voltage Vref. When the feedback voltage Vfb matches the reference voltage Vref, the output voltage Vout matches a predetermined target voltage Vtg. In other words, based on the feedback voltage Vfb, the switching control circuit 10 controls the switching of the output stage circuit MM so that the output voltage Vout is stabilized at the target voltage Vtg (so as to reduce the difference between the output voltage Vout and the target voltage Vtg).

[0029] The control method for stabilizing the output voltage Vout at the target voltage Vtg is arbitrary. In this embodiment, it is taken as an example that the pulse width modulation method is adopted in the control method. The switching control circuit 10 that adopts the pulse width modulation method controls the output duty of the output stage circuit MM. At this time, the switching control circuit 10 performs feedback control to increase the output duty of the output stage circuit MM if "Vfb < Vref", and to decrease the output duty of the output stage circuit MM if "Vfb > Vref". The output duty of the output stage circuit MM is the ratio of the on-period of the transistor MH to the sum of the on-period and the off-period of the transistor MH. In addition, a pulse frequency modulation method or a constant on-time control method may be adopted in the control method for stabilizing the output voltage Vout at the target voltage Vtg.

[0030] The oscillator 20 generates a clock signal CLK having a predetermined reference frequency fref. The clock signal CLK is a rectangular wave signal having high and low levels alternately. The clock signal CLK is input to the switching control circuit 10.

[0031] In principle, the switching control circuit 10 performs the basic switching control shown in FIG. 3 (exceptions will be described later). The signals SET and RST shown in FIG. 3 are generated within the switching control circuit 10. The signals SET and RST are binary signals each having a high level or a low level. A pulse-width modulated signal is formed by the signals SET and RST. A single pulse-width modulated signal indicating the contents of the signals SET and RST may be generated within the switching control circuit 10. The signals SET and RST generally have a low level. In basic switching control, the switching control circuit 10 generates a rising edge in the signal SET at the timing when a rising edge occurs in the clock signal CLK, and generates a rising edge in the signal RST at a timing based on a feedback control signal (not shown). The feedback control signal is generated by the switching control circuit 10 in response to the error between the feedback voltage Vfb and the reference voltage Vref. The feedback control signal may also be generated based on the magnitude of the coil current IL. The length of each high-level period of the signals SET and RST is very short and is sufficiently shorter than the period of the clock signal CLK. A high level signal SET is a signal that commands the state of the output stage circuit MM to be set to an output high state, and a high level signal RST is a signal that commands the state of the output stage circuit MM to be set to an output low state.

[0032] In basic switching control, the switching control circuit 10 repeats the following unit operation. In this unit operation, the switching control circuit 10 switches the state of the output stage circuit MM from the output low state to the output high state when a rising edge occurs in the signal SET, and then switches the state of the output stage circuit MM from the output high state to the output low state when a rising edge occurs in the signal RST. The switching control circuit 10 controls the output duty of the output stage circuit MM by generating a feedback control signal so that the error between the feedback voltage Vfb and the reference voltage Vref approaches zero. In this way, the signals SET and RST are switching control signals that command and control the state of the output stage circuit MM, and the switching control signal is derived based on at least the feedback voltage Vfb so as to reduce the error between the feedback voltage Vfb and the reference voltage Vref (so that the feedback voltage Vfb matches the reference voltage Vref). The duty of the clock signal CLK is arbitrary.

[0033] The switching control circuit 10 is capable of performing overcurrent protection operation. The overcurrent protection operation will be explained with reference to FIG. 4. Although there may be times when the coil current IL becomes negative during light load (when the load current Iout is considerably small), it is assumed here that the power supply device 1 operates in continuous mode, in which the coil current IL is always positive. When the output stage circuit MM is in the output high state, the coil current IL flows between the drain and source of the transistor MH. Therefore, when the transistor MH is on, the coil current IL is equal to the drain current of the transistor MH. When the output stage circuit MM is in the output low state, the coil current IL flows between the drain and source of the transistor ML.

[0034] During the period when the output stage circuit MM is in the high output state (i.e., the on-state of the transistor MH), the coil current IL gradually increases, and during the period when the output stage circuit MM is in the low output state (i.e., the on-state of the transistor ML), the coil current IL gradually decreases. Due to the overcurrent protection operation, the coil current IL (and therefore the drain current of the transistor MH during the on-state of the transistor MH) is limited to the limit current ILIM The switching control circuit 10 for overcurrent protection detects the magnitude of the coil current IL during the ON period of the transistor MH, and determines whether the coil current IL (and therefore the drain current of the transistor MH) during the ON period of the transistor MH is greater than the limit current I LIM As a signal indicating the monitoring result, the switching control circuit 10 outputs an overcurrent protection signal S OCP Generates a limit current I LIM has a predetermined positive current value.

[0035] The coil current IL can be detected by any method. For example, the switching control circuit 10 can detect the coil current IL during the on-period of the transistor MH based on the on-resistance of the transistor MH, which is known to the power supply control device 2, and the drain-source voltage of the transistor MH. Alternatively, the coil current IL can be detected by detecting the current flowing through a replica transistor connected in parallel to the transistor MH during the on-period of the transistor MH. Alternatively, for example, a shunt resistor (not shown) can be connected in series to the transistor MH, and the coil current IL can be detected based on the voltage drop across the shunt resistor.

[0036] Overcurrent protection signal S OCP is a binary signal having a high level or a low level. In principle, the switching control circuit 10 outputs the overcurrent protection signal S OCP is set to low level, and the coil current IL (and therefore the drain current of the transistor MH) is limited to the limit current I LIM When the overcurrent protection signal S OCP is set to high level for a short time. The coil current IL is limited to the current I LIM During this period, the switching control circuit 10 outputs the overcurrent protection signal S OCP The switching control circuit 10 sets the output stage circuit MM to the high output state in response to the rising edge of the signal SET, and then sets the overcurrent protection signal S OCPWhen a rising edge occurs in the signal RST, the output stage circuit MM is immediately switched from the high output state to the low output state without waiting for the rising edge of the signal RST (i.e., without depending on the switching control signal). After that, when the next rising edge of the signal SET occurs, the switching control circuit 10 sets the output stage circuit MM to the high output state again. By this overcurrent protection operation, the coil current IL (and therefore the drain current of the transistor MH) is limited to the limited current I LIM It is limited to the following:

[0037] The signal output circuit 30 is connected to the power-good terminal PG and outputs a signal Spg from the power-good terminal PG in cooperation with a pull-up resistor R3. The signal output circuit 30 includes an output management circuit 31 and a transistor 32. The transistor 32 is an N-channel MOSFET with an open-drain configuration. That is, the drain of the transistor 32 is connected to the power-good terminal PG, and the source of the transistor 32 is connected to ground. The output management circuit 31 is connected to the gate of the transistor 32 and outputs a high-level or low-level gate signal G to the gate of the transistor 32. 32 Gate signal G 32 has a high level, the transistor 32 is on, and the gate signal G 32 has a low level, the transistor 32 is off. Therefore, the output management circuit 31 applies a low level gate signal G 32 By supplying a high level gate signal G 32 When the transistor 32 is in the off state, the signal Spg has a high level (the level of the power supply voltage VDD), and when the transistor 32 is in the on state, the signal Spg has a low level (the level of 0 V).

[0038] The main process executed by the signal output circuit 30 is an output monitoring process. In the output monitoring process, the output management circuit 31 monitors whether the output voltage Vout is within a predetermined normal voltage range RNG based on the feedback voltage Vfb. NML Determine whether it falls within the normal voltage range RNGNML is a voltage range that is not less than a predetermined normal lower limit voltage V_L and not more than a predetermined normal upper limit voltage V_H. The normal lower limit voltage V_L is lower than the target voltage Vtg, and the normal upper limit voltage V_H is higher than the target voltage Vtg. For example, "V_L = Vtg × (1 - k A )" and "V_H = Vtg × (1 + k A )". Here, k A is a predetermined positive coefficient (e.g., 0.03) that is sufficiently smaller than 1.

[0039] Specifically, the output management circuit 31 may be provided with the comparators 31_H and 31_L shown in FIG. 5. The comparator 31_H compares the feedback voltage Vfb with the determination voltage Vh, and the comparator 31_L compares the feedback voltage Vfb with the determination voltage Vl. Here, the determination voltages Vh and Vl have positive DC voltage values that satisfy "Vl < Vh". A window comparator for determining the validity of "Vl ≤ Vfb ≤ Vh" is formed by the comparators 31_H and 31_L.

[0040] When "Vl ≤ Vfb ≤ Vh" holds, the output management circuit 31 determines that the output voltage Vout falls within the normal voltage range RNG NML (that is, it determines that "V_L ≤ Vout ≤ V_H" holds). In the output monitoring process, when it is determined that the output voltage Vout falls within the normal voltage range RNG NML (that is, during the period when "V_L ≤ Vout ≤ V_H" holds), the output management circuit 31 keeps the signal Spg at a high level by controlling the transistor 32 to be in an off state (however, there are exceptions to be described later). When "Vl ≤ Vfb ≤ Vh" does not hold, the output management circuit 31 determines that the output voltage Vout deviates from the normal voltage range RNG NML (that is, it determines that "V_L ≤ Vout ≤ V_H" does not hold). In the output monitoring process, during the period when it is determined that the output voltage Vout deviates from the normal voltage range RNG NML (that is, during the period when "V_L ≤ Vout ≤ V_H" does not hold), the output management circuit 31 keeps the signal Spg at a low level by controlling the transistor 32 to be in an on state (however, there are exceptions to be described later).

[0041] The processor 3 can recognize whether the output voltage Vout is normal or not based on the level of the signal Spg. A high-level signal Spg derived by the output monitoring process indicates that the output voltage Vout is normal, and a low-level signal Spg derived by the output monitoring process indicates that the output voltage Vout is abnormal (i.e., is not normal). An abnormality in the output voltage Vout refers, for example, to a state in which the error between the output voltage Vout and the target voltage Vtg is greater than the product of the output voltage Vout and a fixed coefficient (e.g., 3%).

[0042] The above-mentioned overcurrent protection signal S OCP is supplied to the output management circuit 31. The output management circuit 31 outputs an overcurrent protection signal S OCP How to use it will be described later.

[0043] The temperature detection circuit 40 detects the temperature at the measurement target position and generates a temperature detection signal Stmp corresponding to the temperature at the measurement target position (detected temperature at the measurement target position). The temperature at the measurement target position is referred to as the target temperature TMP. See FIG. 6. A total of (n+1) temperature ranges TRNG[0] to TRNG[n] are defined in the temperature detection circuit 40. n may be 1 or 2. n may be any integer greater than or equal to 3. The temperature ranges TRNG[0] to TRNG[n] do not overlap with each other. For any integer i, the temperature range TRNG[i+1] is higher than the temperature range TRNG[i]. That is, all temperatures belonging to the temperature range TRNG[i+1] are higher than all temperatures belonging to the temperature range TRNG[i]. The temperature Tb[i] is the boundary temperature between the temperature range TRNG[i-1] and the temperature range TRNG[i]. For any integer i, the temperature Tb[i+1] is higher than the temperature Tb[i].

[0044] The temperature range TRNG[0] is the temperature range below temperature Tb[1]. In other words, all temperatures lower than temperature Tb[1] belong to the temperature range TRNG[0]. The temperature range TRNG[1] is the temperature range equal to or greater than temperature Tb[1] and less than temperature Tb[2]. The temperature range TRNG[2] is the temperature range equal to or greater than temperature Tb[2] and less than temperature Tb[3]. The same applies to the other temperature ranges. In other words, if i represents any natural number less than or equal to (n-1), the temperature range TRNG[i] is the temperature range equal to or greater than temperature Tb[i] and less than temperature Tb[i+1]. The temperature range TRNG[n] is the temperature range equal to or greater than temperature Tb[n]. In other words, all temperatures equal to or greater than temperature Tb[n] belong to the temperature range TRNG[n].

[0045] The temperature detection circuit 40 is provided with a temperature sensor (not shown) for detecting the target temperature TMP. The temperature sensor is placed at the position of the measurement target and, in cooperation with a circuit connected to the temperature sensor, outputs a signal corresponding to the target temperature TMP. For example, the temperature sensor is installed at a position suitable for measuring the temperature of the transistor MH or ML, and in this case, the temperature sensor is placed in close proximity to the transistor MH or ML. A silicon diode can be used as the temperature sensor, and the temperature characteristics of the forward voltage of the diode can be used to detect the target temperature TMP. Instead of the forward voltage of the diode, the base-emitter voltage of a bipolar transistor may be used to detect the target temperature TMP.

[0046] The temperature detection circuit 40 generates a temperature detection signal Stmp based on the output signal of the temperature measuring element. The temperature detection circuit 40 detects to which of the temperature ranges TRNG[0] to TRNG[n] the target temperature TMP belongs based on the output signal of the temperature measuring element, and outputs the detection result as the temperature detection signal Stmp. The temperature detection signal Stmp is a digital signal that indicates to which of the temperature ranges TRNG[0] to TRNG[n] the target temperature TMP belongs. For example, if "n=3", the temperature detection signal Stmp can be formed using a 2-bit digital signal. If "n=3", the temperatures Tb[1], Tb[2], and Tb[3] can be set to 125°C, 150°C, and 175°C, respectively. However, the specific value of the temperature Tb[i] is not limited to this, and n may be a value other than 3.

[0047] Although not shown, the power supply control device 2 is provided with an internal power supply circuit that generates an internal power supply voltage based on the input voltage Vin. Each circuit in the power supply control device 2 is driven based on the input voltage Vin or the internal power supply voltage. The gate signal GL is a signal referenced to the ground potential, while the gate signal GH is a signal referenced to the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, while a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. This predetermined voltage is greater than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0048] Alternatively, the power supply 1 may employ a diode rectification system. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is provided in the power supply 1 as a rectifying element. In this case, only the transistor MH is turned on and off in the switching control of the output stage circuit MM. In either case, the input voltage Vin is converted to the output voltage Vout by switching the transistor MH (output transistor) between on and off in the switching control of the output stage circuit MM.

[0049] Incidentally, even if some abnormality or peculiar situation occurs inside the power supply control device 2 while the power supply control device 2 is executing the operation of generating the output voltage Vout, it is generally not easy to determine this from outside the power supply control device 2. If a dedicated external terminal were provided in the power supply control device 2, the occurrence of an abnormality or peculiar situation could be clearly communicated to the outside, but providing a dedicated external terminal leads to an increase in the component size and cost of the power supply control device 2, and also leads to an increase in the overall size and cost of the power supply device 1.

[0050] The power supply control device 2 according to this embodiment has a function of notifying an external device of the occurrence of various abnormalities or unusual situations, using the power good terminal PG that is originally provided for monitoring the output voltage Vout.

[0051] Below, several specific operational examples, application techniques, modified techniques, etc. related to the above functions will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments shown below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0052] <<First Example>> Describe the first embodiment. Regarding a general power control device, it is difficult to determine whether an overcurrent protection operation has occurred from the outside of the power control device even if the overcurrent protection operation works inside the power control device. If it is possible to determine that the overcurrent protection operation has occurred inside the power control device by an external device of the power control device when the overcurrent protection operation works, it is beneficial. For example, based on the determination content, the designer of the power supply device can lower the input voltage or consider changing the capacitance of the output capacitor so that the overcurrent protection operation is less likely to work. When the overcurrent protection operation works, the power control device 2 in FIG. 1 outputs a signal indicating that fact to an external device (processor 3) using the power good terminal PG. This will be specifically described.

[0053] Assume the situation shown in FIG. 7. In the situation shown in FIG. 7, when the input voltage VIN is maintained at a sufficiently high voltage and the output voltage Vout is stabilized near the target voltage Vtg, the value of the load current Iout changes from the current value I1 to the current value I2 steeply at time t A1 and then drops steeply to the current value I1 at time t A4 (I1 < I2). The average value of the coil current IL gradually increases during the period when the load current Iout has the current value I2. Time t A2 is after time t A1 and before time t A4 . Time t A2 is the time when the coil current IL first reaches the limit current I LIM for the first time while the transistor MH is on. Therefore, at time t A2 , a rising edge occurs in the overcurrent protection signal S OCP , and the state of the output stage circuit MM is immediately switched from the output high state to the output low state by the overcurrent protection operation. Note that the average value of the coil current IL refers to the average value of the coil current IL in each switching period of the output stage circuit MM.

[0054] Even after time t A2 , at a time near time t A4 , time t A3Every time the transistor MH is switched from off to on, the coil current IL increases during the on period of the transistor MH until the limit current I LIM At time t, the state of the output stage circuit MM is immediately switched from the high output state to the low output state by the overcurrent protection operation, regardless of the signal RST (i.e., regardless of the switching control signal). A3 is time t A2 It is a time later than time t A3 is time t A4 It may be earlier than time t A4 It may be later than time t A2 The limit current I of the coil current IL is LIM The first arrival occurs at time t A3 The limit current I of the coil current IL is LIM In the example of Figure 7, j = 4, but j represents any integer greater than or equal to 2, and in reality, it often has an integer value that is sufficiently larger than 2 (for example, several hundred to several tens of thousands). In other words, at time t A2 and t A3 During this time, the coil current IL is limited to the current I LIM Repeated attempts to reach occur, with the number of attempts varying.

[0055] With the transistor MH on, the coil current IL is limited to the current I LIM Whenever OCP In the situation shown in Figure 7, a rising edge occurs at time t A2 and t A3 During this period, an overcurrent protection signal S is output once in each switching period of the output stage circuit MM. OCP A rising edge occurs at the OCP has the same frequency as the frequency of the signal SET (and therefore the same frequency as the switching frequency of transistors MH and ML).

[0056] The output management circuit 31 detects whether the output voltage Vout is within the normal voltage range RNG NML Even if the voltage is within the range, a high-level overcurrent protection signal S OCPIn the situation shown in FIG. A1 From before time t A3 and t A4 After that, the output voltage Vout falls within the normal voltage range RNG NML It is assumed that the value is within the range.

[0057] As a basic operation for output voltage monitoring, the signal output circuit 30 monitors whether the output voltage Vout is within the normal voltage range RNG NML and the coil current IL (the drain current of the transistor MH during the ON period of the transistor MH) is within the limit current I LIM During the period when the output voltage Vout is maintained below the normal voltage range RNG, the signal Spg is maintained at a high level by setting and maintaining the transistor 32 off. NML and the coil current IL (the drain current of the transistor MH during the ON period of the transistor MH) exceeds the limit current I LIM During the period when the voltage Vp is maintained below 1 V, the signal Spg is kept at a low level by setting and maintaining the transistor 32 on.

[0058] However, during the period in which the transistor MH is repeatedly switched off by the overcurrent protection operation (hereinafter referred to as the first OCP duration), the signal output circuit 30 performs an operation of outputting a specific signal Sa indicating that the overcurrent protection operation has been performed as a signal Spg from the power-good terminal PG, prior to the above basic operation. The specific signal Sa is a square wave signal that alternates between high and low levels. At time t in FIG. A2 and t A3 The period between these is an example of the first OCP duration. Note that the rectangular wave signal serving as the signal Spg may have waveform distortion that depends on the value of the pull-up resistor R3 and the capacitance (including parasitic capacitance) added to the wiring WRpg.

[0059] During the first OCP duration, each time the transistor MH is switched from off to on at the rising edge of the signal SET, the coil current IL (the drain current of the transistor MH) increases to the limit current I LIM Therefore, during the first OCP duration, every time the state of the output stage circuit MM is switched from the output low state to the output high state, after switching to the output high state, the state of the output stage circuit MM is switched from the output high state to the output low state by the overcurrent protection operation, regardless of the signal RST (i.e., regardless of the switching control signal).

[0060] During the first OCP duration, the signal output circuit 30 determines whether the output voltage Vout is within the normal voltage range RNG NML Alternatively, the signal output circuit 30 may output a square wave signal (specific signal Sa) having alternating high and low levels as the signal Spg from the power-good terminal PG regardless of whether the output voltage Vout falls within the normal voltage range RNG. NML If the value of the overcurrent protection signal S is exceeded, the overcurrent protection signal S is generated regardless of whether the current time is within the first OCP duration or not. OCP Regardless of the input voltage, the signal Spg may be output at a low level by setting and maintaining the transistor 32 on at all times.

[0061] The specific signal Sa that the signal output circuit 30 can output during the first OCP duration is a signal having a predetermined frequency f X where the predetermined frequency f X may be any frequency set independently of the switching frequency of the output stage circuit MM, or may be a frequency proportional to the switching frequency of the output stage circuit MM. A frequency equal to the switching frequency of the output stage circuit MM also belongs to the frequencies proportional to the switching frequency of the output stage circuit MM.

[0062] In the example of Figure 7, time t A2 and t A3 During the first OCP duration, which corresponds to the period between the first OCP and the second OCP, the output management circuit 31 32is set to a low level in principle to turn off the transistor 32 (thus setting the signal Spg to a high level), and the overcurrent protection signal S OCP Whenever a rising edge occurs in the gate signal G 32 After that, when the on-time Ton has elapsed, the gate signal G 32 Therefore, the overcurrent protection signal S OCP Each time a rising edge occurs in the signal S, the transistor 32 is turned on for the on-time Ton, and the signal Spg is at a low level for the on-time Ton. As a result, the specific signal Sa in the example of FIG. 7 becomes a square wave signal having the same frequency as the switching frequency of the output stage circuit MM. The on-time Ton may be a predetermined fixed time. Alternatively, the overcurrent protection signal S OCP The time during which the signal is at a high level may be the on-time Ton, provided that the on-time Ton is shorter than the switching period of the output stage circuit MM (in other words, the reciprocal of the switching frequency of the output stage circuit MM).

[0063] According to the method of the first embodiment, by referring to the signal Spg, it is possible to determine whether or not overcurrent protection has been activated within the power supply control device 2. Based on the results of this determination, the designer of the power supply device 1 can consider lowering the input voltage Vin or changing the capacitance of the output capacitor C1 to make it more difficult for overcurrent protection to be activated, thereby improving the convenience of the power supply device 1 design.

[0064] <<Second Example>> A second embodiment will be described. The power supply control device 2 is provided with a soft start function. The soft start function is a function that gradually increases the output voltage Vout from 0V toward the target voltage Vtg. The switching control circuit 10 generates a voltage Vss to realize the soft start function. With reference to FIG. 8, the soft start function and the overcurrent protection operation that may be performed in the process of increasing the output voltage Vout from 0V to the target voltage Vtg will be described. In the example of FIG. 8, as time progresses, at time t B0 , t B1 , t B2 , tB3 , t B4 , t B5 However, they will be visited in this order.

[0065] time t B0 Before time t, the supply of the input voltage Vin to the input terminal IN is cut off. B0 The supply of the input voltage Vin to the input terminal IN starts at time t B0 After this, the input voltage Vin supplied to the input terminal IN is sufficiently higher than the target voltage Vtg. B0 The power supply control device 2 starts at time t B0 In the initial sequence operation, the output management circuit 31 outputs the gate signal G 32 3. The transistor 32 is turned on by setting the level of the signal Spg to a high level. By setting the transistor 32 to an on-state, the signal Spg has a low level. Although it is different from the situation shown in FIG. 8, if the overcurrent protection operation is not performed thereafter, the output management circuit 31 will detect the output voltage Vout rising from 0V and reaching the normal lower limit voltage V_L (time t B4 (corresponding to the gate signal G 32 The level of the signal Spg is kept at a high level, and the output voltage Vout is kept within the normal voltage range RNG NML As long as the gate signal G 32 The level of the signal Spg is kept at a high level by keeping the level of the signal Spg at a low level.

[0066] After the initial sequence operation is completed, at time t B1 At time t B1 The switching control by the switching control circuit 10 is stopped until time t B1 The switching control of the output stage circuit MM starts from time t B1 At time t B1It monotonically increases at a predetermined rate of change. However, when the voltage Vss reaches a predetermined upper limit voltage Vss_end, the voltage Vss is maintained at the upper limit voltage Vss_end thereafter. The upper limit voltage Vss_end is higher than the above-described reference voltage Vref.

[0067] As described above, the switching control of the output stage circuit MM is performed so that the feedback voltage Vfb matches the reference voltage Vref. The switching control aiming at "Vfb = Vref" is, in detail, the switching control during the period when "Vss≧Vref" holds. That is, in detail, in the switching control circuit 10, the lower voltage between the reference voltage Vref and the voltage Vss (hereinafter, referred to as the comparison voltage Va for convenience) is compared with the feedback voltage Vfb. The switching control circuit 10 performs switching control of the output stage circuit MM so that the feedback voltage Vfb matches the comparison voltage Va. The switching control circuit 10 performs feedback control to increase the output duty of the output stage circuit MM if "Vfb < Va", and to decrease the output duty of the output stage circuit MM if "Vfb > Va". The above-described feedback control signal is generated by the switching control circuit 10 according to the error between the feedback voltage Vfb and the comparison voltage Va. The switching control circuit 10 controls the output duty by generating a feedback control signal so that the error between the feedback voltage Vfb and the comparison voltage Va approaches zero. Since the switching control aiming at "Vfb = Vss" is performed during the period when "Vss < Vref" holds, the output voltage Vout gradually increases toward the target voltage Vtg. In the example of FIG. 8, before time t B5 "Vss < Vref" holds, and at time t B5 "Vss = Vref" holds, and after time t B5 "Vss > Vref" holds.

[0068] At time t B1 when the switching control of the output stage circuit MM is started, the output voltage Vout gradually increases from 0V while the average value of the coil current IL increases. In the example of FIG. 8, at time t B2 the coil current IL first reaches the limit current I for the first time in a state where the transistor MH is on LIMTherefore, at time t B2 Overcurrent protection signal S OCP When a rising edge occurs in the output stage circuit MM, the state of the output stage circuit MM is instantly switched from the high output state to the low output state by the overcurrent protection operation.

[0069] time t B2 Even after time t B3 Every time the transistor MH is switched from off to on, the coil current IL increases during the on period of the transistor MH until the limit current I LIM At time t, the state of the output stage circuit MM is immediately switched from the high output state to the low output state by the overcurrent protection operation, regardless of the signal RST (i.e., regardless of the switching control signal). B2 The limit current I of the coil current IL is LIM The first arrival occurs at time t B3 The limit current I of the coil current IL is LIM In the example of Figure 8, j = 4, but j represents any integer greater than or equal to 2, and in reality, it often has an integer value that is sufficiently larger than 2 (for example, several hundred to several tens of thousands). In other words, at time t B2 and t B3 During this time, the coil current IL is limited to the current I LIM Repeated attempts to reach occur, with the number of attempts varying.

[0070] With the transistor MH on, the coil current IL is limited to the current I LIM Whenever OCP In the situation shown in Figure 8, a rising edge occurs at time t B2 and t B3 During this period, an overcurrent protection signal S is output once in each switching period of the output stage circuit MM. OCP A rising edge occurs at the OCP has the same frequency as the frequency of the signal SET (and therefore the same frequency as the switching frequency of transistors MH and ML).

[0071] The period from the start time of the switching control of the output stage circuit MM until "Vss = Vref" is established, that is, the time t B1 and t B5 The period between them is referred to as the soft start period. In addition, in the period after the time t A1 shown in the first embodiment (see FIG. 7), "Vss > Vref" is established, so the period after the time t A1 does not correspond to the soft start period.

[0072] During the soft start period, as the voltage Vss rises, the output voltage Vout gradually rises from 0V towards the target voltage Vtg. The output management circuit 31, during the soft start period, can control the transistor 32 to turn off based on the high-level overcurrent protection signal S NML even if the output voltage Vout is below the normal lower voltage V_L which is the lower limit of the normal voltage range RNG OCP . In the situation shown in FIG. 8, the output voltage Vout monotonically rises between the time t B1 and t B5 , "Vout < V_L" is established from the time t B1 to just before reaching the time t B2 and t B3 and passing through them, "Vout = V_L" is established at the time t B4 , "Vref = Vss" and the output voltage Vout reaches the target voltage Vtg at the time t B4 , and after the time t B5 , the output voltage Vout is stabilized at the target voltage Vtg. B5 Afterwards, the output voltage Vout is stabilized at the target voltage Vtg.

[0073] As a basic operation related to output voltage monitoring, the signal output circuit 30 keeps the signal Spg at a high level by setting and maintaining the transistor 32 off during the period when the output voltage Vout is within the normal voltage range RNG NML , and keeps the signal Spg at a low level by setting and maintaining the transistor 32 on during the period when the output voltage Vout deviates from the normal voltage range RNG NML .

[0074] However, during the soft start period, in the period when the switching of the transistor MH to off due to the overcurrent protection operation is repeatedly performed (hereinafter referred to as the second OCP continuous period), the signal output circuit 30 gives priority to the above basic operation and outputs a specific signal Sb indicating that the overcurrent protection operation has been executed from the power good terminal PG as the signal Spg. The specific signal Sb is a rectangular wave signal having alternating high and low levels. The period between times t B2 and t B3 in FIG. 8 is an example of the second OCP continuous period. Note that the rectangular wave signal as the signal Spg may have a waveform distortion depending on the value of the pull-up resistor R3 and the capacitance (including parasitic capacitance) added to the wiring WRpg.

[0075] In the second OCP continuous period, each time the transistor MH is switched from off to on triggered by the rising edge of the signal SET, the coil current IL (the drain current of the transistor MH) reaches the limit current I LIM through the increase of the coil current IL during the on period of the transistor MH. Therefore, in the second OCP continuous period, each time the state of the output stage circuit MM is switched from the output low state to the output high state, after the switching to the output high state, regardless of the signal RST (that is, regardless of the switching control signal), the state of the output stage circuit MM is switched from the output high state to the output low state by the overcurrent protection operation.

[0076] The signal output circuit 30 outputs, from the power good terminal PG as the signal Spg, a rectangular wave signal (therefore the specific signal Sb) having alternating high and low levels even if the output voltage Vout deviates from the normal voltage range RNG NML ("Vout < V_L" holds).

[0077] The specific signal Sb that the signal output circuit 30 can output during the second OCP continuous period may be a rectangular wave signal having a predetermined frequency f X Here, the predetermined frequency f XIt may be an arbitrary frequency set independently of the switching frequency of the output stage circuit MM, or may be a frequency proportional to the switching frequency of the output stage circuit MM. The same frequency as the switching frequency of the output stage circuit MM also belongs to the frequencies proportional to the switching frequency of the output stage circuit MM.

[0078] In the example of FIG. 8, the output management circuit 31 B0 at the time between B1 and time t 32 sets the gate signal G B2 to the high level, and then, by the above basic operation, keeps the gate signal G 32 at the high level until immediately before time t B2 to keep the signal Spg at the low level. This is because "Vout < V_L" holds until the time t B4 after time t B2 and t B3 In the second OCP continuous period corresponding to the period between, the output management circuit 31 according to the example of FIG. 8, every time a rise edge occurs in the overcurrent protection signal S OCP generates a fall edge in the gate signal G 32 and then, when the off time Toff elapses, generates a rise edge in the gate signal G 32 . Therefore, every time a rise edge occurs in the overcurrent protection signal S OCP , the transistor 32 turns off for the off time Toff, so that the signal Spg has the high level for the off time Toff. As a result, the specific signal Sb in the example of FIG. 8 becomes a rectangular wave signal having the same frequency as the switching frequency of the output stage circuit MM. The off time Toff may be a predetermined fixed time. Alternatively, the time during which the overcurrent protection signal S OCP has the high level may be the off time Toff. However, the off time Toff is set to be shorter than the switching period of the output stage circuit MM (in other words, the reciprocal of the switching frequency of the output stage circuit MM).

[0079] In the example of FIG. 8, in response to the rise edge of the overcurrent protection signal S B3 at time t OCP , the gate signal G32 is set to low level for the off time Toff, the coil current IL is always limited to the limit current I LIM Therefore, the overcurrent protection signal S OCP Therefore, the output management circuit 31 maintains the low level at time t B3 Overcurrent protection signal S OCP In response to the rising edge of the gate signal G 32 is set to low level for the off time Toff, and then the output voltage Vout reaches the normal lower limit voltage V_L at time t B4 The gate signal G 32 is kept at a high level. B4 Since the output voltage Vout reaches the normal lower limit voltage V_L at 32 A fall edge occurs at time t B4 After this, the output voltage Vout is within the normal voltage range RNG NML Therefore, the output management circuit 31 receives the gate signal G 32 is maintained at a low level, and as a result, the signal Spg is maintained at a high level. B4 After that, if the situation shown in FIG. 7 occurs, the signal Spg may have a low level according to the method shown in the first embodiment.

[0080] According to the method of the second embodiment, by referring to the signal Spg, it is possible to determine whether or not overcurrent protection has been activated within the power supply control device 2 during the soft start period. Based on the results of this determination, the designer of the power supply device 1 can consider lowering the input voltage Vin or changing the capacitance of the output capacitor C1 to make it more difficult for overcurrent protection to be activated, thereby improving the convenience of the power supply device 1 design.

[0081] <<Third Example>> A third embodiment will be described. The signal output circuit 30 according to the third embodiment can control the level of the signal Spg based on the temperature detection signal Stmp. The temperature detection signal Stmp indicates whether the target temperature TMP falls within a specific temperature range. When the target temperature TMP falls within the specific temperature range, the signal output circuit 30 according to the third embodiment outputs a specific signal Sc indicating that the target temperature TMP falls within the specific temperature range from the power-good terminal PG as the signal Spg.

[0082] The specific temperature range is a combined range of the temperature ranges TRNG[1] to TRNG[n-1] (see FIG. 6). That is, the specific temperature range is a range equal to or higher than temperature Tb[1] and lower than temperature Tb[n].

[0083] As a basic operation for output voltage monitoring, the signal output circuit 30 monitors whether the output voltage Vout is within the normal voltage range RNG NML and the target temperature TMP is below the specific temperature range, the transistor 32 is set and maintained off to keep the signal Spg at a high level, and the output voltage Vout is within the normal voltage range RNG NML During the period when the target temperature TMP deviates from the specified temperature range and falls below the specified temperature range, the signal Spg is kept at a low level by turning on and maintaining the transistor 32. The target temperature TMP falling below the specified temperature range means that the target temperature TMP is lower than the lower limit temperature (Tb[1]) of the specified temperature range.

[0084] However, during a period when the target temperature TMP is within the specific temperature range, the signal output circuit 30 performs an operation of outputting a specific signal Sc indicating that the target temperature TMP is within the specific temperature range as a signal Spg from the power-good terminal PG in priority to the above basic operation. During a period when the target temperature TMP is within the specific temperature range, the signal output circuit 30 outputs the output voltage Vout and the normal voltage range RNG NML Regardless of the relationship between the power-good terminal PG and the specific signal Sc, the specific signal Sc is output as a signal Spg from the power-good terminal PG.

[0085] The signal output circuit 30 may keep the signal Spg at a low level by turning on and maintaining the transistor 32 on during a period when the target temperature TMP exceeds the specific temperature range. Alternatively, during a period when the target temperature TMP exceeds the specific temperature range, the signal output circuit 30 may keep the output voltage Vout and the normal voltage range RNG NML In other words, during a period in which the target temperature TMP exceeds the specific temperature range, the signal output circuit 30 sets the level of the signal Spg based only on the relationship between the output voltage Vout and the normal voltage range RNG NML , the signal Spg can be kept at a high level by setting and maintaining the transistor 32 off, and the output voltage Vout is within the normal voltage range RNG NML If the target temperature TMP exceeds the specific temperature range, it means that the target temperature TMP is higher than the upper limit temperature (Tb[n]) of the specific temperature range.

[0086] The specific signal Sc is a square wave signal that alternates between high and low levels. Note that the square wave signal Spg may have waveform distortion that depends on factors such as the value of the pull-up resistor R3 and the capacitance (including parasitic capacitance) added to the wiring WRpg.

[0087] There are (n-1) types of specific signals Sc. The (n-1) types of specific signals Sc are referred to as specific signals Sc[1] to Sc[n-1]. The specific signals Sc[1] to Sc[n-1] are square wave signals having different frequencies. For any natural number i, the frequency of the specific signal Sc[i+1] is lower than the frequency of the specific signal Sc[i] (however, it is also possible to modify the frequency of the specific signal Sc[i+1] to be higher than the frequency of the specific signal Sc[i]). For any natural number i, when the target temperature TMP falls within the temperature range TRNG[i], the signal output circuit 30 outputs the specific signal Sc[i] from the power-good terminal PG as the signal Spg.

[0088] The frequency of each of the specific signals Sc[1] to Sc[n-1] is proportional to the switching frequency of the output stage circuit MM. The same frequency as the switching frequency of the output stage circuit MM also belongs to the frequency proportional to the switching frequency of the output stage circuit MM. However, the frequency of each of the specific signals Sc[1] to Sc[n-1] may be any frequency set independently of the switching frequency of the output stage circuit MM.

[0089] The signal output circuit 30 may generate the specific signals Sc[1] to Sc[n-1] by dividing the clock signal CLK. As described above, the frequency of the clock signal CLK is the reference frequency fref. For example, when the switching frequency of the output stage circuit MM is equal to the reference frequency fref, the signal output circuit 30 may set the frequency of the specific signal Sc[1] to 1 / 2 of the reference frequency fref (i.e., fref / 2) and the frequency of the specific signal Sc[2] to 1 / 4 of the reference frequency fref (i.e., fref / 4).

[0090] 9 illustrates the output operation of the signal Spg according to the target temperature TMP. In the example of FIG. 9, as time progresses, C0 , t C1 , t C2 , t C3 , t C4 , t B5 are visited in this order. Also, in the example of Figure 9, it is assumed that "n=3". Therefore, in the example of Figure 9, the specific temperature range is a combined range of the temperature ranges TRNG[1] and TRNG[2].

[0091] time t C0 Before time t, the supply of the input voltage Vin to the input terminal IN is cut off. C0 The supply of the input voltage Vin to the input terminal IN starts at time t C0 After this, the input voltage Vin supplied to the input terminal IN is sufficiently higher than the target voltage Vtg. C0 The power supply control device 2 starts at time t C0 In the initial sequence operation, the output management circuit 31 outputs the gate signal G32 The transistor 32 is turned on by setting the level of the signal Spg to a high level. With the transistor 32 turned on, the signal Spg is set to a low level. After this, switching control of the output stage circuit MM is started, and the output voltage Vout gradually rises toward the target voltage Vtg due to the soft start function described in the second embodiment. At time t C1 At this point, the output voltage Vout reaches the normal lower limit voltage V_L, and in response, the signal output circuit 30 outputs the gate signal G 32 By generating a falling edge in the signal Spg, a rising edge is generated in the signal Spg.

[0092] time t C2 The target temperature TMP is lower than the temperature Tb[1] until just before the time t C1 From time t C5 The output voltage Vout is within the normal voltage range RNG NML Therefore, at time t C1 From time t C2 The output control circuit 31 follows the basic operation described above until just before the gate signal G 32 By keeping the level of the signal Spg at a low level, the signal Spg is kept at a high level.

[0093] In the example in Figure 9, time t C2 From time t C3 The target temperature TMP is in the temperature range TRNG[1] until just before time t C3 From time t C4 The target temperature TMP is in the temperature range TRNG[2] until just before time t C4 After that, the target temperature TMP falls within the temperature range TRNG[3]. C2 From time t C3 The specific signal Sc[1] is output as the signal Spg from the power good terminal PG until just before the time t C3 From time t C4 The specific signal Sc[2] is output as the signal Spg from the power-good terminal PG until immediately before the power-good terminal PG.

[0094] When the frequency of the specific signal Sc[1] is set to the frequency (fref / 2), the output management circuit 31 C2 From time t C3 Until just before, the gate signal G 32 This operation of switching between high and low levels is repeated at a frequency (fref / 2), thereby outputting a rectangular wave signal of frequency (fref / 2) from the power good terminal PG as the specific signal Sc[1] and the signal Spg. When the frequency of the specific signal Sc[2] is set to the frequency (fref / 4), the output management circuit 31 C3 From time t C4 Until just before, the gate signal G 32 This switching between high and low levels is repeated at a frequency of (fref / 4), causing a square wave signal of frequency (fref / 4) to be output from the power good terminal PG as the specific signal Sc[2] and the signal Spg.

[0095] The temperature detection signal Stmp is also supplied to the switching control circuit 10, and when the temperature detection signal Stmp indicates that the target temperature TMP is equal to or higher than the temperature Tb[n] (i.e., the target temperature TMP is within the temperature range TRNG[n]), the switching control circuit 10 performs a shutdown operation. In the shutdown operation, the switching control circuit 10 stops the switching control of the output stage circuit MM and keeps the output stage circuit MM in both OFF states. In the example of FIG. 9 where "n=3" is assumed, at time t C4 At time t, the target temperature TMP reaches the temperature Tb[n], and the switching control is stopped by the shutdown operation. As a result, the output voltage Vout quickly drops toward 0 V. C5 When the target temperature TMP is within the temperature range TRNG[n], the signal output circuit 30 outputs the gate signal G 32 Alternatively, in the process of the output voltage Vout decreasing due to the shutdown operation based on the fact that the target temperature TMP belongs to the temperature range TRNG[n], the output voltage Vout falls below the normal lower limit voltage V_L, and the signal output circuit 30 outputs the gate signal G32 The signal Spg can be set to a low level by setting the signal Spg to a high level.

[0096] Although not specifically shown in FIG. 9, when the target temperature TMP drops to a temperature (Tb[3]-ΔHYS) or lower due to the stopping of switching control by the shutdown operation, the switching control circuit 10 may resume switching control. The temperature (Tb[3]-ΔHYS) is lower than the temperature Tb[3] by a predetermined hysteresis temperature (for example, 25°C). The behavior of the signal Spg during the process of the target temperature TMP rising has been described with reference to FIG. 9, but the behavior of the signal Spg during the process of the target temperature TMP falling may be similar. That is, for example, the signal output circuit 30 outputs the gate signal G 32 The operation of switching between high level and low level may be repeated at a frequency (fref / 4), thereby outputting a rectangular wave signal of the frequency (fref / 4) from the power-good terminal PG as the specific signal Sc[2] and the signal Spg. Similarly, for example, the signal output circuit 30 may output the gate signal G 32 The operation of switching between high level and low level may be repeated at a frequency (fref / 2), thereby outputting a rectangular wave signal of frequency (fref / 2) from the power good terminal PG as the specific signal Sc[1] and the signal Spg.

[0097] According to the method of the third embodiment, by referring to the signal Spg, it is possible to determine whether the temperature inside the power supply control device 2 has risen abnormally and to what extent. The designer of the power supply device 1 can use the results of this determination to help with thermal margin design, etc., thereby improving the convenience of the power supply device 1 design.

[0098] The processor 3 may also change the switching frequency of the output stage circuit MM based on the specific signal Sc. For this purpose, the external synchronization terminal CIN is used. By connecting the external synchronization terminal CIN to ground in the power supply device 1, the external synchronization terminal CIN can be constantly supplied with ground potential. When a square wave signal having a constant frequency is not supplied to the external synchronization terminal CIN, such as when the external synchronization terminal CIN is supplied with ground potential, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the clock signal CLK, thereby causing the switching frequency of the output stage circuit MM to match the reference frequency fref, which is the frequency of the clock signal CLK.

[0099] However, in the power supply device 1, the processor 3 may be connected to the external synchronization terminal CIN, and the processor 3 may supply ground potential or an external synchronization signal to the external synchronization terminal CIN. In this case, the processor 3 may fix the potential of the external synchronization terminal CIN at ground potential during the period when the specific signal Sc is not output as the signal Spg, and may supply the external synchronization signal to the external synchronization terminal CIN during the period when the specific signal Sc is output as the signal Spg. Here, the external synchronization signal is a square wave signal that alternates between a high level (the level of the power supply voltage VDD) and a low level (ground level). During the period when the external synchronization signal is supplied to the external synchronization terminal CIN, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the external synchronization signal. When the switching of the output stage circuit MM is controlled in synchronization with the external synchronization signal, the switching frequency of the output stage circuit MM matches the frequency of the external synchronization signal. During the period when the external synchronization signal is supplied to the external synchronization terminal CIN, the switching control circuit 10 may generate a rising edge in the signal SET in synchronization with the rising edge of the external synchronization signal each time a rising edge occurs in the external synchronization signal, or may generate a rising edge in the signal SET in synchronization with the falling edge of the external synchronization signal each time a falling edge occurs in the external synchronization signal.

[0100] During a period in which the processor 3 receives the specific signal Sc[1] as the signal Spg, the processor 3 may supply an external synchronization signal of a first frequency to the external synchronization terminal CIN. Here, the first frequency is lower than the reference frequency fref, which is the frequency of the clock signal CLK, and may be the same as the frequency of the specific signal Sc[1] (e.g., fref / 2, for example). Therefore, by supplying the external synchronization signal of the first frequency to the external synchronization terminal CIN, the switching frequency is lower than the reference frequency fref, and a reduction in switching loss is expected, thereby lowering the target temperature TMP. During a period in which the processor 3 receives the specific signal Sc[2] as the signal Spg, the processor 3 may supply an external synchronization signal of a second frequency to the external synchronization terminal CIN. Here, the second frequency is even lower than the first frequency and may be the same as the frequency of the specific signal Sc[2] (e.g., fref / 4, for example). Therefore, by supplying the external synchronization signal of the second frequency to the external synchronization terminal CIN, the switching frequency is lower than the reference frequency fref and the first frequency, and a reduction in switching loss is expected, thereby lowering the target temperature TMP.

[0101] <<Fourth Example>> A fourth embodiment will now be described. In the fourth embodiment, as shown in FIG. 10 , an external synchronization terminal CIN is connected to a wiring WRpg outside the power supply control device 2, thereby supplying a signal Spg to the external synchronization terminal CIN. As described in the third embodiment, when a square wave signal having a constant frequency is not supplied to the external synchronization terminal CIN, such as when the external synchronization terminal CIN is supplied with ground potential, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the clock signal CLK, thereby causing the switching frequency of the output stage circuit MM to coincide with the reference frequency fref, which is the frequency of the clock signal CLK. During the period when the external synchronization signal is supplied to the external synchronization terminal CIN, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the external synchronization signal. When the switching control of the output stage circuit MM is performed in synchronization with the external synchronization signal, the switching frequency of the output stage circuit MM coincides with the frequency of the external synchronization signal. During the period when the external synchronization signal is supplied to the external synchronization terminal CIN, the switching control circuit 10 may generate a rising edge in the signal SET in synchronization with the rising edge of the external synchronization signal each time a rising edge occurs in the external synchronization signal, or may generate a rising edge in the signal SET in synchronization with the falling edge of the external synchronization signal each time a falling edge occurs in the external synchronization signal.

[0102] In the fourth embodiment, the specific signal Sc is supplied to the external synchronization terminal CIN as an external synchronization signal only during the period in which the specific signal Sc is output from the power-good terminal TG.

[0103] 9, during the period when the specific signal Sc[1] is output from the power-good terminal TG, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the specific signal Sc[1], thereby setting the switching frequency of the output stage circuit MM to the frequency of the specific signal Sc[1] (i.e., for example, fref / 2). During the period when the specific signal Sc[1] is output from the power-good terminal TG, a rising edge can be generated in the signal SET in synchronization with the rising edge of the specific signal Sc[1] (and therefore the signal Spg), or a rising edge can be generated in the signal SET in synchronization with the falling edge of the specific signal Sc[1] each time a falling edge occurs in the specific signal Sc[1]. By setting the switching frequency of the output stage circuit MM to the frequency of the specific signal Sc[1], the switching frequency is lowered below the reference frequency fref, which is expected to reduce switching losses and lower the target temperature TMP.

[0104] Similarly, in the example of FIG. 9, during the period when the specific signal Sc[2] is output from the power-good terminal TG, the switching control circuit 10 controls the switching of the output stage circuit MM in synchronization with the specific signal Sc[2], thereby setting the switching frequency of the output stage circuit MM to the frequency of the specific signal Sc[2] (i.e., for example, fref / 4). During the period when the specific signal Sc[2] is output from the power-good terminal TG, a rising edge may be generated in the signal SET in synchronization with the rising edge of the specific signal Sc[2] each time a rising edge occurs in the specific signal Sc[2] (and therefore the signal Spg), or a rising edge may be generated in the signal SET in synchronization with the falling edge of the specific signal Sc[2] each time a falling edge occurs in the specific signal Sc[2]. By setting the switching frequency of the output stage circuit MM to the frequency of the specific signal Sc[2], the switching frequency is lower than the reference frequency fref and the frequency of the specific signal Sc[1], and a decrease in the target temperature TMP is expected through reduced switching loss.

[0105] <<Fifth Example>> A fifth embodiment will be described. In the third embodiment, the specific signal Sc may be a pulse-width modulated signal. That is, when the target temperature TMP falls within the temperature range TRNG[i], the signal output circuit 30 may output the specific signal Sc[i] shown in FIG. 11 as the signal Spg from the power-good terminal PG.

[0106] The specific signal Sc[i] shown in FIG. PLS The specific signal Sc[i] shown in FIG. 11 has a period Tcyc. The period Tcyc may have a predetermined length. The specific signal Sc[i] shown in FIG. 11 has a pulse width T PLS [i] has a low level, and the pulse width T PLS It is a pulse width modulation signal that has a high level for a time period shorter than [i]. However, in each cycle Tcyc, the pulse width T PLS [i] has a high level, and the pulse width T PLS The specific signal Sc[i] may be a pulse width modulated signal that has a low level for a period of time that is shorter than [i].

[0107] Pulse width T of specific signals Sc[1] to Sc[n] PLS [1]~T PLS [n] are different from each other. Therefore, the processor 3 can determine whether or not the specific signal Sc is output from the power-good terminal PG based on the signal of the wiring WRpg, and when the specific signal Sc is output from the power-good terminal PG, can determine which of the specific signals Sc[1] to Sc[n] the specific signal Sc is. For example, for an arbitrary integer i, as shown in FIG. PLS [i+1] is the pulse width T PLS [i] is longer than the pulse width T PLS [i+1] is the pulse width T PLS It may be shorter than [i].

[0108] As shown in FIG. 13, a low-pass filter 5 may be provided on the wiring connecting the power-good terminal PG and the processor 3. The signal Spg_LPF obtained by passing only the low-frequency components of the signal Spg may be input to the processor 3. In the configuration shown in FIG. 13, the low-pass filter 5 includes a resistor 5a and a capacitor 5b. A first terminal of a pull-up resistor R3 is connected to the terminal to which the power supply voltage VDD is applied. A second terminal of the pull-up resistor R3 is connected to the wiring WRpg and the power-good terminal PG and also to the first terminal of the resistor 5a. A second terminal of the resistor 5a is connected to the first terminal of the capacitor 5b at a node 5c. The second terminal of the capacitor 5b is connected to ground. The signal at the power-good terminal PG is the signal Spg, and the signal at the node 5c is the signal Spg_LPF. The signal Spg_LPF is a DC voltage signal having substantially the average voltage value of the signal Spg. Based on the level (voltage value) of the signal Spg_LPF, the processor 3 can determine whether or not a specific signal Sc is output from the power-good terminal PG, and when a specific signal Sc is output from the power-good terminal PG, can determine which of the specific signals Sc[1] to Sc[n] the specific signal Sc is.

[0109] <<Sixth Example>> A sixth embodiment will now be described.

[0110] Although the power supply 1 in FIG. 1 is a step-down switching power supply (switching regulator), the power supply 1 may also be a step-up switching power supply. A step-up switching power supply generates an output voltage Vout higher than the input voltage Vin by boosting the input voltage Vin. FIG. 14 is a partial configuration diagram of the power supply 1 when the power supply 1 is a step-up switching power supply. When the power supply 1 is a step-up switching power supply, as shown in FIG. 14, a first end of the coil L1 is connected to the input voltage Vin application terminal (the terminal to which the input voltage Vin is applied), a second end of the coil L1 is connected to the drain of the transistor MH and the source of the transistor ML, the source of the transistor MH is connected to ground, and the drain of the transistor ML is connected to the output terminal OUT and also to ground via the output capacitor C1. A switching control circuit 10 controls the switching of the output stage circuit MM (transistors MH and ML are alternately turned on and off) so that the feedback voltage Vfb coincides with the reference voltage Vref. However, during the soft-start period, the switching control circuit 10 controls the switching of the output stage circuit MM so that the feedback voltage Vfb coincides with the voltage Vss (transistors MH and ML are alternately turned on and off). In the configuration of FIG. 14, the transistor ML serving as a rectifying element may be replaced with a synchronous rectifying diode having an anode connected to the drain of the transistor MH and a cathode connected to the output terminal OUT. In either case, the output transistor (MH) is switched on and off during the switching control of the output stage circuit MM, generating an output voltage Vout based on the current (IL) flowing through the coil L1. The power supply device 1 may be a step-up / step-down switching power supply device.

[0111] The power supply device 1 can be mounted in any electrical device. The entire power supply system including the power supply device 1 and the processor 3 can be mounted in any electrical device. The electrical device in question may be an electrical component mounted in a vehicle such as an automobile, a computer device, a home appliance, or an industrial device.

[0112] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0113] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0114] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0115] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0116] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0117] A power supply control device according to one aspect of the present disclosure (see first and second embodiments) is a power supply control device (2) provided in a switching power supply device (1) configured to convert an input voltage (Vin) into an output voltage (Vout) through switching of an output transistor (MH), and includes: a switching control circuit (10) configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage (Vfb) corresponding to the output voltage; a signal output terminal (PG); and a signal output circuit (30) configured to be able to output a signal corresponding to whether the output voltage is normal or not from the signal output terminal based on the feedback voltage, and the switching control circuit controls a current flowing through the output transistor to a limit current (I LIM ) or less, and when the current flowing through the output transistor reaches the limited current, the signal output circuit outputs a specific signal (Sa, Sb) from the signal output terminal indicating the execution of the overcurrent protection operation (first configuration).

[0118] According to the first configuration, an external device to the power supply control device can determine whether overcurrent protection has been activated within the power supply control device. In this case, a specific signal indicating the activation of overcurrent protection can be output using a signal output terminal originally provided for monitoring the output voltage. This prevents increases in component size and cost due to the installation of a dedicated terminal.

[0119] In the power supply control device according to the first configuration, the signal output circuit may be configured (second configuration) to output a signal having a predetermined frequency as the specific signal from the signal output terminal during a period in which the current flowing through the output transistor reaches the limited current each time the output transistor is set on by the switching control.

[0120] In the power supply control device according to the second configuration, the signal output circuit may be configured (third configuration) to output a signal having the same frequency as the switching frequency of the output transistor as the specific signal from the signal output terminal during a period in which the current flowing through the output transistor reaches the limited current each time the output transistor is set on by the switching control.

[0121] In the power supply control device according to the first configuration (see FIG. 7 or FIG. 8), the switching control circuit alternately turns the output transistor on and off in the switching control, and when the current flowing through the output transistor reaches the limit current while the output transistor is being controlled to be on in the switching control, switches the output transistor off by the overcurrent protection operation, and the signal output circuit sets the level of the signal at the signal output terminal to one of two levels, and performs an operation of switching the level of the signal at the signal output terminal from one of the two levels to the other level and then back to one level every time the output transistor is switched off by the overcurrent protection operation, thereby outputting the specific signal from the signal output terminal (fourth configuration).

[0122] In the power supply control device according to any one of the first to third configurations (see FIG. 7), the signal output circuit outputs a signal of a first level from the signal output terminal during a period in which the output voltage is within a normal voltage range and the current flowing through the output transistor is maintained below the limit current, and outputs a signal of a second level from the signal output terminal during a period in which the output voltage deviates from the normal voltage range and the current flowing through the output transistor is maintained below the limit current, and the signal output circuit outputs a signal of a second level from the signal output terminal during a period in which the current flowing through the output transistor reaches the limit current (for example, time t A2 and t A3The fifth configuration may be such that a rectangular wave signal having the first level and the second level alternately is output as the specific signal (Sa) from the signal output terminal during the period between the first level and the second level.

[0123] In the power supply control device according to any one of the first to third configurations (see FIG. 8), the signal output circuit is configured to: B2 and t B3 During the rising process, the signal output circuit outputs a rectangular wave signal having a first level and a second level alternately from the signal output terminal as the specific signal (Sb), and during a period during which the output voltage is lower than the lower limit voltage of the normal voltage range and the current flowing through the output transistor is maintained below the limited current (for example, from time t B1 and t B2 The sixth configuration may be such that a signal at either the first level or the second level is output from the signal output terminal during the period between the first level and the second level.

[0124] A power supply control device according to another aspect of the present disclosure (see Examples 3 to 5) is a power supply control device (2) provided in a switching power supply device (1) configured to convert an input voltage (Vin) into an output voltage (Vout) through switching of an output transistor (MH), and includes: a switching control circuit (10) configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage (Vfb) corresponding to the output voltage; a signal output terminal (PG); a signal output circuit (30) configured to be able to output a signal from the signal output terminal based on the feedback voltage in accordance with whether the output voltage is normal; and a temperature detection circuit (40) configured to detect whether a target temperature (TMP) within the power supply control device falls within a specific temperature range (TRNG[1] to TRNG[n-1]); and when the target temperature falls within the specific temperature range, the signal output circuit outputs a specific signal (Sc) indicating that the target temperature falls within the specific temperature range from the signal output terminal (seventh configuration).

[0125] According to the seventh configuration, an external device of the power supply control device can determine whether the target temperature in the power supply control device falls within a specific temperature range. In this case, a signal output terminal originally provided for monitoring the output voltage can be used to output a specific signal indicating that the target temperature falls within the specific temperature range. This prevents increases in component size and cost due to the installation of a dedicated terminal.

[0126] In the power supply control device according to the seventh configuration (see FIG. 9, etc.), the specific temperature range may be a composite temperature range of multiple temperature ranges including a first temperature range (TRNG[1]) and a second temperature range (TRNG[2]) higher than the first temperature range, the temperature detection circuit detects which of the multiple temperature ranges the target temperature belongs to, and the signal output circuit may be configured (eighth configuration) to output a first specific signal (Sc[1]) from the signal output terminal as the specific signal when the target temperature belongs to the first temperature range, and to output a second specific signal (Sc[2]) different from the first specific signal from the signal output terminal as the specific signal when the target temperature belongs to the second temperature range.

[0127] This makes it possible for an external device to determine which of the multiple temperature ranges that make up the specific temperature range the target temperature belongs to.

[0128] In the power supply control device according to the eighth configuration, the first specified signal and the second specified signal may be signals having frequencies proportional to the switching frequency of the output transistor, and the frequencies of the first specified signal and the second specified signal may be different from each other (ninth configuration).

[0129] In the power supply control device according to the ninth configuration, when the target temperature is lower than the lower limit of the first temperature range, the switching frequency may have a reference frequency (fref), the frequency of the first specified signal is lower than the reference frequency, and the frequency of the second specified signal is even lower than the frequency of the first specified signal (tenth configuration).

[0130] The power supply control device according to the tenth configuration may further include an external synchronization terminal (CIN), and the switching control circuit may be configured such that, when the output signal of the signal output circuit is input to the external synchronization terminal (see FIG. 10), if the first specified signal is output from the signal output terminal, the switching control is performed in synchronization with the first specified signal to set the switching frequency to the frequency of the first specified signal, and when the second specified signal is output from the signal output terminal, the switching control is performed in synchronization with the second specified signal to set the switching frequency to the frequency of the second specified signal (eleventh configuration).

[0131] When the first or second specified signal is output from the signal output terminal, by performing switching control in synchronization with the first or second specified signal, it is expected that the target temperature will be lowered through a reduction in switching loss.

[0132] In the power supply control device according to any of the seventh to eleventh configurations, the signal output circuit may be configured to output a first level signal (e.g., a high level signal) from the signal output terminal during a period when the output voltage is within the normal voltage range and the target temperature is below the specific temperature range, and to output a second level signal (e.g., a low level signal) from the signal output terminal during a period when the output voltage deviates from the normal voltage range and the target temperature is below the specific temperature range, and the signal output circuit may be configured to output a rectangular wave signal having the first level and the second level alternately from the signal output terminal as the specific signal when the target temperature falls within the specific temperature range, regardless of the relationship between the output voltage and the normal voltage range (twelfth configuration). [Explanation of symbols]

[0133] 1 Power supply (switching power supply) 2 Power supply control device 3 processors CS chassis L1 coil C1 Output capacitor R1, R2 feedback resistors R3 pull-up resistor LD load IN input terminal OUT output terminal SW Switch terminal GND Ground terminal FB Feedback terminal PG Power Good pin CIN External synchronization terminal Vin Input voltage Vout Output voltage Vsw Switch voltage Vfb Feedback voltage Vref Reference voltage VDD power supply voltage IL Coil current Iout Load current MM output stage circuit MH, ML, 32 transistors 10 Switching control circuit 20 oscillators 30 Signal output circuit 31 Output management circuit 31_H, 31_L Comparator 40 Temperature detection circuit CLK Clock signal S OCP Overcurrent protection signal SET, RST signal G.H., G.L., G. 32 Gate Signal 5 Low-pass filter 5a resistance 5b capacitor

Claims

1. A power supply control device provided in a switching power supply device configured to convert an input voltage into an output voltage through switching of an output transistor, a switching control circuit configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage corresponding to the output voltage; A signal output terminal; a signal output circuit configured to be able to output a signal corresponding to whether the output voltage is normal or not from the signal output terminal based on the feedback voltage, the switching control circuit is configured to be able to perform an overcurrent protection operation of limiting a current flowing through the output transistor to a limited current or less; When the current flowing through the output transistor reaches the limit current, the signal output circuit outputs a specific signal from the signal output terminal, which indicates that the overcurrent protection operation is to be performed. , power control device.

2. During a period in which the current flowing through the output transistor reaches the limit current each time the output transistor is set to on by the switching control, the signal output circuit outputs a signal having a predetermined frequency as the specific signal from the signal output terminal. The power supply control device according to claim 1 .

3. During a period in which the current flowing through the output transistor reaches the limit current each time the output transistor is set to on by the switching control, the signal output circuit outputs a signal having the same frequency as a switching frequency of the output transistor as the specific signal from the signal output terminal. The power supply control device according to claim 2 .

4. the switching control circuit alternately turns on and off the output transistor in the switching control, and when a current flowing through the output transistor reaches the limit current while the output transistor is being controlled to be on in the switching control, switches off the output transistor through the overcurrent protection operation; The signal output circuit sets the level of the signal at the signal output terminal to one of two levels, and performs an operation of switching the level of the signal at the signal output terminal from one of the two levels to the other level and then returning it to one level every time the output transistor is switched off by the overcurrent protection operation, thereby outputting the specific signal from the signal output terminal. The power supply control device according to claim 1 .

5. the signal output circuit outputs a signal of a first level from the signal output terminal during a period in which the output voltage is within a normal voltage range and the current flowing through the output transistor is maintained below the limit current, and outputs a signal of a second level from the signal output terminal during a period in which the output voltage deviates from the normal voltage range and the current flowing through the output transistor is maintained below the limit current; The signal output circuit outputs a rectangular wave signal having the first level and the second level alternately as the specific signal from the signal output terminal during a period in which the current flowing through the output transistor reaches the limited current every time the output transistor is set to on by the switching control.

4. The power supply control device according to claim 1.

6. the signal output circuit outputs a rectangular wave signal having a first level and a second level alternately as the specific signal from the signal output terminal during a period in which the output voltage is lower than a lower limit voltage of a normal voltage range and the current flowing through the output transistor reaches the limited current each time the output transistor is set to on by the switching control during a process in which the output voltage increases toward the target voltage of the output voltage; The signal output circuit outputs a signal of either the first level or the second level from the signal output terminal during a period in which the output voltage is lower than a lower limit voltage of the normal voltage range and the current flowing through the output transistor is maintained below the limited current during the rising process.

4. The power supply control device according to claim 1.

7. A power supply control device provided in a switching power supply device configured to convert an input voltage into an output voltage through switching of an output transistor, a switching control circuit configured to stabilize the output voltage by controlling the switching of the output transistor based on a feedback voltage corresponding to the output voltage; A signal output terminal; a signal output circuit configured to be able to output a signal from the signal output terminal in accordance with whether the output voltage is normal or not based on the feedback voltage; a temperature detection circuit configured to detect whether a target temperature in the power supply control device falls within a specific temperature range; When the target temperature falls within the specific temperature range, the signal output circuit outputs a specific signal indicating that the target temperature falls within the specific temperature range from the signal output terminal. , power control device.

8. the specific temperature range is a composite temperature range of a plurality of temperature ranges including a first temperature range and a second temperature range higher than the first temperature range, the temperature detection circuit detects to which of the plurality of temperature ranges the target temperature belongs; The signal output circuit outputs a first specified signal from the signal output terminal as the specified signal when the target temperature falls within the first temperature range, and outputs a second specified signal different from the first specified signal from the signal output terminal as the specified signal when the target temperature falls within the second temperature range. The power supply control device according to claim 7 .

9. The first and second specified signals are signals having frequencies proportional to the switching frequency of the output transistor, and the frequencies of the first and second specified signals are different from each other. The power supply control device according to claim 8 .

10. When the target temperature is lower than a lower limit of the first temperature range, the switching frequency has a reference frequency; The frequency of the first specific signal is lower than the reference frequency, and the frequency of the second specific signal is even lower than the frequency of the first specific signal. The power supply control device according to claim 9 .

11. Further provided with an external synchronization terminal, When the output signal of the signal output circuit is input to the external synchronization terminal and the first specified signal is output from the signal output terminal, the switching control circuit performs the switching control in synchronization with the first specified signal to set the switching frequency to the frequency of the first specified signal, and when the second specified signal is output from the signal output terminal, performs the switching control in synchronization with the second specified signal to set the switching frequency to the frequency of the second specified signal. The power supply control device according to claim 10.

12. the signal output circuit outputs a signal of a first level from the signal output terminal during a period when the output voltage is within a normal voltage range and the target temperature is below the specific temperature range, and outputs a signal of a second level from the signal output terminal during a period when the output voltage is outside the normal voltage range and the target temperature is below the specific temperature range; When the target temperature falls within the specific temperature range, the signal output circuit outputs a rectangular wave signal having the first level and the second level alternately as the specific signal from the signal output terminal, regardless of the relationship between the output voltage and the normal voltage range.

12. The power supply control device according to claim 7.

Images