communication equipment

Abstract

To adjust a cancellation signal in a short adjustment period. [Solution] A communication device according to an embodiment includes a first generating means, a sharing means, a second generating means, a suppression means, an output means, a filter means, and a determination means. The output means outputs a control signal that controls the amount of change in amplitude and phase for generating a cancellation signal by the second generating means, so that the cancellation signal gradually changes during an adjustment period, and so that the cancellation signal remains constant during a suppression period. The filter means provides the second generating means with frequency components of the control signal that are equal to or lower than a first frequency during the adjustment period, and provides the second generating means with frequency components of the control signal that are equal to or lower than a second frequency that is lower than the first frequency during the suppression period. The determination means inputs a carrier wave to the input terminal during the adjustment period, and determines the amplitude and phase of the cancellation signal to be generated by the second generating means during the suppression period based on the output of the suppression means.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a communication device. [Background technology]

[0002] In communication devices that share an antenna for both transmission and reception, a portion of the transmission signal may be superimposed on the reception signal and enter the reception system. This superimposed transmission signal component may become a self-interference signal, which may cause saturation of the reception system and increase noise, resulting in a deterioration of communication quality. Therefore, a technique is known in which a cancellation signal having an opposite phase to the self-interference signal is generated from a transmission signal, and this cancellation signal is used to cancel out the self-interference signal.

[0003] The self-interference signal varies depending on the surrounding environment, so a carrier wave is transmitted prior to receiving a response signal from a wireless tag to generate a self-interference signal, and a cancellation signal is adjusted to effectively cancel out the self-interference signal. However, until this adjustment of the cancellation signal is completed, communication cannot be performed while canceling out the self-interference signal, so it has been desired to shorten the time required for this adjustment as much as possible. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-244457 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a communication device that can adjust a cancellation signal in a short adjustment period. [Means for solving the problem]

[0006] A communication device according to an embodiment receives a response signal transmitted from a wireless tag that operates using power obtained from a received carrier wave, and includes a first generating means, a sharing means, a second generating means, a suppression means, an output means, a filter means, and a determination means. The first generating means generates a carrier wave. The sharing means receives the carrier wave generated by the first generating means from an input terminal and outputs it from an input / output terminal, and also outputs the signal input from the input / output terminal from an output terminal. The second generating means generates a cancellation signal by changing the amplitude and phase of the carrier wave generated by the first generating means. The suppression means suppresses a self-interference signal included in the output signal from the output terminal using the cancellation signal generated by the second generating means. The output means outputs a control signal that controls the amount of change in amplitude and phase of the second generating means so as to gradually change the cancellation signal during an adjustment period and to keep the cancellation signal constant during a suppression period. The filter means, during the adjustment period, provides to the second generating means frequency components of the control signal output by the output means that are equal to or lower than a first frequency, and during the suppression period, provides to the second generating means frequency components of the control signal output by the output means that are equal to or lower than a second frequency that is lower than the first frequency. The determination means, during the adjustment period, inputs the carrier wave output by the first generating means to the input terminal, and determines the amplitude and phase of the cancellation signal to be generated by the second generating means during the suppression period based on the output of the suppression means. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram showing the main circuit configuration of a reading device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the circuit configuration of a filter means in FIG. 1; [Figure 3] 10 is a flowchart of a control process. [Figure 4] 10 is a diagram showing an example of a change in one of the I control signal and the Q control signal input to the filter means during a sweep. FIG. [Figure 5] FIG. 10 is a diagram illustrating an example of changes in the phase of a cancellation signal when it is swept. [Figure 6]FIG. 10 is a diagram illustrating an example of changes in the amplitude of a cancellation signal during a sweep. [Figure 7] 10 is a diagram showing an example of a change in one of the I control signal and the Q control signal input to the filter means when a response signal is received. FIG. [Figure 8] FIG. 10 is a diagram illustrating an example of a change in the phase of a cancellation signal when a response signal is received. [Figure 9] FIG. 10 is a diagram illustrating an example of a change in the amplitude of a cancellation signal when a response signal is received. [Figure 10] FIG. 10 is a block diagram showing a modified configuration example of the filter means. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. The following description will be made taking as an example a reading device that reads data stored in an RFID (radio frequency identification) tag. This reading device wirelessly communicates with the RFID tag when reading the data, and is an example of a communication device. The RFID tag is also an example of a wireless tag.

[0009] FIG. 1 is a block diagram showing the main circuit configuration of a reading device 100 according to this embodiment. The reading device 100 includes an oscillator 11, a phase shifter 12, a DA (digital to analog) converter 13, a quadrature modulator 14, a BPF (band-pass filter) 15, a power amplifier 16, an LPF (low-pass filter) 17, an antenna duplexer 18, a feeder line 19, an antenna 20, an amplitude / phase adjustment unit 21, a DA converter 22, a filter unit 23, a power combiner 24, a quadrature detector 25, an LPF 26, an AC (alternating current) coupled amplifier 27, an AD (analog to digital) converter 28, an LPF 29, an AD converter 30, a control unit 31, and a memory 32. The antenna 20, or the feeder line 19 and the antenna 20, may not be included in the reading device 100, and any separate device may be connectable.

[0010] The oscillator 11 generates a sine wave of a predetermined frequency as a carrier wave. Phase shifter 12 shifts the phase of the carrier wave generated by oscillator 11 by 90 degrees, and outputs a cosine wave as another carrier wave. The oscillator 11 and the phase shifter 12 are an example of a first generating means.

[0011] The DA converter 13 converts into analog form the two systems of transmit baseband signals that are output in digital form from the control unit 31. In the following, the two systems of transmit baseband signals are referred to as I signals and Q signals, respectively. The quadrature modulator 14 receives as modulated waves the I and Q signals converted to analog form by the DA converter 13. The quadrature modulator 14 receives as input the carrier wave generated by the oscillator 11 and the carrier wave output from the phase shifter 12 as I and Q system carrier waves, respectively. The quadrature modulator 14 then obtains a transmission signal by quadrature modulation.

[0012] The BPF 15 removes low-frequency components and high-frequency components from the transmission signal obtained by the quadrature modulator 14 in order to limit the band. The power amplifier 16 amplifies the power of the transmission signal that has passed through the BPF 15 to a level suitable for wireless transmission.

[0013] The LPF 17 removes harmonic components from the transmission signal amplified by the power amplifier 16 . The transmission signal becomes a signal for radio transmission through the processes of the BPF 15, power amplifier 16, and LPF 17. That is, the BPF 15, power amplifier 16, and LPF 17 generate a transmission signal for radio transmission.

[0014] The antenna duplexer 18 has an input terminal TI, an input / output terminal TIO, an output terminal TOA, and an output terminal TOB. The transmission signal that has passed through the LPF 17 is input to the input terminal TI. The antenna duplexer 18 outputs the transmission signal input to the input terminal TI from the input / output terminal TIO and the output terminal TOB. The antenna duplexer 18 outputs the signal input to the input / output terminal TIO from the output terminal TOA. The signal output from the output terminal TOA of the antenna duplexer 18 is a signal obtained by combining the received signal generated at the antenna 20 and a self-interference signal, which will be described later, and this signal will be simply referred to as the received signal below. The antenna duplexer 18 is an example of a sharing means.

[0015] The feeder line 19 supplies the transmission signal output from the input / output terminal TIO of the antenna duplexer to the antenna 20. The feeder line 19 transmits the reception signal generated at the antenna 20 to the input / output terminal TIO of the antenna duplexer . The antenna 20 emits radio waves corresponding to the transmission signal supplied by the power supply line 19. The antenna 20 generates an electric signal corresponding to the incoming radio waves as a reception signal.

[0016] The amplitude / phase adjustment unit 21 changes the amplitude and phase of the transmission signal output from the output terminal TOB of the antenna duplexer 18. For example, the amplitude / phase adjustment unit 21 attenuates the I component and Q component of the transmission signal output from the output terminal TOB of the antenna duplexer 18 with individual gains to individually change the signal vectors of each component and then recombine the signals. The gains of the I component and Q component are determined according to the voltage levels of the control signals for the I component and Q component supplied from the filter unit 23. The transmission signal after being attenuated and phase-shifted by the amplitude / phase adjustment unit 21 is hereinafter referred to as a cancellation signal. Thus, the amplitude / phase adjustment unit 21 functions as a second generation means for generating a cancellation signal. The amplitude / phase adjustment unit 21 also has a function to stop outputting the cancellation signal under control of the control unit 31.

[0017] The DA converter 22 converts the control data for the I component and the Q component output from the control unit 31 into analog control signals, and supplies them to the filter unit 23. Note that, hereinafter, the control signal for the I component will be referred to as an I control signal, and the control signal for the Q component will be referred to as a Q control signal.

[0018] The filter unit 23 removes high frequency components from each of the I control signal and Q control signal output from the DA converter 22 in order to remove noise and disturbance noise generated in the DA converter 22, and outputs the low frequency components to be provided to the amplitude / phase adjustment unit 21. The power combiner 24 combines the power of the received signal output from the output terminal TOA of the antenna duplexer 18 with the cancellation signal output from the amplitude / phase adjustment unit 21. In this way, the power combiner 24 reduces the self-interference signal included in the received signal. The power combiner 24 is an example of a suppression means.

[0019] The quadrature detector 25 performs quadrature detection on the received signal output from the power combiner 24 using two carrier waves output from the oscillator 11 and the phase shifter 12. The quadrature detector 25 outputs, in parallel, two systems of analog received baseband signals obtained by quadrature detection. The LPF 26 removes unnecessary frequency components other than the baseband components from each of the two systems of received baseband signals output from the quadrature detector 25 .

[0020] The AC coupling amplifier 27 cuts out the DC component from each of the two systems of received baseband signals that have passed through the LPF 26, while amplifying the AC component that corresponds to the response wave. The LPF 29 removes harmonic components contained in each of the two systems of received baseband signals output from the quadrature detector 25 .

[0021] The AD converter 30 digitizes each of the two systems of received baseband signals output from the LPF 29 . The memory 32 stores an information processing program that describes information processing to be executed by the CPU 311. One of the information processing programs stored in the memory 32 is a control program PRA related to control processing, which will be described later. The memory 32 stores various types of data that are necessary for the CPU 311 to execute various types of information processing. The memory 32 stores various types of data that are generated or acquired when the CPU 311 executes various types of information processing.

[0022] The control unit 31 includes a CPU 311 and an FPGA (field programmable gate array) 312 . When communicating with the RFID tag 200, the CPU 311 outputs an I signal and a Q signal according to a predetermined sequence. The CPU 311 reconstructs the data sent from the RFID tag 200 based on the two systems of received signals digitized by the AD converter 28. The CPU 311 executes information processing, which will be described later, for adjusting the gain and phase shift amount in the amplitude / phase adjustment unit 21 based on the two systems of received baseband signals digitized by the AD converter 30.

[0023] The FPGA 312 performs pre-programmed signal processing to quickly execute various calculations associated with the information processing by the CPU 311. One of the functions of the FPGA 312 is to calculate the amount of suppression of the self-interference signal by the cancellation signal based on the levels of the two systems of received baseband signals digitized by the AD converter 30. Another function of the FPGA 312 is to output control data for controlling the amplitude and phase of the cancellation signal generated by the amplitude / phase adjustment unit 21.

[0024] FIG. 2 is a block diagram showing an example of the circuit configuration of the filter unit 23. As shown in FIG. The filter unit 23 includes filter circuits 231, 232, 233, and 234 and switches 235 and 236. The filter circuit 231 receives the I control signal output from the DA converter 22. The filter circuit 231 passes the low frequency components of the input I control signal. The filter circuit 232 receives the Q control signal output from the DA converter 22. The filter circuit 232 passes the low frequency components of the input Q control signal. The cutoff frequency of the filter circuits 231 and 232 is designated as FCA. The cutoff frequency FCA may be determined as appropriate by, for example, a person who determines the specifications of the reading device 100. The cutoff frequency FCA corresponds to a first frequency. The filter circuits 231 and 232 are each an example of a first filter.

[0025] The I control signal that has passed through the filter circuit 231 is input to the filter circuit 233 via the switch 235. The filter circuit 233 passes the low-frequency components of the input I control signal. The Q control signal that has passed through the filter circuit 231 is input to the filter circuit 234 via the switch 236. The filter circuit 234 passes the low-frequency components of the input Q control signal. The cutoff frequency of the filter circuits 233 and 234 is designated as FCB. The cutoff frequency FCB is smaller than the cutoff frequency FCA. In other words, the filter circuits 233 and 234 do not pass a portion of the frequency components that have passed through the filter circuits 231 and 232. The I control signal and the Q control signal that have passed through the filter circuits 233 and 234 are provided to the amplitude / phase adjustment unit 21 as the output of the filter unit 23. The cutoff frequency FCB may be determined as appropriate by, for example, a person who determines the specifications of the reader 100. The cutoff frequency FCB corresponds to the second frequency. The filter circuits 233 and 234 are each an example of a second filter.

[0026] Switch 235 selectively forms a first path or a second path under the control of CPU 311. When forming the first path, switch 235 takes the state indicated by the dashed line in Fig. 2 and provides the I control signal output from filter circuit 231 to amplitude / phase adjustment unit 21 without passing through filter circuit 233. When forming the second path, switch 235 takes the state indicated by the solid line in Fig. 2 and provides the I control signal output from filter circuit 231 to amplitude / phase adjustment unit 21 via filter circuit 233. Switch 235 is an example of a switching unit.

[0027] Switch 236 selectively forms a first path or a second path under the control of CPU 311. When forming the first path, switch 236 takes the state indicated by the dashed line in Fig. 2 and provides the Q control signal output from filter circuit 232 to amplitude / phase adjustment unit 21 without passing through filter circuit 234. When forming the second path, switch 236 takes the state indicated by the solid line in Fig. 2 and provides the Q control signal output from filter circuit 232 to amplitude / phase adjustment unit 21 via filter circuit 234.

[0028] Next, the operation of the reading device 100 configured as above will be described. Before describing the operation, a self-interference signal will be described. The antenna duplexer 18 is designed so that a transmit signal input to the input terminal TI is not output from the output terminal TOA. However, in an actual circuit configuration, it is difficult to completely prevent the transmit signal input to the input terminal TI from leaking out from the output terminal TOA. For this reason, a portion of the transmit signal input to the input terminal TI is output directly from the output terminal TOA. Furthermore, a portion of the transmit signal output from the input / output terminal TIO of the antenna duplexer 18 is reflected at the feed point of the antenna 20 and transmitted to the antenna duplexer 18 via the feed line 19. This reflected signal is output from the output terminal TOA by the function of the antenna duplexer 18. Thus, the signal output from the output terminal TOA of the antenna duplexer 18 includes a component of the transmit signal that leaks out without being output from the input / output terminal TIO and a component of the transmit signal that is input to the input / output terminal TIO as a reflected signal. The signal resulting from the combination of these transmit signal components is a self-interference signal. The reflection characteristics of the transmit signal at the feed point of the antenna 20 vary depending on the environment surrounding the antenna 20, such as the proximity of the RFID tag 200 and other objects to the antenna 20. Therefore, the amplitude and phase of the signal reflected at the feed point of the antenna 20 also vary depending on the environment around the antenna 20. As a result, the amplitude and phase of the self-interference signal also vary depending on the environment around the antenna 20.

[0029] The self-interference signal is a signal derived from the transmission signal. Therefore, by combining a cancellation signal generated by changing the amplitude and phase of a signal branched from the transmission signal with the reception signal output from the output terminal TOA of the antenna duplexer 18, the self-interference signal contained in the reception signal can be canceled out. In the reader 100, the cancellation signal obtained by changing the amplitude and phase in the amplitude / phase adjustment unit 21 is combined with the reception signal output from the output terminal TOA of the antenna duplexer 18 in the power combiner 24, thereby reducing the self-interference signal contained in the reception signal.

[0030] The amplitude and phase of the self-interference signal fluctuate when there is another metal or the like near the reader 100 and the RFID tag 200, but do not change significantly when there is no such disturbance. In principle, the reader 100 reads the RFID tag 200 in a situation where there are no disturbances (hereinafter referred to as a standard situation). Even if a significant fluctuation in the self-interference signal occurs due to a disturbance, it is assumed that this will be resolved within a short period of time.

[0031] FIG. 3 is a flowchart of the control process. When it becomes necessary to read the RFID tag 200, the CPU 311 executes the control process shown in FIG. 3 based on the control program PRA. In ACT1, the CPU 311 selects the first path as the path in the filter unit 23. That is, the CPU 311 controls the switches 235 and 236 of the filter unit 23 to be in the selected state indicated by the dashed lines in FIG.

[0032] In ACT2, the CPU 311 starts transmitting the carrier wave. That is, the CPU 311 puts the quadrature modulator 14 into a state in which the carrier wave output from the oscillator 11 and the phase shifter 12 is output as is. In ACT3, the CPU 311 stops the cancellation of the self-interference signal. That is, the CPU 311 stops the output of the cancellation signal from the amplitude / phase adjuster 21, for example.

[0033] In ACT4, the CPU 311 measures the amplitude and phase of the self-interference signal. At this time, the reader 100 transmits a carrier wave, but the RFID tag 200 does not activate and does not transmit a response signal until the power obtained by rectifying this carrier wave exceeds the activation power. Therefore, only the self-interference signal is input to the quadrature detector 25. Since cancellation is stopped, the output signal of the quadrature detector 25 changes in level depending on the self-interference signal. Therefore, the FPGA 312 performs predetermined arithmetic processing on the two systems of digital received baseband signals output from the AD converter 30 to determine the amplitude and phase of the self-interference signal. As ACT4, the CPU 311 acquires the amplitude and phase determined by the FPGA 312 as described above.

[0034] In ACT 5, the CPU 311 starts cancellation, that is, the CPU 311 causes the amplitude / phase adjuster 21 to start outputting a cancellation signal. As ACT6, the CPU 311 changes the voltage levels of the I control signal and the Q control signal to sweep the amplitude and phase of the cancellation signal within a predetermined sweep range. The sweep range is a range that includes the amplitude and phase of a self-interference signal that may occur under standard conditions. The sweep range may be determined as appropriate by, for example, the person who determines the specifications of the reading device 100. The CPU 311 then determines the operating state of the amplitude / phase adjustment unit 21 when the level of the output signal from the quadrature detector 25 is minimum (hereinafter referred to as the minimum point). The CPU 311 then determines the voltage levels of the I control signal and the Q control signal to form the minimum point.

[0035] FIG. 4 is a diagram showing an example of a change in one of the I control signal and the Q control signal input to the filter unit 23 during a sweep. The CPU 311 instructs the FPGA 312 to output control data so as to gradually increase the voltage levels of the I control signal and the Q control signal. In response to this instruction, the FPGA 312 outputs predetermined control data so as to gradually increase the voltage levels of the I control signal and the Q control signal output from the DA converter 22. Thus, cooperation between the control unit 31 and the DA converter 22 realizes the function of output means that outputs the I control signal and the Q control signal so as to gradually change the cancellation signal.

[0036] The I control signal and Q control signal based on the above control data should not contain high-frequency components. However, high-frequency components may be mixed irregularly as noise and disturbance noise generated in the DA converter 22. For this reason, the voltage levels of the I control signal and Q control signal input to the filter unit 23 change, for example, as shown by the solid lines in FIG. 4.

[0037] At this time, filter unit 23 forms a first path. Therefore, filter unit 23 provides the I control signal to amplitude / phase adjustment unit 21 only via filter circuit 231, and the Q control signal to amplitude / phase adjustment unit 21 only via filter circuit 232. Note that the cutoff frequencies FCA of filter circuits 231 and 232 are determined taking into consideration that the time constants do not become too large so as not to cause a large delay in the I control signal and the Q control signal, and it is not possible to sufficiently remove high-frequency components mixed into the I control signal and the Q control signal.

[0038] If a second path is formed in filter unit 23, the I control signal and the Q control signal pass through filter circuits 233 and 234. The cutoff frequencies FCB of filter circuits 233 and 234 should be determined taking into consideration the ability to sufficiently remove high-frequency components mixed into the I control signal and the Q control signal. For this reason, filter circuits 233 and 234 have larger time constants than filter circuits 231 and 232, and when a second path is formed, a significant delay occurs in the I control signal and the Q control signal output from filter unit 23, as shown by the dashed dotted lines in FIG. 4, for example.

[0039] FIG. 5 is a diagram showing an example of a change in the phase of the cancellation signal during a sweep. FIG. 6 is a diagram showing an example of a change in the amplitude of the cancellation signal during a sweep. By supplying the I control signal and the Q control signal, which are in a changing state as shown by the solid lines in Figure 4 and have a predetermined relationship with each other, to the amplitude / phase adjustment unit 21, the phase and amplitude of the cancellation signal change, for example, as shown by the solid lines in Figures 5 and 6, respectively.

[0040] As can be seen from Figures 5 and 6, during the sweep of the cancellation signal, fluctuations in phase and amplitude occur due to high-frequency components remaining in the I control signal and the Q control signal. If the state in which this fluctuation occurs becomes the minimum point, CPU 311 will determine that the cancellation signal in which the phase and amplitude fluctuating due to the high-frequency components are the cancellation signal that forms the minimum point. In other words, in this case, CPU 311 will determine that the operating state of amplitude / phase adjustment unit 21, which is different from the actual minimum point, is the minimum point.

[0041] 5 and 6 represent changes in the phase and amplitude of the cancellation signal when the I control signal and Q control signal, which change as shown by the dashed line in Fig. 4, are supplied to amplitude / phase adjustment unit 21. As can be seen, the changes in phase and amplitude shown by the solid lines in Fig. 5 and 6 shorten the time required for sweeping compared to the changes in phase and amplitude shown by the dashed line.

[0042] In ACT7, the CPU 311 sets the operating state of the amplitude / phase adjustment unit 21 to the minimum point determined as described above. That is, the CPU 311 instructs the FPGA 312 to continuously output the control data that was being output at the minimum point determined as described above. In response to this instruction, the FPGA 312 then continuously outputs the specified control data.

[0043] As a result, a cancellation signal with fixed phase and amplitude is generated by the amplitude / phase adjustment unit 21, and a state is created in which this cancellation signal suppresses the self-interference signal. Thus, the control unit 31 and the DA converter 22 work together to realize the function of output means that outputs the I control signal and the Q control signal so as to keep the cancellation signal constant.

[0044] In ACT8, the CPU 311 checks whether the specified suppression state is reached. The specified suppression state is a state in which the influence of the self-interference signal is sufficiently suppressed. More specifically, as an example, the specified suppression state is a state in which the level of the self-interference signal component (hereinafter referred to as the residual signal) remaining in the output signal of the quadrature detector 25 has decreased to -20 dB or less compared to when the signal is not suppressed. That is, the CPU 311 checks the amount of suppression measured by the FPGA 312, and if it is confirmed that this amount has decreased to -20 dB or less compared to when the signal is not suppressed, it determines that the specified suppression state is reached. Note that the specified suppression state is preferably defined as a state in which the minimum amount of suppression is obtained so that the quadrature detector 25 does not saturate due to the influence of the residual signal. The specified suppression state is appropriately defined, for example, by the person who determines the specifications of the reading device 100. For example, the level of the self-interference signal when the signal is not suppressed can be the level of the output signal of the quadrature detector 25 measured in ACT4.

[0045] For example, if the signal levels of the two received baseband signals are represented as LI and LQ, then the FPGA 312 2 +LQ 2 That is, the larger the amount of suppression, the smaller the level of the residual signal, so the amount of suppression is calculated as the level of the residual signal.

[0046] If the CPU 311 confirms that the specified suppression state is reached, it determines YES in ACT8 and proceeds to ACT9. The period from when the CPU 311 performs the processing in ACT1 until it determines YES in ACT8 is the adjustment period. Then, under the control of the control unit 31, the filter unit 23 provides the frequency components of the I control signal and the Q control signal that are equal to or lower than the cutoff frequency FCA as the first frequency to the amplitude / phase adjustment unit 21 during the adjustment period. Thus, the filter unit 23 and the control unit 31 cooperate to realize the function of a filter means. Furthermore, when the CPU 311 determines YES here, it has determined that the amplitude and phase of the cancellation signal at the minimum point determined in ACT6 will be the amplitude and phase of the cancellation signal during the adjustment period. Thus, the CPU 311 is an example of a determination means.

[0047] In ACT9, the CPU 311 selects the second path as the path in the filter unit 23. That is, the CPU 311 controls the switches 235 and 236 of the filter unit 23 to be in the selected state indicated by the dashed lines in FIG. As ACT10, the CPU 311 reads the RFID tag 200. That is, the CPU 311 performs processing for receiving the response signal after the RFID tag 200 starts up and transmits the response signal. The processing for receiving the response signal may be similar to that performed by another existing reading device.

[0048] At this time, as described above, the FPGA 312 continuously outputs the control data specified by the CPU 311. For this purpose, the voltage levels of the I control signal and the Q control signal output by the DA converter 22 are essentially constant. However, high-frequency components may be irregularly mixed in as noise generated by the DA converter 22 and external disturbance noise.

[0049] FIG. 7 is a diagram showing an example of a change in one of the I control signal and the Q control signal input to the filter unit 23 when a response signal is received. The voltage levels of the I control signal and the Q control signal input to the filter unit 23 change, for example, as indicated by the solid lines in FIG.

[0050] At this time, filter unit 23 forms a second path. Therefore, filter unit 23 provides the I control signal to amplitude / phase adjustment unit 21 via filter circuits 231 and 233, and the Q control signal to amplitude / phase adjustment unit 21 via filter circuits 232 and 234. The I control signal and Q control signal output from filter unit 23 pass through filter circuits 233 and 234, which have smaller cutoff frequencies, and therefore high-frequency components are sufficiently removed, and the I control signal and Q control signal are set to a constant voltage, for example, as indicated by the dashed dotted line in FIG. 7.

[0051] By supplying the I control signal and Q control signal, which are in a changing state as shown by the dashed lines in Figure 7, to the amplitude / phase adjustment unit 21, the phase and amplitude of the cancellation signal become constant, as shown by the dashed lines in Figures 8 and 9, for example. FIG. 8 is a diagram showing an example of a change in the phase of the cancellation signal when a response signal is received. FIG. 9 is a diagram showing an example of a change in amplitude of the cancellation signal when a response signal is received.

[0052] If the I control signal and Q control signal in the changing state shown by the solid lines in Figure 7 are supplied as is to the amplitude / phase adjustment unit 21, the phase and amplitude of the cancellation signal will change, for example, as shown by the solid lines in Figures 8 and 9, respectively. The self-interference signal during reading is suppressed by a cancellation signal with a fixed phase and amplitude, as shown by the dashed lines in Figures 8 and 9. Note that the I control signal and the Q control signal are delayed by the filter circuits 233 and 234, but this does not affect the suppression of the self-interference signal because the voltage level is constant.

[0053] Then, when CPU 311 has completed reading the response signal, it proceeds to ACT 11. The period during which the response signal is being read in this manner is the suppression period. Under the control of control unit 31, filter unit 23 provides frequency components of the I control signal and the Q control signal that are equal to or lower than cutoff frequency FCB as the second frequency to amplitude / phase adjustment unit 21 during the suppression period. Thus, cooperation between filter unit 23 and control unit 31 realizes the function of a filter means. In ACT 11, the CPU 311 stops transmitting the carrier wave, and then ends this control process.

[0054] If the reading device 100 is in a standard condition, the amplitude and phase of the self-interference signal are likely to be within the sweep range. Therefore, the CPU 311 determines YES in ACT8 and executes ACT9 to ACT11. However, if the reading device 100 is not in a standard condition due to, for example, the presence of a metal object nearby, the CPU 311 may not be able to determine the minimum point at which the specified suppression state can be achieved by the sweep process in ACT6. Furthermore, due to the influence of high-frequency components contained in the I control signal and the Q control signal, the CPU 311 may determine an operating state of the amplitude / phase adjustment unit 21 that is different from the actual minimum point as the minimum point in ACT7, and the specified suppression state may not be achieved at the determined minimum point. In such cases, the CPU 311 determines NO in ACT8 and proceeds to ACT12.

[0055] In ACT 12, the CPU 311 counts up the number of attempts. In ACT 13, the CPU 311 checks whether the number of attempts has exceeded the limit. If the number of attempts counted up in ACT 12 has not exceeded the predetermined limit, the CPU 311 determines the answer as NO and returns to ACT 4, where it executes the subsequent steps as described above. The limit is determined as appropriate, for example, by the person who determines the specifications of the reading device 100.

[0056] On the other hand, if the number of attempts exceeds the limit, the CPU 311 determines YES in ACT13 and proceeds to ACT14. In ACT14, the CPU 311 stops transmitting the carrier wave. In ACT15, the CPU 311 executes error processing. For example, as error processing, the CPU 311 executes processing to display an error to inform the operator that the environment is not appropriate for reading. As error processing, the CPU 311 may execute other processing, such as playing a voice message. Furthermore, the CPU 311 may execute multiple types of processing as error processing. Then, once the error processing is completed, the CPU 311 ends the current control processing.

[0057] As described above, when canceling a self-interference signal when reading an RFID tag 200, the reader 100 supplies the I control signal and Q control signal to the amplitude / phase adjustment unit 21 via the filter circuits 233, 234 with a small cutoff frequency, thereby preventing the cancellation signal from fluctuating due to the influence of high-frequency components mixed in the I control signal and Q control signal and preventing the suppression state of the self-interference signal from becoming unstable. Then, during the period when the cancellation signal is adjusted to obtain the required suppression state, the I control signal and Q control signal are supplied to the amplitude / phase adjustment unit 21 without passing through the filter circuits 233, 234, so that the cancellation signal can be adjusted in a short adjustment period.

[0058] This embodiment can be modified in various ways as follows. FIG. 10 is a block diagram showing a modified configuration example of the filter unit 23. In FIG. As shown in FIG. 10 , filter circuits 237 and 238 may be added to the filter unit 23. That is, when the first path is formed, the I control signal and the Q control signal may be provided to the amplitude / phase adjustment unit 21 via the filter circuits 237 and 238. In this case, the cutoff frequencies FCC of the filter circuits 237 and 238 are determined taking into consideration that the time constant is not too large so as not to cause a large delay in the I control signal and the Q control signal, and high-frequency components mixed in the I control signal and the Q control signal cannot be sufficiently removed. In other words, the cutoff frequencies of each filter have a relationship of FCA>FCC>FCB. The cutoff frequency FCC may be determined appropriately by, for example, a person who determines the specifications of the reading device 100. The cutoff frequency FCC corresponds to a third frequency. The filter circuits 237 and 238 are each an example of a third filter.

[0059] The amplitude / phase adjustment unit 21 may be configured, for example, by connecting a variable attenuator and a variable phase shifter in series. In this case, a control signal specifying the gain of the variable attenuator and a control signal specifying the phase shift amount of the variable phase shifter are used instead of the I control signal and the Q control signal, but the configuration of the filter unit 23 may be the same as in the above embodiment.

[0060] It may also be realized as a communication device that communicates with wireless tags such as the RFID tag 200 for purposes other than reading data stored in the RFID tag 200 from the RFID tag 200 .

[0061] Some or all of the functions realized by the CPU 311 through information processing can be realized by hardware that executes information processing not based on a program, such as a logic circuit, etc. Each of the above functions can also be realized by combining hardware such as the above logic circuit with software control.

[0062] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0063] 100...reader, 200...RFID tag, 11...oscillator, 12...phase shifter, 13...DA converter, 14...quadrature modulator, 16...power amplifier, 18...antenna duplexer, 19...feed line, 20...antenna, 21...amplitude / phase adjustment unit, 22...DA converter, 23...filter unit, 231, 232, 233, 234, 237, 238...filter circuit, 235, 236...switch, 24...power combiner, 25...quadrature detector, 27...AC coupled amplifier, 28...AD converter, 30...AD converter, 31...control unit, 311...CPU, 312...FPGA, 32...memory

Claims

1. A communication device that receives a response signal transmitted from a wireless tag that operates using power obtained from a received carrier wave, a first generating means for generating the carrier wave; a sharing means for receiving the carrier wave generated by the first generating means from an input terminal and outputting it from an input / output terminal, and for outputting the signal inputted from the input / output terminal from an output terminal; a second generating means for generating a cancellation signal by changing the amplitude and phase of the carrier wave generated by the first generating means; a suppression means for suppressing a self-interference signal included in the output signal from the output terminal by using the cancellation signal generated by the second generation means; an output means for outputting a control signal for controlling the amount of change in amplitude and amount of change in phase in the second generation means so as to gradually change the cancellation signal during an adjustment period and to keep the cancellation signal constant during a suppression period; a filter means for supplying to the second generating means, during the adjustment period, frequency components of the control signal output by the output means that are equal to or lower than a first frequency, and for supplying to the second generating means, during the suppression period, frequency components of the control signal output by the output means that are equal to or lower than a second frequency that is lower than the first frequency; a determination means for determining the amplitude and phase of a cancellation signal to be generated by the second generation means during the suppression period based on the output of the suppression means while inputting the carrier wave output by the first generation means to the input terminal during the adjustment period; A communication device equipped with:

2. The filter means a first filter that passes frequency components of the control signal output by the output means that are equal to or lower than the first frequency; a second filter that passes frequency components of the control signal that has passed through the first filter that are equal to or lower than the second frequency; a switching unit that provides the control signal that has passed through the first filter to the second generating means without passing through the second filter during the adjustment period, and that provides the control signal that has passed through the first filter to the second generating means via the second filter during the suppression period; The communication device of claim 1 , comprising:

3. The filter means a third filter that passes a frequency component of the control signal that has passed through the first filter, the frequency component being equal to or less than a third frequency that is lower than the first frequency and higher than the second frequency; During the adjustment period, the switching unit provides the control signal that has passed through the first filter to the second generating means via the third filter.

3. The communication device of claim 2, comprising:

4. the output means outputs an I component signal and a Q component signal as control signals, the first filter and the second filter include a filter for an I component signal and a filter for a Q component signal, respectively; The communication device according to claim 2 or 3.

5. the output means outputs an I component signal and a Q component signal as control signals, the third filter includes a filter for an I component signal and a filter for a Q component signal; The communication device according to claim 3 .

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