Image processing device, image processing method, and program

Abstract

This enables image processing modules to work together with simple processing without changing the DMAC specifications. [Solution] A first module, which writes image data to memory in first band units, defines a line as the smallest unit in the y direction of image data composed of two-dimensional pixel data, and defines a unit consisting of one or more lines as a band. A first transmission signal is transmitted for each first band, indicating that writing has been completed. A second module, which reads the image data output to memory by the first module in second band units different from the first band units, transmits a second transmission signal for each second band, indicating that reading has been completed. The second transmission signal is converted for each second band according to the number of lines contained in the second band. Whether or not the first module can write one band is determined based on the first transmission signal and the second transmission signal converted by the first conversion means.

Description

[Technical Field]

[0001] The present invention relates to an image processing device, an image processing method, and a program. [Background technology]

[0002] An image processing device is composed of multiple image processing modules with different processing capabilities, and generates desired image data by controlling the transfer of data via a buffer (ring buffer) that connects each image processing module. Image processing modules typically consist of a read DMAC that acquires image data from DRAM, an image processing unit that processes the image data acquired by the read DMAC, and a write DMAC that stores the image data processed by the image processing unit in DRAM. Furthermore, the DMAC and its startup control are required to be flexible in responding to development time, quality, and specification changes, and are therefore developed for general use. For example, Patent Document 1 provides a general-purpose and flexible buffer management means that enables image processing modules to be easily connected via memory using a common interface, thereby shortening development time and improving quality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-98915 Summary of the Invention [Problem to be solved by the invention]

[0004] With improvements in the throughput of printers and scanners, the data processing performance required of image processing devices is also increasing year by year. In addition, by configuring the buffer management means provided in Patent Document 1 together with a general-purpose DMAC, and further notifying each image processing module of an end signal for each processing unit and controlling and referencing the retention counters between linked buffers, it becomes possible to achieve high-speed startup control of image processing modules with a simpler configuration and without the intervention of a CPU.

[0005] Some image processing modules require a process in which the data size to be processed changes for each processing unit. Examples of such processes include stepless interpolation scaling and cropping. Controlling the cooperation of such image processing modules requires notification of the completion of each processing unit, as well as notification of the processing size change for the next processing unit. This is necessary to ensure proper control of the linked buffer and prevent deadlocks and image abnormalities. One method for controlling this notification for each processing unit is firewall control by the CPU. However, such control requires processing time for interrupt handling, etc., which can lead to delays in the processing time of the image processing modules. Another possible solution is to extend the interface between DMACs to enable notification of processing size. However, this would require modifications to the specifications of the general-purpose DMACs, significantly impacting development time and quality. In light of the above, a notification method is needed that enables high-speed size change notification between DMACs without modifying the specifications of the general-purpose DMACs.

[0006] An object of the present invention is to enable cooperation between image processing modules through simple processing without changing the specifications of the DMAC. [Means for solving the problem]

[0007] To achieve the object of the present invention, for example, an image processing apparatus according to one embodiment includes the following configuration: a first transmission means for transmitting a first transmission signal for each first band indicating that a first module that writes image data to a memory in first band units has completed writing the image data in first band units, where the smallest unit in the y direction of image data composed of two-dimensional pixel data is a line and a unit composed of one or more of the lines is a band, a second transmission means for transmitting a second transmission signal for each second band indicating that a second module that reads the image data output to the memory by the first module from the memory in second band units different from the first band units has completed reading the image data, which is output to the memory by the first module, in second band units different from the first band units, a first conversion means for converting the second transmission signal for each second band in accordance with the number of lines included in the second band, and a first determination means for determining whether or not the first module can write one band based on the first transmission signal and the second transmission signal converted by the first conversion means. [Effects of the Invention]

[0008] This enables image processing modules to work together with simple processing without changing the DMAC specifications. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of a hardware configuration of an image processing apparatus. [Figure 2] FIG. 2 is a block diagram showing an example of the functional configuration of an image processing module. [Figure 3] FIG. 2 is a block diagram showing an example of a configuration for connections between image processing modules. [Figure 4] FIG. 10 is a diagram for explaining an example of input / output data between concatenated buffers. [Figure 5] FIG. 10 is a diagram showing an example of control timing for data input / output processing between concatenated buffers. [Figure 6]1A is a schematic diagram of data written by an image processing module, FIG. 1B is a schematic diagram of data read by an image processing module, and FIG. 1C is a diagram showing an example of conversion determination processing by a conversion number determination unit. [Figure 7] FIG. 10 is a diagram showing an example of processing timing when FW control is performed on concatenated buffer processing. [Figure 8] FIG. 4 is a block diagram showing an example of the functional configuration of a call count conversion unit. [Figure 9] 10 is a flowchart showing an example of the progress of a call count conversion process. [Figure 10] FIG. 10 is a block diagram showing another example of the functional configuration of the image processing module. [Figure 11] FIG. 10 is a diagram showing another example of processing timing when FW control is performed on the concatenated buffer processing. [Figure 12] 10A is a schematic diagram of data written by an image processing module according to a second embodiment, and FIG. 10B is a schematic diagram of data read by an image processing module according to a second embodiment. [Figure 13] FIG. 10 is a block diagram showing an example of the functional configuration of an image processing module according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing an example of the timing of FW control processing according to the second embodiment. [Figure 15] FIG. 11 is a block diagram showing an example of the functional configuration of an image processing module according to a third embodiment. [Figure 16] (a) Schematic diagram of data written by an image processing module according to embodiment 3, (b) Schematic diagram of data read by an image processing module according to embodiment 3, (c) Schematic diagram of other data written by an image processing module according to embodiment 3, (d) Schematic diagram of other data read by an image processing module according to embodiment 3. [Figure 17] FIG. 11 is a diagram showing an example of the timing of FW control processing according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0011] [Embodiment 1] FIG. 1 is a block diagram showing an example of the hardware configuration of an image processing device 100 according to this embodiment. The image processing device 100 includes a host I / F 102 that transmits and receives image data to and from an external host device 101, a scanning device control unit 117 that controls image input formed by a scanning device 116, a group of image processing modules 107-113 that processes image data input to the image processing device 100, and a recording device control unit 114 that transfers image data to a recording device 115. A CPU 103 controls the entire image processing device 100 in accordance with program information stored in a ROM 104. Image data processed within the image processing device 100 is stored in a concatenation buffer formed in a RAM 105 via a data bus 106. The image processing modules 107-113 read image data to be processed from the concatenation buffer, perform image processing, and write the processed image data to the concatenation buffer. The concatenation buffer is formed by the CPU 103. Specifically, the CPU 103 determines the number of link buffers and the capacity and area of ​​each link buffer according to the type of image data input to the image processing device 100 and the type of image data to be recorded, and notifies the image processing modules 107 to 113 of these as link buffer information parameters. The startup control of each image processing module is controlled by managing the amount of data input to and output from each link buffer. Notification of this information related to startup control is performed via the image processing module connection unit 118.

[0012] The image processing device 100 according to this embodiment, as will be described in detail later, defines a line as the minimum unit of image data in the y direction, and defines a unit consisting of one or more lines as a band. The image processing device 100 transmits a first transmission signal for each first band, indicating that a first module (image processing module A) that writes image data to memory in first band units has completed writing the image data, to a second module (image processing module B) that reads the image data from memory in second band units (different from the first band units). The image processing device 100 then transmits a second transmission signal for each second band, indicating that image processing module B has completed reading the image data output by the first module to memory. The image processing device 100 converts the second transmission signal for each second band according to the number of lines included in the second band, and determines whether or not image processing module A can write one band based on the first transmission signal and the converted second transmission signal. The processing performed by the image processing device 100 will be described below with reference to FIGS. 2 to 5.

[0013] FIG. 2 is a block diagram showing an example of the functional configuration and internal data of the image processing modules 107 to 113 according to this embodiment. Hereinafter, the startup control process performed by the image processing modules 107 to 113 will be described in detail with reference to FIG. 2. Each image processing module is made up of a DMAC 201 that reads and writes image data from the RAM 105, an image processing unit 200 that processes the read image data, a management unit 202 that manages the amount of data in a linkage buffer P in which the image data to be read is stored, and a management unit 203 that manages the amount of data in a linkage buffer Q in which the image data to be written is stored. Parameter A group 212 and parameter B group 213 include management information for the linkage buffer P notified by the CPU 103. Parameter C group 218 and parameter D group 219 include management information for the linkage buffer Q notified by the CPU 103. In this embodiment, all of the image processing modules of the image processing device 100 have functional components including the read DMAC 204 and write DMAC 205 shown in Figure 2, and are described as being capable of reading (reading) and writing (writing) image data in band units as described below, but the image processing module may also include an image processing module that has only either the read DMAC 204 or the write DMAC 205 and is capable of performing only one of reading and writing.

[0014] The image processing module also receives a write completion notification 210 via the image processing module connection unit 118 from the image processing module that writes image data to the concatenated buffer P. Upon receiving the write completion notification 210, the concatenated buffer P retention counter is counted up by a predetermined size (here, the count number recorded as the parameter A group 212). The read activation determination unit 209 constantly monitors the concatenated buffer P retention counter value, and when the concatenated buffer P retention counter value reaches an amount that can activate the read DMAC 204 (here, the value recorded as the parameter B group 213), it transmits an activation notification to the read DMAC 204. Upon receiving the activation notification, the read DMAC 204 reads image data to be processed by the image processing unit 200 from the concatenated buffer P and transfers the data to the image processing unit 200 via the image data bus 206. Upon completion of the transfer, the read completion transmission unit transmits a read completion signal 211 to the image processing module. The read completion signal 211 is transmitted to the management unit 202 and is used to control the countdown of the concatenated buffer P retention counter 208. The read completion signal 211 is also transmitted via the image processing module connection unit 118 to the image processing module that writes the image data into the concatenated buffer P.

[0015] Furthermore, the image data processed by the image processing unit 200 is transferred to the write DMAC 205 via the image data bus 207. The write DMAC 205 writes the data to the concatenation buffer Q in accordance with the determination result of the write activation determination unit 215. The write activation determination unit 215 constantly monitors the count value of the concatenation buffer Q retention counter 214 to determine whether the concatenation buffer Q has free space of a predetermined size (here, the value recorded as the parameter C group 218). If there is free space, it determines that writing is possible and notifies the write DMAC 205 of write permission. When the write DMAC 205 has completed writing the data processed by the image processing unit 200 to the concatenation buffer Q, it transmits a write completion signal 217 via a write completion communication unit. The write completion signal is transmitted to the management unit 203 and is used to control the count-up of the concatenation buffer Q retention counter 214. The value counted up here is included in the parameter D group 219 notified by the CPU. The write end signal is transmitted to the image processing module that reads the image data from the concatenation buffer Q via the image processing module connection unit 118. Furthermore, the management unit 203 receives a read end notification 216 from the image processing module that reads the image data from the concatenation buffer Q, and uses this to control the countdown of the concatenation buffer Q retention counter. The value counted down here is included in the parameter A group 212 notified by the CPU.

[0016] FIG. 3 is a block diagram showing an example of a connection between image processing modules according to this embodiment. FIG. 3 illustrates an example in which image processing module A and image processing module B exchange image data via a linkage buffer P105. Image processing module A writes image data processed by the image processing unit 200 to the linkage buffer P using a write DMAC. When the write DMAC 205 completes writing the processed image data, it sends a write completion signal 217 to the image processing module using a write completion signaling unit. Furthermore, image processing module B reads the image data written by image processing module A from the linkage buffer P using a read DMAC. When the read DMAC 204 completes reading the image data required for processing, it sends a read completion signal 211 using a read completion signaling unit. The write completion signal 217 and the read completion signal 211 are notified to each other's linkage buffer P retention counters 214 and 208 via the image processing module connection unit 118.

[0017] 4 is a diagram for explaining input / output data between concatenated buffers when the processing unit size of image processing modules A and B is constant (the number of lines included in a band unit is common between bands for each image processing module). Input / output data to the concatenated buffer is a collection of two-dimensional pixel data in the x and y directions, and when a collection of pixels equivalent to one pixel in the y direction is defined as a line, the concatenated buffer forms a ring buffer in line units. Furthermore, when a collection of lines is defined as a band, the image processing module according to this embodiment performs input / output to the concatenated buffer in band units.

[0018] FIG. 4(a) shows output data written by image processing module A to concatenation buffer P. In FIG. 4(a), image processing module A writes image data (401-406) in bands of four lines each according to the free space in the concatenation buffer. In FIG. 4(a), when four or more lines are free in the concatenation buffer (timing 407), output by bands begins, and when output by bands is completed (timing 408), a write end signal 217 is sent. FIG. 4(b) shows input data read by image processing module B from concatenation buffer P. In FIG. 4(b), image processing module B reads image data (411-418) in bands of three lines each according to the amount of data stored in the concatenation buffer. Here, the amount of data stored in the concatenation buffer is defined as the number of lines of image data written to the concatenation buffer but not yet read. In FIG. 4(b), when three or more lines are stored in the concatenation buffer (timing 419), input by bands begins, and when input by bands is completed (timing 420), a read end signal 211 is sent.

[0019] FIG. 5 is a timing chart showing an example of the timing of the input / output control process of the concatenated buffer described in FIG. 4. Operations 502, 505, 509, 511, 512, and 514 of image processing module A are operations during the write transfer period of image data 401 to 406 in units of bands in FIG. 4. Operations 517, 521, 523, 524, 526, 528, 530, and 531 of image processing module B are operations during the read transfer period of image data 411 to 418 in units of bands in FIG. 4. The transition of the retention counters indicates the transition of the count values ​​of the retention counters 214 and 208 constituting image processing modules A and B. The count is incremented at the timing when the write of image processing module A ends, for example, at timing 503 when the write transfer of image data 401 in units of bands is completed. The count is decremented at the timing when the read of image processing module B ends, for example, at timing 518 when the read transfer of image data 411 in units of bands is completed.

[0020] The write transfer start process of image processing module A is controlled to start if the free space is equal to or greater than the processing unit (four lines) of image processing module A according to the count values ​​of linkage buffer P retention counters 214 and 208. For example, when the initial value of the linkage buffer P retention counter is 0 and the capacity of the linkage buffer P is eight lines, the write activation determination unit 215 determines that image processing module A can be activated because the free space is eight lines, and notifies activation (timing 501). On the other hand, when the count value of the linkage buffer P retention counter is five or greater, the write activation determination unit 215 determines that image processing module A cannot be activated because the free space is three lines or less, and performs wait control (periods 507, 510, 513).

[0021] The read transfer start process of image processing module B is performed in accordance with the count values ​​of linkage buffer P retention counters 214 and 208, and activation control is performed if the count value is equal to or greater than the processing unit (three lines) of image processing module B. For example, when the linkage buffer P retention counter value is four, the read activation determination unit 209 determines that image processing module B can be activated because the accumulated capacity is four lines, and notifies activation (timing 516). On the other hand, when the count value of the linkage buffer P retention counter is two or less, the read activation determination unit 209 determines that image processing module B cannot be activated because the accumulated capacity is less than three lines, and performs wait control (periods 515, 519, 522, 525, and 527).

[0022] As described above, when the processing unit sizes of image processing modules A and B are constant, the image processing modules can cooperate with each other by mutually notifying each other of the write end signal 217 of image processing module A and the read end signal 211 of image processing module B via the image processing module connection unit 118, without the intervention of CPU 103 in the startup control of each processing unit. Furthermore, by mutually notifying each other of the write end signal 217 of module A and the read end signal 211 of image processing module B via CPU 103 rather than the image processing module connection unit 118, it is possible to perform FW control.

[0023] 4 and 5 show cooperation in which the processing unit size of image processing modules A and B is constant, but depending on the content of image processing (for example, stepless interpolation magnification), there may be cases where the processing unit size differs depending on the image position to be processed (the number of lines included in a band unit varies for each band) (hereinafter referred to as the processing unit size being variable). The image processing according to this embodiment will be described in more detail below.

[0024] 6 is a diagram for explaining input / output data between linked buffers when the processing unit size of image processing module B according to this embodiment is variable. For example, the processing unit size of input data required for image processing module B to perform stepless interpolation scaling processing can be calculated using the calculation method shown in FIG. 6(c). Note that this explanation is for an example in which the processing unit size of image processing module B is variable, but since such an image processing module can be implemented using known image processing technology, detailed explanation here will be omitted.

[0025] 6(a) is a schematic diagram of output data that image processing module A writes to concatenation buffer P. In FIG. 6(a), image processing module A writes image data 601 to 606 in band units of four lines each according to the available capacity of the concatenation buffer. In FIG. 6(a), when four or more lines become available in the concatenation buffer (timing 607), output in band units begins, and when output in band units is completed (timing 608), a write end signal 217 is sent.

[0026] FIG. 6B is a schematic diagram of input data read by image processing module B from concatenation buffer P. In FIG. 6B, image processing module B reads image data 611 to 618, each of which has a different number of lines for each band, according to the amount of data stored in the concatenation buffer. For image data 611, 612, 614, 615, 617, and 618, when three or more lines are stored in the concatenation buffer (timing 619), input on a band-by-band basis is started, and when input on a band-by-band basis is completed (timing 620), a read end signal 211 is transmitted. For image data 613 and 616, when two or more lines are stored (timing 619), input on a band-by-band basis is started, and when input on a band-by-band basis is completed (timing 620), a read end signal 211 is transmitted. In this case, a configuration can be adopted in which the processing unit of image processing module B is notified to image processing module A every time image processing module B is started.

[0027] 7 is a timing chart showing an example of the timing of each process when the CPU 103 intervenes and controls the firewall to control the link buffer with a variable processing unit size. When image processing module B in FIG. 6B completes reading the image data 612 (timing 723), the CPU 103 is notified of the read end signal 211. Upon receiving the notification, the CPU 103 notifies image processing module A of the end of reading by image processing module B and the number of lines of the image data 613 that image processing module B will process next (timing 723). In this way, by having the CPU intervene and having the firewall control the link buffer each time the number of lines per band in image processing module B changes, image processing module A and image processing module B can operate in cooperation, but the processing load on the CPU 103 increases. Furthermore, an increase in the processing load on the CPU 103 causes delays in the startup of each image processing module (FWs 729 and 739), which leads to a decrease in the data processing speed of the image processing device. Therefore, it is preferable to cooperate with the image processing modules via the image processing module connection unit 118.

[0028] From this perspective, the image processing device 100 according to this embodiment is configured with a transmission count conversion unit in each image processing module that can convert the number of transmissions of the write end signal 217 and the number of transmissions of the read end signal 211 based on variable information, thereby enabling cooperation between image processing modules without the intervention of a CPU when the number of lines per band is variable.

[0029] FIG. 8 is a block diagram showing an example of the functional configuration of a transmission count converter 800 (described later) included in the image processing device 100 according to this embodiment. The transmission count converter 800 transmits a transmission signal to another image processing module via a signal line. Here, the transmission count converter 800 converts the transmission signal to be transmitted according to the number of lines included in the band each time a read or write process for each processed band is completed. The transmission count converter 800 according to this embodiment can, for example, convert the transmission signal to be transmitted into a transmission signal with a width or number according to the number of lines included in the read band. Below, a specific example of processing performed by the transmission count converter 800 will be described.

[0030] The transmission count conversion unit 800 according to this embodiment can generate a converted processing end signal 815 using a processing position determination unit 810 that counts the number of triggers of an input signal (processing end trigger 801) and determines a currently processed processing position 813, a conversion number determination unit 811 that determines a converted transmission number 814 based on the processing position 813, and an end trigger conversion unit 812 that converts the trigger number of the input signal based on the converted transmission number. Furthermore, the transmission count conversion unit 800 includes a selection unit 820 that can select whether to output the input signal 801 or the converted signal 815. The selection unit 820 selects whether to output the input signal 801 or the converted signal 815 based on an operation mode, and outputs the selected signal as signal 802.

[0031] The operation of the transmission count conversion unit will be explained in detail using the processing flowchart of Figure 9. Each circuit constituting the oscillation circuit conversion unit 800 operates in synchronization with the operation clock 900. For more specific explanation, it is assumed here that the conversion number determination unit 811 determines the number of conversions using the calculation method shown in Figure 6(c). First, the processing position 813 of the processing position determination unit 810 in the initial state indicates 0, which indicates the origin. Then, based on the processing position 0, the conversion number determination unit 811 determines the number of conversions to be 3 (step 902). When the processing end trigger 801 is input (step 903), the end trigger conversion unit 812 increments the number of conversions (step 904), and when a post-conversion trigger is output, the conversion unit addition / subtraction counter, which decrements, generates a post-conversion processing end signal 815 (step 905). Specifically, a trigger can be generated when the conversion unit addition / subtraction counter is not 0. Furthermore, when a processing end trigger 801 is input (step 903), the processing position determination unit 810 counts up the processing position to 1, which indicates the next processing position, and the conversion number determination unit 814 determines the number of conversions to be 3. By operating in this manner, in FIG. 9, four processing end triggers are converted into 11 post-conversion processing end triggers. Note that in FIG. 9, the explanation has been given assuming that there is 0 cycle between triggers and that conversion is performed into a signal with a pulse width corresponding to the number of lines included in the band unit, but this is not limited to this. In other words, an interval of one cycle or more may be provided between triggers.

[0032] FIG. 10 is a diagram showing an example of a configuration of connections between image processing modules according to this embodiment. In addition to the components described in FIG. 2, the image processing module B shown in FIG. 10 includes a call count converter 1000 that functions similarly to the call count converter 800 described in FIGS. 8 and 9. More specifically, a read completion signal 211 generated by a read completion signaling unit included in the read DMAC 204 is connected as an input signal 801 to the call count converter, and a signal 802 generated by the call count converter is connected via a signal line 1001. When input of image data 611 to 618, each of which has a different number of lines per band in FIG. 6(b), is completed in band units (timing 620), the image processing module B shown in FIG. 10 transmits a read completion signal 211 to the image processing module A once. By transmitting this read completion signal 211 via the call count converter 1000, it is possible to accurately transmit the change in the number of lines per band to the image processing module A. That is, here, the transmission count conversion unit 1000 converts the number of triggers before conversion, which is the number of band units of 8, into the number of triggers after conversion, which is the sum of the number of lines in each band, 22 (3+3+2+3+3+2+3+3).

[0033] 11 is a timing chart showing an example of the timing of the linked buffer control process with a variable processing unit size according to this embodiment. Below, the control timing when processing the input / output data shown in FIGS. 6(a) and 6(b) will be described with reference to image processing modules A and B shown in FIG.

[0034] Operations 1102, 1105, 1109, 1111, 1113, and 1115 of image processing module A are operations during the write transfer period of image data 601 to 606 in band units in Fig. 6(a). Operations 1117, 1121, 1123, 1124, 1126, 1129, 1130, and 1131 of image processing module B are operations during the read transfer period of image data 611 to 618 in band units in Fig. 6(b). The transition of the retention counters indicates the transition of the count values ​​of linkage buffer P retention counters 214 and 208 constituting image processing modules A and B.

[0035] Counting up occurs at the timing when image processing module A finishes writing, for example, at timing 1103 when write transfer of image data 611 in units of bands is completed. Also, counting down occurs at the timing when image processing module B finishes reading, for example, at timing 1118 when read transfer of image data 411 in units of bands is completed. In this embodiment, the value to be counted down is included in parameter group A 212 or group D 219 notified from the CPU, and is 1 in this case.

[0036] The write transfer start process of image processing module A is controlled by activation if the free space is equal to or greater than the processing unit (four lines) of image processing module A according to the count values ​​of linkage buffer P retention counters 214 and 208. For example, when the initial value of the linkage buffer P retention counter is 0 and the capacity of the linkage buffer P is eight lines, the write activation determination unit 215 determines that image processing module A can be activated because the free space is eight lines, and notifies activation (timing 1101). On the other hand, when the count value of the linkage buffer P retention counter is five or greater, the write activation determination unit 215 determines that image processing module A cannot be activated because the free space is three lines or less, and performs wait control (periods 1107, 1110, 1112, 1114).

[0037] The read transfer start process of image processing module B is controlled by the count values ​​of linkage buffer P retention counters 214 and 208, and activation control is performed if the count value is equal to or greater than the processing unit (three lines) of image processing module B. For example, when the linkage buffer P retention counter value is four, the read activation determination unit 209 determines that image processing module B can be activated because the accumulated capacity is four lines, and notifies activation (timing 1116). On the other hand, when the count value of the linkage buffer P retention counter is two or less, the read activation determination unit 209 determines that image processing module B cannot be activated because the accumulated capacity is less than three lines, and performs wait control (timings 1115, 1122, 1127, 1128).

[0038] As described above, when the processing unit size of image processing module B is variable, the signal 820 converted by the transmission count conversion unit 1000, which starts from the write end signal 217 of image processing module A and the read end signal 211 of image processing module B, is notified to each other via the image processing module connection unit 118, thereby enabling the image processing modules to cooperate with each other without the intervention of CPU 103 in controlling the startup of each processing unit.

[0039] Although the present embodiment illustrates an example in which the image processing module B performs stepless magnification processing, the present invention is not limited to this. For example, the transmission signal conversion processing by the image processing device 100 according to the present embodiment can be applied to cases in which the number of processing lines varies depending on the pixel position to be processed, such as in a trimming process in which the processing unit of the first or last band is variable. Furthermore, for example, the image processing device 100 may convert the transmission signal only when the band unit of the image processing module B is variable (as shown in FIG. 6). In the case in which the processing unit size is constant as shown in FIG. 4, cooperation is possible by notifying the signal before conversion via the selection unit 820 included in the transmission count conversion unit 1000. Furthermore, the image processing device 100 may acquire user input and, based on the acquired user input, set whether or not the transmission signal should be converted by the transmission count conversion unit 1000. For example, the transmission count conversion unit 1000 may convert the transmission signal only when the user input is set to convert the transmission signal.

[0040] [Embodiment 2] 6 of the first embodiment, a case has been described in which the processing unit size of image processing module B, which is a module that reads from concatenated buffer P, is variable. On the other hand, in this embodiment, a case will be described in which the processing unit size of image processing module A, which is a module that writes to concatenated buffer P, is variable. The image processing device 100 according to this embodiment basically has the same configuration as that according to the first embodiment and can execute the same processes, so duplicated explanations will be omitted.

[0041] 12 is a diagram for explaining input / output data between linked buffers when the processing unit size of the image processing module according to this embodiment is variable. Here, FIG. 12 shows an example in which image processing module A outputs image data that has undergone stepless interpolation scaling processing. Even when image processing module A performs stepless interpolation scaling processing in this way, the processing unit size can be calculated in the same way using the calculation method shown in FIG. 6(c).

[0042] FIG. 12(a) is a schematic diagram of output data that image processing module A writes to concatenation buffer P. In FIG. 12(a), image processing module B writes image data 1201 to 1209, each with a different number of lines for each band, according to the available capacity of the concatenation buffer. For image data 1201, 1202, 1204, 1205, 1207, and 1208, when there is available capacity of three or more lines in the concatenation buffer (timing 1210), output of the image data in band units becomes possible, and when output of the image data in band units is completed (timing 1211), a write completion signal 217 is transmitted. Also, for image data 1203, 1206, and 1209, when there is available capacity of two or more lines (timing 1210), output of the image data in band units becomes possible, and when output of the image data in band units is completed (timing 1211), a write completion signal 217 is transmitted.

[0043] Fig. 12(b) is a schematic diagram of input data that image processing module B reads from concatenation buffer P. In Fig. 12(b), image processing module B reads image data 1212 to 1217 in band units of four lines each according to the amount of data stored in the concatenation buffer. In Fig. 12(b), when four or more lines are stored in the concatenation buffer (timing 1218), input in band units begins, and when input in band units is completed (timing 1219), a read end signal 211 is sent.

[0044] FIG. 13 is a diagram showing an example of a configuration of connections between image processing modules according to this embodiment. In addition to the components described in FIG. 2, the image processing module A shown in FIG. 13 includes a transmission count converter 1300 that functions similarly to the transmission count converter 800 described in FIGS. 8 and 9. More specifically, a write completion signal 217 generated by a write completion communication unit included in the write DMAC 205 is connected as an input signal 801 to the transmission count converter 1300, and a signal 802 generated by the transmission count converter 1300 is connected via a signal line 1301. The image processing module A shown in FIG. 13 transmits a write completion signal 211 once each band of image data 1201-1209, each of which has a different number of lines per band in FIG. 12(a), is output (timing 1211). By transmitting this write completion signal via the transmission count converter 1300, it is possible to accurately transmit changes in the number of lines per band to the image processing module B. That is, here, the transmission count conversion unit 1300 converts the number of band units, 9, which is the number of triggers before conversion, into the total number of lines in each band, 24 (3+3+2+3+3+2+3+3+2), as the number of triggers after conversion.

[0045] Fig. 14 is a timing chart showing an example of the timing of the linked buffer control process with a variable processing unit size according to this embodiment. Below, the control timing when processing the input / output data shown in Fig. 12(a) and (b) will be described with reference to image processing modules A and B shown in Fig. 13.

[0046] Operations 1402, 1405, 1408, 1409, 1410, 1412, 1413, 1414, and 1416 of image processing module A indicate operations during a write transfer period of image data in band units 1201 to 1209 in Fig. 12(a). Operations 1419, 1422, 1424, 1426, 1428, and 1430 of image processing module B indicate operations during a read transfer period of image data 1211 to 1217 in band units in Fig. 12(b). The transition of the retention counters indicates the transition of the count values ​​of linkage buffer P retention counters 214 and 208 constituting image processing modules A and B.

[0047] Counting up occurs at the timing when image processing module A finishes writing, for example, at timing 1403 when the write transfer of image data 1201 in units of bands is completed. In this embodiment, the value to be counted up is included in parameter group A 212 or group D 219 notified from the CPU, and is 1 in this case. Counting down also occurs at the timing when image processing module B finishes reading, for example, at timing 1420 when the read transfer of image data 1212 in units of bands is completed. The counting down is the same as in embodiment 1, so a description thereof will be omitted.

[0048] The write transfer start process of image processing module A is controlled by activation if the free space is equal to or greater than the processing unit (3 lines) of image processing module A according to the count values ​​of linkage buffer P retention counters 214 and 208. For example, when the initial value of the linkage buffer P retention counter is 0 and the capacity of the linkage buffer P is 8 lines, the write activation determination unit 215 determines that image processing module A can be activated because the free space is 8 lines, and issues a notification of activation (timing 1401). On the other hand, when the count value of the linkage buffer P retention counter is 6 or greater, the write activation determination unit 215 determines that image processing module A cannot be activated because the free space is 2 lines or less, and performs wait control 1407, 1411, and 1415.

[0049] The read transfer start process of image processing module B is performed in accordance with the count values ​​of linkage buffer P retention counters 214 and 208, and activation control is performed if the count value is equal to or greater than the processing unit (four lines) of image processing module B. For example, when the linkage buffer P retention counter value is four, the read activation determination unit 209 determines that image processing module B can be activated because the accumulated capacity is four lines, and issues a notification of activation (timing 1418). On the other hand, when the count value of the linkage buffer P retention counter is three or less, the read activation determination unit 209 determines that image processing module B cannot be activated because the accumulated capacity is less than four lines, and performs wait control 1417, 1421, 1423, 1425, 1427, and 1429.

[0050] As described above, when the processing unit size of image processing module A is variable, by notifying each other via image processing module connection unit 118 of the read end signal 211 of image processing module B and the signal 1301 converted by transmission count conversion unit 1300 starting from the write end signal 217 of image processing module A, image processing modules can cooperate with each other without CPU 103 intervening in the startup control of each processing unit.

[0051] In this embodiment, an example has been shown in which the image processing module A performs stepless magnification processing, but this is not limited to this. For example, the conversion processing of the transmission signal by the image processing device 100 according to this embodiment can be applied to cases in which the number of processing lines varies depending on the pixel position to be processed, such as trimming processing in which the processing unit of the first band or the last band is variable. Furthermore, this is not limited to cases in which the number of processing lines varies depending on the pixel position to be processed. Even when the processing unit size shown in FIG. 4 is constant, cooperation is possible if the selection unit 820 included in the transmission count conversion unit 1300 notifies the signal before conversion.

[0052] [Embodiment 3] In the first and second embodiments, an example in which two image processing modules work together has been described, but the number of image processing modules that work together is not limited to this and may be, for example, three or more. In the third embodiment, a case in which three or more image processing modules work together will be described.

[0053] Fig. 15 is a diagram showing an example of a configuration of connections between image processing modules according to this embodiment. Fig. 15 shows an example in which image processing module A and image processing module B exchange image data via linkage buffer P105, and image processing module B and image processing module C exchange image data via linkage buffer Q105.

[0054] Image processing module A writes image data processed by image processing unit 200 to concatenated buffer P using a write DMAC. When write DMAC 205 provided in the image processing module completes writing the processed image data, it sends a write completion signal 217 to image processing module B using a write completion communication unit. Image processing module B reads the image data written by image processing module A from concatenated buffer P using a read DMAC 204. When read DMAC 204 completes reading the image data required for processing, it sends a read completion signal 211 to image processing module A using a read completion communication unit. The write completion signal 217 and the read completion signal 211 are input to transmission count conversion units 1520 and 1523, respectively, and are notified via image processing module connection unit 118 as converted signals 1521 and 1522. This configuration allows image processing modules to cooperate without CPU 103 intervention in controlling the startup of each processing unit.

[0055] Furthermore, image processing module B writes the image data processed by image processing unit 200 to link buffer Q using write DMAC 1505. When write of the processed image data is complete, write DMAC 1505 transmits write end signal 517 to image processing module C. Image processing module C reads the image data written by image processing module B from link buffer Q using read DMAC 1504. When read DMAC 1504 completes reading of the image data required for processing, it transmits read end signal 1511 to image processing module B using a read end communication unit. Write end signal 1517 and read end signal 1511 are input to transmission count conversion units 1524 and 1527, respectively, and are notified via image processing module connection unit 118 as converted signals 1525 and 1526. This configuration allows image processing modules to cooperate without CPU 103 intervention in controlling the startup of each processing unit.

[0056] Fig. 16 is a diagram showing an example of input / output data between concatenated buffers in the image processing device 100 according to this embodiment. Fig. 16(a) shows output data written by image processing module A to concatenated buffer P. In Fig. 16(a), image processing module A outputs image data in band units of four lines in accordance with the free space in concatenated buffer P, and when the output of each band unit is complete, it sends a write end signal 217 to image processing module B.

[0057] 16(b) shows input data that image processing module B reads from concatenated buffer P. In FIG. 16(b), image processing module B starts inputting image data with a different number of lines for each band according to the amount of data stored in the concatenated buffer P, and sends a read end signal 211 to image processing module A when input for each band is completed.

[0058] Figure 16(c) shows the output data written by image processing module B to concatenation buffer Q. Image processing module B according to this embodiment converts 22 lines of input data into 32 lines using stepless interpolation scaling processing, and then deletes the bottom two lines using trimming processing in the final operation. In Figure 16(c), image processing module B outputs image data in band units of four lines each (only the final band is trimmed to output two lines), according to the available space in concatenation buffer Q, and when the output of each band is complete, it sends a write end signal 1517 to image processing module C.

[0059] 16(d) shows input data that image processing module C reads from concatenation buffer Q. In FIG. 16(d), image processing module C starts inputting image data in band units for each line according to the amount of data stored in the concatenation buffer, and when input in band units is completed, it sends a read end signal 1511 to image processing module B.

[0060] Fig. 17 is a timing chart showing an example of the timing of the linked buffer control process with a variable processing unit size according to this embodiment. The following describes the control timing when the image processing modules A, B, and C shown in Fig. 15 process the input / output data shown in Fig. 16(a), (b), (c), and (d).

[0061] Operations 1701 to 1706 of image processing module A indicate operations during a write transfer period of image data in band units in Fig. 16(a). Operations 1721 to 1728 of image processing module B indicate operations during a read transfer period of image data in band units in Fig. 16(b). The transition of the retention counter indicates the transition of the count values ​​of the link buffer P retention counters 214 and 208 that constitute image processing modules A and B.

[0062] Counting up occurs at the timing when image processing module A finishes writing, for example, at timing 1712 when write transfer of image data in units of bands is completed. In this embodiment, the value to be counted up is included in parameter group A 212 or group D 219 notified from the CPU, and is 1 in this case. Also, counting down occurs at the timing when image processing module B finishes reading, for example, at timing 1738 when read transfer of image data in units of bands is completed.

[0063] The write transfer start process of the image processing module A is controlled to start up (for example, at timing 1711) if the free space is equal to or larger than the processing unit (four lines) (band unit) of the image processing module A according to the count values ​​of the linkage buffer P retention counters 214 and 208. On the other hand, when the count value of the linkage buffer P retention counter is five or larger, the write activation determination unit 215 determines that the free space is three lines or less and therefore the image processing module A cannot be activated, and performs wait control 1707 to 1710.

[0064] The read transfer start process of image processing module B is controlled in accordance with the count values ​​of linkage buffer P retention counters 214 and 208, and if the count value is equal to or greater than the processing unit (three lines) of image processing module B, activation control is performed (for example, at timing 1737). On the other hand, if the count value of the linkage buffer P retention counter is 2 or less, the read activation determination unit 209 determines that image processing module B cannot be activated because the accumulated amount is less than three lines, and performs wait control 1729 to 1731.

[0065] Furthermore, operations 1741 to 1748 of image processing module B indicate operations during a write transfer period of image data in band units in Fig. 16(c). Operations of image processing module C indicate operations during a read transfer period of image data in band units in Fig. 16(d). Transitions of the retention counters indicate transitions of the count values ​​of link buffer Q retention counters 1514 and 1508 constituting image processing modules B and C.

[0066] Counting up occurs at the timing when image processing module B finishes writing, for example, at timing 1760 when write transfer of image data in units of bands is completed. In this embodiment, the value to be counted up is included in parameter group A 1512 or group D 1519 notified from the CPU, and is 1 in this case. Also, counting down occurs at the timing when image processing module C finishes reading, for example, at timing 1763 when read transfer of image data in units of bands is completed.

[0067] The write transfer start process of image processing module B is controlled to start in accordance with the count values ​​of linkage buffer Q retention counters 1514 and 1508 if the available capacity is equal to or greater than the processing unit (4 lines) of image processing module B (for example, timing 1759). The read transfer start process of image processing module C is controlled to start in accordance with the count values ​​of linkage buffer Q retention counters 1514 and 1508 if the count values ​​are equal to or greater than the processing unit (1 line) of image processing module C (for example, timing 1762).

[0068] Incidentally, image processing module B receives a notification of write DMAC activation permission (for example, at timing 1759) if there is free space in the concatenation buffer Q according to the count values ​​of concatenation buffer Q retention counters 1514 and 1508. However, if there is no processed data, it does not perform a write transfer (periods 1749 to 1751). Then, image processing module B performs a write transfer if processed data exists (timing 1757). Furthermore, even if processed data exists, image processing module B does not perform a write transfer until it receives a notification of write DMAC activation permission (periods 1752 to 1756). At this time, data being processed accumulates in the image processing unit, and when the internal buffer becomes full, it cannot receive any more data, so the read operation stops (periods 1732 to 1736).

[0069] As described above, even in the case of cooperation between three or more image processing modules, the image processing modules that share a linked buffer can cooperate with each other by notifying each other via the image processing module connection unit 118 of signals converted by the transmission count conversion unit, which start with the read end signal and write end signal. The image processing modules can cooperate without the intervention of the CPU 103 in controlling the startup of each processing unit. In other words, by unifying the image processing modules into the image processing modules 107 to 113 shown in FIG. 1 and switching the connection via the image processing module connection unit 118, cooperation control between any image processing modules is possible even when image processing with a variable processing unit size is required. Furthermore, the connection switching in the image processing module connection unit 118 can be performed based on a processing mode input by the user. For example, when a user inputs an arbitrary image from an external host and prints it using a recording device, by connecting the signals converted by the transmission count conversion unit starting from the read end signals and write end signals of image processing modules 107 and 111, and image processing modules 111 and 112, it becomes possible to link rendering processing, quantization processing, and compressed data generation without the need for CPU 103 to intervene in startup control between each module.

[0070] The disclosure of this specification includes the following image processing device, image processing method, and program. (Item 1) The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band. a first transmission means for transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a second transmission means for transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; a first conversion means for converting the second transmission signal for each of the second bands in accordance with the number of lines included in the second band; a first determination means for determining whether or not the first module can write one band of data based on the first transmission signal and the second transmission signal converted by the first conversion means; An image processing device comprising: (Item 2) Item 1, the image processing device characterized in that the first conversion means converts the second transmission signal into a transmission signal of a width or number corresponding to the number of lines contained in the second band. (Item 3) 3. The image processing device according to item 1 or 2, wherein the number of lines included in the second band unit varies for each of the second bands. (Item 4) The image processing device described in any one of items 1 to 3, characterized in that the first conversion means converts the second transmission signal even when the number of lines included in the first band unit is common between the first bands. (Item 5) The image processing device described in any one of items 1 to 4, characterized in that the first conversion means converts the second transmission signal when the number of lines included in the second band unit varies for each second band. (Item 6) further comprising an acquisition means for acquiring a user input for setting whether or not the first conversion means should convert the second transmission signal; 3. The image processing device according to item 1 or 2, characterized in that the first conversion means converts the second transmission signal when the first conversion means is set to convert the second transmission signal based on the user input. (Item 7) The image processing device described in any one of items 1 to 6, characterized in that the first determination means determines, based on the first transmission signal and the converted second transmission signal, to execute writing of one band by the first module when the available capacity of the memory is equal to or greater than the first band unit by the first module. (Item 8) a third transmission means for transmitting a third transmission signal for each third band, which indicates that the third module has finished writing the image data read by the second module into a second memory in third band units; a fourth transmission means for transmitting a fourth transmission signal for each of the fourth bands, the fourth transmission signal indicating that the data output to the second memory by the third module has been read from the memory in fourth band units different from the third band units; a second conversion means for converting the fourth transmission signal for each of the fourth bands in accordance with the number of lines included in the fourth band; a second determination means for determining whether or not the third module can write one band of data based on the third transmission signal and the fourth transmission signal converted by the second conversion means; 8. The image processing device according to any one of items 1 to 7, further comprising: (Item 9) Item 9. The image processing device according to item 8, further comprising a switching means for switching whether or not to perform control by the third transmission means, the fourth transmission means, the second conversion means, and the second determination means based on user input. (Item 10) The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band. a first transmission means for transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a second transmission means for transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; a third conversion means for converting the first transmission signal for each of the first bands in accordance with the number of lines included in the first band; a third determination means for determining whether or not the second module can read one band based on the first transmission signal converted by the third conversion means and the second transmission signal; An image processing device comprising: (Item 11) Item 11. The image processing device according to item 10, wherein the third conversion means converts the first transmission signal into a transmission signal of a width or number corresponding to the number of lines contained in the first band. (Item 12) Item 12. The image processing device according to item 10 or 11, wherein the number of lines included in the first band unit varies for each of the first bands. (Item 13) The image processing device described in any one of items 10 to 12, characterized in that the third conversion means converts the first transmission signal even when the number of lines included in the first band unit is common between the first bands. (Item 14) The image processing device described in any one of items 10 to 13, characterized in that the third conversion means converts the first transmission signal when the number of lines included in the first band unit varies for each of the first bands. (Item 15) further comprising an acquisition means for acquiring a user input for setting whether or not the third conversion means should convert the first transmission signal; Item 10 or 11, characterized in that the third conversion means converts the first transmission signal when set to convert the first transmission signal based on the user input. (Item 16) The image processing device described in any one of items 10 to 15, characterized in that the third determination means determines, based on the converted first transmission signal and the second transmission signal, to execute reading of one band by the second module when the accumulated amount of image data written to the memory but not yet read is equal to or greater than a first band unit by the first module. (Item 17) a third transmission means for transmitting a third transmission signal for each third band, which indicates that the third module has finished writing the image data read by the second module into a second memory in third band units; a fourth transmission means for transmitting a fourth transmission signal for each of the fourth bands, the fourth transmission signal indicating that the data output to the second memory by the third module has been read from the memory in fourth band units different from the third band units; a fourth conversion means for converting the third transmission signal for each of the third bands in accordance with the number of lines included in the third band; a fourth determination means for determining whether or not the fourth module can read one band based on the third transmission signal converted by the fourth conversion means and the fourth transmission signal; 17. The image processing device according to any one of items 10 to 16, further comprising: (Item 18) Item 18. The image processing device according to item 17, further comprising a switching means for switching whether or not to perform control by the third transmission means, the fourth transmission means, the third conversion means, and the fourth determination means based on user input. (Item 19) The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band. transmitting a first transmission signal for each first band, which indicates that a first module that writes image data into a memory in units of the first band has finished writing the image data; a step of transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; converting the second transmission signal for each of the second bands according to the number of lines included in the second band; determining whether or not the first module can write one band of data based on the first transmission signal and the converted second transmission signal; An image processing method comprising: (Item 20) The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band. transmitting a first transmission signal for each first band, which indicates that a first module that writes image data into a memory in units of the first band has finished writing the image data; a step of transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; converting the first transmission signal for each of the first bands according to the number of lines included in the first band; determining whether or not the second module can read one band based on the converted first transmission signal and the converted second transmission signal; An image processing method comprising: (Item 21) A program for causing a computer to function as each means of the image processing device according to any one of items 1 to 9. (Item 22) A program for causing a computer to function as each means of the image processing device according to any one of items 10 to 18.

[0071] (Other Examples) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0072] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0073] 100: Image processing device, 101: External host device, 115: Recording device, 116: Scanning device

Claims

1. The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band, a first transmission means for transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a second transmission means for transmitting a second transmission signal for each second band, indicating that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; a first conversion means for converting the second transmission signal for each of the second bands in accordance with the number of lines included in the second band; a first determination means for determining whether or not the first module can write one band of data based on the first transmission signal and the second transmission signal converted by the first conversion means; An image processing device comprising:

2. 2. The image processing device according to claim 1, wherein the first conversion means converts the second transmission signal into a transmission signal having a width or number corresponding to the number of lines included in the second band.

3. 2. The image processing device according to claim 1, wherein the number of lines included in the second band unit varies for each of the second bands.

4. 2. The image processing device according to claim 1, wherein the first conversion means converts the second transmission signal even when the number of lines included in the first band unit is common between the first bands.

5. 2. The image processing device according to claim 1, wherein the first conversion means converts the second transmission signal when the number of lines included in the second band unit varies for each second band.

6. further comprising an acquisition means for acquiring a user input for setting whether or not the second transmission signal is to be converted by the first conversion means; 2. The image processing device according to claim 1, wherein the first conversion means converts the second transmission signal when the first conversion means is set to convert the second transmission signal based on the user input.

7. 2. The image processing device according to claim 1, wherein the first determination means determines, based on the first transmission signal and the converted second transmission signal, to execute writing of one band by the first module when the available capacity of the memory is equal to or greater than a first band unit by the first module.

8. a third transmission means for transmitting a third transmission signal for each third band, which indicates that the third module has finished writing the image data read by the second module into a second memory in third band units; a fourth transmission means for transmitting a fourth transmission signal for each of the fourth bands, the fourth transmission signal indicating that the data output to the second memory by the third module has been read from the memory in fourth band units different from the third band units, has been read; a second conversion means for converting the fourth transmission signal for each of the fourth bands in accordance with the number of lines included in the fourth band; a second determination means for determining whether or not the third module can write one band of data based on the third transmission signal and the fourth transmission signal converted by the second conversion means; The image processing device according to claim 1 , further comprising:

9. 9. The image processing device according to claim 8, further comprising: a switching unit that switches whether or not to perform control by the third transmitting unit, the fourth transmitting unit, the second converting unit, and the second determining unit based on a user input.

10. The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band, a first transmission means for transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a second transmission means for transmitting a second transmission signal for each second band, indicating that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; a third conversion means for converting the first transmission signal for each of the first bands in accordance with the number of lines included in the first band; a third determination means for determining whether or not the second module can read one band based on the first transmission signal converted by the third conversion means and the second transmission signal; An image processing device comprising:

11. 11. The image processing device according to claim 10, wherein the third conversion means converts the first transmission signal into a transmission signal having a width or number corresponding to the number of lines included in the first band.

12. 11. The image processing device according to claim 10, wherein the number of lines included in the first band unit varies for each of the first bands.

13. 11. The image processing device according to claim 10, wherein the third conversion means converts the first transmission signal even when the number of lines included in the first band unit is common between the first bands.

14. 11. The image processing device according to claim 10, wherein the third conversion means converts the first transmission signal when the number of lines included in the first band unit varies for each of the first bands.

15. further comprising an acquisition means for acquiring a user input for setting whether or not the third conversion means should convert the first transmission signal; 11. The image processing device according to claim 10, wherein the third conversion means converts the first transmission signal when the third conversion means is set to convert the first transmission signal based on the user input.

16. 11. The image processing device according to claim 10, wherein the third determination means determines, based on the converted first transmission signal and the second transmission signal, to execute reading of one band by the second module when the amount of image data written to the memory but not yet read is equal to or greater than a first band unit by the first module.

17. a third transmission means for transmitting a third transmission signal for each third band, which indicates that the third module has finished writing the image data read by the second module into a second memory in third band units; a fourth transmission means for transmitting a fourth transmission signal for each of the fourth bands, the fourth transmission signal indicating that the data output to the second memory by the third module has been read from the memory in fourth band units different from the third band units, has been read; a fourth conversion means for converting the third transmission signal for each of the third bands in accordance with the number of lines included in the third band; a fourth determination means for determining whether or not the fourth module can read one band based on the third transmission signal converted by the fourth conversion means and the fourth transmission signal; The image processing device according to claim 10, further comprising:

18. 18. The image processing device according to claim 17, further comprising: a switching unit that switches whether or not to perform control by the third transmitting unit, the fourth transmitting unit, the third converting unit, and the fourth determining unit, based on a user input.

19. The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band, transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a step of transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; converting the second transmission signal for each of the second bands according to the number of lines included in the second band; determining whether or not the first module can write one band of data based on the first transmission signal and the converted second transmission signal; An image processing method comprising:

20. The minimum unit in the y direction of image data composed of two-dimensional pixel data is defined as a line, and a unit composed of one or more of the lines is defined as a band, transmitting a first transmission signal for each first band, the first transmission signal indicating that a first module that writes image data into a memory in units of a first band has finished writing the image data; a step of transmitting a second transmission signal for each second band, which indicates that the second module has finished reading the image data output to the memory by the first module from the memory in second band units different from the first band units; converting the first transmission signal for each of the first bands according to the number of lines included in the first band; determining whether or not the second module can read one band based on the converted first transmission signal and the converted second transmission signal; An image processing method comprising:

21. A program for causing a computer to function as each of the means of the image processing device according to any one of claims 1 to 9.

22. A program for causing a computer to function as each of the means of the image processing device according to any one of claims 10 to 18.

Images