Memory device

Abstract

To provide a storage device that can store data with high precision. [Solution] The first memory cell includes a first magnetoresistive element and a first switching element connected to the first magnetoresistive element. The first wiring is connected to the first end of the first memory cell. The second wiring is connected to the second end of the first memory cell. The first switch has a third end connected to the second wiring and a fourth end. The third wiring is connected to the fourth end. The second switch has a fifth end connected to the third wiring and a sixth end. The fourth wiring is connected to the sixth end. The first transistor has a gate connected to the third wiring and a seventh end connected to the fourth wiring. The third switch is connected between the seventh end and a first node receiving a first voltage. The sense amplifier circuit is connected to the fourth wiring.

Description

Technical Field

[0001] Embodiments generally relate to a memory device.

Background Art

[0002] A memory device using a magnetoresistive effect element is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device capable of storing data with high precision.

Means for Solving the Problems

[0005] A memory device according to an embodiment includes a first memory cell, a first wiring, a second wiring, a first switch, a third wiring, a second switch, a fourth wiring, a first transistor, a third switch, and a sense amplifier circuit. The first memory cell includes a first magnetoresistive effect element and a first switching element connected to the first magnetoresistive effect element. The first wiring is connected to a first end of the first memory cell. The second wiring is connected to a second end of the first memory cell. The first switch has a third end connected to the second wiring and a fourth end. The third wiring is connected to the fourth end. The second switch has a fifth end connected to the third wiring and a sixth end. The fourth wiring is connected to the sixth end. The first transistor has a gate connected to the third wiring and a seventh end connected to the fourth wiring. The third switch is connected between the seventh end and a first node that receives a first voltage. The sense amplifier circuit is connected to the fourth wiring. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the functional block of the storage device according to the first embodiment. [Figure 2] Figure 2 shows the functional block of the core circuit of the storage device according to the first embodiment. [Figure 3] Figure 3 shows the components and connections of the GWL selector and GBL selector of the storage device in the first embodiment. [Figure 4] Figure 4 shows the functional block of the subcore circuit of the memory device according to the first embodiment. [Figure 5] Figure 5 shows the components and connections of the WL selector and BL selector of the storage device in the first embodiment. [Figure 6] Figure 6 is a perspective view of a portion of the memory cell array of the storage device according to the first embodiment. [Figure 7] Figure 7 shows a cross-sectional view of an example of the memory cell structure of the first embodiment of the storage device. [Figure 8] Figure 8 shows an example of the voltage and current characteristics of a memory cell in the first embodiment of the storage device. [Figure 9] Figure 9 shows the components of the conversion circuit of the storage device according to the first embodiment, the connections of the components, and related components. [Figure 10] Figure 10 shows an example of the components and connections of the read circuit of the storage device according to the first embodiment. [Figure 11] Figure 11 shows a partial layout of the storage device of the first embodiment. [Figure 12] Figure 12 shows the potentials of several signals and wiring over time during data retrieval from the storage device of the first embodiment. [Figure 13] Figure 13 shows the components and connections of the sense amplifier circuit of a modified memory device according to the first embodiment. [Figure 14] Figure 14 shows the potentials of several signals and wiring over time during data retrieval from the storage device in the second embodiment. [Figure 15] Figure 15 shows the potentials of several signals and wiring over time during data retrieval from the storage device in the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may have additional numbers or letters appended to the end of their reference numerals to distinguish them from one another. Embodiments following a previously described embodiment primarily describe the differences from the previously described embodiment. All descriptions of an embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded.

[0008] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0009] The following embodiments are described using a three-dimensional Cartesian coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, with upwards pointing in the Z direction. The direction opposite to the Z direction is referred to as the -Z direction, with downwards pointing in the -Z direction.

[0010] 1. First Embodiment 1.1.Configuration (Structure) Figure 1 shows the functional block of the storage device according to the first embodiment. The storage device 1 includes a core circuit 111, an input / output circuit 12, a control circuit 13, a decode circuit 14, a page buffer 15, and a voltage generation circuit 16.

[0011] The core circuit 11 is a circuit that includes multiple memory cells MC, as well as wiring and circuits for accessing the memory cells MC.

[0012] The input / output circuit 12 is a circuit that performs input / output of data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, address information ADD, and data DAT from outside the storage device 1, for example, from a memory controller. The input / output circuit 12 outputs the data DAT.

[0013] The control circuit 13 receives the command CMD and the control signal CNT from the input / output circuit 12. Based on the control instructed by the command CMD and the control signal CNT, the control circuit 13 controls the core circuit 11 and controls the reading of data from the memory cell MC and the writing of data to the memory cell MC. The control circuit 13 controls the voltage generation circuit 16 based on the control instructed by the command CMD and the control signal CNT.

[0014] The decode circuit 14 is a circuit that decodes the address information ADD. The decode circuit 14 receives the address information ADD from the input / output circuit 12. The decode circuit 14 decodes the address information ADD and generates a signal for selecting the memory cell MC to be the target of data reading or data writing based on the result of the decoding. The generated signal is transmitted to the core circuit 11.

[0015] The page buffer 15 is a circuit that temporarily stores data of a certain size. The page buffer 15 receives the data DAT to be written to the memory cell MC from the input / output circuit 12, temporarily stores the data, and transfers the data to the core circuit 11. The page buffer 15 receives the data read from the memory cell MC, temporarily stores the read data, and transfers the data DAT to the input / output circuit 12.

[0016] The voltage generation circuit 16 supplies the voltage used for data writing to the core circuit 11 during the writing of data to the memory cell MC. The voltage generation circuit 16 supplies the voltage used for data reading to the core circuit 11 during the reading of data from the memory cell MC.

[0017] Figure 2 shows the functional blocks of the core circuit of the memory device according to the first embodiment. As shown in Figure 2, the core circuit 11 includes a plurality of subcore circuits SCC, a plurality of global word lines GWL, a plurality of global bit lines GBL, a GWL selector GWS, a GBL selector GBS, a conversion circuit set CCS, wiring FWL, wiring FBL, a write circuit 18, and a read circuit 19.

[0018] Each subcore circuit (SCC) is a set of multiple components, including multiple memory cells (MCs), multiple selectors, and multiple wirings. Each subcore circuit (SCC) is connected to one global word line (GWL) and one global bit line (GBL).

[0019] Each global word line (GWL) is connected to multiple sub-core circuits (SCC). Each global bit line (GBL) is connected to multiple sub-core circuits (SCC).

[0020] A GWL selector GWS is a circuit that selects one of several global word lines GWL. Each GWL selector GWS receives an address information ADD or a signal based on address information ADD, and connects one of the several global word lines GWL identified by the received address information ADD or signal based on address information to a wiring FWL.

[0021] A GBL selector (GBS) is a circuit that selects one of several global bit lines (GBLs). Each GBL selector (GBS) receives an address information ADD or a signal based on an address information ADD and connects one of the several global bit lines (GBLs) identified by the received address information ADD or signal based on an address information ADD to a wiring FBL.

[0022] The conversion circuit set CCS is a set of circuits that convert current to voltage. The conversion circuit set CCS is connected between the wiring FBL and the global bit line GBL. The conversion circuit set CCS applies a voltage to the wiring FBL whose magnitude is based on the current flowing through the global bit line GBL.

[0023] The writing circuit 18 is a circuit that controls the writing of data to the memory cell MC. The writing circuit 18 receives the write data DAT from the input / output circuit 12 and the voltage for data writing from the voltage generation circuit 16. Based on the control of the control circuit 13 and the write data DAT, the writing circuit 18 supplies the voltage and current used for data writing to the wiring FWL and FBL.

[0024] The read circuit 19 is a circuit that controls the reading of data from the memory cell MC. The read circuit 19 receives a voltage used for data reading from the voltage generation circuit 16. Based on the control of the control circuit 13, the read circuit 19 uses the voltage used for data reading to determine the data stored in the memory cell MC. The determined data is supplied to the input / output circuit 12 as read data DAT. The read circuit 19 includes multiple sense amplifier circuits SAC. The sense amplifier circuits SAC are circuits that output data that is determined to be stored in the memory cell MC to be read, using a voltage based on the data stored in the memory cell MC to be read. Details of the sense amplifier circuits SAC will be described later.

[0025] Figure 3 shows the components and connections of the GWL selector and GBL selector of the storage device in the first embodiment. As shown in Figure 3, the GWL selector GWS includes the same number of switches GWSW as the number of subcore circuits SCC connected to each global bit line GBL. Each switch GWSW is connected to a wiring FWL at one end and to a single global word line GWL at the other end. Each switch GWSW is a p-type or n-type MOSFET, or a p-type and n-type MOSFET connected in parallel and receiving complementary signals at their respective gates. This description of the switch GWSW also applies to the switches GWSW, WSW, BSW, SW1, SW2, SW3, SW4, SW5, SW6, SW11, and SW12 described later. Each switch GWSW is turned on or off by control of the read circuit 19 or write circuit 18 based on address information ADD or a signal based on address information.

[0026] The GBL selector GBS includes the same number of switches GBSW as the number of subcore circuits SCC connected to each global word line GWL. Each switch GBSW is connected to a wiring FBL at one end and to a single global bit line GBL at the other end. Each switch GBSW is turned on or off by control of a read circuit 19 or a write circuit 18 based on address information ADD or a signal based on address information.

[0027] A conversion circuit set CCS includes the same number of conversion circuits CC as the number of subcore circuits SCC connected to each global word line GWL. Each conversion circuit CC is connected between a wiring FBL and one global bit line GBL. Each conversion circuit CC applies a voltage to the global bit line GBL connected to it, the voltage being determined by the current flowing through the wiring FBL to which it is connected.

[0028] Figure 4 shows the functional blocks of the subcore circuits of the memory device according to the first embodiment. As shown in Figure 4, each subcore circuit SCC includes a memory cell array MCA, multiple word lines WL, multiple bit lines BL, a WL selector WS, a BL selector BS, a global word line GWL, and a global bit line GBL.

[0029] A memory cell array (MCA) is a collection of multiple memory cells (MCs) arranged in a sequence. Memory cells (MCs) can store data non-volatilely. Word lines (WL) and bit lines (BL) are also located within the memory cell array (MCA). The following description is based on an example where word lines (WL) are associated with rows and bit lines (BL) are associated with columns. Word lines (WL) and bit lines (BL) are simply names used to distinguish between two types of wiring, and they may have opposite names. Each memory cell (MC) is connected to one word line (WL) and one bit line (BL). A single memory cell (MC) is identified by selecting one row and one column.

[0030] Each word line WL is connected to multiple memory cells MC. Each bit line BL is connected to multiple memory cells MC. Each memory cell MC contains one MTJ element MTJ and one switching element SE. In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SE of each memory cell MC is connected to one word line WL. The MTJ element MTJ of each memory cell MC is connected to one bit line BL.

[0031] MTJ elements are elements that exhibit the tunnel magnetoresistance effect, such as magnetic tunnel junctions (MTJs). MTJ elements are also called magnetoresistive element MTJs. MTJ elements are variable resistor elements that can switch between a low-resistance state and a high-resistance state. MTJ elements can store 1-bit data by utilizing the difference between the two resistance states. In one example, an MTJ element stores "0" data in the low-resistance state and "1" data in the high-resistance state.

[0032] A switching element SE has two terminals and is an element that performs electrical connection or disconnection between the two terminals. When the voltage applied between the two terminals in the first direction is below a certain threshold voltage, the switching element SE is in a high-resistance state, for example, electrically non-conductive (off state). When the voltage applied between the two terminals increases and exceeds the threshold voltage, the switching element SE becomes low-resistance, for example, electrically conductive (on state). When the voltage applied between the two terminals of the low-resistance switching element SE decreases and falls below the threshold voltage, the switching element SE becomes high-resistance. The switching element SE has the same function of switching between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction, but also in a second direction opposite to the first direction. In other words, the switching element SE is a bidirectional switching element. By turning the switching element SE on or off, it is possible to control whether or not current is supplied to the MTJ element MTJ connected to the switching element SE, i.e., the selection or deselection of the MTJ element MTJ.

[0033] Each WL selector WS is a circuit that selects one of several word lines WL. Each WL selector WS receives an address information ADD or a signal based on an address information ADD, and connects one word line WL, identified by the received address information ADD or a signal based on an address information ADD, to a single global word line GWL.

[0034] Each BL selector BS is a circuit that selects one of several bit lines BL. Each BL selector BS receives address information ADD or a signal based on address information ADD, and connects one bit line BL, identified by the received address information ADD or a signal based on address information ADD, to one global bit line GBL.

[0035] Figure 5 shows the components and connections of the WL selector and BL selector of the storage device in the first embodiment. As shown in Figure 5, the WL selector WS includes the same number of switches WSW as the number of memory cells MC connected to each bit line BL. Each switch WSW is connected to a global word line GWL at one end and to a word line WL at the other end. Each switch WSW is turned on or off by control of a read circuit 19 based on address information ADD or a signal based on address information ADD.

[0036] The BL selector BS includes the same number of switches BSW as the number of memory cells MC connected to each word line WL. Each switch BSW is connected to a global bit line GBL at one end and to a single bit line BL at the other end. Each switch BSW is turned on or off by control of a read circuit 19 based on address information ADD or a signal based on address information ADD.

[0037] In the examples of Figures 2, 3, 4, and 5, the core circuit 11 has two layers. The lowest first layer includes the configuration shown in Figure 4, namely the set of memory cell MC, word line WL, bit line BL, WL selector WS, and BL selector BS. The second layer includes the configuration shown in Figure 2, namely the set of subcore circuit SCC, global word line GWL, global bit line GBL, GWL selector GWS, and GBL selector GBS.

[0038] The core circuit 11 may have three or more layers. When the selector switch in each layer is turned on, one word line WL is connected to the write circuit 18 and the read circuit 19. Similarly, when the selector switch in each layer is turned on, one bit line BL is connected to the write circuit 18 and the read circuit 19.

[0039] Figure 6 is a perspective view of a portion of the memory cell array of the storage device according to the first embodiment. As shown in Figure 6, a plurality of conductors 21 and a plurality of conductors 22 are provided.

[0040] The conductors 21 have a linear shape, extend in the X direction, and are aligned in the Y direction. Each conductor 21 functions as at least part of a word line WL.

[0041] The conductor 22 is located in the Z direction relative to the conductor 21. The conductor 22 has a linear shape, extends in the Y direction, and is aligned in the X direction. Each conductor 22 functions as at least part of one bit line BL.

[0042] One memory cell MC is provided at each intersection of conductor 21 and conductor 22. The memory cell MCs are arranged in a matrix along the xy-plane, which consists of the X and Y directions. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as an MTJ element MTJ each include one or more layers. For example, the structure that functions as an MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of one conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of one conductor 22.

[0043] Figure 7 shows a cross-section of an example of the structure of a memory cell of a first embodiment of a memory device. The switching element SE includes a variable resistance material 32. The variable resistance material 32 is a material that exhibits dynamically variable resistance and has, for example, a layered shape. The variable resistance material 32 is a two-terminal switching element, where the first terminal of the two terminals is one of the upper and lower surfaces of the variable resistance material 32, and the second terminal of the two terminals is the other of the upper and lower surfaces of the variable resistance material 32. When the voltage applied between the two terminals is less than a certain threshold voltage, the variable resistance material is in a "high resistance" state, for example, electrically non-conductive. When the voltage applied between the two terminals increases and exceeds the threshold voltage, the variable resistance material enters a "low resistance" state, for example, electrically conductive. When the voltage applied between the two terminals of the low-resistance variable resistance material 32 decreases and falls below the threshold voltage, the variable resistance material enters a high resistance state.

[0044] In one example, the variable resistor material 32 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide and a material substantially composed of SiO2 or SiO2. The dopant includes, in one example, arsenic (As) and germanium (Ge). The phrase "substantially composed of" and similar phrases means that the "substantially composed" components may contain unintended impurities.

[0045] The switching element SE may further include a lower electrode 31 and an upper electrode 33. Figure 7 shows such an example. The variable resistor material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistor material 32.

[0046] The MTJ element includes a ferromagnetic layer 35, an insulating layer 36, and a ferromagnetic layer 37. For example, as shown in Figure 7, the insulating layer 36 is located on the upper surface of the ferromagnetic layer 35, and the ferromagnetic layer 37 is located on the upper surface of the insulating layer 36.

[0047] The ferromagnetic layer 35 is a layer of material exhibiting ferromagnetism. The ferromagnetic layer 35 has an easy magnetization axis aligned with the direction penetrating the interface between the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° to 90° with respect to the interface, and in another example, it has an easy magnetization axis aligned with a direction perpendicular to the interface. The direction of magnetization of the ferromagnetic layer 35 remains unchanged even when data is read and written in the memory cell MC. The ferromagnetic layer 35 can function as a so-called reference layer RL. The ferromagnetic layer 35 may include multiple layers. Hereinafter, the ferromagnetic layer 35 may be referred to as the reference layer RL.

[0048] The insulating layer 36 is an insulating layer. The insulating layer 36 contains, for example, magnesium oxide (MgO) or is substantially composed of MgO and functions as a so-called tunnel barrier (TB).

[0049] The ferromagnetic layer 37 is a layer of ferromagnetic material. The ferromagnetic layer 37 contains, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer 37 has an easy magnetization axis along the direction that penetrates the interface of the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° to 90° with respect to the interface, and in another example, it has an easy magnetization axis along the direction perpendicular to the interface. The direction of magnetization of the ferromagnetic layer 37 is variable by writing data to the memory cell MC, and the ferromagnetic layer 37 can function as a so-called memory layer (SL). Hereinafter, the ferromagnetic layer 37 may be referred to as the memory layer SL.

[0050] When the magnetization direction of the memory layer SL is parallel to the magnetization direction of the reference layer RL, the MTJ element MTJ has a certain low resistance. When the magnetization direction of the memory layer SL is antiparallel to the magnetization direction of the reference layer RL, the MTJ element MTJ has a higher resistance than when the magnetization directions of the memory layer SL and the reference layer RL are antiparallel.

[0051] When a current of a certain magnitude, Icp or greater, flows from the memory layer SL towards the reference layer RL, the magnetization direction of the memory layer SL becomes parallel to the magnetization direction of the reference layer RL. When a current of a certain magnitude, Icap or greater, flows from the reference layer RL towards the memory layer SL, the magnetization direction of the memory layer SL becomes antiparallel to the magnetization direction of the reference layer RL.

[0052] The MTJ element may include further layers.

[0053] Figure 8 shows an example of the voltage and current characteristics of a memory cell in the first embodiment of the memory device. The horizontal axis of the graph shows the magnitude of the terminal voltage of the memory cell MC (i.e., the potential difference across its terminals). The vertical axis of the graph shows the magnitude of the current flowing through the memory cell MC on a logarithmic scale. In Figure 8, hypothetical characteristics that do not actually occur are shown by dashed lines. Figure 8 shows the cases where the memory cell MC is in a low-resistance state and a high-resistance state.

[0054] As the voltage increases from zero, the current continues to increase until it reaches the threshold voltage Vth. Until the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is off, i.e., non-conducting.

[0055] When the voltage is further increased and reaches the threshold voltage Vth, i.e., point A, the relationship between voltage and current shows a discontinuous change, exhibiting the characteristics shown at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly larger than the magnitude of the current at point A. This abrupt change in current is due to the switching element SE of the memory cell MC being turned on. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.

[0056] When the voltage is reduced from a state where the switching element SE is ON, for example, a state where the voltage and current have the relationship shown at point B1 or point B2 and points with higher voltages than them, the current continues to decrease.

[0057] When the voltage is further reduced and reaches a certain magnitude, the relationship between voltage and current shows a discontinuous change. The voltage at which the relationship between voltage and current begins to show a discontinuity depends on the terminal voltage of the MTJ element of the memory cell MC, that is, whether the MTJ element is in a high-resistance state or a low-resistance state. When the MTJ element is in a low-resistance state, the relationship between voltage and current shows a discontinuity from point C1. When the MTJ element is in a high-resistance state, the relationship between voltage and current shows a discontinuity from point C2. When the relationship between voltage and current reaches points C1 and C2, it begins to show the characteristics shown at points D1 and D2, respectively. The magnitude of the current at points D1 and D2 is significantly smaller than the magnitude of the current at points C1 and C2, respectively. This abrupt change in current is based on the switching element SE of the memory cell MC being turned off.

[0058] The terminal voltage at point D1 of a memory cell MC containing a low-resistance MTJ element is called the low-hold voltage VhdL. The terminal voltage at point D2 of a memory cell MC containing a high-resistance MTJ element is called the high-hold voltage VhdH.

[0059] Figure 9 shows the components of the conversion circuit of the storage device according to the first embodiment, the connections of the components, and related components. Figure 9 shows an example of Q+1 global bit lines GBL_0 to GBL_Q.

[0060] Each conversion circuit CC includes an n-type MOSFET Tr1 and a switch SW1. The transistor Tr1 and switch SW1 are connected in series between the wiring FBL and the node receiving the ground voltage VSS. The transistor Tr1 is connected at its gate to one global bit line GBL. Switch SW1_0 receives the signal S1_0. Switch SW1_0 is turned on or off by the signal S1_0. Similarly, for all cases where α is an integer between 1 and Q, switch SW1_α receives the signal S1_α. Switch SW1_α is turned on or off by the signal S1_α. Signals S1_0 to S1_Q are supplied from the readout control circuit RCC. The readout control circuit RCC is included in the readout circuit 19.

[0061] Switch SW1 remains ON when it receives a high-level or "H" level signal S1, maintaining an electrically connected state between one end of Switch SW1 and the other end. Switch SW1 remains OFF when it receives a low-level or "L" level signal S1, maintaining an electrically disconnected state between one end of Switch SW1 and the other end.

[0062] The same applies to the switch SWn and signal Sn described later, where n is an integer greater than or equal to 2. That is, for switch SWn, the description for switch SW1 is replaced with the description for switch SWn, and for signal Sn, the description for signal S1 is replaced with the description for signal Sn.

[0063] For all cases where α is an integer between 0 and Q (inclusive), the read control circuit RCC maintains the signal S1_α at a high level during data readout, provided that the address information ADD specifies the global bit line GBL_α.

[0064] Figure 10 shows an example of the components and connections of the read circuit of the storage device according to the first embodiment. Figure 10 also shows, as a representative example, one memory cell MC to be read and the components associated with this memory cell MC. Hereinafter, the memory cell MC to be read or written may be referred to as the selected memory cell MC_s.

[0065] The switch GBSW used to connect the selected memory cell MC_s to the wiring FBL is referred to as switch GBSW_s. The signal that switch GBSW receives at the control terminal is referred to as signal SGB, and the signal that switch GBSW_s receives at the control terminal is sometimes referred to as signal SGB_s.

[0066] The readout circuit 19 further includes switches SW2, SW3, SW4, SW5, and SW6, an n-type MOSFET Tr2, and a sense amplifier circuit SAC.

[0067] Switch SW2 is connected between the node receiving the precharge voltage VPRCH and the wiring FBL. In one example, the precharge voltage VPRCH is supplied from the voltage generation circuit 16. The precharge voltage VPRCH is higher than the ground voltage VSS.

[0068] Switch SW3 is connected between wiring FBL and a node that receives a non-selective voltage VUSEL of a certain magnitude. In one example, the non-selective voltage VUSEL is supplied from a voltage generation circuit 16. The non-selective voltage VUSEL has a height between the ground voltage VSS and the precharge voltage VPRCH. In one example, the non-selective voltage VUSEL has a height of half the precharge voltage VPRCH.

[0069] Transistor Tr2 is connected at one end to a node that receives a constant positive voltage Vhh. The voltage Vhh is the internal power supply voltage of the memory device 1, and in one example, is lower than the power supply voltage VDD. In one example, the voltage Vhh is supplied from the voltage generation circuit 16. Transistor Tr2 receives a constant positive voltage Vload at its gate, and the voltage Vload is higher than the ground voltage VSS. In one example, the voltage Vload is supplied from the voltage generation circuit 16. Transistor Tr2 supplies a constant current at its other end, the magnitude of which depends on the magnitudes of the voltages Vhh and Vload.

[0070] Switch SW4 is connected between the other end of transistor Tr2 and wiring FBL.

[0071] The sense amplifier circuit SAC outputs data OUT, which is determined to be stored in the selected memory cell MC_s to be read, based on the supplied voltage. In one example, the sense amplifier circuit SAC includes an operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to wiring FBL. The inverting input of the operational amplifier OP receives a voltage VREF of a constant magnitude. In one example, the voltage VREF has a height between a high hold voltage VhdH and a low hold voltage VhdL.

[0072] Switch SW5 is connected between the wiring FWL and the node receiving the non-selective voltage VUSEL. Switch SW6 is connected between the wiring FWL and the node receiving the ground voltage VSS.

[0073] The readout control circuit RCC outputs signals S2, S3, S4, S5, and S6.

[0074] Figure 11 shows a partial layout of the storage device of the first embodiment. As shown in Figure 11, the storage device 1 includes a substrate 41. The substrate 41 extends along the xy plane. The storage device 1 includes regions 42_1 and 42_2.

[0075] Region 42_1 includes multiple source / drain regions 43_1 and multiple conductors 45_1. The source / drain regions 43_1 have various dimensions and shapes. The conductors 45_1 have various dimensions and shapes. The source / drain regions 43_1 are arranged irregularly. Each source / drain region 43_1 and the portion of the conductor 45_1 that overlaps with this source / drain region 43_1 function as a transistor TR_1. In one example, the transistor TR_1 is a transistor in a sense amplifier circuit SAC.

[0076] Region 42_2 includes multiple source / drain regions 43_2 and multiple conductors 45_2. The source / drain regions 43_2 and conductors 45_2 are arranged regularly. In the example in Figure 11, the source / drain regions 43_2 have the same dimensions or dimensions equal to a certain standard dimension and are arranged in a matrix. The conductors 45_2 are also arranged regularly. In the example in Figure 11, the conductors 45_2 have the same dimensions in the Y direction and are aligned in the X direction.

[0077] Each source / drain region 43_2 and the portion of the conductor 45_2 that overlaps with this source / drain region 43_2 function as a transistor TR_2. In one example, the transistor TR_2 is the switches GWSW, GBSW, WSW, and BSW. In another example, the transistor TR_2 is the transistor Tr1 and the switch SW1. That is, the conversion circuit CC is located in region 42_2.

[0078] Region 42_2 does not contain source / drain regions and conductors with irregular shapes, dimensions, and / or arrangements like those in region 42_1.

[0079] 1.2.Operation Figure 12 shows the potentials of several signals and wirings over time during data readout of the storage device in the first embodiment. Figure 12 shows the state in which one selected memory cell MC_s for data readout is selected. That is, the switches BSW, WSW, and GWSW connected to the selected memory cell MC_s are ON for the period shown in Figure 12. The operation during the period shown in Figure 12 begins when data readout starts with the selected memory cell MC_s for data readout selected.

[0080] During the period shown in Figure 12, the selected memory cell MC_s for data readout is selected, and for that purpose, the signal SB_s is high during the period shown in Figure 12. The signal SB_s is a signal that turns on or off the switch BSW connected to the selection bit line BL_s. The selection bit line BL_s is the bit line BL connected to the selected memory cell MC_s. Due to the high-level signal SB_s, during the period shown in Figure 12, the selection bit line BL_s is connected to one global bit line GBL via the ON switch BSW. Hereinafter, the global bit line GBL connected to the selection bit line BL_s via the ON switch BSW may be referred to as the selected global bit line GBL_s.

[0081] During the period shown in Figure 12, the signal SGB_ns is at a low level. The signal SGB_ns is a signal that turns on or off the switch GBSW_ns connected to a global bit line GBL other than the selected global bit line GBL_s. Hereinafter, global bit lines GBL other than the selected global bit line GBL_s may be referred to as unselected global bit lines GBL_ns. Due to the low level signal SGB_ns, the switch GBSW_ns is off, and therefore, during the period shown in Figure 12, the unselected global bit line GBL_ns is disconnected from the wiring FBL.

[0082] During the period shown in Figure 12, the signal S1_ns has a low level. Signal S1_ns is the signal S1 supplied to switch SW1 in the conversion circuit CC connected to the unselected global bit line GBL_ns.

[0083] At time t1, signal S1_s is at a low level. Signal S1_s is the signal S1 supplied to switch SW1 in the conversion circuit CC connected to the selected global bit line GBL_s. Due to the low level of signal S1_s, switch SW1 in the conversion circuit CC connected to the selected global bit line GBL_s is turned off.

[0084] At time t1, signals S2, S4, and S6 are at a low level, while signals S3 and S5 are at a high level. Therefore, switches SW2, SW4, and SW6 are off, and switches SW3 and SW5 are on.

[0085] At time t1, signal SGB_s is at a low level. Signal SGB_s is a signal that turns on or off switch GBSW_s, which is connected to the global bit line GBL, which is connected to the ON switch BSW. Due to the low level of signal SGB_s, switch GBSW_s is OFF.

[0086] Based on the fact that switch SW2 is off and switch SW3 is on, wiring FBL is subjected to a non-selective voltage VUSEL, and therefore the potential of the selective bit line BL_s (selective bit line potential) VBL has a non-selective potential VUSEL. The non-selective potential VUSEL is the magnitude of the potential that the wiring has due to being subjected to the non-selective voltage VUSEL, and in one example, it has substantially the same height as the non-selective voltage VUSEL.

[0087] Based on the fact that switch SW6 is off and switch SW5 is on, the wiring FWL is subjected to a non-selection voltage VUSEL, and therefore the potential (selection word line potential) VWL of the word line (selection word line) WL connected to the selection memory cell MC_s has a non-selection potential VUSEL.

[0088] At time t2, the signal SGB_s is set to a high level. As a result, the selected global bit line GBL_s is connected to the wiring FBL.

[0089] At time t2, signal S2 is set to a high level and signal S3 is set to a low level. As a result, switch SW2 is turned on and switch SW3 is turned off. Therefore, from time t2, the selected bit line potential VBL rises and reaches the precharge potential VPRCH. The precharge potential VPRCH is the potential of the wire when the precharge voltage VPRCH is applied, and in one example, it has substantially the same height as the precharge voltage VPRCH.

[0090] At time t3, signal S2 is set to a low level. As a result, switch SW2 is turned off, and wiring FBL, the selected global bit line GBL_s, and the selected bit line BL_s become electrically floating. After time t3, the selected bit line potential VBL remains at the precharge potential VPRCH.

[0091] At time t3, the signal SGB_s is set to a low level. As a result, the switch GBSW_s is turned off, and the selected global bit line GBL_s is disconnected from the wiring FBL.

[0092] At time t4, signal S5 is set to a low level and signal S6 is set to a high level. As a result, switch SW5 is turned off and switch SW6 is turned on. Therefore, the selected word line potential VWL decreases toward the ground potential VSS. The ground potential VSS is the potential that the wiring has when it receives the ground voltage VSS, and in one example, it is substantially the same height as the ground voltage VSS.

[0093] At time t5, the difference between the selected word line potential VWL and the selected bit line potential VBL reaches the threshold voltage Vth. As a result, the switching element SE of the selected memory cell MC_s turns on. Therefore, the selected word line WL is electrically connected to the selected bit line BL_s via the switched-on switching element SE in the selected memory cell MC_s. Consequently, cell current flows from the selected bit line BL_s towards the selected word line WL.

[0094] Since the selected bit line BL_s is electrically floating, the selected bit line potential VBL decreases as cell current flows. At this time, the decrease in the selected bit line potential VBL occurs at different rates depending on the state of the MTJ element MTJ of the selected memory cell MC_s. When the MTJ element MTJ of the selected memory cell MC_s is in a high-resistance state, the selected bit line potential VBL decreases more slowly than when the MTJ element MTJ of the selected memory cell MC_s is in a low-resistance state.

[0095] At time t6, the selected bit line potential VBL becomes the height based on the resistance state of the MTJ element MTJ of the selected memory cell MC_s. That is, as the selected bit line potential VBL decreases, the difference between the selected bit line potential VBL and the selected bit line potential VBL decreases. As a result, when the terminal voltage of the selected memory cell MC_s reaches a certain height, the switching element SE of the selected memory cell MC_s turns off. Consequently, the decrease of the selected bit line potential VBL stops, and the selected bit line potential VBL comes to have a certain height.

[0096] As a result of the operation from time t4 to time t6, the selected bit line potential VBL, and consequently the selected global bit line GBL_s, will have a potential based on the state of the selected memory cell MC_s. Hereafter, the operation from time t4 to time t6 may be referred to as the signal output operation.

[0097] At time t7, signals S4 and S1_s are set to high level. As a result, switches SW1 and SW4 are turned on, and a constant current is applied to wiring FBL. At time t7, the selected global bit line GBL_s has a potential corresponding to the state of the selected memory cell MC_s, and therefore a voltage based on the state of the selected memory cell MC_s is applied to the gate of transistor Tr1. Consequently, the potential of wiring FBL becomes a potential based on the state of the selected memory cell MC_s. In this way, a cell current of a magnitude based on the state of the selected memory cell MC_s is converted into a potential (voltage).

[0098] Next, the sense amplifier circuit SAC outputs data that is determined to have been stored in the selected memory cell MC_s, based on the potential of the wiring FBL.

[0099] At time t8, signals S4 and S1_s are set to a low level. The operation between time t7 and time t8 is sometimes referred to as the sense operation.

[0100] The signal S1_s may be high only during the signal output operation and the sense operation, that is, from time t4 onwards and low until time t4.

[0101] 1.3. Advantages (Effects) According to the first embodiment, a storage device can be provided that has a high operating margin and stores data with high accuracy, as described below.

[0102] As an example for reference, consider a configuration where the input of the conversion circuit CC, i.e., the gate of transistor Tr1, is connected to the wiring FBL, and the output of the conversion circuit CC, i.e., the drain of transistor Tr1, is connected to the sense amplifier circuit SAC. In this case, the switch GBSW is kept ON during signal output operation and sense operation. As is clear from the above, referring to Figure 3, the wiring FBL has many global bit lines GBL and many elements are connected via global bit lines GBL, so the parasitic capacitance of the wiring FBL is large. Due to the large parasitic capacitance, the cell current that flows when the switching element SE of the selected memory cell MC_s is turned ON is large. This can cause read disturb. Read disturb can cause unintended data erroneous writing to the selected memory cell MC_s, and furthermore, can destroy the selected memory cell MC_s.

[0103] To suppress read disturbance, a signal output operation may be performed while the selected bit line BL_s is disconnected from the selected global bit line GBL_s or wiring FBL. After the signal output operation causes a potential Vout based on the state of the selected memory cell MC_s to appear on the selected bit line BL_s, the selected bit line BL_s is connected to the selected global bit line GBL_s and wiring FBL, and the charge stored on the selected bit line BL_s is transferred to the wiring FBL by charge sharing. In this state, a sense operation is performed. In this case, because the capacitance of the selected bit line BL_s is small, the charge stored on the selected bit line BL_s with potential Vout is small. Therefore, the cell current is suppressed, and read disturbance is suppressed. On the other hand, because the small charge stored on the selected bit line BL_s is charge-shared, the potential of the wiring FBL after charge sharing is smaller than the potential Vout. Therefore, the current input to the conversion circuit CC is small, and thus the margin for the sense operation is small.

[0104] According to the first embodiment, the input of the conversion circuit CC is connected to the global bit line GBL, and the output of the conversion circuit CC is connected to the wiring FBL. Signal output operation and sense operation are performed while the selected global bit line GBL_s is disconnected from the wiring FBL. Because the selected global bit line GBL_s is disconnected from the wiring FBL, during the signal output operation, the selected bit line BL_s and the selected global bit line GBL_s have a potential Vout based on the state of the selected memory cell MC_s, while the charge accumulated on the selected bit line BL_s and the selected global bit line GBL_s is small. Therefore, the cell current when the switching element SE of the selected memory cell MC_s is turned on is small. On the other hand, because the selected bit line BL_s and the selected global bit line GBL_s have a potential Vout based on the state of the selected memory cell MC_s, the output of the conversion circuit CC is large. Thus, high-precision data storage and a high operating margin can be achieved.

[0105] 1.4. Variations The sense amplifier circuit SAC may have the components and connections of the components shown in Figure 13. Figure 13 shows the components and connections of the components of a sense amplifier circuit for a modified memory device of the first embodiment.

[0106] As shown in Figure 13, the sense amplifier circuit SAC includes switches SW11 and SW12, capacitors CP1 and CP2, and operational amplifier OP.

[0107] Switch SW11 is connected between wiring FBL and node SAMP. In one example, signal S11 is supplied from readout control circuit RCC.

[0108] Capacitor CP1 is connected between node SAMP and the node receiving the ground voltage VSS.

[0109] Switch SW12 is connected between wiring FBL and node EVAL. In one example, signal S12 is supplied from readout control circuit RCC.

[0110] Capacitor CP2 is connected between node EVAL and the node receiving the ground voltage VSS.

[0111] The operational amplifier OP is connected to node SAMP at the inverting input and to node EVAL at the non-inverting input.

[0112] The data reading operation is as follows: First, with switch SW11 turned ON, the operation described above is performed as shown in Figure 12. As a result, the potential based on the state of the selected memory cell MC_s appears at node SAMP. Subsequently, switch SW11 is turned OFF, and as a result, the potential based on the state of the selected memory cell MC_s is stored at node SAMP. Of the operation described above as shown in Figure 12, the data judgment by the sense amplifier circuit SAC after time t7 is not performed.

[0113] Predetermined, fixed reference data is written to the selected memory cell MC_s. The reference data may be "0" or "1". The following description is based on the example of "0" data.

[0114] With switch SW12 ON, the operations described above are performed as shown in Figure 12. As a result, a potential based on the state of the selected memory cell MC_s appears at node EVAL. The potential is based on reference data in the selected memory cell MC_s. Subsequently, switch SW12 is turned OFF, and as a result, the potential based on the state of the selected memory cell MC_s is stored at node EVAL. Of the operations described above as shown in Figure 12, the data judgment by the sense amplifier circuit SAC after time t7 is not performed.

[0115] When the operational amplifier OP is enabled, data OUT is output, which has a value based on the potentials of node SAMP and node EVAL. Data OUT has a value based on the data that the selected memory cell MC_s is determined to be storing at the start of data reading. In the case where the selected memory cell MC_s is storing "0" data at the start of data reading, the data stored in the selected memory cell MC_s at the start of data reading is the same as the reference data that was written. Data OUT is output with a value that reflects this.

[0116] On the other hand, in the case where the selected memory cell MC_s stores the data "1" at the start of data reading, the data stored in the selected memory cell MC_s at the start of data reading is different from the reference data that was written. Data OUT with a value that reflects this difference is output.

[0117] After the data OUT signal is output, the data that the selected memory cell MC_s was determined to have stored at the start of data reading is written to the selected memory cell MC_s.

[0118] In the modified version, the potential based on the state of the selected memory cell MC_s (the potential of node SAMP) is compared with the potential based on the known data written to this selected memory cell MC_s (the potential of node EVAL), thereby determining the data of the selected memory cell MC_s. Even if the characteristics of the memory cell MC inevitably vary, the effect of these variations is suppressed more effectively than in the case where the potential based on the state of the selected memory cell MC_s is compared with a common potential.

[0119] Furthermore, identical components with the same function but located in different positions (for example, switches GBSW connected to different global bit lines GBL) can inevitably have different characteristics. Even when reading data from multiple memory cells that store the same data, variations in the characteristics of the components involved in reading data from the memory cell MC can result in different data readouts. In a modified example, the data in a selected memory cell MC_s is determined by comparing the potential read from the selected memory cell MC_s with the potential based on known reference data written to the selected memory cell MC_s. Therefore, the components involved in reading data from the selected memory cell MC_s and the components involved in reading the written reference data are the same. Thus, variations in the results of reading the same data from different memory cells MC due to variations in the characteristics of multiple components are suppressed.

[0120] 2. Second Embodiment The second embodiment differs from the first embodiment in terms of the data reading operation.

[0121] Figure 14 shows the potentials of several signals and wirings over time during data readout of the storage device in the second embodiment. Figure 14, like Figure 12 of the first embodiment, shows the state in which one memory cell MC for data readout is selected. The operation during the period shown in Figure 14 begins when data readout starts with the memory cell MC for data readout selected.

[0122] As shown in Figure 14, at time t4, the signal SB_s is set to a low level. As a result, at time t4, the selected bit line BL_s is disconnected from the selected global bit line GBL_s. Therefore, the signal output operation is performed with the selected bit line BL_s and the selected global bit line GBL_s disconnected.

[0123] At time t7, the signal SB_s is set to a high level. As a result, the selected bit line BL_s is connected to the selected global bit line GBL_s. Therefore, the sense operation is performed with the selected bit line BL_s and the selected global bit line GBL_s connected.

[0124] According to the second embodiment, during signal output operation, the selection bit line BL_s is disconnected from the selection global bit line GBL_s. Therefore, the parasitic capacitance of the wiring connected to the selection memory cell MC_s (i.e., the selection bit line BL_s) during signal output operation is smaller than in the first embodiment. Consequently, the cell current is even smaller.

[0125] 3. Third Embodiment The third embodiment is implemented in addition to the first embodiment.

[0126] Figure 15 shows the potentials of several signals and wirings over time during data readout of the storage device in the third embodiment. Figure 15, like Figure 12 of the first embodiment, shows the state in which one selected memory cell MC_s for data readout is selected. The operation during the period shown in Figure 15 begins when data readout starts with the selected memory cell MC_s for data readout selected.

[0127] As shown in Figure 15, at time t7, the signal SB_s is set to a low level. This disconnects the selected bit line BL_s from the selected global bit line GBL_s. The disconnection of the selected bit line BL_s from the selected global bit line GBL_s continues until the end of the period shown in Figure 15.

[0128] According to the third embodiment, data can be read with high accuracy, as described below. Even when the switching element SE is off, a small leakage current may flow through the switching element SE. Therefore, during data reading, the selected bit line potential VBL may decrease after the switching element SE of the selected memory cell MC_s is turned off (time t5 in Figure 15). This can lead to a decrease in data reading accuracy and / or a decrease in the data reading margin. According to the third embodiment, after the signal output operation, the selected bit line BL_s is disconnected from the selected global bit line GBL_s. Therefore, after the signal output operation, the decrease in charge of the wiring FBL used for data determination due to leakage through the switching element SE is suppressed. This leads to a suppression of a decrease in data reading accuracy and / or a decrease in the read margin. Even if the amount of charge accumulated in the wiring connected to the selected memory cell MC_s by the signal output operation is small, a decrease in data reading accuracy and / or a decrease in the read margin is suppressed.

[0129] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0130] 1...Storage device, 11…Core circuit, 12…Input / Output Circuits, 13…Control circuits, 14...Decode circuit, 15...page buffer, 16...Voltage generation circuit, MC…Memory cell FWL...wiring, FBL...wiring, CCS...Conversion circuit set, 18... Programming circuit, 19...Read circuit

Claims

1. A first memory cell including a first magnetoresistive element and a first switching element connected to the first magnetoresistive element, A first wiring connected to the first end of the first memory cell, A second wiring connected to the second end of the first memory cell, A first switch having a third end connected to the second wiring and a fourth end, The third wiring connected to the aforementioned fourth terminal, A second switch having a fifth end connected to the third wiring and a sixth end, The fourth wiring connected to the sixth terminal, A first transistor having a gate connected to the third wiring and a seventh terminal connected to the fourth wiring, A third switch is connected between the seventh terminal and the first node that receives the first voltage, The sense amplifier circuit connected to the fourth wiring, A storage device equipped with the following features.

2. A first region including a plurality of first source / drain regions having different shapes and dimensions, and a plurality of first gate electrodes having different shapes and dimensions, A second region in which multiple sets of second source / drain regions aligned in the first direction are repeatedly provided in the second direction, and a second gate electrode extending in the second direction is repeatedly provided in the first direction, The sense amplifier circuit includes one of the plurality of first source / drain regions and at least a portion of one of the plurality of first gate electrodes. The first transistor includes one of the plurality of second source / drain regions and at least a portion of the second gate electrode. The storage device according to claim 1.

3. The period for reading data from the first memory cell includes the first period, During the first period, the first switch and the third switch are kept on, and the second switch is kept off. The storage device according to claim 1.

4. A second memory cell comprising a second magnetoresistive element and a second switching element connected to the second magnetoresistive element, A fifth wiring connected to the eighth end of the second memory cell, The sixth wiring connected to the ninth end of the second memory cell, A fourth switch having a tenth end connected to the sixth wiring and an eleventh end, The seventh wiring connected to the eleventh terminal, A fifth switch having a twelfth end connected to the seventh wiring and a thirteenth end connected to the fourth wiring, A second transistor having a gate connected to the seventh wiring and a fourteenth terminal connected to the fourth wiring, A sixth switch is connected between the fourteenth terminal and the second node that receives the first voltage, Equipped with, During the read operation, the fourth switch, the fifth switch, and the sixth switch remain in the off position. The storage device according to claim 3.

5. In a second period prior to the first period, the fourth wiring is electrically floated after a second voltage is applied to it, and while the fourth wiring is electrically floated, a third voltage lower than the second voltage is applied to the first wiring. During the first period, a fourth voltage lower than the third voltage is applied to the first wiring. The storage device according to claim 4.

6. The aforementioned reading period further includes a third period following the first period, During the third period, the third switch is kept ON, while the first and second switches are kept OFF. The storage device according to claim 3.

7. In a second period prior to the first period, the fourth wiring is electrically floated after a second voltage is applied to it, and while the fourth wiring is electrically floated, a third voltage lower than the second voltage is applied to the first wiring. During the first period, a fourth voltage lower than the third voltage is applied to the first wiring. The storage device according to claim 6.

8. The period for reading data from the first memory cell includes a first period and a third period following the first period. During the first period, the third switch is kept ON, and the first and second switches are kept OFF. During the third period, the first switch is kept on and the second switch is kept off. The storage device according to claim 1.

9. In a second period prior to the first period, the fourth wiring is electrically floated after a second voltage is applied to it, and while the fourth wiring is electrically floated, a third voltage lower than the second voltage is applied to the first wiring. During the first period, a fourth voltage lower than the third voltage is applied to the first wiring. The storage device according to claim 8.

10. The aforementioned sense amplifier circuit is A seventh switch is connected between the fourth wiring and the eighth wiring, A first capacitor having one end connected to the eighth wiring, An eighth switch connected between the fourth wiring and the ninth wiring, A second capacitor having one end connected to the ninth wiring, An operational amplifier having a first input connected to the eighth wiring and a second input connected to the ninth wiring, including, The storage device according to any one of claims 1 to 9.

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