Memory device

Abstract

To provide a storage device with suppressed malfunctions. [Solution] The second conductor is located in a first direction from the first conductor. The third conductor extends in a first direction, intersects with the first and second conductors, and has a first end and a second end, the first end being located in a first direction from the second end. The first memory cell is connected to the first and third conductors. The second memory cell is connected to the second and third conductors. The first switch is connected to the first end of the third conductor. The second switch is connected to the second end of the third conductor. When reading data from the first memory cell, the first switch is kept on and the second switch is kept off. When reading data from the second memory cell, the second switch is kept on and the first switch is kept off.

Description

Technical Field

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[0001] Embodiments generally relate to memory devices.

Background Art

[0002] Memory devices that store data using elements having a dynamically variable resistance are known. The memory device is required to write data in a short time.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device in which malfunction is suppressed.

Means for Solving the Problems

[0005] A memory device according to one embodiment comprises a first conductor, a second conductor, a third conductor, a first memory cell, a second memory cell, a first switch, and a second switch. The second conductor is located in a first direction from the first conductor. The third conductor extends in the first direction, intersects with the first and second conductors, and has a first end and a second end, the first end being located in the first direction from the second end. The first memory cell is connected to the first and third conductors. The second memory cell is connected to the second and third conductors. The first switch is connected to the first end of the third conductor. The second switch is connected to the second end of the third conductor. When data is read from the first memory cell, the first switch is kept on and the second switch is kept off. When reading data from the second memory cell, the second switch remains ON, while the first switch remains OFF. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the functional block of the storage device according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram of the memory cell array of the first embodiment of the storage device. [Figure 3] Figure 3 is a perspective view of a portion of the memory cell array of the first embodiment of the storage device. [Figure 4] Figure 4 shows a cross-sectional view of an example of the memory cell structure of the first embodiment of the storage device. [Figure 5] Figure 5 shows some of the functional blocks and components of the storage device according to the first embodiment. [Figure 6] Figure 6 shows a partial layout and circuit configuration of the storage device according to the first embodiment. [Figure 7] Figure 7 shows the components of the row selection circuit of the memory device according to the first embodiment. [Figure 8] Figure 8 shows the components of the column selection circuit of the storage device according to the first embodiment. [Figure 9]Figure 9 shows an example of the classification of memory cells in the first embodiment of the storage device. [Figure 10] Figure 10 is a circuit diagram of the read circuit of the storage device according to the first embodiment. [Figure 11] Figure 11 shows an example of one state during the operation of the storage device of the first embodiment. [Figure 12] Figure 12 shows an example of one state during the operation of the storage device in the first embodiment. [Figure 13] Figure 13 shows an example of the classification of memory cells in a second embodiment of a storage device. [Figure 14] Figure 14 shows an example of one state during the operation of the storage device in the second embodiment. [Figure 15] Figure 15 shows an example of one state during the operation of the storage device in the second embodiment. [Figure 16] Figure 16 shows an example of one state during the operation of the storage device in the second embodiment. [Figure 17] Figure 17 shows some functional blocks and components of the storage device according to the third embodiment. [Figure 18] Figure 18 shows the components of the column selection circuit of the memory device according to the third embodiment. [Figure 19] Figure 19 shows an example of one state during the operation of the storage device in the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may have additional numbers or letters appended to the end of their reference numerals to distinguish them from one another. Embodiments following a previously described embodiment primarily describe the differences from the previously described embodiment. All descriptions of an embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded.

[0008] In this specification and the claims, when a first element is "connected" or "connected to" a second element, it includes that the first element is directly or constantly or selectively connected to the second element through an element that becomes conductive.

[0009] Hereinafter, an XYZ orthogonal coordinate system is used to describe embodiments. In some cases, the positive direction of the vertical axis of the figure is referred to as the upper side, and the negative direction is referred to as the lower side. In some cases, the positive direction of the horizontal axis of the figure is referred to as the right side, and the negative direction is referred to as the left side. That is, in a plan view showing the XY plane (XY plane view (hereinafter the same)), the upper side points to the +Y direction, the lower side points to the -Y direction, the right side points to the +X direction, and the left side points to the -X direction.

[0010] 1. First Embodiment 1.1. Configuration (Structure) FIG. 1 shows a functional block of a magnetic memory device according to the first embodiment. The memory device 1 is a device for storing data. The memory device 1 stores data using a stack of magnetic materials showing variable resistance. As shown in FIG. 1, the memory device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0011] The memory cell array 11 is a set of a plurality of arranged memory cells MC. The memory cell MC can store data non-volatilely. In the memory cell array 11, a plurality of word lines WL and a plurality of bit lines BL are located. Each memory cell MC is connected to one word line WL and one bit line BL. The word line WL is associated with a row (row). The bit line BL is associated with a column (column). One memory cell MC is specified by the selection of one row and the selection of one column.

[0012] The input / output circuit 12 is a circuit that performs input / output of data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, address information ADD, and data DAT from outside the storage device 1, for example, from a memory controller. The input / output circuit 12 outputs the data DAT. The data DAT is write data in the case of data writing in the storage device 1. The data DAT is read data in the case of data reading from the storage device 1.

[0013] The voltage generation circuit 18 is a circuit that generates voltages of various magnitudes from a voltage received from outside the storage device 1. The voltage generation circuit 18 outputs a voltage of a certain magnitude used for data reading. The voltage generation circuit 18 outputs a voltage of a certain magnitude used for data writing.

[0014] The writing circuit 16 is a circuit that controls writing of data to the memory cell MC. The writing circuit 16 receives the write data DAT from the input / output circuit 12 and receives a voltage for data writing from the voltage generation circuit 18. The writing circuit 16 outputs a voltage and a current used for data writing based on the control of the control circuit 13 and the write data DAT.

[0015] The reading circuit 17 is a circuit that controls reading of data from the memory cell MC. The reading circuit 17 receives a voltage for data reading from the voltage generation circuit 18. The reading circuit 17 determines the data held in the memory cell MC using the voltage used for data reading based on the control of the control circuit 13. The determined data is supplied to the input / output circuit 12 as the read data DAT. The reading circuit 17 includes a sense amplifier.

[0016] The row selection circuit 14 is a circuit that selects a row of memory cell MC. The row selection circuit 14 receives address information ADD from the input / output circuit 12. The row selection circuit 14 receives a voltage for data writing from the write circuit 16. The row selection circuit 14 receives a voltage for data reading from the read circuit 17. During data writing, the row selection circuit 14 uses the voltage for data writing to select one or more word lines WL associated with the row identified by the received address information ADD. During data reading, the row selection circuit 14 uses the voltage for data reading to select one or more word lines WL associated with the row identified by the received address information ADD.

[0017] The column selection circuit 15 is a circuit that selects a column of memory cells MC. The column selection circuit 15 receives address information ADD from the input / output circuit 12. The column selection circuit 15 receives a voltage for data writing from the write circuit 16. The column selection circuit 15 receives a voltage for data reading from the read circuit 17. During data writing, the column selection circuit 15 uses the voltage for data writing to select one or more bit lines BL associated with the column identified by the received address information ADD. During data reading, the column selection circuit 15 uses the voltage for data reading to select one or more bit lines BL associated with the column identified by the received address information ADD.

[0018] The control circuit 13 is a circuit that controls the operation of the memory device 1. The control circuit 13 receives a control signal CNT and a command CMD from the input / output circuit 12. Based on the control indicated by the control signal CNT and the command CMD, the control circuit 13 controls the write circuit 16 and the read circuit 17. Specifically, the control circuit 13 controls the write circuit 16 to supply the voltage received by the voltage generation circuit 18 to the row selection circuit 14 and the column selection circuit 15 while writing data to the memory cell MC. The control circuit 13 controls the read circuit 17 to supply the voltage received by the voltage generation circuit 18 to the row selection circuit 14 and the column selection circuit 15 while reading data from the memory cell MC.

[0019] Figure 2 is a circuit diagram of the memory cell array of the first embodiment of the memory device. As shown in Figure 2, the memory cell array 11 contains M+1 (where M is a positive integer) word lines WL (WL_0, WL_1, ..., WL_M) and N+1 (where N is a positive integer) bit lines BL (BL_0, BL_1, ..., BL_N).

[0020] Each memory cell MC is connected to one word line WL and one bit line BL. Each memory cell MC contains one MTJ element MTJ and one switching element SE. In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SE of each memory cell MC is connected to one word line WL. The MTJ element MTJ of each memory cell MC is connected to one bit line BL.

[0021] MTJ elements are elements that exhibit the tunnel magnetoresistance effect, such as magnetic tunnel junctions (MTJs). MTJ elements are also called magnetoresistance effect elements. MTJ elements are variable resistor elements that can switch between a low-resistance state and a high-resistance state. MTJ elements can store 1-bit data by utilizing the difference between the two resistance states. For example, an MTJ element can store "0" data in the low-resistance state and "1" data in the high-resistance state.

[0022] A switching element SE is an element that electrically connects or disconnects its own terminals. A switching element SE has two terminals. When the voltage applied between the two terminals of a switching element SE is below a certain first threshold, it is in a high-resistance state, for example, electrically non-conductive (off state). When the voltage applied between the two terminals increases to or above the first threshold, the switching element SE enters a low-resistance state, for example, electrically conductive (on state). When the voltage applied between the two terminals of the low-resistance switching element SE decreases to or below a second threshold, the switching element SE enters a high-resistance state. The switching element SE has the same function of switching between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction, but also in a second direction opposite to the first. That is, the switching element SE is a bidirectional switching element. The on or off state of the switching element SE can control whether or not current is supplied to the MTJ element MTJ connected to it, i.e., the selection or deselection of the MTJ element MTJ.

[0023] Figure 3 is a perspective view of a portion of the memory cell array of the first embodiment of the storage device. As shown in Figure 3, a plurality of conductors 21 and a plurality of conductors 22 are provided.

[0024] The conductor 21 has a linear shape and extends along the x-axis. The conductors 21 are aligned along the y-axis. The y-axis is perpendicular to the x-axis. Each conductor 21 functions as one word line WL.

[0025] Conductor 22 is located above conductor 21 on the z-axis. The z-axis is perpendicular to the x-axis and y-axis. Conductor 22 has a linear shape, extends along the y-axis, and is aligned along the x-axis. Each conductor 22 functions as one bit line BL.

[0026] A memory cell MC is provided at each intersection of the conductor 21 and the conductor 22. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as an MTJ element MTJ each include one or more layers. In one example, the structure that functions as an MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of one conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of one conductor 22.

[0027] Figure 4 shows a cross-section of an example of the structure of a memory cell of a first embodiment of a memory device. As shown in Figure 4, the switching element SE includes a variable resistance material 32. The variable resistance material 32 is a material that exhibits dynamically variable resistance and has, for example, a layered shape. The variable resistance material 32 is a two-terminal switching element, where the first terminal of the two terminals is one of the upper and lower surfaces of the variable resistance material 32, and the second terminal of the two terminals is the other of the upper and lower surfaces of the variable resistance material 32. When the voltage applied between the two terminals is less than a certain first threshold (threshold voltage Vth), the variable resistance material is in a "high resistance" state, for example, electrically non-conductive. When the voltage applied between the two terminals increases and becomes above the first threshold, the variable resistance material becomes in a "low resistance" state, for example, electrically conductive. When the voltage applied between the two terminals of the low-resistance variable resistance material 32 decreases and becomes below a second threshold, the variable resistance material becomes high resistance. The variable resistance material 32 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide, and a material substantially composed of SiO2 or SiO2. The dopant includes, for example, arsenic (As) and germanium (Ge). In this embodiment, the variable resistor material 32 is described as having the above composition, but is not limited to this composition. The phrase "substantially composed of (or composed of)" and similar phrases means that the "substantially composed" components may contain unintended impurities.

[0028] The switching element SE may further include a lower electrode 31 and an upper electrode 33. Figure 4 shows such an example. The variable resistor material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistor material 32.

[0029] The MTJ element includes a ferromagnetic layer 35, an insulating layer 36, and a ferromagnetic layer 37. For example, as shown in Figure 4, the insulating layer 36 is located on the upper surface of the ferromagnetic layer 35, and the ferromagnetic layer 37 is located on the upper surface of the insulating layer 36.

[0030] The ferromagnetic layer 35 is a layer of material exhibiting ferromagnetism. The ferromagnetic layer 35 has an easy magnetization axis aligned with the direction penetrating the interface between the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37. For example, it may have an easy magnetization axis at an angle of 45° to 90° with respect to the interface, or an easy magnetization axis aligned with a direction perpendicular to the interface. The direction of magnetization of the ferromagnetic layer 35 is intended to remain unchanged even during data reading and writing in the memory cell MC. The ferromagnetic layer 35 can function as a so-called reference layer. The ferromagnetic layer 35 may include multiple layers. Hereinafter, the ferromagnetic layer 35 may be referred to as the reference layer 35.

[0031] The insulating layer 36 is an insulating layer. The insulating layer 36 contains, for example, magnesium oxide (MgO) or is substantially composed of MgO and functions as a so-called tunnel barrier.

[0032] The ferromagnetic layer 37 is a layer of material exhibiting ferromagnetism. The ferromagnetic layer 37 contains, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer 37 has an easy magnetization axis along the direction that penetrates the interface of the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37, for example, an easy magnetization axis at an angle of 45° to 90° with respect to the interface, or for example, an easy magnetization axis along the direction perpendicular to the interface. The direction of magnetization of the ferromagnetic layer 37 is variable by writing data to the memory cell MC, and the ferromagnetic layer 37 can function as a so-called memory layer. Hereinafter, the ferromagnetic layer 37 may be referred to as the memory layer 37.

[0033] When the magnetization direction of the memory layer 37 is parallel to the magnetization direction of the reference layer 35, the MTJ element MTJ has a certain low resistance. When the magnetization direction of the memory layer 37 is antiparallel to the magnetization direction of the reference layer 35, the MTJ element MTJ has a higher resistance than when the magnetization directions of the memory layer 37 and the reference layer 35 are parallel. Hereinafter, the state in which the magnetization direction of the ferromagnetic layer 37 of a certain MTJ element MTJ is parallel to the magnetization direction of the reference layer 35 may be referred to as the MTJ element MTJ being in a "parallel state" or in a "P state". The state in which the magnetization direction of the ferromagnetic layer 37 of a certain MTJ element MTJ is antiparallel to the magnetization direction of the reference layer 35 may be referred to as the MTJ element MTJ being in an "antiparallel state" or in an "AP state".

[0034] When a current of a certain magnitude, Icp or greater, flows from the memory layer 37 to the reference layer 35, the magnetization direction of the memory layer 37 becomes parallel to the magnetization direction of the reference layer 35.

[0035] When a current of a certain magnitude, Icap or greater, flows from the reference layer 35 to the memory layer 37, the direction of magnetization of the memory layer 37 becomes antiparallel to the direction of magnetization of the reference layer 35.

[0036] The MTJ element may include further layers.

[0037] Figure 5 shows some functional blocks and components of the storage device of the first embodiment. As shown in Figure 5, the read circuit 17 is connected to the global word line GWL and the global bit line GBL.

[0038] The global word line GWL is connected to the row selection circuit 14. The row selection circuit 14 connects the global word line GWL to one word line WL identified by the address information ADD.

[0039] The global bit line GBL is connected to the column selection circuit 15. The column selection circuit 15 connects the global bit line GBL to one bit line BL identified by the address information ADD.

[0040] Figure 6 shows a partial layout and circuit configuration of the memory device of the first embodiment. Figure 6 shows the layout of conductors 21 and 22, as well as switches SX, SYL, and SYU described later, and the circuit configuration of other components. Figure 6 shows an example of eight conductors 21 and eight conductors 22, i.e., an example where M=N=7. The figures from Figure 6 onward and the following description are based on this example.

[0041] As shown in Figure 6, for all cases where α is greater than or equal to 0 and less than or equal to M, the conductor 21_α, which functions as the word line WL_α, is located in the Y direction as the α value increases. For all cases where β is greater than or equal to 0 and less than or equal to N, the conductor 22_β, which functions as the bit line BL_β, is located in the X direction as the β value increases.

[0042] The row selection circuit 14 includes M+1 switches SX, i.e., 8 switches SX_0 to SX_7 based on the current example. Switches SX_0 to SX_7 are located on the -X side of the conductor 21. For all cases where α is greater than or equal to 0 and less than or equal to 7, one end of switch SX_α is connected to the -X side end of conductor 21_α by wiring (conductor). The other end of each switch SX_0 to SX_7 is connected to the global word line GWL via wiring. Examples of each switch SX include n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), p-type MOSFETs, and p-type and n-type MOSFETs connected in parallel.

[0043] The column selection circuit 15 includes N+1 switches SYL, i.e., 8 switches SYL_0 to SYL_7 based on the current example. Switches SYL_0 to SYL_7 are located in the -Y direction from the conductor 21. For all cases where β is greater than or equal to 0 and less than or equal to 7, one end of switch SYL_β is connected to the -Y side end of conductor 22_β by wiring (conductor). The other end of each switch SYL_0 to SYL_7 is connected to the global bit line GBL via wiring. Examples of each switch SYL include an n-type MOSFET, a p-type MOSFET, and p-type and n-type MOSFETs connected in parallel.

[0044] The column selection circuit 15 includes N+1 switches SYU, i.e., 8 switches SYU_0 to SYU_7 based on the current example. Switches SYU_0 to SYU_7 are located in the Y direction relative to the conductor 21. For all cases where β is greater than or equal to 0 and less than or equal to 7, one end of switch SYU_β is connected to the Y-direction side end of conductor 22_β by wiring (conductor). The other end of each of switches SYU_0 to SYU_7 is connected to the global bit line GBL via wiring. Examples of each switch SYU include an n-type MOSFET, a p-type MOSFET, and p-type and n-type MOSFETs connected in parallel.

[0045] Figure 7 shows the components of the low-selection circuit of the memory device according to the first embodiment. As shown in Figure 7, switches SX_0 to SX_7 each receive signals CX_0 to CX_7 at their control terminals (or gate electrodes). Switches SX_0 to SX_7 remain on or off based on signals CX_0 to CX_7. Switches SX_0 to SX_7 remain on, respectively, if signals CX_0 to CX_7 have an assertion level logic (or asserted logic level). The assertion level logic for n-type MOSFETs is high level. The assertion level logic for p-type MOSFETs is low level.

[0046] Signals CX_0 to CX_7 are supplied from the decoder (decoder circuit) 141 in the row selection circuit 14. The decoder 141 receives the address information ADD and decodes the address information ADD. The decoder 141 outputs signals CX_0 to CX_7, which have logic levels based on the decoding result.

[0047] Figure 8 shows the components of the column selection circuit of the memory device according to the first embodiment. As shown in Figure 8, switches SYL_0 to SYL_7 receive signals CYL_0 to CYL_7 at their control terminals (or gate electrodes), respectively. Switches SYL_0 to SYL_7 remain on or off based on signals CYL_0 to CYL_7, respectively. If signals CYL_0 to CYL_7 have assertion level logic, switches SYL_0 to SYL_7 are on, respectively.

[0048] Switches SYU_0 to SYU_7 each receive signals CYU_0 to CYU_7 at their control terminals (or gate electrodes). Switches SYU_0 to SYU_7 remain either on or off based on signals CYU_0 to CYU_7. Switches SYU_0 to SYU_7 remain on while signals CYU_0 to CYU_7 have assertion level logic.

[0049] Signals CYL_0~CYL_7 and CYU_0~CYU_7 are supplied from the decoder (decoder circuit) 151 in the column selection circuit 15. The decoder 151 receives the address information ADD and decodes the address information ADD. The decoder 151 outputs signals CYL_0~CYL_7 and CYU_0~CYU_7, which have logic levels based on the decoding result.

[0050] Figure 9 shows an example of the classification of memory cells in the first embodiment of the storage device. Memory cells MC are classified into two groups. For example, when conductors 21 are arranged in M / 2 in the positive direction and M / 2 in the negative direction, starting from the center of conductor 22 on the x-axis, for all cases where α is 0 or greater and less than (M+1) / 2, memory cells MC connected to conductor 21_α belong to group G1. In other words, for all cases where β is 0 or greater and less than or equal to N, if the distance of the current path from a certain memory cell MC to switch SYL_β via a current path including a part of conductor 22_β is shorter than the distance of the current path from this memory cell MC to switch SYU_β via a current path including a part of conductor 22_β, then this memory cell MC belongs to group G1. Based on the current example, memory cells MC connected to any of conductors 21_0, 21_1, 21_2, and 21_3 belong to group G1. In other words, the conductors 21_0, 21_1, 21_2, and 21_3 are closer to the -Y direction end (lower end) of the conductor 22 than to the Y direction end (upper end).

[0051] For all cases where α is greater than or equal to (M+1) / 2 and less than or equal to M, the memory cell MC connected to the conductor 21_α belongs to group G2. In other words, for all cases where β is greater than or equal to 0 and less than or equal to N, if the distance of the current path from a certain memory cell MC to the switch SYU_β via a current path including a part of the conductor 22_β is shorter than the distance of the current path from this memory cell MC to the switch SYL_β via a current path including a part of the conductor 22_β, then this memory cell MC belongs to group G2. Based on the current example, any memory cell MC connected to any of the conductors 21_4, 21_5, 21_6, and 21_7 belongs to group G2. That is, conductors 21_4, 21_5, 21_6, and 21_7 are closer to the upper end of the conductor 22 than to the lower end.

[0052] Figure 10 is a circuit diagram of the read circuit of the memory device according to the first embodiment. Figure 10 shows a representative state in which one memory cell MC is selected. That is, as described above with reference to Figure 1, one word line WL is selected by the row selection circuit 14 and one bit line BL is selected by the column selection circuit 15. One memory cell MC connected to the one selected word line WL and one selected bit line BL is selected, and data is read from the selected memory cell MC. The word line WL, bit line BL, and memory cell MC shown in Figure 10 are in a selected state.

[0053] As shown in Figure 10, the readout circuit 17 is connected to the global word line GWL and the global bit line GBL. The readout circuit 17 includes a sense amplifier circuit SAC, switches SW3, SW4, SW5, and SW6, and a readout control circuit RCC. Examples of switches SW3, SW4, SW5, and SW6 include n-type MOSFETs, p-type MOSFETs, and p-type and n-type MOSFETs connected in parallel.

[0054] Switch SW3 is connected between a node that receives a precharge voltage VPRCH of a constant magnitude and the global word line GWL. The node that receives the precharge voltage VPRCH also functions as a node that supplies the precharge voltage VPRCH. In one example, the precharge voltage VPRCH is supplied from a voltage generation circuit 18. The precharge voltage VPRCH is higher than the ground voltage VSS. Switch SW3 is on while it receives the assertion level logic signal S3.

[0055] Switch SW4 is connected between the global word line GWL and a node that receives a non-selective voltage VUSEL of a constant magnitude. The node that receives the non-selective voltage VUSEL functions as a node that supplies the non-selective voltage VUSEL. In one example, the non-selective voltage VUSEL is supplied from a voltage generation circuit 18. The non-selective voltage VUSEL has a magnitude between the ground voltage VSS and the precharge voltage VPRCH, and the potential difference between the precharge voltage VPRCH and the non-selective voltage VUSEL, and the potential difference between the non-selective voltage VUSEL and the ground voltage VSS are smaller than the first threshold of the switching element SE. In one example, the non-selective voltage VUSEL has half the magnitude of the precharge voltage VPRCH. Switch SW4 is on while receiving the assertion level logic signal S4.

[0056] The sense amplifier circuit SAC outputs data that is determined to be stored in the selected memory cell MC to be read, based on the supplied voltage. In one example, the sense amplifier circuit SAC includes an operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to the global word line GWL. The inverting input of the operational amplifier OP is connected to a reference voltage VREF. In one example, the reference voltage VREF has a potential between the magnitude of a high hold voltage VhdH and the magnitude of a low hold voltage VhdL. The high hold voltage VhdH is the terminal voltage of the memory cell MC containing a high-resistance MTJ element MTJ. The low hold voltage VhdL is the terminal voltage of the memory cell MC containing a low-resistance MTJ element MTJ.

[0057] Switch SW5 is connected between the global bit line GBL and the node receiving the non-selection voltage VUSEL. Switch SW5 is on while receiving the assertion level logic signal S5.

[0058] Switch SW6 is connected between the global bit line GBL and a node receiving the ground voltage VSS. Switch SW6 is on while receiving the assertion level logic signal S6.

[0059] The readout control circuit RCC outputs signals S4 to S6.

[0060] 1.2.Operation Figure 11 shows an example of a state during the operation of the memory device of the first embodiment. Figure 11 shows the state during which data is read from a memory cell MC belonging to group G1, and as an example, shows the state during which data is read from memory cell MC_3_0. Memory cell MC_p_q is a memory cell MC connected to a word line WL_p and a bit line BL_q. Hereinafter, the memory cell MC from which data is read may be referred to as a selected memory cell MC. The word line WL and bit line BL connected to the selected memory cell MC may be referred to as a selected word line WL and a selected bit line BL, respectively. Word lines WL other than the selected word line WL may be referred to as unselected word lines WL. Bit lines BL other than the selected bit line BL may be referred to as unselected bit lines BL.

[0061] Switch SX connected to the selected word line WL (conductor 21 functioning as the selected word line WL) is kept ON, while switches SX connected to the non-selected word line WL (conductor 21 functioning as the non-selected word line WL) are kept OFF. In the example in Figure 11, switch SX_3 is kept ON, while all other switches SX except switch SX_3 are kept OFF.

[0062] If the memory cell MC from which data is to be read belongs to group G1, switch SYU is kept ON and switch SYL is kept OFF among the switches SYL and SYU connected to the selection bit line BL (conductor 22 that functions as a selection bit line BL). Switches SYL and SYU connected to the non-selection bit line BL (conductor 22 that functions as a non-selection bit line BL) are kept OFF. In the example in Figure 11, switch SYU_0 is kept ON, and all switches SYU except switch SYU_0 and all switches SYL are kept OFF.

[0063] Figure 12 shows an example of a state during the operation of the memory device of the first embodiment. Figure 12 shows the state while data is being read from memory cell MC belonging to group G2, and as an example, it shows the state while data is being read from memory cell MC_7_7.

[0064] Switches SX connected to the selected word line WL are kept ON, while switches SX connected to the unselected word line WL are kept OFF. In the example in Figure 12, switch SX_7 is kept ON, while all other switches SX are kept OFF.

[0065] If the memory cell MC from which data is to be read belongs to group G2, switch SYL is kept ON and switch SYU is kept OFF among the switches SYL and SYU connected to the selection bit line BL. Switches SYL and SYU connected to the non-selection bit line BL are kept OFF. In the example in Figure 12, switch SYL_7 is kept ON, and all switches SYL except switch SYL_7 and all switches SYU are kept OFF.

[0066] A data read operation is performed while the selected memory cell MC is connected to the global word line GWL and the global bit line GBL according to the rules described above, with reference to Figures 11 and 12. The read operation can be performed in any form. An example of a read operation is described below. First, a voltage VUSEL is applied to the global word line GWL and the global bit line GBL. This is done by keeping switches SW3 and SW6 off and switches SW4 and SW5 on.

[0067] While a non-selective voltage VUSEL is applied to the global bit line GBL, a pre-charge voltage VPRCH is applied to the global word line GWL. This is done by keeping switch SW4 off and switch SW3 on. Then, by keeping switch SW3 off, the global word line GWL is kept electrically floating.

[0068] While the global word line GWL is electrically floating, a ground voltage VSS is applied to the global bit line GBL. This is done by keeping switch SW5 off and switch SW6 on. As a result, the difference between the potential of the selection word line WL and the selection bit line BL reaches the threshold voltage Vth of the switching element SE of the selection memory cell MC. As a result, the switching element SE of the selection memory cell MC turns on. This causes cell current to flow from the selection word line WL to the selection bit line BL through the selection memory cell MC, and the potential of the selection word line WL decreases. Due to the decrease in the potential of the selection word line WL, if the MTJ element MTJ of the selection memory cell MC is in a low resistance state, the terminal voltage of the selection memory cell MC becomes a low hold voltage VhdL, and if the MTJ element MTJ of the selection memory cell MC is in a high resistance state, the terminal voltage of the selection memory cell MC becomes a high hold voltage VhdH, causing the switching element SE of the selection memory cell MC to turn off. Therefore, the global word line GWL has a potential whose magnitude is based on the resistance state of the MTJ element MTJ of the selection memory cell MC. This potential is used by the read circuit 17 to determine the data stored in the selected memory cell MC.

[0069] 1.3. Advantages (Effects) According to the storage device of the first embodiment, data erroneous writing and destruction of memory cells MC can be suppressed, as described below.

[0070] It is conceivable that the set of switches SYL_0 to SYL_7 is not provided, and only the set of switches SYL_0 to SYL_7 is provided. In this case, the length of the current path including the memory cell MC differs greatly depending on the location of the memory cell MC. That is, the current path including a memory cell MC located far from both the row selection circuit 14 and the column selection circuit 15 (e.g., memory cell MC_7_7) is long, and therefore the resistance of the current path is high. On the other hand, the current path including a memory cell MC located close to both the row selection circuit 14 and the column selection circuit 15 (e.g., memory cell MC_0_0) is short, and therefore the resistance of the current path is low. The difference between the longest and shortest current paths is large. In this case, even though the current paths are different, the charge charged by the precharge voltage VPRCH is the same, and during data reading from the memory cell MC included in the short current path, the charge is discharged with a small parasitic resistance, so a large peak cell current flows. Depending on the magnitude of the peak cell current, the resistance state of the MTJ element MTJ of the memory cell MC included in the short current path may change, and data erroneous writing may occur. Depending on the magnitude of the cell current, the memory cell MC may also be destroyed.

[0071] According to the first embodiment, switches SYU and SYL are connected to one end and the other end of each conductor 22 (bit line BL), respectively. During data reading, the switch SYU or SYL connected to the selection bit line BL that is further from the selection memory cell MC is kept ON, and the other is kept OFF. That is, each conductor 21 is connected to the global bit line GBL via the further away switch SYU or SYL, even though it is possible to connect to the global bit line GBL via the closer switch SYU or SYL. Therefore, short current paths are not used, even if they can be formed. This leads to suppression of the difference between the length of the longest current path used (e.g., the case of selection memory cell MC_7_7) and the shortest current path used (e.g., the case of selection memory cell MC_3_0). Because the difference between the longest and shortest current paths is small, the difference between the resistance of the longest current path and the resistance of the shortest current path is small. Therefore, even with the same precharge voltage VPRCH, the difference in the magnitude of the cell current peak due to the difference in current paths is suppressed. Therefore, data erroneous writing to memory cells (MC) and damage to memory cells are suppressed.

[0072] 2. Second Embodiment The second embodiment differs from the first embodiment in terms of the classification of the memory cell MC.

[0073] 2.1. Structure Figure 13 shows an example of the classification of memory cells in the storage device of the second embodiment. The memory cells MC are classified into three groups. For all cases where β is greater than or equal to P and less than or equal to N, MCs connected to conductor 22_β belong to group GB1. In other words, memory cells MC located far from switch SX belong to group GB1. An example of P is the smallest integer greater than or equal to (N+1) / 2. Another example of P is the smallest integer greater than or equal to (N+1)×2 / 3. Based on the current example, P is 6, and the following description is based on this example. Based on the current example, memory cells MC connected to either conductor 22_6 or conductor 22_7 belong to group GB1.

[0074] For all cases where β is greater than or equal to 0 and less than P, and for all cases where α is greater than or equal to 0 and less than (M+1) / 2, a memory cell MC connected to conductors 22_β and 21_α belongs to group GB2. In other words, a memory cell MC that is located close to switch SX and, for all cases where β is greater than or equal to 0 and less than P, has a current path distance from a memory cell MC to switch SYL_β via a current path including a portion of conductor 22_β (bit line BL_β) that is shorter than the current path distance from this memory cell MC to switch SYU_β via a current path including a portion of conductor 22_β that belongs to group GB2. Based on the current example, a memory cell MC connected to any of conductors 22_0, 22_1, 22_2, 22_3, 22_4, and 22_5, and also connected to any of conductors 21_0, 21_1, 21_2, and 21_3, belongs to group GB2.

[0075] For all cases where β is greater than or equal to 0 and less than P, and α is greater than or equal to (M+1) / 2 and less than or equal to M, a memory cell MC connected to conductor 22_β and conductor 21_α belongs to group GB3. In other words, a memory cell MC that is located close to switch SX and, for all cases where β is greater than or equal to 0 and less than P, has a current path distance from a memory cell MC to switch SYU_β via a current path including a portion of conductor 22_β (bit line BL_β) that is shorter than the current path distance from this memory cell MC to switch SYL_β via a current path including a portion of conductor 22_β that belongs to group GB3. Based on the current example, a memory cell MC connected to any of conductors 22_0, 22_1, 22_2, 22_3, 22_4, and 22_5, and also connected to any of conductors 21_4, 21_5, 21_6, and 21_7, belongs to group GB3.

[0076] 2.2.Operation Figure 14 shows an example of a state during the operation of the storage device of the second embodiment. Figure 14 shows the state while data is being read from memory cell MC belonging to group GB1, and as an example, it shows the state while data is being read from memory cell MC_3_7.

[0077] Switches SX connected to the selected word line WL are kept ON, while switches SX connected to the unselected word line WL are kept OFF. In the example in Figure 14, switch SX_3 is kept ON, while all other switches SX are kept OFF.

[0078] If the memory cell MC from which data is to be read belongs to group GB1, both switches SYL and SYU connected to the selection bit line BL are kept ON. Switches SYL and SYU connected to the non-selection bit line BL are kept OFF. In the example in Figure 14, switches SYL_7 and SYU_7 are kept ON, while all switches SYL except SYL_7 and all switches SYU except SYU_7 are kept OFF.

[0079] Figure 15 shows an example of a state during the operation of the storage device of the second embodiment. Figure 15 shows the state while data is being read from memory cell MC belonging to group GB2, and as an example, it shows the state while data is being read from memory cell MC_3_0.

[0080] Switches SX connected to the selected word line WL are kept ON, while switches SX connected to the unselected word line WL are kept OFF. In the example in Figure 15, switch SX_3 is kept ON, while all other switches SX are kept OFF.

[0081] If the memory cell MC from which data is to be read belongs to group GB2, switch SYU is kept ON and switch SYL is kept OFF among the switches SYL and SYU connected to the selection bit line BL. Switches SYL and SYU connected to the non-selection bit line BL are kept OFF. In the example in Figure 15, switch SYU_0 is kept ON, and all switches SYU except switch SYU_0 and all switches SYL are kept OFF.

[0082] Figure 16 shows an example of a state during the operation of the storage device of the second embodiment. Figure 16 shows the state while data is being read from memory cell MC belonging to group GB3, and as an example, it shows the state while data is being read from memory cell MC_7_5.

[0083] Switches SX connected to the selected word line WL are kept ON, while switches SX connected to the unselected word line WL are kept OFF. In the example in Figure 16, switch SX_7 is kept ON, while all other switches SX are kept OFF.

[0084] If the memory cell MC from which data is to be read belongs to group GB3, switch SYL is kept ON and switch SYU is kept OFF among the switches SYL and SYU connected to the selection bit line BL. Switches SYL and SYU connected to the non-selection bit line BL are kept OFF. In the example in Figure 16, switch SYL_5 is kept ON, and all switches SYL except switch SYL_5 and all switches SYU are kept OFF.

[0085] The read operation when the memory cell MC is selected is the same as in the first embodiment.

[0086] 2.3. Advantages Memory cells MC located far from switch SX have high resistance due to conductor 21. According to the second embodiment, as in the first embodiment, switches SYU and SYL are connected to one end and the other end of each conductor 21, respectively. During data reading from the selected memory cell MC that is in contact with the portion of conductor 21 far from switch SX, both switches SYU and SYL, which are connected to conductor 22 connected to the selected memory cell MC, are kept ON. Therefore, the resistance between switch SX, which is connected to the selected memory cell MC via the word line WL, and switches SYU and SYL, which are connected to the selected memory cell MC via conductor 22, is lower than in the case where only one of switches SYU or SYL is used. Therefore, when the resistance due to conductor 21 is high due to distance from switch SX, it is possible to suppress the peak of the cell current without excessively increasing the resistance due to conductor 22. This suppresses variations in cell current due to variations in the resistance of the current path.

[0087] Furthermore, according to the second embodiment, as in the first embodiment, during data reading from a selected memory cell MC that is in contact with the portion of the conductor 21 not far from the switch SX, one of the switches SYU and SYL connected to the selected bit line BL that is farther from the selected memory cell MC is turned on, and the other is kept off. Therefore, the same advantages as in the first embodiment are obtained when reading data from a selected memory cell MC that is in contact with the portion of the conductor 21 not far from the switch SX. Thus, according to the second embodiment, the variation in cell current due to the position of the memory cell MC is smaller than the variation in the first embodiment.

[0088] 3. Third Embodiment The third embodiment relates to data writing. The third embodiment may be implemented in addition to the first or second embodiment.

[0089] Figure 17 shows some functional blocks and components of the storage device of the third embodiment. As shown in Figure 17, the write circuit 16 is connected to the global word line GWL and the global bit line GBL.

[0090] Figure 18 shows the components of the column selection circuit of the storage device according to the second embodiment. As shown in Figure 18, the decoder 151 further receives a command CMD. Based on the result of decoding the address information ADD and the command CMD, the decoder 151 outputs signals CYL_0 to CYL_7 and CYU_0 to CYU_7 having logical levels based on the decoding result.

[0091] Figure 19 shows an example of a state during the operation of the memory device of the third embodiment. As an example, Figure 19 shows the state while data is being written to the memory cell MC_3_4. As in the first and second embodiments, the switch SX connected to the selected word line WL is kept ON, and the switch SX connected to the unselected word line WL is kept OFF.

[0092] The column selection circuit 15 keeps both switches SYL and SYU connected to the selection bit line BL on while data is being written to the selected memory cell MC. That is, when the decoder 151 of the column selection circuit 15 receives a command CMD instructing data writing, it keeps both switches SYL and SYU connected to the selection bit line BL on. In the example shown in Figure 19, switches SYL_4 and SYU_4 are kept on during data writing. During data writing, the two switches SYL and SYU connected to each non-selected bit line BL are kept off. With switches SYU and SYL thus kept on or off, the write circuit 16 applies voltage to the global word line GWL and the global bit line GBL so that a cell current oriented according to the data being written to the selected memory cell MC flows through the selected memory cell MC.

[0093] According to the third embodiment, as in the first and second embodiments, switches SYU and SYL are connected to one end and the other end of each conductor 22, respectively. During data writing, both switches SYU and SYL, which are connected to the conductor 22 connected to the selection memory cell MC, are kept ON. Therefore, the resistance between switch SX, which is connected to the selection memory cell MC via the word line WL, and switches SYU and SYL, which are connected to the selection memory cell MC via the conductor 22, is lower than in the case where only one of switches SYU or SYL is used. As a result, the resistance of the current path is suppressed, and a large cell current can flow through such a current path. This suppresses the reduction of cell current due to the resistance of the current path.

[0094] 3. Variant The description so far is based on the example where the boundary between group G1 and group G2, or the boundary between group GB2 and group GB3, is located in the center of the conductor 22, that is, the number of memory cells MCs aligned along the y-axis in group G1 or group GB2 is equal to the number of memory cells MCs aligned along the y-axis in group G2 or group GB3. The number of memory cells MCs aligned along the y-axis in group G1 or group GB2 may be different from the number of memory cells MCs aligned along the y-axis in group G2 or group GB3.

[0095] The description so far is based on two examples where the group of memory cells (MCs) is arranged along the y-axis. However, there may be three or more groups of memory cells (MCs) arranged along the y-axis.

[0096] The first and second embodiments are based on an example in which switch SX is connected to only one end of conductor 21 and switches SYL and SYU are connected to both ends of conductor 22, respectively. Alternatively, switch SY (e.g., corresponding to switch SYL) may be connected to only one end of conductor 22 (e.g., the end on the -Y direction), and switches SXL and SXR may be connected to both ends of conductor 21, respectively. In this case, in the first embodiment, group G1 includes memory cell MCs closer to switch SXL, and group G2 includes memory cell MCs closer to switch SXR. In the second embodiment, group GB1 includes memory cell MCs further from switch SY, group GB2 includes memory cell MCs close to both switch SY and switch SXL, and group GB3 includes memory cell MCs close to both switch SY and switch SXR. Regarding operation, the descriptions of switches SYL and SYU in the first and second embodiments are replaced with descriptions of switches SXL and SXR, and the description of switch SX is replaced with a description of switch SY.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0098] 1...Storage device, 11…Memory cell array, 12…Input / Output Circuits, 13…Control circuits, 14... Row selection circuit, 15…Column selection circuit, 16…Writing circuit, 17...Read circuit, 18…Voltage generation circuit, MC…Memory cell WL... Word line, BL... bit line, 21... Conductor, 22... Conductor, 32... Variable resistor material, 31...Lower electrode, 33...upper electrode, 35...Ferromagnetic layer, 36...Insulating layer, 37...Ferromagnetic layer, GWL...Global Word Line, GBL...Global Bit Line, SX... Switch, SYL... Switch, SYU... Switch,

Claims

1. First conductor and, A second conductor located in a first direction from the first conductor, A third conductor extending in the first direction, intersecting the first and second conductors, having a first end and a second end, the first end being located in the first direction from the second end, A first memory cell connected to the first conductor and the third conductor, The second memory cell connected to the second conductor and the third conductor, A first switch connected to the first end of the third conductor, A second switch connected to the second end of the third conductor, Equipped with, When reading data from the first memory cell, the first switch is kept ON and the second switch is kept OFF. When reading data from the second memory cell, the second switch is kept ON and the first switch is kept OFF. storage device.

2. The first conductor and the second conductor extend in a second direction, The first conductor has a third end on the side in the second direction, The second conductor has a fourth end on the side of the second direction, The storage device further comprises a third switch connected to the third end of the first conductor and a fourth switch connected to the fourth end of the second conductor. When reading data from the first memory cell, the third switch is kept ON. When reading data from the second memory cell, the fourth switch remains ON. The storage device according to claim 1.

3. Further comprising the first wiring, The first switch is connected between the first end of the third conductor and the first wiring, The second switch is connected between the second end of the third conductor and the first wiring. The storage device according to claim 2.

4. Further equipped with a second wiring, The third switch is connected between the third end of the first conductor and the second wiring, The fourth switch is connected between the fourth end of the second conductor and the second wiring, One of the first and second wirings is connected to the node and sense amplifier circuit of the first voltage. The other end of the first wiring and the second wiring is connected to a node with a second voltage lower than the first voltage. The storage device according to claim 3.

5. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 4.

6. The memory cell array further comprises a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located in the first direction relative to the memory cell array, The second switch is located in the direction opposite to the first direction relative to the memory cell array. The storage device according to claim 5.

7. The memory cell array further comprises a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located in the first direction relative to the memory cell array, The second switch is located in the direction opposite to the first direction relative to the memory cell array. The storage device according to claim 4.

8. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 2.

9. The memory cell array further comprises a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located in the first direction relative to the memory cell array, The second switch is located in the direction opposite to the first direction relative to the memory cell array. The storage device according to claim 8.

10. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 1.

11. The memory cell array further comprises a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located in the first direction relative to the memory cell array, The second switch is located in the direction opposite to the first direction relative to the memory cell array. The storage device according to claim 10.

12. The memory cell array further comprises a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located in the first direction relative to the memory cell array, The second switch is located in the direction opposite to the first direction relative to the memory cell array. The storage device according to claim 1.

13. Extending in the first direction, located in the direction opposite to the second direction from the third conductor, intersecting the first and second conductors, having a fifth end and a sixth end, the fifth end being connected to a fourth conductor located in the first direction from the sixth end, A third memory cell connected to one of the first conductor and the second conductor, and the fourth conductor, A fifth switch connected to the fifth end of the fourth conductor, A sixth switch connected to the sixth end of the fourth conductor, Equipped with, When reading data from the third memory cell, the fifth switch and the sixth switch are kept ON. The storage device according to claim 1.

14. The first conductor and the second conductor extend in the second direction, The first conductor has a third end on the side in the second direction, The second conductor has a fourth end on the side of the second direction, The storage device further comprises a third switch connected to the third end of the first conductor and a fourth switch connected to the fourth end of the second conductor. When reading data from the first memory cell, the third switch is kept ON. When reading data from the second memory cell, the fourth switch remains ON. The storage device according to claim 13.

15. Further comprising the first wiring, The first switch is connected between the first end of the third conductor and the first wiring, The second switch is connected between the second end of the third conductor and the first wiring, The fifth switch is connected between the fifth end of the fourth conductor and the first wiring, The sixth switch is connected between the sixth end of the fourth conductor and the first wiring. The storage device according to claim 14.

16. Further equipped with a second wiring, The third switch is connected between the third end of the first conductor and the second wiring, The fourth switch is connected between the fourth end of the second conductor and the second wiring, One of the first and second wirings is connected to the node and sense amplifier circuit of the first voltage. The other end of the first wiring and the second wiring is connected to a node with a second voltage lower than the first voltage. The storage device according to claim 15.

17. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 16.

18. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 14.

19. The first conductor is located closer to the second end than the first end of the third conductor. The second conductor is located closer to the first end than the second end of the third conductor. The storage device according to claim 13.

20. Each of the first memory cell and the second memory cell includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The storage device according to any one of claims 1 to 19.

21. First conductor and, Intersecting with the first conductor, extending in a first direction, having a first end and a second end, the first end being located in the first direction relative to the second end, A memory cell connected to the first conductor and the second conductor, A first switch connected to the first end of the second conductor, A second switch connected to the second end of the second conductor, Equipped with, When data is written to the memory cell, the first switch and the second switch are kept on. storage device.

22. The first conductor extends in a second direction, The first conductor has a third end on the side in the second direction, The storage device further comprises a third switch connected to the third end of the first conductor, When data is written to the memory cell, the third switch is kept on. The storage device according to claim 21.

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