Indication device

Abstract

It helps to suppress the decline in reliability. [Solution] According to one embodiment, the display device comprises a substrate having an upper surface, an organic insulating layer disposed facing the upper surface and extending over a display area for displaying an image and a peripheral area outside the display area, an inorganic insulating layer disposed over the display area and the peripheral area and covering the organic insulating layer, a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, a lower part disposed on the inorganic insulating layer and having conductivity and contacting the upper electrode, and an upper part disposed on the lower part, a partition wall formed in an overhang shape, and a dam portion spaced apart from the organic insulating layer, surrounding the organic insulating layer and covered by the inorganic insulating layer, wherein the first height from the upper surface to the top of the dam portion is greater than the second height from the upper surface to the top of the upper part.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for suppressing a decrease in reliability are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of suppressing a decrease in reliability.

Means for Solving the Problems

[0005] According to an embodiment, a display device The device comprises a substrate having an upper surface, an organic insulating layer disposed over a display area facing the upper surface and extending to a peripheral area outside the display area, an inorganic insulating layer disposed over the display area and the peripheral area and covering the organic insulating layer, a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, a lower part disposed on the inorganic insulating layer and having conductivity and contacting the upper electrode, and an upper part disposed on the lower part, a partition wall formed in an overhang shape, and a dam portion spaced apart from the organic insulating layer, surrounding the organic insulating layer and covered by the inorganic insulating layer, wherein the first height from the upper surface to the top of the dam portion is greater than the second height from the upper surface to the top of the upper part.

[0006] According to the embodiment, the display device is A substrate, a display area for displaying an image, and a first organic insulating layer disposed over a peripheral area outside the display area, a second organic insulating layer covering the first organic insulating layer, an inorganic insulating layer disposed over the display area and the peripheral area and covering the second organic insulating layer, a lower electrode disposed on the second organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, and the inorganic insulating layer The device comprises a partition wall formed in an overhang shape, having a lower part that is conductive and in contact with the upper electrode, and an upper part positioned above the lower part, and a dam portion positioned in the peripheral region, spaced apart from the second organic insulating layer, and surrounding the second organic insulating layer, wherein the dam portion comprises a first layer formed of the same material as the first organic insulating layer, a second layer formed of the same material as the second organic insulating layer and covering the first layer, and a third layer formed of an organic insulating material, covering the second layer and covered by the inorganic insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX. [Figure 3] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the display device DSP to illustrate the structure of the surrounding region SA. [Figure 5] Figure 5 is a magnified plan view of a portion of the surrounding area SA shown in Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view of the display device DSP along the CD line in the peripheral region SA shown in Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view, enlarged from a portion of Figure 6. [Figure 8] Figure 8 is a schematic cross-sectional view of the contact section CT for electrically connecting the detection wiring DL and the detection electrode DT. [Figure 9] Figure 9 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 10] Figure 10 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 11] Figure 11 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 12] Figure 12 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 13] Figure 13 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 14] Figure 14 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 15] Figure 15 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 16] Figure 16 is a diagram illustrating the manufacturing method of a display device DSP. [Figure 17A] Figure 17A is a diagram illustrating another method for manufacturing a display device DSP. [Figure 17B]FIG. 17B is a diagram for explaining another manufacturing method of the display device DSP. [Figure 18] FIG. 18 is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 5. [Figure 19] FIG. 19 is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 5. [Figure 20] FIG. 20 is a cross-sectional view showing another configuration example of the display device DSP along the C-D line of the peripheral region SA shown in FIG. 5. MODE FOR CARRYING OUT THE INVENTION

[0008] The embodiments will be described with reference to the drawings. The disclosure is merely an example, and those that can be easily conceived by those skilled in the art for appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. Also, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect for clearer explanation, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above with respect to the already presented figures may be assigned the same reference numerals, and detailed descriptions that overlap may be omitted as appropriate.

[0009] In the drawings, for easy understanding as needed, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is called a plan view. Note that terms indicating the positional relationship between two or more components such as above, upper, between, and opposite include not only the case where the two or more target components are in direct contact but also the case where they are separated from each other with a gap or other components interposed therebetween. Also, the positive direction of the Z-axis is referred to as up or above.

[0010] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] Figure 1 shows an example configuration of a display device DSP.

[0012] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0013] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in plan view. However, the shape of the display area DA in plan view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors from each other. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] Note that the rounded portion RD of the display area DA is a shape that is visible macroscopically, while microscopically it is a shape formed by the arrangement of multiple pixels PX in a stepped pattern.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. In the illustrated example, the scan line GL and power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0020] The display device DSP further includes a terminal section T located in the peripheral region SA. The terminal section T has multiple terminals and is electrically connected to, for example, an IC chip for driving a display element DE or a flexible circuit board.

[0021] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX.

[0022] In the illustrated example, sub-pixels SP2 and SP3 are aligned in the second direction Y. Sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0023] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0024] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs.

[0025] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the apertures AP1, AP2, and AP3. The partition wall 6, like the inorganic insulating layer 5, can also be said to have apertures OP1, OP2, and OP3 in the sub-pixels SP1, SP2, and SP3, respectively. Aperture OP1 overlaps with aperture AP1, aperture OP2 overlaps with aperture AP2, and aperture OP3 overlaps with aperture AP3. The partition wall 6 is conductive and is electrically connected to the common voltage terminal at the terminal section T shown in Figure 1.

[0026] The sub-pixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively.

[0027] The display element DE1 of the sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, organic layer OR1, and upper electrode UE1 constituting the display element DE1 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view.

[0028] The display element DE2 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, organic layer OR2, and upper electrode UE2 constituting the display element DE2 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view.

[0029] The sub-pixel SP3 display element DE3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, organic layer OR3, and upper electrode UE3 constituting the display element DE3 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view.

[0030] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown may not accurately reflect their actual shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode and are in contact with the partition wall 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0033] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3.

[0034] The partition wall 6 has multiple slits ST. In the illustrated example, each slit ST extends in the second direction Y. For example, sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are arranged between two adjacent slits ST in the first direction X. Note that the slits ST may be omitted.

[0035] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2.

[0036] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, various wirings such as scan lines GL, signal lines SL, and power lines PL, and various insulating layers.

[0037] The organic insulating layer 12 is placed on top of the circuit layer 11. The organic insulating layer 12 is formed, for example, to flatten the irregularities caused by the circuit layer 11.

[0038] The lower electrode LE1 of sub-pixel SP1, LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are arranged on the organic insulating layer 12 and spaced apart from each other.

[0039] The inorganic insulating layer 5 is placed on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the aperture AP2 overlaps with the lower electrode LE2, and the aperture AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the organic insulating layer 12. Note that the contact holes of the organic insulating layer 12 are omitted in Figure 3.

[0040] The partition wall 6 is formed in an overhang shape and has a conductive lower part 61 placed on the inorganic insulating layer 5 and an upper part 62 placed on the lower part 61.

[0041] In the illustrated example, the lower part 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5, and an axial layer 64 placed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a greater width than the axial layer 64. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0042] The upper section 62 is positioned on top of the axial layer 64. The upper section 62 has a greater width than the axial layer 64. Both ends of the upper section 62 protrude from the sides of the axial layer 64. In this specification, the sides of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper section 62. In the illustrated example, the upper section 62 has a greater width than the bottom layer 63. The bottom layer 63 may also have a greater width than the upper section 62.

[0043] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0044] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0045] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0046] Furthermore, contact between each of the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper part 62.

[0047] In the illustrated example, sub-pixel SP1 has a cap layer CP1 and a sealing layer SE11, sub-pixel SP2 has a cap layer CP2 and a sealing layer SE12, and sub-pixel SP3 has a cap layer CP3 and a sealing layer SE13. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0048] The cap layer CP1 is placed on top of the upper electrode UE1. The cap layer CP2 is placed on top of the upper electrode UE2. The cap layer CP3 is placed on top of the upper electrode UE3.

[0049] The sealing layer SE11 is positioned on top of the cap layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE11 is in contact with the axial layer 64 and upper layer 62 of the partition wall 6 surrounding the display element DE1.

[0050] The sealing layer SE12 is positioned on top of the cap layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE12 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE2.

[0051] The sealing layer SE13 is positioned on top of the cap layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. The sealing layer SE13 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE3.

[0052] In the following explanation, a multilayer structure containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer structure containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer structure containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0053] The ends of the sealing layers SE11, SE12, and SE13 are located on the partition wall 6. In the illustrated example, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the same partition wall 6. Similarly, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the same partition wall 6.

[0054] The laminated films FL1, FL2, and FL3 are not formed on the partition wall 6. Cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0055] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills the cavity formed above the partition wall 6.

[0056] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 is placed on top of the sealing layer SE2.

[0057] The detection electrode DT, which enables the touch sensor function to detect contact or approach of an object to the display area DA, is placed on the sealing layer SE2 and covered with a resin layer RS2. The detection electrode DT is a multilayer body including, for example, an aluminum layer formed of an aluminum-based material and a titanium layer formed of a titanium-based material. The touch sensor function is realized by detecting a change in capacitance of the sensor part composed of the detection electrode DT.

[0058] The inorganic insulating layer 5, sealing layers SE11, SE12, SE13, and sealing layer SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). In one example, the inorganic insulating layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride.

[0059] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is made of a titanium-based material, such as titanium or a titanium compound. The axial layer 64 is made of a different material from the bottom layer 63 and the upper part 62, and is made of an aluminum-based material, such as aluminum or an aluminum compound.

[0060] The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper part 62 is formed of a different material from the lower part 61. For example, the upper part 62 is formed of a titanium-based material such as titanium or a titanium compound, or an oxide conductive material such as indium tin oxide (ITO).

[0061] The lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a transparent layer formed from an oxide conductive material such as indium tin oxide (ITO), and a reflective layer formed from a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a reflective layer between a pair of transparent layers.

[0062] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials. In one example, light-emitting layer EM1 is formed from a material that emits light in the blue wavelength range, light-emitting layer EM2 is formed from a material that emits light in the green wavelength range, and light-emitting layer EM3 is formed from a material that emits light in the red wavelength range. Alternatively, light-emitting layer EM1 may be formed from a material that emits light in the green wavelength range, and light-emitting layer EM2 may be formed from a material that emits light in the blue wavelength range.

[0063] Furthermore, each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, another hole blocking layer, an electron transport layer, and an electron injection layer.

[0064] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0065] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0066] The illustrated circuit layer 11, organic insulating layer 12, inorganic insulating layer 5, and partition wall 6 are arranged across the display area DA and the surrounding area SA.

[0067] Figure 4 is a schematic plan view of the display device DSP to illustrate the structure of the surrounding region SA.

[0068] The display device DSP includes a dam structure DS located in the surrounding region SA. In the illustrated example, the dam structure DS includes annular dam sections DM1, DM2, DM3, and DM4.

[0069] Dam section DM1 is formed to surround the display area DA. Dam section DM2 is formed to surround dam section DM1. Dam section DM3 is formed to surround dam section DM2. Dam section DM4 is formed to surround dam section DM3.

[0070] Each of the dam sections DM1, DM2, DM3, and DM4 has an arc-shaped curved section CV and straight sections LN connected to both ends of the curved section CV. The curved section CV is formed, for example, along the rounded section RD of the display area DA. The straight section LN is located, for example, between the display area DA and the terminal section T and extends along the first direction X.

[0071] Note that the shapes of the dam sections DM1, DM2, DM3, and DM4 are not limited to the examples shown. Also, the number of dam sections in the dam structure DS may be three or fewer, or five or more.

[0072] Figure 5 is a magnified plan view of a portion of the surrounding area SA shown in Figure 4.

[0073] The aforementioned organic insulating layer 12 is also placed in the surrounding region SA. The organic insulating layer 12 is located inside the dam section DM1. That is, the dam section DM1 surrounds the organic insulating layer 12. The edge E0 of the organic insulating layer 12 is spaced apart from the dam section DM1.

[0074] Dam sections DM1, DM2, DM3, and DM4 are located between the edge E0 and the edge 10E of the substrate 10. Dam section DM2 is separated from dam section DM1, dam section DM3 is separated from dam section DM2, and dam section DM4 is separated from dam section DM3.

[0075] The partition wall 6 described above extends into the surrounding region SA and, in a plan view, overlaps with the organic insulating layer 12 overall. That is, the edge E1 of the partition wall 6 is located above the organic insulating layer 12. In the illustrated example, the partition wall 6 has multiple openings 6A. The multiple openings 6A are arranged in a matrix in the first direction X and the second direction Y.

[0076] In the illustrated example, the multilayer film FL and the sealing layer SE1 are located in the peripheral region SA. Here, the multilayer film FL is one of the multilayer films FL1, FL2, or FL3 shown in Figure 3. Similarly, the sealing layer SE1 is one of the sealing layers SE11, SE12, or SE13 shown in Figure 3. In a plan view, the multilayer film FL and the sealing layer SE1 overlap the organic insulating layer 12 overall. That is, the edges E2 of the multilayer film FL and the sealing layer SE1 are located above the organic insulating layer 12.

[0077] The partition wall 6, the laminated film FL, and the sealing layer SE1 are located inside the dam section DM1. That is, the dam section DM1 surrounds the partition wall 6, the laminated film FL, and the sealing layer SE1. In the illustrated example, the edges E0, E1, and E2 are spaced apart from the dam section DM1 and are formed in the same arc shape as the dam section DM1. Edge E2 is located between edge E1 and edge E0.

[0078] Figure 6 is a schematic cross-sectional view of the display device DSP along the CD line in the peripheral region SA shown in Figure 5.

[0079] The circuit layer 11 shown in Figure 3 comprises insulating layer 111, insulating layer 112, insulating layer 113, insulating layer 114, and insulating layer 115.

[0080] Insulating layer 111 is located on substrate 10. Insulating layer 112 is located on insulating layer 111. Insulating layer 113 is located on insulating layer 112. Insulating layer 114 is located on insulating layer 113. Insulating layer 115 is located on insulating layer 114. Insulating layers 111, 112, 113, and 114 are formed of inorganic insulating material, extend to the edge 10E of substrate 10, and are located directly beneath dam portions DM1, DM2, DM3, and DM4. Insulating layer 115 is formed of organic insulating material and is covered by organic insulating layer 12. Insulating layer 115 is spaced apart from dam portion DM1. Organic insulating layer 12 extends between insulating layer 115 and dam portion DM1.

[0081] The inorganic insulating layer 5 covers the organic insulating layer 12. Between the organic insulating layer 12 and the dam section DM1, the inorganic insulating layer 5 covers the insulating layer 114. The partition wall 6 extending into the surrounding region SA is shown in a simplified manner, but it is positioned on top of the inorganic insulating layer 5. The laminated film FL is positioned on the upper part 62 of the partition wall 6, and also on top of the inorganic insulating layer 5 between the partition wall 6 and the dam section DM1. In other words, the laminated film FL is separated by the partition wall 6. This blocks the pathway for moisture intrusion through the laminated film FL.

[0082] The sealing layer SE1 covers the laminated film FL that overlaps the partition wall 6 and the laminated film FL that overlaps the inorganic insulating layer 5. All of these partition wall 6, laminated film FL, and sealing layer SE1 are located directly above the region where the insulating layer 115 and the organic insulating layer 12 overlap.

[0083] Each of the dam sections DM1, DM2, DM3, and DM4 is placed on the insulating layer 114 and covered with an inorganic insulating layer 5. Between dam section DM1 and dam section DM2, between dam section DM2 and dam section DM3, between dam section DM3 and dam section DM4, and between dam section DM4 and edge section 10E, the inorganic insulating layer 5 covers the insulating layer 114.

[0084] In the illustrated example, each of the dam sections DM1, DM2, DM3, and DM4 comprises a first layer 115A, a second layer 12A, and a third layer 30.

[0085] The first layer 115A is formed simultaneously with the insulating layer 115 using the same material and has the same thickness as the insulating layer 115. The second layer 12A is formed simultaneously with the organic insulating layer 12 using the same material and has the same thickness as the organic insulating layer 12. The third layer 30 is made of an organic insulating material. Note that thickness corresponds to the length along the third direction Z.

[0086] The first layer 115A is placed on top of the insulating layer 114. The second layer 12A covers the first layer 115A. The third layer 30 covers the second layer 12A and is covered with an inorganic insulating layer 5. These first layer 115A, second layer 12A, and third layer 30 are all made of the same type of organic insulating material, for example, polyimide.

[0087] Dam sections DM1, DM2, DM3, and DM4 have the same thickness T11. Here, thickness T11 corresponds to the distance along the third direction Z from the top surface of the insulating layer 114 to the top of the dam section (the top of the third layer 30). In other words, thickness T11 corresponds to the sum of the thickness of the first layer 115A, the thickness of the second layer 12A, and the thickness of the third layer 30.

[0088] On the other hand, no insulating layer corresponding to the third layer 30 is provided between the organic insulating layer 12 and the inorganic insulating layer 5. The sum T12 of the thickness of the insulating layer 115 and the thickness of the organic insulating layer 12 is smaller than the thickness T11 of the dam section (T11 > T12). In one example, the thickness of the first layer 115A is approximately 1.5 μm, the thickness of the second layer 12A is approximately 3 μm, and the thickness of the third layer 30 is 2 to 3 μm, so the thickness T11 is 1.4 times or more the thickness T12.

[0089] The first heights H1 along the third direction Z from the top surface 10A of the substrate 10 to the tops of each of the dam sections DM1, DM2, DM3, and DM4 are equal to each other and greater than the second height H2 along the third direction Z from the top surface 10A to the top of the upper part 62 (H1 > H2).

[0090] Furthermore, the first height H1 is greater than the third height H3 along the third direction Z from the top surface 10A to the top of the sealing layer SE1 (H1 > H3).

[0091] The resin layer RS1 covers the sealing layer SE1 and is positioned on top of the inorganic insulating layer 5, filling the space between the organic insulating layer 12 and the dam portion DM1, and between the dam portions DM1 and DM2. The edge E11 of the resin layer RS1 overlaps the dam portion DM2. In the illustrated example, the edge E11 overlaps the top of the dam portion DM2. Furthermore, the upper surface of the resin layer RS1 is convex in the peripheral region SA and is formed as a smooth surface with almost no local depressions.

[0092] Such a resin layer RS1 is formed by applying a liquid organic insulating material. The dam portions DM1 and DM2 have the function of preventing the spread of the applied organic insulating material. When the case in which the thickness T11 of the dam portions DM1 and DM2 is equivalent to the thickness T12 is used as a comparative example, the dam portions DM1 and DM2 in the illustrated example have a higher damming capacity than the comparative example. Therefore, even if more organic insulating material is applied than in the comparative example, the spread of the organic insulating material can be reliably prevented at the dam portions DM1 and DM2. In addition, because a large amount of organic insulating material can be applied, a sufficient amount of organic insulating material can be filled between the organic insulating layer 12 and the dam portion DM1, and between the dam portions DM1 and DM2. This suppresses insufficient application of organic insulating material and prevents the formation of undesirable depressions in the resin layer RS1.

[0093] The sealing layer SE2 covers the resin layer RS1. The sealing layer SE2 extends outward beyond the edge E11 of the resin layer RS1 and contacts the inorganic insulating layer 5 at a position overlapping the dam portion DM2. In the illustrated example, the edge E12 of the sealing layer SE2 is located inward from the edge 10E of the substrate 10 and overlaps the dam portion DM4. In other words, the resin layer RS1 is surrounded by the sealing layer SE1, the inorganic insulating layer 5, and the sealing layer SE2. This suppresses the penetration of moisture into the resin layer RS1.

[0094] The resin layer RS2 is disposed on the sealing layer SE2 and is filled between the dam portions DM2 and DM3 and between the dam portions DM3 and DM4. In the illustrated example, the edge E13 of the resin layer RS2 overlaps the dam portion DM4 and is located inside the edge E12.

[0095] FIG. 7 is a schematic cross-sectional view enlarging a part of FIG. 6.

[0096] The circuit layer 11 further includes a power supply line CL and a connection electrode CN. The power supply line CL is disposed on the insulating layer 113. Also, a part of the power supply line CL is covered with the insulating layer 114. The power supply line CL is a wiring for supplying a common voltage to the partition wall 6. The connection electrode CN is disposed on the insulating layer 114 and is also disposed between the first layer 115A and the second layer 12A in the dam portion DM1 and is in contact with the power supply line CL.

[0097] The organic insulating layer 12 has a first portion P1 having a thickness T1 and a second portion P2 having a thickness T2. The thickness T2 is smaller than the thickness T1 (T2 < T1). The second portion P2 is formed at the periphery of the first portion P1. The insulating layer 115 is disposed below the first portion P1. A stepped portion 12a is formed in the organic insulating layer 12 near the edge E3 of the insulating layer 115. For example, the boundary B between the first portion P1 and the second portion P2 is located at the lower end of the stepped portion 12a.

[0098] The relay electrode RL is disposed across the first portion P1, the second portion P2, and the stepped portion 12a. If the organic insulating layer 12 does not have the second portion P2, the stepped portion 12a becomes steeper. When the relay electrode RL is formed along such a steep stepped portion 12a, there is a possibility of shape abnormalities such as disconnection of the relay electrode RL. On the other hand, when the organic insulating layer 12 has the second portion P2, the stepped portion 12a is alleviated and the formation abnormality of the relay electrode RL is suppressed.

[0099] The intermediate electrode RL is formed of the same material as, for example, the lower electrode LE1 described above, and is electrically connected to the partition wall 6 in a region not shown. The intermediate electrode RL is in contact with the connecting electrode CN between the edge E0 and the dam DM1. This electrically connects the power supply line CL and the partition wall 6. Such an intermediate electrode RL is covered with an inorganic insulating layer 5.

[0100] The edge E1 of the partition wall 6, and the edge E2 of the laminated film FL and the sealing layer SE1 are located above the first portion P1. Edge E1 corresponds to the end of the upper part 62 of the partition wall 6. Furthermore, both edge E1 and edge E2 are located on the display area DA side (left side in the figure) of the edge E3 of the insulating layer 114.

[0101] Figure 8 is a schematic cross-sectional view of the contact section CT for electrically connecting the detection wiring DL and the detection electrode DT.

[0102] The contact section CT is located outside the dam section DM2. The contact section CT comprises a detection wiring DL, connecting electrodes CN1 and CN2, and a terminal TE. In the contact section CT, the insulating layer 115B is spaced apart from the first layer 115A of the dam section DM2 and is placed on top of the insulating layer 114. The insulating layer 12B is spaced apart from the second layer 12A of the dam section DM2 and is placed on top of the insulating layer 115B. The insulating layer 115B is formed simultaneously with the first layer 115A using the same material as the first layer 115A. The insulating layer 12B is formed simultaneously with the second layer 12A using the same material as the second layer 12A.

[0103] The detection wiring DL is positioned between insulating layer 111 and insulating layer 112 in the surrounding region SA and is electrically connected to a detection circuit (not shown). The connecting electrode CN1 is positioned between insulating layer 112 and insulating layer 113 and is in contact with the detection wiring DL through a through-hole in insulating layer 112. The connecting electrode CN2 is positioned between insulating layer 113 and insulating layer 114 and is in contact with the connecting electrode CN1 through a through-hole in insulating layer 113. The terminal TE is positioned on insulating layer 115B and is in contact with the connecting electrode CN2 through through-holes in insulating layers 114 and 115B. Thus, the terminal TE is electrically connected to the detection wiring DL.

[0104] The insulating layer 12B covers a portion of terminal TE and, around terminal TE, covers insulating layers 114 and 115B. The insulating layer 12B has a different thickness from the second layer 12A. That is, the thickness T21 of the insulating layer 12B along the third direction Z that overlaps the upper surface of insulating layer 115B around terminal TE is smaller than the thickness T22 of the second layer 12A along the third direction Z that overlaps the upper surface of the first layer 115A in the dam section DM2 (T21 <T22)。

[0105] The inorganic insulating layer 5 and the sealing layer SE2 cover the insulating layer 12B.

[0106] The detection electrode DT is positioned on the sealing layer SE2, led out to the contact portion CT, and contacts the terminal TE through the insulating layer 12B, the inorganic insulating layer 5, and the through-hole in the sealing layer SE2. This electrically connects the detection electrode DT to the detection wiring DL. The detection electrode DT is covered with a resin layer RS2.

[0107] In the contact portion CT, as described above, the thickness T21 of the insulating layer 12B is smaller than the thickness T22 of the second layer 12A. Therefore, when the liquid organic insulating material for forming the resin layer RS2 is applied, a sufficient amount of organic insulating material can be filled between the contact portion CT and the dam portion DM2. This makes it possible to suppress the formation of undesirable voids in the resin layer RS2.

[0108] Furthermore, as explained with reference to Figure 6, the formation of undesirable recesses is suppressed in the resin layer RS1, allowing the detection electrode DT to be formed on a smooth surface. This suppresses abnormalities in the formation of the detection electrode DT, such as short circuits between adjacent detection electrodes DT. Therefore, it is possible to suppress a decrease in reliability.

[0109] Next, we will explain the manufacturing method of the DSP display device.

[0110] First, a processing substrate SUB is prepared as shown in Figure 9. The process of preparing the processing substrate SUB includes the steps of forming a circuit layer 11 including insulating layers 111, 112, 113, 114, and 115 on the substrate 10, and forming an organic insulating layer 12 on the insulating layer 114.

[0111] In the process of forming the insulating layer 115, first, an organic insulating material is applied to the display area DA and the surrounding area SA of the processing substrate SUB. Then, by curing a portion of the organic insulating material, the insulating layer 115 is formed, and the first layer 115A of the dam section DM is formed in the surrounding area SA. At this time, the insulating layer 115B of the contact section CT shown in Figure 8 is also formed simultaneously. The dam section DM here corresponds to the dam sections DM1, DM2, DM3, and DM4 described above.

[0112] In the process of forming the organic insulating layer 12, first, an organic insulating material is applied to the display area DA and the surrounding area SA of the processing substrate SUB. Then, by curing a portion of the organic insulating material, the organic insulating layer 12 is formed, and the second layer 12A of the dam portion DM is formed in the surrounding area SA. At this time, the insulating layers 12B of the first portion P1 and the second portion P2 shown in Figure 7, and the contact portion CT shown in Figure 8 are also formed simultaneously.

[0113] Next, as shown in Figure 10, the third layer 30 of the dam section DM is formed in the peripheral region SA. In the process of forming the third layer 30, first, an organic insulating material is applied to the display region DA and the peripheral region SA of the processing substrate SUB. Then, the third layer 30 of the dam section DM is formed by curing a portion of the organic insulating material in the peripheral region SA. In the display region DA, the applied organic insulating material is removed.

[0114] Next, as shown in Figure 11, the lower electrodes LE1 of the sub-pixel SP1, LE2 of the sub-pixel SP2, and LE3 of the sub-pixel SP3 are formed on the organic insulating layer 12 of the display area DA. Subsequently, an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively, and a partition wall 6 having a lower part 61 located above the inorganic insulating layer 5 and an upper part 62 located above the lower part 61 are formed. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 with openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition wall 6 is formed. The inorganic insulating layer 5 is formed not only in the display area DA but also in the surrounding area SA, covering the dam section DM.

[0115] The first height H1 from the top surface 10A of the substrate 10 to the top of the dam section DM is greater than the height H12 from the top surface 10A of the display area DA to the top of the upper part 62 of the partition wall 6 (H1 > H12). Note that the height H12 is equivalent to the second height H2 of the peripheral area SA shown in Figure 6.

[0116] Next, the display element DE1 is formed. Note that in Figures 12 to 15, only the cross-section of the display area DA is shown, and the elements below the organic insulating layer 12 are omitted.

[0117] First, as shown in Figure 12, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The laminated film FL1 has an organic layer OR1 including an emissive layer EM1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed continuously in a vacuum environment in the deposition apparatus. The laminated film FL1 is divided by the overhanging partition wall 6.

[0118] Then, a sealing layer SE11 is formed that continuously covers the laminated film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0119] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and in the display area DA, they are located not only on the sub-pixel SP1 but also on the sub-pixels SP2 and SP3. Although not shown in the figures, in the peripheral area SA, the laminated film FL1 and the sealing layer SE11 are formed to cover the dam area DM.

[0120] Next, as shown in Figure 13, a resist RS patterned to a predetermined shape is formed on the sealing layer SE11. The resist RS overlaps the sub-pixel SP1 and a portion of the surrounding partition wall 6.

[0121] Next, as shown in Figure 14, the sealing layer SE11 and the multilayer film FL1 are patterned using the resist RS as a mask. By performing various etching processes using the resist RS as a mask, the sealing layer SE11 exposed from the resist RS is removed, and then the cap layer CP1, upper electrode UE1, and organic layer OR1 contained in the multilayer film FL1 are sequentially removed.

[0122] This patterning exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3. In addition, the multilayer film FL1 and the sealing layer SE11 are removed in the peripheral region SA.

[0123] Subsequently, the resist RS is removed. This forms the display element DE1 on the sub-pixel SP1. In the illustrated example, the laminated film FL1 stacked on the partition wall 6 is removed during the process from patterning the laminated film FL1 to removing the resist RS. As a result, a cavity GP is formed between the sealing layer SE11 and the partition wall 6.

[0124] Next, as shown in Figure 15, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL2 is formed on the lower electrode LE2. The multilayer film FL2 has an organic layer OR2 including an emissive layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE12 is formed on the multilayer film FL2. Then, a resist is formed on the sealing layer SE12. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE12 and the multilayer film FL2 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0125] As a result, the display element DE2 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed. Also, in the illustrated example, the laminated film FL2 on top of the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE12 and the partition wall 6.

[0126] Next, as shown in Figure 16, the display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL3 is formed on the lower electrode LE3. The multilayer film FL3 has an organic layer OR3 including an emissive layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE13 is formed on the multilayer film FL3. Then, a resist is formed on the sealing layer SE13. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE13 and the multilayer film FL3 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0127] As a result, the display element DE3 is formed on the sub-pixel SP3. Also, in the illustrated example, the laminated film FL3 on the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE13 and the partition wall 6.

[0128] In this case, the first height H1 from the top surface 10A of the substrate 10 to the top of the dam section DM is greater than the height H13 from the top surface 10A to the tops of the sealing layers SE11, SE12, and SE13 in the display area DA (H1 > H13). Note that the height H13 is equivalent to the third height H3 of the peripheral area SA shown in Figure 6.

[0129] In the above manufacturing process, we assumed that the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0130] Subsequently, an organic insulating material is applied and cured to form a resin layer RS1. At this time, as explained with reference to Figure 6, a sufficient amount of organic insulating material is filled between the organic insulating layer 12 and the dam portion DM1, and between the dam portion DM1 and the dam portion DM2, so that a resin layer RS1 with a smooth surface is formed.

[0131] Subsequently, an inorganic insulating material is deposited to form a sealing layer SE2. The sealing layer SE2 extends beyond the edge E11 of the resin layer RS1, contacts the inorganic insulating layer 5, and seals the resin layer RS1.

[0132] Subsequently, a metal layer is formed on the sealing layer SE2, and this metal layer is patterned to form the detection electrode DT. As shown in Figure 8, the detection electrode DT extends beyond the dam section DM2 and contacts the terminal TE, which is electrically connected to the detection wiring DL, at the contact section CT.

[0133] When forming the detection electrode DT, if a recess is formed in the underlying resin layer RS1, a patterning defect in the metal layer formed in the recess may cause a short circuit between adjacent detection electrodes DT.

[0134] In this embodiment, as described above, the resin layer RS ​​is formed to have a smooth surface. Therefore, patterning defects in the metal layer are suppressed, and abnormal formation of the detection electrode DT is suppressed.

[0135] Subsequently, an organic insulating material is applied and cured to form a resin layer RS2. At this time, as explained with reference to Figure 8, the step difference between the dam section DM2 and the contact section CT is reduced, so a sufficient amount of organic insulating material is filled around the contact section CT.

[0136] After the above steps, the DSP display device is completed.

[0137] In the above example configuration, the three-layer dam section DM is formed through the steps of forming the first layer 115A together with the insulating layer 115, forming the second layer 12A together with the organic insulating layer 12, and forming the third layer 30.

[0138] The following describes other manufacturing methods for the dam section DM.

[0139] First, as shown in Figure 17A, a processing substrate SUB is prepared. In the process of preparing the processing substrate SUB, insulating layers 111, 112, 113, and 114 are formed on the substrate 10, and then the insulating layer 115 and the first layer 115A of the dam section DM are formed.

[0140] Subsequently, an organic insulating material IL is applied to the display area DA and the surrounding area SA of the processing substrate SUB. The organic insulating material IL is a positive-type photosensitive material that becomes soluble in the developer solution upon light irradiation. In other words, the organic insulating material IL applied here can form a desired step depending on the amount of exposure.

[0141] Subsequently, the organic insulating material IL is exposed through a mask MK having partially different transmittances. Regarding the transmittance of the mask MK, for example, in the peripheral region SA, the area around the dam section DM is set to the maximum transmittance Tmax, the area around the dam section DM is set to the minimum transmittance Tmin, and the display area DA is set to an intermediate transmittance Tmid between the maximum transmittance Tmax and the minimum transmittance Tmin.

[0142] Next, as shown in Figure 17B, the exposed organic insulating material IL is developed. This forms the organic insulating layer 12 and the second layer 12A of the dam section DM. The thickness of the second layer 12A is greater than the thickness of the organic insulating layer 12. In addition, the organic insulating material IL is removed around the dam section DM, exposing the insulating layer 114. The dam section DM formed in this way has a two-layer structure consisting of the first layer 115A and the second layer 12A, and can achieve the same damming function as the three-layer structure dam section DM described above.

[0143] According to this manufacturing method, the step of forming the third layer 30, as explained with reference to Figure 10, can be omitted, reducing the number of manufacturing steps and lowering manufacturing costs.

[0144] Next, other configuration examples will be described. Note that for components identical to those in the above configuration examples, the same reference numerals may be used, and detailed explanations may be omitted.

[0145] Figure 18 is a cross-sectional view showing another example of a display device DSP configuration along the CD line of the peripheral region SA shown in Figure 5.

[0146] The configuration example shown in Figure 18 differs from the configuration example shown in Figure 6 in that, among the multiple dam sections, the thickness T14 of dam section DM1, which is closer to the organic insulating layer 12 than dam section DM2, is smaller than the thickness T11 of dam section DM2. Dam sections DM3 and DM4 have the same thickness T11 as dam section DM2.

[0147] The height H4 from the top surface 10A to the top of the dam section DM1 is less than the height H1 from the top surface 10A to the top of the dam section DM2 (H4

[0148] Even in this configuration example, when forming the resin layer RS1, the dam portion DM2 can exhibit a high damming capacity against the applied organic insulating material. Therefore, the same effect as in the above configuration example can be obtained in the illustrated configuration example.

[0149] Figure 19 is a cross-sectional view showing another example of a display device DSP configuration along the CD line of the peripheral region SA shown in Figure 5.

[0150] The configuration example shown in Figure 19 differs from the configuration example shown in Figure 6 in that, among the multiple dam sections, the thickness T15 of dam sections DM3 and DM4, which are closer to the edge 10E of the substrate 10 than dam section DM2, is smaller than the thickness T11 of dam section DM2. Dam section DM1 has the same thickness T11 as dam section DM2.

[0151] The height H5 from the top surface 10A to the top of the dam section DM3 is less than the height H1 from the top surface 10A to the top of the dam section DM2 (H5

[0152] Even in this configuration example, when forming the resin layer RS1, the dam sections DM1 and DM2 can exhibit a high damming capacity against the applied organic insulating material. Therefore, the same effect as in the above configuration example can be obtained in the illustrated configuration example.

[0153] Figure 20 is a cross-sectional view showing another example of a display device DSP configuration along the CD line of the peripheral region SA shown in Figure 5.

[0154] The configuration example shown in Figure 20 differs from the configuration example shown in Figure 19 in that the thickness T14 of the dam section DM1 is smaller than the thickness T11 of the dam section DM2.

[0155] ​​The height H4 from the top surface 10A to the top of the dam section DM1 is less than the height H1 from the top surface 10A to the top of the dam section DM2 (H4

[0156] Even in this configuration example, when forming the resin layer RS1, the dam portion DM2 can exhibit a high damming capacity against the applied organic insulating material. Therefore, the same effect as in the above configuration example can be obtained in the illustrated configuration example. In addition, for dam sections DM1, DM3, and DM4, which are separate from the main dam section DM2 that contributes to the damming of the resin layer RS1, reducing their thickness can suppress the generation of undesirable residues of conductive material (e.g., material forming the lower electrode, material forming the partition wall, material forming the detection electrode, etc.) between adjacent dam sections.

[0157] In the above embodiment, for example, dam section DM1 corresponds to the inner dam section, and dam sections DM3 and DM4 correspond to the outer dam sections. The sealing layers SE11, SE12, and SE13 correspond to the first sealing layer, the resin layer RS1 corresponds to the first resin layer, the sealing layer SE2 corresponds to the second sealing layer, and the resin layer RS2 corresponds to the second resin layer.

[0158] Insulating layer 115 corresponds to the first organic insulating layer, and organic insulating layer 12 corresponds to the second organic insulating layer. Insulating layer 115B corresponds to the first insulating layer, and insulating layer 12B corresponds to the second insulating layer. Insulating layer 111 corresponds to the first inorganic insulating layer, insulating layer 112 corresponds to the second inorganic insulating layer, insulating layer 113 corresponds to the third inorganic insulating layer, and insulating layer 114 corresponds to the fourth inorganic insulating layer.

[0159] As described above, according to this embodiment, it is possible to provide a display device that can suppress a decrease in reliability.

[0160] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0161] ​Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications to the above-described embodiments in which a person skilled in the art has appropriately added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0162] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0163] DSP...Display device DA...Display area SA...Peripheral area DE1, DE2, DE3... Display elements LE1, LE2, LE3…lower electrode OR1, OR2, OR3…Organic layer UE1, UE2, UE3...upper electrode SE11, SE12, SE13, SE2...Sealing layer RS1, RS2...Resin layer DM1, DM2, DM3, DM4... Dam section 5…Inorganic insulating layer 115...Insulating layer 115A...First layer 115B...Insulating layer 12...Organic insulating layer 12A...Second layer 12B...Insulating layer 30...Third layer 6...Bulkhead 61...Lower 62...Upper CT...Contact part DT...Detection electrode DL...Detection wiring TE...Terminal

Claims

1. A substrate having an upper surface, An organic insulating layer is arranged facing the upper surface, extending to a display area for displaying an image, and to a peripheral area outside the display area. An inorganic insulating layer is arranged across the display area and the surrounding area and covers the organic insulating layer, In the display area, a lower electrode is placed on the organic insulating layer and has a peripheral portion covered by the inorganic insulating layer, Displaced on the aforementioned lower electrode, an organic layer including a light-emitting layer, An upper electrode placed on the aforementioned organic layer, A partition wall formed in an overhang shape comprises a lower part disposed on the inorganic insulating layer and having conductivity, which contacts the upper electrode, and an upper part disposed on the lower part, A dam section that is separated from the organic insulating layer, surrounds the organic insulating layer, and is covered with the inorganic insulating layer, Equipped with, The first height from the upper surface to the top of the dam section is greater than the second height from the upper surface to the top of the upper section. Display device.

2. Furthermore, in the peripheral region, the laminated film disposed on the upper part, It comprises a first sealing layer formed of an inorganic insulating material and covering the laminated film, The first height is greater than the third height from the top surface to the top of the first sealing layer. The display device according to claim 1.

3. Furthermore, it comprises a first resin layer covering the first sealing layer, The edge of the first resin layer overlaps the dam portion. The display device according to claim 2.

4. Furthermore, it includes an inner dam section located between the organic insulating layer and the dam section, and spaced apart from the organic insulating layer. The first resin layer is filled between the organic insulating layer and the inner dam portion, and between the inner dam portion and the dam portion. The display device according to claim 3.

5. The height from the upper surface to the top of the inner dam section is equal to the first height. The display device according to claim 4.

6. The height from the upper surface to the top of the inner dam section is less than the first height. The display device according to claim 4.

7. Furthermore, a second sealing layer formed of an inorganic insulating material and covering the first resin layer, A second resin layer disposed on the second sealing layer, The device comprises a detection electrode disposed on the second sealing layer and covered with the second resin layer for detecting contact or approach of an object to the display area, The second sealing layer is in contact with the inorganic insulating layer at a position overlapping the dam portion. The display device according to claim 3.

8. Furthermore, it is equipped with an outer dam section surrounding the aforementioned dam section, The second resin layer is filled between the dam section and the outer dam section. The display device according to claim 7.

9. The height from the upper surface to the top of the outer dam section is equal to the first height. The display device according to claim 8.

10. The height from the upper surface to the top of the outer dam section is less than the first height. The display device according to claim 8.

11. Furthermore, it includes an inner dam section located between the organic insulating layer and the dam section, and spaced apart from the organic insulating layer. The height from the upper surface to the top of the inner dam section is less than the first height. The display device according to claim 10.

12. circuit board and A display area for displaying an image, and a first organic insulating layer arranged over a peripheral area outside the display area, A second organic insulating layer covering the first organic insulating layer, An inorganic insulating layer is arranged over the display area and the surrounding area and covers the second organic insulating layer, In the display area, a lower electrode is placed on the second organic insulating layer and has a peripheral portion covered by the inorganic insulating layer, Displaced on the aforementioned lower electrode, an organic layer including a light-emitting layer, An upper electrode placed on the aforementioned organic layer, A partition wall formed in an overhang shape comprises a lower part disposed on the inorganic insulating layer and having conductivity, which contacts the upper electrode, and an upper part disposed on the lower part, A dam portion is arranged in the aforementioned peripheral region, spaced apart from the second organic insulating layer, and surrounding the second organic insulating layer, Equipped with, The aforementioned dam section is A first layer formed of the same material as the first organic insulating layer, A second layer formed of the same material as the second organic insulating layer and covering the first layer, It comprises a third layer formed of an organic insulating material, covering the two aforementioned layers, and covered by the inorganic insulating layer, Display device.

13. The thickness of the dam section is 1.4 times or more the sum of the thicknesses of the first organic insulating layer and the second organic insulating layer. The display device according to claim 12.

14. Furthermore, in the display area, a cap layer is placed on the upper electrode, A first sealing layer formed of an inorganic insulating material, disposed on the cap layer and in contact with the partition wall, A first resin layer disposed on the first sealing layer, A second sealing layer, formed of an inorganic insulating material and disposed on the first resin layer, A second resin layer disposed on the second sealing layer, The device comprises a detection electrode disposed on the second sealing layer and covered with the second resin layer for detecting contact or approach of an object to the display area, The display device according to claim 12.

15. The first resin layer is filled between the second organic insulating layer and the dam portion in the peripheral region. The edge of the first resin layer overlaps the dam portion, The second sealing layer is in contact with the inorganic insulating layer at a position overlapping the dam portion. The display device according to claim 14.

16. Furthermore, the surrounding area is equipped with detection wiring, The detection electrode is electrically connected to the detection wiring at the contact portion outside the dam portion. The display device according to claim 15.

17. Furthermore, in the contact portion, A first insulating layer, spaced apart from the dam section and made of the same material as the first layer, A terminal is placed on the first insulating layer and electrically connected to the detection wiring, The device comprises a second insulating layer, which is placed on the first insulating layer, covers a portion of the terminal, and is made of the same material as the second layer, The second insulating layer is covered with the inorganic insulating layer and the second sealing layer. The detection electrode is in contact with the terminal exposed from the second insulating layer, the inorganic insulating layer, and the second sealing layer. The display device according to claim 16.

18. The thickness of the second insulating layer that overlaps the first insulating layer around the terminal is smaller than the thickness of the second layer that overlaps the first layer in the dam portion. The display device according to claim 17.

19. The lower part of the partition wall comprises a bottom layer disposed on the inorganic insulating layer and an axial layer disposed between the bottom layer and the upper part. Both ends of the bottom layer and the upper part protrude from the side surface of the axial layer. The display device according to claim 1 or 12.

20. At least a portion of the outer edge of the display area includes a rounded portion. The dam section has an arc-shaped curved section that follows the rounded section. The display device according to claim 1 or 12.

Images