electronic machinery

Abstract

To obtain electronic equipment that can perform effective debugging even when the control system cannot enter debug mode. [Solution] The CPU 11 executes a predetermined control system program. When a debug request is detected and the CPU 11 is operational, the CPU 11 starts supplying power and clock to the debug circuit 16, and the debug circuit 16 performs the collection of debug information. On the other hand, when a debug request is detected and the CPU 11 is not operational, the boot sequencer 19 (a) saves the debug information to the non-volatile memory 14, then restarts the control system, and (b) after the restart, starts supplying power and clock to the debug circuit 16 and restores the debug information. After the debug information is restored, the debug circuit 16 performs the collection of debug information.

Description

Technical Field

[0001] The present invention relates to an electronic device.

Background Art

[0002] Some electronic devices have a normal operation mode and a debug mode as operation modes. When an abnormal operation is detected during the initial operation or subsequent operation when the power is turned on, the device switches to the debug mode and starts supplying power to the debug circuit to enable debugging (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the control system in the electronic device becomes inoperable due to an abnormal operation or the like, it may not be possible to immediately switch to the debug mode, and effective debugging may not be possible.

[0005] The present invention has been made in view of the above problems, and an object thereof is to obtain an electronic device that can perform effective debugging even when the control system cannot switch to the debug mode.

Means for Solving the Problems

[0006] The electronic device according to the present invention comprises a processor that executes a program for a predetermined control system, a boot sequencer that performs startup processing of the control system on the processor, a debug circuit that collects debug information for the control system, and a non-volatile memory. When a debug request is detected and the processor is operational, the processor starts supplying power and a clock to the debug circuit, and the debug circuit performs the collection of the debug information. On the other hand, when a debug request is detected and the processor is not operational, the boot sequencer (a) saves the debug information to the non-volatile memory and then restarts the control system, and (b) after the restart, starts supplying power and a clock to the debug circuit and restores the debug information, and after the debug information is restored, the debug circuit performs the collection of the debug information. [Effects of the Invention]

[0007] According to the present invention, an electronic device is obtained that can perform effective debugging even when the control system cannot switch to debug mode.

[0008] The above or other objects, features, and advantages of the present invention will become even more apparent from the following detailed description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. [Figure 2] Figure 2 is a flowchart illustrating the operation of the electronic device shown in Figure 1. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the figures.

[0011] Figure 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. The electronic device shown in Figure 1 comprises a CPU (Central Processing Unit) 11 as a processor, signal lines 12 such as a system bus, RAM (Random Access Memory) 13, non-volatile memory 14 such as flash memory or EEPROM (Electrically Erasable Programmable Read Only Memory), and a processing module 15. For example, the CPU 11, signal lines 12, RAM 13, non-volatile memory 14, and processing module 15 are implemented using one or more semiconductor integrated circuits.

[0012] The CPU 11 executes a predetermined control system program and performs the processing described in the program, thereby controlling the processing module 15, etc. The CPU 11, RAM 13, non-volatile memory 14, and processing module 15 are connected to signal lines 12, and the CPU 11 and processing module 15 can communicate with each other via signal lines 12, and can also read and write data to the RAM 13 and non-volatile memory 14.

[0013] The processing module 15 is a hardware module having a predetermined function, which executes a predetermined process according to a command from the CPU 11, and outputs an interrupt signal to the CPU 11 as necessary.

[0014] Furthermore, the electronic device shown in Figure 1 further includes a debug circuit 16, a debug interface 17, a debug device 18, a boot sequencer 19, a power supply circuit 20, and a clock circuit 21.

[0015] The debug circuit 16 is equipped with debug input / output ports and collects debug information of the control system described above (such as values ​​of specific registers that indicate the state of the control system). The debug circuit 16 is implemented as a single functional block in the semiconductor integrated circuit and operates in synchronization with the operating clock. The semiconductor integrated circuit has power isolation for each functional block, and the debug circuit 16 (or its functional block) is implemented in the debug power hierarchy 16a, which is one of the power hierarchy levels separated for each functional block.

[0016] The debug interface 17 is a physical port used for data communication with the debug circuit 16 and is connected to the debug input / output port.

[0017] The debug device 18 is an external device that acquires debug information from the debug circuit via the debug interface 17 and performs analysis of the debug information (such as identifying the type of malfunction and the cause of the malfunction).

[0018] The boot sequencer 19 performs the control system startup process on the CPU 11.

[0019] The power supply circuit 20 individually switches power on and off for each power level of multiple functional blocks in the semiconductor integrated circuit. Specifically, the power supply circuit 20 starts and stops the power supply to the debug circuit 16. Here, the power supply circuit 20 starts and stops the power supply to the debug interface 17 and the debug device 18 (synchronized with this) along with the start and stop of the power supply to the debug circuit 16. The clock circuit 21 also switches the supply of the operating clock to the debug circuit 16 on and off.

[0020] When the CPU 11 or boot sequencer 19 detects a debug request as a predetermined event (such as a predetermined interrupt signal or a predetermined abnormal state), it attempts to collect debug information using the debug circuit 16.

[0021] Here, when the CPU 11 is operable upon detecting a debug request, the CPU 11 starts supplying power and clock to the debug circuit 16 via the power supply circuit 20 and the clock circuit 21, and the debug circuit 16 executes collection of debug information.

[0022] On the other hand, when the CPU 11 is not operable upon detecting a debug request, the boot sequencer 19: (a) saves the debug information (from registers etc.) to the non-volatile memory 14, then restarts the control system, and (b) after restart, starts supplying power and clock to the debug circuit 16 via the power supply circuit 20 and the clock circuit 21 and restores the debug information (to the original registers etc.). After restoring the debug information, the debug circuit 16 executes collection of debug information.

[0023] Thus, when a debug request occurs during operation of the control system and the CPU 11 stalls and is not operable, a restart (warm boot) of the CPU 11 (i.e., the control system) is executed.

[0024] On the other hand, during initial startup (cold boot) such as when power is turned on, the boot sequencer 19 cuts off the supply of power and clock to the debug circuit 16. Thereby, during normal operation (i.e., until a debug request occurs), power and clock are not supplied to the debug circuit 16, so power consumption can be reduced.

[0025] Next, the operation of the above electronic device will be described. FIG. 2 is a flowchart for explaining the operation of the electronic device shown in FIG. 1.

[0026] When the power of the said electronic device is turned on (step S1), the boot sequencer 19 performs initial startup of the control system and causes the CPU 11 to execute the program of the control system while stopping the power supply to the debug system (debug circuit 16, debug interface 17, and debug device 18) and the clock supply to the debug circuit 16. (step S2).

[0027] Subsequently, when a debug request occurs and is detected while the control system is operating normally (step S3), if the CPU 11 is operational (step S4), the CPU 11 (control system) starts supplying power to the debug system and the clock to the debug circuit 16 using the power supply circuit 20 and the clock circuit 21 (step S5), and the debug system performs debugging (such as collecting and analyzing debug information) according to predetermined debug specifications (step S6). Then, when debugging is complete, the CPU 11 (control system) stops supplying power to the debug system and the clock to the debug circuit 16 using the power supply circuit 20 and the clock circuit 21 (step S7).

[0028] On the other hand, if the CPU 11 is inoperable in step S4, when a debug request occurs and is detected while the control system is operating normally, the boot sequencer 19 detects the inoperability of the CPU 11 based on the type of debug request and an activity check based on communication with the CPU 11. Upon detecting the inoperability of the CPU 11, the boot sequencer 19 first reads debug information from registers and writes it to the non-volatile memory 14 (step S8), and then restarts the control system (step S9).

[0029] After the control system restarts, the boot sequencer 19 starts supplying power to the debug system and the clock to the debug circuit 16 using the power supply circuit 20 and the clock circuit 21 (step S10), reads the debug information from the non-volatile memory 14, and writes it to registers and restores it (step S11). After the debug information is restored, the debug system performs debugging according to the predetermined debug specifications (step S6). Then, when debugging is complete, the CPU 11 (control system) stops supplying power to the debug system and the clock to the debug circuit 16 using the power supply circuit 20 and the clock circuit 21 (step S7).

[0030] As described above, according to the above embodiment, the CPU 11 executes a predetermined control system program. When a debug request is detected and the CPU 11 is operational, the CPU 11 starts supplying power and clock to the debug circuit 16, and the debug circuit 16 performs the collection of debug information. On the other hand, when a debug request is detected and the CPU 11 is not operational, the boot sequencer 19 (a) saves the debug information to the non-volatile memory 14, restarts the control system, and (b) after the restart, starts supplying power and clock to the debug circuit 16 and restores the debug information. After the debug information is restored, the debug circuit 16 performs the collection of debug information.

[0031] This ensures that debugging information is saved even after the control system is restarted, allowing for effective debugging after a restart, even if the control system cannot enter debug mode.

[0032] Furthermore, various changes and modifications to the embodiments described above will be obvious to those skilled in the art. Such changes and modifications may be made without deviating from the spirit and scope of the subject matter and without diminishing the intended advantages. In other words, such changes and modifications are intended to be included in the claims. [Industrial applicability]

[0033] The present invention is applicable, for example, to electronic devices equipped with a debugging circuit. [Explanation of symbols]

[0034] 11. CPU (an example of a processor) 14 Non-volatile memory 16 Debugging Circuit 17 Debugging Interface 18 Debugging Devices 19 Boot Sequencer

Claims

1. A processor that executes a program for a predetermined control system, The aforementioned processor includes a boot sequencer that performs startup processing for the control system, A debug circuit that collects debug information of the control system, Equipped with non-volatile memory, When a debug request is detected and the processor is operational, the processor starts supplying power and clock to the debug circuit, and the debug circuit performs the collection of the debug information. If the processor is not operational when a debug request is detected, the boot sequencer (a) saves the debug information to the non-volatile memory and then restarts the control system; (b) after the restart, starts supplying power and clock to the debug circuit and restores the debug information; and after the debug information is restored, the debug circuit performs the collection of the debug information. Electronic devices characterized by the following:

2. The electronic device according to claim 1, characterized in that the boot sequencer cuts off the supply of power and clock to the debug circuit during initial startup.

3. A power supply circuit that starts and stops the power supply to the debug circuit, A debug interface for communicating with the aforementioned debug circuit, The system further comprises a debug device that acquires the debug information via the debug interface, The power supply circuit starts and stops the power supply to the debug circuit, as well as the power supply to the debug interface and the debug device. thing, The electronic device according to claim 1 or claim 2, characterized by the above.

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