Semiconductor equipment

Abstract

In semiconductor devices with small-capacity memory, the aim is to reduce the area required and lower the defect rate in the market. [Solution] Each latch cell in the latch cell array LCARY is composed of 12 MOS transistors, including a first CMOS switch for transferring write data and a second CMOS switch for transferring read data. Here, a test is assumed in which the storage node on the write bit line WBLN[i] side of each latch cell is rewritten from the first to the second logic level while the first and second CMOS switches are controlled to be ON for overlapping time. In this case, the disturb test circuit DTBR precharges the read bit line RBL[i] to the second logic level before the second CMOS switch is controlled to be ON.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and for example, to a semiconductor device having a memory.

Background Art

[0002] Non-Patent Document 1 shows a SRAM macro including a memory cell composed of 12 transistors. The memory cell is composed of a write port circuit, a latch circuit, and a read port circuit. The write port circuit is composed of a transfer gate composed of 2 transistors. The latch circuit is composed of 6 transistors including two cross-coupled CMOS inverter circuits. The read port circuit is composed of a driver circuit composed of 4 transistors.

[0003] Non-Patent Document 2 shows a SRAM macro including a memory cell composed of 16 transistors. The memory cell is composed of a write port circuit, a latch circuit, and a read port circuit. The write port circuit is composed of a driver circuit composed of 4 transistors. The latch circuit includes two cross-coupled CMOS inverter circuits and is composed of 8 transistors also corresponding to a bit write mask operation. The read port circuit is composed of a driver circuit composed of 4 transistors.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] In recent years, semiconductor devices that handle various AI (Artificial Intelligence) processing, such as image recognition, have become widespread. Such semiconductor devices require the temporary storage of processing data at various points distributed within the device. Therefore, high-speed, relatively small-capacity memory is necessary. Flip-flops and SRAM (Static Random Access Memory) are known examples of such memory.

[0006] In the case of a single-port SRAM, for example, the memory cell can be composed of six transistors. However, SRAM requires peripheral circuits including various circuits such as decoders, sense amplifiers, write assist circuits, and read assist circuits. Therefore, in SRAM, the area per bit increases as the capacity decreases, meaning that the area efficiency decreases. On the other hand, a flip-flop only requires a decoder as peripheral circuitry. However, a flip-flop is composed of two D latches, each consisting of about 20 transistors. Therefore, flip-flops have a large area per bit and are only practically applicable when the capacity is sufficiently small.

[0007] Therefore, from the perspective of improving area efficiency, there is a need for a memory that complements the gap between SRAM and flip-flops. Specifically, there is a need for a memory suitable for holding approximately 16 to 64 128-bit data points. One such memory is the D-latch macro. The D-latch macro can be composed of a memory cell consisting of 16 transistors, in other words, a latch cell, as shown in Non-Patent Document 2. Furthermore, the D-latch macro can also be configured as a two-port memory that can perform read and write operations independently.

[0008] Here, for example, if we consider a case where many small-capacity D-latch macros are arranged in a semiconductor device, further reduction in the area of ​​the D-latch macro is desirable. Reducing the number of transistors in the latch cell is beneficial for area reduction. However, in this case, especially when the D-latch macro is configured as a 2-port memory, the effects of inter-port interference become significant, and the stability of the latch cell may decrease. Inter-port interference is a phenomenon in 2-port memory where, when a read operation and a write operation occur simultaneously in the same latch cell, one operation interferes with the other.

[0009] On the other hand, manufacturing variations can occur in latch cells. Therefore, if the effects of inter-port interference become significant, unstable latch cells that may be defective in the market may be produced. Thus, it is desirable to reproduce the worst-case scenario where the effects of inter-port interference are greatest during wafer testing and detect unstable latch cells. This allows for the early removal of semiconductor devices with unstable latch cells. Alternatively, if the semiconductor device has a backup latch cell, the unstable latch cell can be salvaged. As a result, the defect rate of semiconductor devices can be reduced during final testing after wafer testing or in the market after shipment.

[0010] However, using only standard external signals to the D-latch macro sometimes made it difficult to reproduce the worst-case scenario. Alternatively, it was necessary to input and output complex test patterns using multiple cycles to reproduce the worst-case scenario. As a result, simply performing standard wafer testing using standard external signals may not be sufficient to reduce the failure rate of semiconductor devices in the market.

[0011] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0012] A semiconductor device according to one embodiment includes a pair of write selection lines, a pair of read selection lines, multiple pairs of bit write mask selection lines, and multiple latch cells connected thereto. The pair of write selection lines are activated during a write operation. The pair of read selection lines are activated during a read operation. The multiple pairs of bit write mask selection lines are activated when a high-impedance write operation is performed on any of the multiple latch cells. The semiconductor device also includes multiple read bit lines for transferring read data from the multiple latch cells and multiple write bit lines for transferring write data to the multiple latch cells. Furthermore, the semiconductor device includes multiple first test circuits connected to the multiple read bit lines. Each of the multiple latch cells includes first and second storage nodes, first, second, third, fourth, fifth, and sixth nMOS transistors, and first, second, third, fourth, fifth, and sixth pMOS transistors. The first and second storage nodes store complementary data. The first nMOS transistor is connected between the first memory node and the first intermediate node, with its gate connected to the second memory node. The second nMOS transistor is connected between the second memory node and the low-potential power supply node, with its gate connected to the first memory node. The third nMOS transistor is connected between the first intermediate node and the low-potential power supply node and is controlled by a pair of write select lines. The sixth nMOS transistor is connected between the first intermediate node and the low-potential power supply node and is controlled by a pair of bit write mask select lines. The first, second, third, and sixth pMOS transistors are provided between the high-potential power supply node and the first, second, third, and sixth nMOS transistors in the same manner as the first, second, third, and sixth nMOS transistors. The fourth nMOS transistor and the fourth pMOS transistor constitute a first CMOS switch controlled by a pair of write select lines, which, when controlled to be ON, connects a predetermined write bit line to the first memory node. The fifth nMOS transistor and the fifth pMOS transistor constitute a second CMOS switch controlled by a pair of read selection lines, which, when controlled to be ON, connect the second memory node to a predetermined read bit line.Here, a test in which the first memory node is rewritten from the first logic level to the second logic level while the first and second CMOS switches are controlled to be ON for overlapping periods is called a disturb write test. Multiple first test circuits precharge multiple read bit lines to the second logic level before the second CMOS switch is controlled to be ON when performing a disturb write test. [Effects of the Invention]

[0013] According to the above embodiment, in a semiconductor device having a small-capacity memory, it is possible to reduce the area and the defect rate in the market. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a semiconductor device according to one embodiment. [Figure 2] Figure 2 is a schematic diagram showing an example of the configuration of the main peripheral circuits in the memory shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing an example of the latch cell configuration in Figure 1. [Figure 4A] Figure 4A is a timing chart showing an example of a write operation using the latch cell shown in Figure 3. [Figure 4B] Figure 4B is a schematic diagram that provides supplementary explanation to the operation shown in Figure 4A. [Figure 5A] Figure 5A is a timing chart showing an example of a read operation using the latch cell shown in Figure 3. [Figure 5B] Figure 5B is a schematic diagram that provides supplementary explanation for the operation shown in Figure 5A. [Figure 6A] Figure 6A is a timing chart showing an example of bit write mask operation using the latch cell shown in Figure 3. [Figure 6B] Figure 6B is a schematic diagram that provides supplementary explanation to the operation shown in Figure 6A. [Figure 7]FIG. 7 is a schematic diagram showing an example of a worst state associated with port interference during a write operation in the semiconductor device shown in FIGS. 1 and 3. [Figure 8] FIG. 8 is a schematic diagram showing an example of a worst state associated with port interference during a read operation in the semiconductor device shown in FIGS. 1 and 3. [Figure 9] FIG. 9 is a circuit diagram showing a more detailed configuration example of the data input / output circuit in FIG. 2. [Figure 10] FIG. 10 is a timing chart showing an operation example of a disturb write test using the disturb test circuit shown in FIG. 9. [Figure 11] FIG. 11 is a schematic diagram for supplementarily explaining the precharge operation by the disturb test circuit in FIG. 10. [Figure 12] FIG. 12 is a timing chart showing an operation example of a disturb read test using two disturb test circuits shown in FIG. 9. [Figure 13] FIG. 13 is a schematic diagram for supplementarily explaining the precharge operation by two disturb test circuits in FIG. 12. [Figure 14] FIG. 14 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] FIG. 1� is a flowchart showing an example of the disturb write test in FIG. 14. [Figure 16] FIG. 16 is a flowchart showing an example of the disturb read test in FIG. 14. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a latch cell as a comparative example.

Embodiments of the Invention

[0015] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. However, unless otherwise specified, they are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements (including number, numerical value, quantity, range, etc.), the number is not limited to that specific number unless otherwise specified or when it is clearly limited in principle. In other words, the number of elements may be greater than or less than a specific number.

[0016] Furthermore, in the embodiments, the constituent elements (including element steps) are not necessarily essential unless specifically stated or considered fundamentally essential. Similarly, when referring to the shape, positional relationship, etc., of constituent elements, it includes those that substantially approximate or resemble their shape, etc., unless specifically stated or considered fundamentally not essential. The same applies to the numerical values ​​and ranges mentioned above.

[0017] Furthermore, in this embodiment, a MOSFET (MOS Field Effect Transistor) is referred to as a MOS transistor. A p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively. In this embodiment, for the sake of simplicity, the explanation will be given using a MOS transistor that uses an oxide film as the gate insulating film. However, the gate insulating film is not necessarily limited to an oxide film.

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings used to illustrate the embodiments, the same reference numerals are generally used for identical components, and repeated descriptions of such components will be omitted.

[0019] <Overview of Semiconductor Devices> Figure 1 is a schematic diagram showing an example configuration of a semiconductor device according to one embodiment. Figure 2 is a schematic diagram showing an example configuration of the main peripheral circuit in the memory MEM shown in Figure 1. The semiconductor device according to one embodiment includes at least a memory MEM as shown in Figure 1. The memory MEM is, for example, a D latch macro composed of hard macros. The semiconductor device includes, for example, various logic circuits that are responsible for various AI processing. In this case, the semiconductor device may have memory MEMs as shown in Figure 1 distributed and mounted in various locations within the device in order to temporarily store the processing data of the various logic circuits.

[0020] The memory MEM shown in Figure 1 is a two-port memory capable of independent read and write operations. The memory MEM comprises a latch cell array LCARY, a memory control circuit CTRL, a word driver circuit WD, and a data input / output circuit IOC. The memory control circuit CTRL, the word driver circuit WD, and the data input / output circuit IOC are peripheral circuits of the latch cell array LCARY. The latch cell array LCARY comprises "N (=n+1)*M (=m+1)" latch cells LC[0,0]-LC[n,m] arranged in a matrix. In this specification, multiple latch cells LC[0,0]-LC[n,m] are collectively referred to as latch cells LC.

[0021] The memory control circuit CTRL controls the entire memory MEM. As shown in Figure 2, the memory control circuit CTRL mainly comprises a clock generation circuit CKG and an address decoder ADEC. The clock generation circuit CKG receives various input signals from outside the memory MEM. These input signals include the clock signal CLKW and chip enable signal CENW for writing, and the clock signal CLKR and chip enable signal CENR for reading.

[0022] The clock generation circuit CKG outputs a write-decode instruction signal DECW to the address decoder ADEC based on the write clock signal CLKW and the chip enable signal CENW. In parallel, the clock generation circuit CKG outputs a write-enable signal WTEN to the data input / output circuit IOC. Furthermore, the clock generation circuit CKG outputs a read-decode instruction signal DECR to the address decoder ADEC based on the read clock signal CLKR and the chip enable signal CENR. In parallel, the clock generation circuit CKG outputs a read-enable signal RDEN to the data input / output circuit IOC.

[0023] The address decoder ADEC receives the address signal ADRW for writing from outside the memory MEM. In response to the write decode instruction signal DECW, the address decoder ADEC activates one write word line WWLN[k] based on the write address signal ADRW. This write word line WWLN[k] is one of the N write word lines WWLN[n:0] shown in Figure 1.

[0024] Similarly, the address decoder ADEC receives the address signal ADRR for reading from outside the memory MEM. In response to the read-decode instruction signal DECR, the address decoder ADEC activates one read word line RWLN[k] based on the read address signal ADRR. This read word line RWLN[k] is one of the N read word lines RWLN[n:0] shown in Figure 1.

[0025] In this case, in a two-port memory, the write address signal ADRW and the read address signal ADRR, both of which are set to the same value, may be input during overlapping time periods. In this case, the write word line WWLN[k] and the read word line RWLN[k], both directed to the same latch cell LC, may be activated during overlapping time periods.

[0026] As will be explained in more detail later, the clock generation circuit CKG also receives a test clock signal TCLK. In response to the test clock signal TCLK, the clock generation circuit CKG activates the write word line WWLN[k] and read word line RWLN[k] directed to the same latch cell LC during overlapping time periods. For example, the clock generation circuit CKG activates the write word line WWLN[k] and read word line RWLN[k] simultaneously. The write word line WWLN[k] and read word line RWLN[k] to be activated are determined, for example, by two address signals ADRW and ADRR, both having the same value.

[0027] The word driver circuit WD drives a pair, specifically N pairs, of complementary signal lines, called read selection lines RCP[n:0] and RCPN[n:0], as shown in Figure 1. The N read selection lines RCP[n:0] are the non-inverting signal lines. In this specification, these N read selection lines RCP[n:0] are collectively referred to as the non-inverting read selection lines RCP, or simply as read selection lines RCP. On the other hand, the remaining N read selection lines RCPN[n:0] are the inverting signal lines. In this specification, these N read selection lines RCPN[n:0] are collectively referred to as the inverting read selection lines RCPN, or simply as read selection lines RCPN.

[0028] Furthermore, the word driver circuit WD drives a pair, specifically N pairs, of complementary signal lines, namely the write selection lines WCP[n:0] and WCPN[n:0]. The N write selection lines WCP[n:0] are the non-inverting signal lines. In this specification, these N write selection lines WCP[n:0] are collectively referred to as the non-inverting write selection lines WCP, or simply as the write selection lines WCP. On the other hand, the remaining N write selection lines WCPN[n:0] are the inverting signal lines. In this specification, these N write selection lines WCPN[n:0] are collectively referred to as the inverting write selection lines WCPN, or simply as the write selection lines WCPN.

[0029] As shown in Figure 2, the word driver circuit WD receives the signal from each read word line RWLN[k] and drives each inverted read selection line RCPN[k]. The word driver circuit WD also drives each non-inverted read selection line RCP[k] by inverting the signal from each read word line RWLN[k]. Similarly, the word driver circuit WD receives the signal from each write word line WWLN[k] and drives each inverted write selection line WCPN[k]. The word driver circuit WD also drives each non-inverted write selection line WCP[k] by inverting the signal from each write word line WWLN[k].

[0030] The data input / output circuit (IOC) controls the input and output of data to and from the memory (MEM) and its external environment. Specifically, the data input / output circuit (IOC) primarily comprises a write latch circuit (DLT) and a write driver (WDV) as its write circuit. The data input / output circuit (IOC) also primarily comprises a read switch (RSW) and a read latch circuit (QLT) as its read circuit.

[0031] Furthermore, the data input / output circuit (IOC), as detailed below, includes two disturb test circuits, DTBR and DTBW. These two disturb test circuits, DTBR and DTBW, are used to perform disturb tests to detect unstable latch cells LC that are susceptible to inter-port interference. The DTBR disturb test circuit is enabled / disabled based on an external test mode signal TMR. Similarly, the DTBW disturb test circuit is enabled / disabled based on an external test mode signal TMW.

[0032] During a write operation, the data input / output circuit IOC receives M bits of external input data D[m:0] from outside the memory MEM, as shown in Figure 1. The write latch circuit DLT latches the M bits of external input data D[m:0] as write data in accordance with the write enable signal WTEN. The write driver WDV transfers the latched M bits of write data to the latch cell array LCARY via M inverted write bit lines WBLN[m:0].

[0033] The M bits of write data transferred from the write driver WDV are written to M latch cells LC connected to the activated write selection line WCP. In this specification, the inverted write bit lines WBLN[m:0] of these M lines are collectively referred to as the inverted write bit lines WBLN, or simply the write bit lines WBLN.

[0034] On the other hand, during a read operation, the data input / output circuit IOC receives the read data from M latch cells LC via M non-inverting read bit lines RBL[m:0]. These M latch cells LC are cells connected to the activated read selection line RCP. In this specification, these M non-inverting read bit lines RBL[m:0] are collectively referred to as non-inverting read bit lines RBL, or simply read bit lines RBL.

[0035] The read latch circuit QLT receives and latches read data from M latch cells LC via the read switch RSW in response to the read enable signal RDEN. In other words, unlike a typical SRAM, the read latch circuit QLT receives and latches read data without going through a sense amplifier. The read latch circuit QLT then outputs the M-bit read data to the outside as M-bit external output data Q[m:0].

[0036] Furthermore, as shown in Figure 1, the data input / output circuit IOC also receives an M-bit bit write mask signal BWM[m:0] from outside the memory MEM. The bit write mask signal BWM[m:0] is used to mask some bits of the M-bit external input data D[m:0] during the write operation. This eliminates the need for, for example, read-modify-write operations.

[0037] During bit write mask operation, the write driver WDV shown in Figure 2 outputs a high impedance to the write bit line WBLN[k] of the bit to be masked. As a result, the latch cell LC connected to the write bit line WBLN[k] can maintain the data it currently stores regardless of the write operation.

[0038] Furthermore, during bit write mask operation, the data input / output circuit IOC drives a pair of complementary signal lines, specifically M pairs of bit write mask selection lines BW[m:0] and BWB[m:0]. As will be described in detail later, by driving these selection lines, the latch cell LC can maintain the data it currently stores. In this specification, the M inverted bit write mask selection lines BWB[m:0] are collectively referred to as the inverted bit write mask selection line BWB, or simply the bit write mask selection line BWB. Similarly, the M non-inverted bit write mask selection lines BW[m:0] are collectively referred to as the non-inverted bit write mask selection line BW, or simply the bit write mask selection line BW.

[0039] In Figure 1, the value of M (=m+1), which represents the bit width, is, for example, 128, 256, 512, or 1024. The value of N (=n+1), which represents the word line count, is, for example, 16, 32, or 64. Generally, within this range of memory capacity, the D-latch macro can be advantageous compared to flip-flops and SRAM in terms of area efficiency. The D-latch macro can also be described as a macro whose area ratio between data storage area and peripheral circuit area is intermediate between that of flip-flops and SRAM.

[0040] For example, SRAM may include a number of sense amplifiers and various assist circuits within its data input / output circuit (IOC) corresponding to the bit width. Therefore, as the bit width increases, the area ratio of the data input / output circuit (IOC) increases. On the other hand, D-latch macros do not require such sense amplifiers or assist circuits. Consequently, the area ratio of the data input / output circuit (IOC) does not increase significantly even as the bit width increases. As a result, D-latch macros can improve area efficiency even with larger bit widths.

[0041] <Configuration of a latch cell (embodiment)> Figure 3 is a circuit diagram showing an example configuration of the latch cell LC in Figure 1. The latch cell LC shown in Figure 3 comprises a write port circuit WTC, a latch circuit LT, and a read port circuit RDC. The latch cell LC also includes an inverting storage node (first storage node) SNb and a non-inverting storage node (second storage node) SNt that store complementary data.

[0042] The latch circuit LT comprises four nMOS transistors MN1-MN3, MN6 and four pMOS transistors MP1-MP3, MP6. The pMOS transistor (first pMOS transistor) MP1 and the nMOS transistor (first nMOS transistor) MN1 constitute a first inverter circuit. This first inverter circuit performs signal inversion using the non-inverting memory node SNt and the inverting memory node SNb as input and output.

[0043] The pMOS transistor (second pMOS transistor) MP2 and the nMOS transistor (second nMOS transistor) MN2 constitute a second inverter circuit. This second inverter circuit performs signal inversion using the inverting memory node SNb and the non-inverting memory node SNt as input and output.

[0044] The pMOS transistor (third pMOS transistor) MP3 is connected between the first inverter circuit and the high-potential power supply node Nvd. The nMOS transistor (third nMOS transistor) MN3 is connected between the first inverter circuit and the low-potential power supply node Nvs. The high-potential power supply node Nvd is supplied with the high-potential power supply voltage VDD. The low-potential power supply node Nvs is supplied with the low-potential power supply voltage VSS.

[0045] Furthermore, the pMOS transistor (the sixth pMOS transistor) MP6 is connected in parallel with the pMOS transistor MP3. The nMOS transistor (the sixth nMOS transistor) MN6 is connected in parallel with the nMOS transistor MN3. As will be explained in detail later, the pMOS transistor MP6 and the nMOS transistor MN6 are provided to implement the bit write mask function. Therefore, the pMOS transistor MP6 and the nMOS transistor MN6 can be omitted if the bit write mask function is not required.

[0046] The write port circuit (WTC) consists of a pMOS transistor (the fourth pMOS transistor) MP4 and an nMOS transistor (the fourth nMOS transistor) MN4. The pMOS transistor MP4 and the nMOS transistor MN4 constitute a CMOS (Complementary MOS) switch (the first CMOS switch) CSW1, in other words, a transfer gate. When controlled to be ON, the CMOS switch CSW1 transfers the write data to the inverting memory node SNb.

[0047] On the other hand, the read port circuit RDC consists of a pMOS transistor (the fifth pMOS transistor) MP5 and an nMOS transistor (the fifth nMOS transistor) MN5. The pMOS transistor MP5 and the nMOS transistor MN5 constitute a CMOS switch (the second CMOS switch) CSW2, in other words, a transfer gate. When controlled to be ON, the CMOS switch CSW2 transfers read data from the non-inverting memory node SNt.

[0048] Here, the latch cell LC shown in Figure 3 is connected, more specifically, to eight signal lines (WCP, WCPN, RCP, RCPN, BW, BWB, WBLN, RBL) as described in Figures 1 and 2. A pair of write selection lines WCP and WCPN are activated during write operations. A pair of read selection lines RCP and RCPN are activated during read operations. The read bit line RBL transfers read data from the latch cell LC. The write bit line WBLN transfers write data to the latch cell LC.

[0049] The pair of bit write mask selection lines BW and BWB are activated when performing a bit write mask operation. Specifically, the pair of bit write mask selection lines BW and BWB are activated when performing a high-impedance write operation on any of the multiple latch cells LC. In other words, these signal lines are activated to maintain data stored in any of the multiple latch cells regardless of the write operation.

[0050] The nMOS transistor (first nMOS transistor) MN1 is connected between the inverting memory node SNb and the intermediate node (first intermediate node) ND1. The gate of nMOS transistor MN1 is connected to the non-inverting memory node SNt. The nMOS transistor (second nMOS transistor) MN2 is connected between the non-inverting memory node SNt and the low-potential power supply node Nvs. The gate of nMOS transistor MN2 is connected to the inverting memory node SNb. The nMOS transistor (third nMOS transistor) MN3 is connected between the intermediate node ND1 and the low-potential power supply node Nvs. The gate of nMOS transistor MN3 is connected to the inverting write selection line WCPN.

[0051] The first pMOS transistor MP1 is connected between the inverting memory node SNb and the intermediate node (second intermediate node) ND2. The gate of pMOS transistor MP1 is connected to the non-inverting memory node SNt. The second pMOS transistor MP2 is connected between the non-inverting memory node SNt and the high-potential power supply node Nvd. The gate of pMOS transistor MP2 is connected to the inverting memory node SNb. The third pMOS transistor MP3 is connected between the intermediate node ND2 and the high-potential power supply node Nvd. The gate of pMOS transistor MP3 is connected to the non-inverting write selection line WCP.

[0052] The nMOS transistor (fourth nMOS transistor) MN4 and the pMOS transistor (fourth pMOS transistor) MP4 are connected in parallel between the write bit line WBLN and the inverting memory node SNb. The gate of the nMOS transistor MN4 is connected to the non-inverting write selection line WCP. The gate of the pMOS transistor MP4 is connected to the inverting write selection line WCPN. Thus, the CMOS switch CSW1 is controlled by the pair of write selection lines WCP,WCPN.

[0053] The nMOS transistor (the fifth nMOS transistor) MN5 and the pMOS transistor (the fifth pMOS transistor) MP5 are connected in parallel between the read bit line RBL and the non-inverting memory node SNt. The gate of the nMOS transistor MN5 is connected to the non-inverting read selection line RCP. The gate of the pMOS transistor MP5 is connected to the inverting read selection line RCPN. Thus, the CMOS switch CSW2 is controlled by the pair of read selection lines RCP,RCPN.

[0054] The nMOS transistor (the sixth nMOS transistor) MN6 is connected between the intermediate node ND1 and the low-potential power supply node Nvs. The gate of nMOS transistor MN6 is connected to the non-inverting bit write mask selection line BW. The pMOS transistor (the sixth pMOS transistor) MP6 is connected between the intermediate node ND2 and the high-potential power supply node Nvd. The gate of pMOS transistor MP6 is connected to the inverting bit write mask selection line BWB. Thus, nMOS transistor MN6 and pMOS transistor MP6 are controlled by a pair of bit write mask selection lines BW,BWB.

[0055] <Operation of a latch cell> [Writing operation] Figure 4A is a timing chart showing an example of a write operation using the latch cell LC shown in Figure 3. Figure 4B is a schematic diagram to supplement the operation shown in Figure 4A. Figure 4B shows the state of each signal line and the on / off state of each transistor in the latch cell LC during the write period. In Figure 4A, the write period Twt is the period from time t1 to time t2, which is one period of the write clock signal CLKW.

[0056] During the write period Twt, the read selection line RCP is inactive, in this case at the "L" level. Therefore, the pMOS transistor MP5 and nMOS transistor MN5 are in the off state. Also, the read bit line RBL holds either the "H" level or the "L" level based on the previous read data.

[0057] Meanwhile, the write selection line WCP transitions from an inactive state to an active state, specifically from the "L" level to the "H" level. Consequently, pMOS transistor MP4 and nMOS transistor MN4 switch from the off state to the on state. Also, pMOS transistor MP3 and nMOS transistor MN3 switch from the on state to the off state. Since no bit write mask operation is performed here, the bit write mask selection line BW transitions from an active state to an inactive state, specifically from the "H" level to the "L" level. Consequently, pMOS transistor MP6 and nMOS transistor MN6 switch from the on state to the off state.

[0058] In this state, let's consider a case where the inverted memory node SNb is rewritten from the "L" level to the "H" level. The write bit line, specifically the inverted write bit line WBLN, is at the "H" level at time t1. The ON state pMOS transistor MP4 and nMOS transistor MN4 transfer this "H" level to the "L" level memory node SNb.

[0059] In this process, the write bit line WBLN is driven by the write driver WDV shown in Figure 2. Meanwhile, the power supply voltage VSS to the nMOS transistor MN1 is cut off. As a result, the inverting memory node SNb can be rewritten to the "H" level. Furthermore, by inputting this "H" level, the nMOS transistor MN2 can rewrite the non-inverting memory node SNt from the "H" level to the "L" level.

[0060] Subsequently, the write selection line WCP transitions from the active state to the inactive state. The bit write mask selection line BW transitions from the inactive state to the active state. Consequently, the pMOS transistor MP4 and the nMOS transistor MN4 switch from the on state to the off state. The two pMOS transistors MP3 and MP6 and the two nMOS transistors MN3 and MN6 switch from the off state to the on state. This completes the write operation.

[0061] [Read operation] Figure 5A is a timing chart showing an example of read operation using the latch cell LC shown in Figure 3. Figure 5B is a schematic diagram to supplement the operation shown in Figure 5A. Figure 5B shows the state of each signal line in the latch cell LC and the on / off state of each transistor during the read period. In Figure 5A, the read period Trd is the period from time t3 to time t4, which is one period of the read clock signal CLKR.

[0062] During the read period Trd, the write selection line WCP is inactive, in this case at the "L" level. Therefore, pMOS transistor MP4 and nMOS transistor MN4 are in the off state. pMOS transistor MP3 and nMOS transistor MN3 are in the on state. Also, the bit write mask selection line BW is active, in this case at the "H" level. Therefore, pMOS transistor MP6 and nMOS transistor MN6 are in the on state. On the other hand, the read selection line RCP transitions from inactive to active, in this case from the "L" level to the "H" level. Consequently, pMOS transistor MP5 and nMOS transistor MN5 switch from the off state to the on state.

[0063] In this state, consider, for example, the case where the non-inverting storage node SNt, which is storing an "L" level, is read. The read bit line RBL is at either an "H" or "L" level at time t3. The ON state pMOS transistor MP5 and nMOS transistor MN5 connect the non-inverting storage node SNt to the read bit line RBL, which is holding either an "H" or "L" level. At this time, the voltage level of the non-inverting storage node SNt may temporarily rise if the read bit line RBL is already holding an "H" level. Accordingly, the voltage level of the inverting storage node SNb may also temporarily drop slightly from the "H" level.

[0064] Subsequently, the read selection line RCP transitions from the active state to the inactive state at a predetermined time when the read data on the read bit line RBL, in this case at the "L" level, is determined. Accordingly, the pMOS transistor MP5 and the nMOS transistor MN5 switch from the on state to the off state. This completes the read operation.

[0065] [Bitlight mask operation] Figure 6A is a timing chart showing an example of bit write mask operation using the latch cell LC shown in Figure 3. Figure 6B is a schematic diagram to supplement the operation shown in Figure 6A. Figure 6B shows the state of each signal line and the on / off state of each transistor in the latch cell LC during the bit write mask period. In Figure 6A, the bit write mask period Tbwm is the period from time t5 to time t6, which is one period of the clock signal CLKW for writing.

[0066] The state of the bit write mask selection line BW differs between the bit write mask period Tbwm and the write period Twt shown in Figure 4A. Specifically, during the bit write mask period Tbwm, the bit write mask selection line BW is in the active state, in this case at the "H" level. Consequently, the pMOS transistor MP6 and the nMOS transistor MN6 are in the ON state. As a result, the inverting memory node SNb is driven by either the high-potential power supply voltage VDD or the low-potential power supply voltage VSS, unlike in the case of Figure 4A.

[0067] In this state, let's assume, for example, that the inverting memory node SNb is storing an "L" level. As described in Figures 1 and 2, the write bit line WBLN is high impedance during the bit write mask period Tbwm. That is, the voltage level of the write bit line WBLN is undefined. The ON state pMOS transistor MP4 and nMOS transistor MN4 connect the write bit line WBLN, which has an undefined voltage level, to the inverting memory node SNb.

[0068] In this case, if the write bit line WBLN maintains an "H" level, the voltage level of the inverting memory node SNb may temporarily rise slightly from the "L" level. Accordingly, the voltage level of the non-inverting memory node SNt may also temporarily drop slightly from the "H" level. However, since each memory node SNb and SNt is driven by the high-potential power supply voltage VDD or the low-potential power supply voltage VSS, their original voltage levels can be maintained. As a result, the inverting memory node SNb can maintain an "L" level regardless of the write operation.

[0069] This section describes the case where write and read operations do not overlap within the same latch cell LC. However, in a two-port memory, write and read operations may overlap within the same latch cell LC. In this case, the priority given to either the write or read operation is determined by the specifications or settings. It is desirable that the latch cell LC be able to handle both priority situations.

[0070] For example, if write operation is prioritized, the read selection line RCP is also activated in Figures 4A and 4B. Accordingly, the pMOS transistor MP5 and nMOS transistor MN5 are also controlled to be ON. In this state, it is necessary to ensure that the correct write data can be written to the inverting memory node SNb.

[0071] On the other hand, when read operations are prioritized, the write selection line WCP is also activated in Figures 5A and 5B. Accordingly, the pMOS transistor MP4 and nMOS transistor MN4 are also controlled to be ON. At this time, the write bit line WBLN becomes high impedance due to the activation of the bit write mask selection line BW, as indicated by the write driver WDV shown in Figure 2. In this state, it is necessary to ensure that the correct read data can be read from the non-inverting memory node SNt.

[0072] <Regarding the memory used as a comparative example> Figure 17 is a circuit diagram showing an example configuration of a comparative latch cell LCx. The comparative latch cell LCx differs from the configuration example shown in Figure 3 in the configuration of the write port circuit WTC and the read port circuit RDC. The write port circuit WTC shown in Figure 17 consists of a driver circuit consisting of two pMOS transistors MP7 and MP8 and two nMOS transistors MN7 and MN8. The read port circuit RDC consists of a driver circuit consisting of a pMOS transistor MP9 and an nMOS transistor MN9, and a transfer gate. The transfer gate consists of a pMOS transistor MP5 and an nMOS transistor MN5, as in the case of Figure 3.

[0073] As shown above, the comparative example latch cell LCx is composed of a total of 16 transistors. On the other hand, the latch cell LC shown in Figure 3 is composed of a total of 12 transistors. As a result, area reduction can be achieved in semiconductor devices with small memory capacity. More specifically, area reduction of the semiconductor device can be achieved by using the D latch macro itself. In addition, by reducing the number of transistors in the latch cell LC, the area of ​​the D latch macro itself can be reduced, further reducing the area of ​​the semiconductor device. In particular, even when D latch macros are distributed throughout the semiconductor device, the increase in area can be suppressed.

[0074] However, as shown in Figure 3, if the write port circuit WTC and the read port circuit RDC are each composed only of transfer gates, the latch cell LC becomes susceptible to inter-port interference. Inter-port interference, as mentioned above, is a phenomenon in which one operation interferes with the other when a read operation and a write operation occur simultaneously in the same latch cell LC. Specifically, it is a phenomenon in which the write bit line WBLN and the read bit line RBL interfere with each other via the latch circuit LT.

[0075] For example, in the configuration shown in Figure 17, the write bit line WBLN and the latch circuit LT are separated by the driver circuit within the write port circuit WTC. Similarly, the read bit line RBL and the latch circuit LT are separated by the driver circuit within the read port circuit RDC. This reduces the impact of inter-port interference. On the other hand, if, for the sake of saving space, the write port circuit WTC and the read port circuit RDC are each composed only of transfer gates, as shown in Figure 3, the impact of inter-port interference becomes larger.

[0076] When the effects of inter-port interference become significant, unstable latch cells that may be defective in the market may occur depending on manufacturing variations in the latch cell LC. For this reason, it is desirable to perform a disturb test in wafer testing to reproduce the worst-case scenario in which the effects of inter-port interference are greatest. It is desirable to detect unstable latch cell LCs through this process and either remove semiconductor devices containing unstable latch cell LCs or replace them with replacement latch cell LCs.

[0077] In this worst-case scenario, the write bit line WBLN and read bit line RBL each retain the previous write and read data through parasitic capacitance. The worst-case scenario is reproduced based on a combination of factors, such as the logic level of the retained data and the logic level of the stored data in the latch circuit LT. Therefore, reproducing the worst-case scenario is not easy.

[0078] In other words, it was sometimes difficult to reproduce the worst-case scenario using only the normal external input signals to the D-latch macro, as shown in Figures 1 and 2. Alternatively, it was necessary to input and output complex test patterns using multiple cycles to reproduce the worst-case scenario. If the worst-case scenario cannot be reproduced, the failure rate of semiconductor devices may increase during final testing after wafer testing or in the market after shipment.

[0079] <About Disturb Tests> Figure 7 is a schematic diagram illustrating an example of a worst-case scenario resulting from inter-port interference during a write operation in the semiconductor device shown in Figures 1 and 3. Figure 7 shows the on / off states of each transistor in the latch cell LC shown in Figure 3, and the worst-case scenario for each signal line that maximizes inter-port interference. This worst-case scenario can occur in a two-port memory when the write operation is prioritized, as described above.

[0080] In Figure 7, the CMOS switch CSW2 is further controlled to be ON for each transistor's ON / OFF state as shown in Figure 4B. The inverting memory node SNb and the non-inverting memory node SNt pre-store the "H" level and "L" level, respectively. The read bit line RBL also holds the "L" level due to parasitic capacitance following the previous read operation. Now, let's consider the case where the inverting memory node SNb is rewritten from the "H" level to the "L" level via the CMOS switch CSW1.

[0081] In this case, the non-inverting memory node SNt is connected to the read bit line RBL, which maintains an "L" level, via the CMOS switch CSW2. Therefore, the non-inverting memory node SNt tends to maintain an "L" level. Consequently, the inverting memory node SNb tends to maintain an "H" level. As a result, an unstable latch cell LC may be created that cannot be rewritten to an "L" level for the inverting memory node SNb. The same problem can occur when rewriting the inverting memory node SNb from an "L" level to an "H" level by swapping the logic levels of each signal.

[0082] The disturb write test is a test that reproduces such a worst-case scenario and detects unstable latch cells LC that cannot successfully rewrite the inverting memory node SNb. In other words, the disturb write test is a test in which the inverting memory node SNb is rewritten from the first logic level to the second logic level, which is its inverse phase, while two CMOS switches CSW1 and CSW2 are controlled to be ON for overlapping time. Furthermore, as a prerequisite, the disturb write test is a test in which the read bit line RBL is precharged to the second logic level before the CMOS switch CSW2 is controlled to be ON.

[0083] Figure 8 is a schematic diagram illustrating an example of a worst-case scenario resulting from inter-port interference during read operations in the semiconductor device shown in Figures 1 and 3. Figure 8 shows the on / off states of each transistor in the latch cell LC shown in Figure 3, and the worst-case scenario for each signal line that maximizes inter-port interference. This worst-case scenario can occur in a two-port memory when read operations are prioritized, as described above.

[0084] In Figure 8, the CMOS switch CSW1 is controlled to be ON in addition to the ON / OFF state of each transistor shown in Figure 5B. The inverting memory node SNb and the non-inverting memory node SNt pre-store the "H" level and "L" level, respectively. The read bit line RBL also holds the "H" level due to parasitic capacitance from the previous read operation. Furthermore, the write bit line WBLN also holds the "L" level due to parasitic capacitance from the previous write operation. In this state, we consider the case where the "L" level is read from the non-inverting memory node SNt via the CMOS switch CSW2.

[0085] In this process, the inverting memory node SNb is connected to the write bit line WBLN, which is holding an "L" level, via the CMOS switch CSW1. Therefore, the inverting memory node SNb is prone to transitioning from an "H" level to an "L" level. Consequently, the non-inverting memory node SNt is prone to transitioning from an "L" level to an "H" level.

[0086] Furthermore, the non-inverting memory node SNt is connected to the read bit line RBL, which holds an "H" level, via the CMOS switch CSW2. Therefore, the non-inverting memory node SNt is more prone to transitioning from an "L" level to an "H" level. As a result, an unstable latch cell LC may be created that cannot read an "L" level from the non-inverting memory node SNt. Note that a similar problem can occur when reading an "H" level from the non-inverting memory node SNt by swapping the logic levels of each signal.

[0087] The disturb read test reproduces this worst-case scenario and detects unstable latch cells LC that cannot perform normal readouts from the non-inverting memory node SNt. Specifically, the disturb read test involves controlling two CMOS switches CSW1 and CSW2 to be ON for overlapping periods while the inverting memory node SNb is storing the first logic level. The disturb read test then reads a second logic level, which is in the opposite phase to the first logic level, from the non-inverting memory node SNt via the CMOS switch CSW2.

[0088] Furthermore, as a prerequisite, the disturb read test is a test in which the read bit line RBL is precharged to a first logic level before the CMOS switch CSW2 is controlled to turn ON. In addition to this, the disturb read test is a test in which the write bit line WBLN is precharged to a second logic level before the CMOS switch CSW1 is controlled to turn ON.

[0089] As mentioned above, such disturb write and disturb read tests can be difficult to reproduce using only the normal external input signals to the D latch macro. Therefore, the data input / output circuit IOC shown in Figure 2 is equipped with two disturb test circuits DTBR and DTBW. The two disturb test circuits DTBR and DTBW precharge the read bit line RBL[i] or the write bit line WBLN[i] to a predetermined logic level.

[0090] <Details of the data input / output circuit> Figure 9 is a circuit diagram showing a more detailed configuration example of the data input / output circuit IOC in Figure 2. The data input / output circuit IOC shown in Figure 9 comprises a write circuit WCT and a read circuit RCT. The write circuit WCT comprises the write latch circuit DLT, write driver WDV, and disturb test circuit DTBW shown in Figure 2. In addition, the write circuit WCT comprises a disturb data setting circuit DTBD, bit write mask latch circuit BWMLT, and NOR gate NR.

[0091] On the other hand, the readout circuit RCT, as in Figure 2, includes a readout latch circuit QLT, a readout switch RSW, and a disturb test circuit DTBR. First, we will describe the circuit excluding the disturb data setting circuit DTBD and the two disturb test circuits DTBW and DTBR.

[0092] In the write circuit WCT, the write latch circuit DLT latches the external input data D[i] as write data in accordance with the write enable signal WTEN, as shown in Figure 2. The write driver WDV drives the write bit line WBLN[i] based on the latched write data.

[0093] The bit write mask latch circuit BWMLT latches an external bit write mask signal BWM[i] in accordance with the write enable signal WTEN. The bit write mask latch circuit BWMLT then outputs a bit write mask enable signal BWE, which is the result of the latch. For example, if the bit write mask signal BWM[i] is at the "H" level, i.e., the assert level, then the bit write mask enable signal BWE will also be at the "H" level.

[0094] Here, the write driver WDV is a tristate circuit controlled by the bit write mask enable signal BWE. When the bit write mask enable signal BWE is at the "H" level, the write driver WDV outputs a high impedance to the write bit line WBLN[i]. On the other hand, when the bit write mask enable signal BWE is at the "L" level, the write driver WDV drives the write bit line WBLN[i] in reverse phase based on the write data from the write latch circuit DLT.

[0095] The NOR gate NR takes the inverted write enable signal WTENB (the inverted signal of the write enable signal WTEN) and the bit write mask enable signal BWE as inputs and performs a NOR operation. The NOR gate NR then outputs the signal obtained by the NOR operation to the inverted bit write mask selection line BWB[i]. The NOR gate NR also outputs the signal obtained by the NOR operation to the non-inverted bit write mask selection line BW[i] via an inverter circuit.

[0096] For example, when the write enable signal WTEN is at the "L" level, i.e., in non-write operation, the non-inverting bit write mask selection line BW[i] is fixed at the "H" level. On the other hand, when the write enable signal WTEN is at the "H" level, the logic level of the non-inverting bit write mask selection line BW[i] is controlled based on the bit write mask enable signal BWE. That is, the logic level of the non-inverting bit write mask selection line BW[i] is controlled to the "H" / "L" level depending on whether the bit write mask enable signal BWE is at the "H" / "L" level, respectively.

[0097] In the read circuit RCT, the read latch circuit QLT receives the read data from the read bit line RBL[i] via the read switch RSW, as shown in Figure 2. The read latch circuit QLT latches the input read data according to the read enable signal RDEN. The read latch circuit QLT then outputs the latched read data to the outside as external output data Q[i].

[0098] The read switch RSW is, for example, composed of a CMOS switch. The read switch RSW is controlled by the read enable signal RDEN and its inverted signal, the inverted read enable signal RDENB. When the read enable signal RDEN is at the "H" level, i.e., the assert level, the read switch RSW connects the read bit line RBL[i] to the read latch circuit QLT.

[0099] <Details of the Disturb Test Circuit> The disturb test circuit (first test circuit) DTBR is connected to the read bit line RBL[i]. On the other hand, the disturb test circuit (second test circuit) DTBW is connected to the write bit line WBLN[i]. The disturb test circuit DTBR is used both when performing the disturb write test described in Figure 7 and when performing the disturb read test described in Figure 8. On the other hand, the disturb test circuit DTBW is used when performing the disturb read test.

[0100] The disturb test circuit DTBR precharges the read bit line RBL[i] to a second logic level before the CMOS switch CSW2 is controlled to turn ON during a disturb write test. In the example shown in Figure 7, the second logic level is the "L" level. The disturb test circuit DTBR also precharges the read bit line RBL[i] to a first logic level before the CMOS switch CSW2 is controlled to turn ON during a disturb read test. In the example shown in Figure 8, the first logic level is the "H" level.

[0101] Here, the disturb test circuit DTBR utilizes external input data D[i] to determine the second or first logic level. The same applies to the disturb test circuit DTBW, although details will be described later. Therefore, the disturb data setting circuit DTBD generates positive-phase input data DT[i], which is in phase with the external input data D[i], and negative-phase input data DN[i], which is in opposite phase. This allows for flexible use of the external input data D[i].

[0102] The disturb test circuit DTBR comprises, in detail, a charge / discharge circuit (first charge / discharge circuit) CDC1 and a test mode switch (first test mode switch) TSW1. The charge / discharge circuit CDC1 charges or discharges the read bit line RBL[i] based on the positive-sequence input data DT[i], and consequently the external input data D[i], during the negate period of the read enable signal RDEN. During the negate period of the read enable signal RDEN, the CMOS switch CSW2 is controlled to be off.

[0103] The test mode switch TSW1 connects the charge / discharge circuit CDC1 to the read bit line RBL[i] during the assertion period of the test mode signal TMR. The test mode signal TMR maintains its assertion level during the period in which the disturb write test is being performed. Furthermore, the test mode signal TMR also maintains its assertion level during the period in which the disturb read test is being performed. The test mode switch TSW1 is composed of, for example, a CMOS switch. In this case, the on / off state of the test mode switch TSW1 is controlled by the test mode signal TMR and its inverted signal, the inverted test mode signal TMRN.

[0104] The charge / discharge circuit CDC1 comprises, more specifically, two test pMOS transistors MPt1 and MPt2, and two test nMOS transistors MNt1 and MNt2. The two test pMOS transistors MPt1 and MPt2 are connected in series between the high-potential power node Nvd and the read bit line RBL[i] via a test mode switch TSW1. The two test nMOS transistors MNt1 and MNt2 are connected in series between the low-potential power node Nvs and the read bit line RBL[i] via a test mode switch TSW1.

[0105] The on / off states of the test pMOS transistor (first test pMOS transistor) MPt1 and the test nMOS transistor (first test nMOS transistor) MNt1 are complementaryly controlled based on the positive-sequence input data DT[i]. On the other hand, the on / off state of the test pMOS transistor (second test pMOS transistor) MPt2 is controlled by the read enable signal RDEN. The on / off state of the test nMOS transistor (second test nMOS transistor) MNt2 is controlled by the inverted read enable signal RDENB.

[0106] As a result, the test pMOS transistor MPt2 and the test nMOS transistor MNt2 are controlled to be ON during the negate period of the read enable signal RDEN, and consequently during the OFF period of the CMOS switch CSW2. Accordingly, the disturb test circuit DTBR precharges the read bit line RBL[i] to the high-potential power supply voltage VDD or the low-potential power supply voltage VSS during the OFF period of the CMOS switch CSW2. On the other hand, the disturb test circuit DTBR outputs a high E-pin dance to the read bit line RBL[i] during the assert period of the read enable signal RDEN, and consequently during the ON period of the CMOS switch CSW2.

[0107] The disturb test circuit DTBW precharges the write bit line WBLN[i] to a second logic level before the CMOS switch CSW1 is controlled to turn ON during a disturb read test. In the example shown in Figure 8, the second logic level is the "L" level. Similar to the disturb test circuit DTBR, the disturb test circuit DTBW determines the second logic level using the external input data D[i].

[0108] The disturb test circuit DTBW comprises, in detail, a charge / discharge circuit (second charge / discharge circuit) CDC2 and a test mode switch (second test mode switch) TSW2. The charge / discharge circuit CDC2 charges or discharges the write bit line WBLN[i] based on the inverse phase input data DN[i], and thus the external input data D[i], during the negate period of the write enable signal WTEN. That is, when the external input data D[i] is input to the charge / discharge circuit CDC1, the charge / discharge circuit CDC2 is configured to receive the data with the inverse phase. During the negate period of the write enable signal WTEN, the CMOS switch CSW1 is controlled to be off.

[0109] The test mode switch TSW2 connects the charge / discharge circuit CDC2 to the write bit line WBLN[i] during the assertion period of the test mode signal TMW. The test mode signal TMW maintains its assertion level during the period in which the disturb read test is being performed. The test mode switch TSW2 is, for example, a CMOS switch. In this case, the on / off state of the test mode switch TSW2 is controlled by the test mode signal TMW and its inverted signal, the inverted test mode signal TMWN.

[0110] The charge / discharge circuit CDC2 comprises, more specifically, two test pMOS transistors MPt3 and MPt4, and two test nMOS transistors MNt3 and MNt4. The two test pMOS transistors MPt3 and MPt4 are connected in series between the high-potential power node Nvd and the write bit line WBLN[i] via the test mode switch TSW2. The two test nMOS transistors MNt3 and MNt4 are connected in series between the low-potential power node Nvs and the write bit line WBLN[i] via the test mode switch TSW2.

[0111] The on / off states of the test pMOS transistor (third test pMOS transistor) MPt3 and the test nMOS transistor (third test nMOS transistor) MNt3 are complementaryly controlled based on the inverse-phase input data DN[i]. On the other hand, the on / off state of the test pMOS transistor (fourth test pMOS transistor) MPt4 is controlled by the write enable signal WTEN. The on / off state of the test nMOS transistor (fourth test nMOS transistor) MNt4 is controlled by the inverted write enable signal WTENB. The inverted write enable signal WTENB is the inverse of the write enable signal WTEN.

[0112] As a result, the test pMOS transistor MPt4 and the test nMOS transistor MNt4 are controlled to be ON during the negate period of the write enable signal WTEN, and consequently during the OFF period of the CMOS switch CSW1. Accordingly, the disturb test circuit DTBW precharges the write bit line WBLN[i] to the high-potential power supply voltage VDD or the low-potential power supply voltage VSS during the OFF period of the CMOS switch CSW1. On the other hand, the disturb test circuit DTBW outputs a high E-pin dance to the write bit line WBLN[i] during the assert period of the write enable signal WTEN, and consequently during the ON period of the CMOS switch CSW1.

[0113] Thus, the two disturb test circuits DTBW and DTBR precharge the write bit line WBLN[i] and the read bit line RBL[i] during the off period of the CMOS switches CSW1 and CSW2. For this reason, particularly high-speed response is not required for the two disturb test circuits DTBW and DTBR. As a result, each MOS transistor can be made in a relatively small size, and the area overhead caused by providing the two disturb test circuits DTBW and DTBR can also be suppressed.

[0114] <Details of the Disturb Write Test> Figure 10 is a timing chart showing an example of the operation of a disturb write test using the disturb test circuit DTBR shown in Figure 9. Figure 11 is a schematic diagram to supplement the explanation of the precharge operation by the disturb test circuit DTBR in Figure 10. In Figure 10, the disturb write test described in Figure 7 is performed. Figure 11 shows the on / off state of each transistor and the state of each signal line in the data input / output circuit IOC shown in Figure 9 during the precharge period TpR shown in Figure 10.

[0115] In Figure 10, the test mode signals TMR and TMW are controlled to the assert level and negate level, respectively. Consequently, only one of the test mode switches, TSW1, is controlled to be ON. The memory control circuit CTRL shown in Figures 1 and 2 receives the test clock signal TCLK. In response to the rising edge of the test clock signal TCLK at time t12, the memory control circuit CTRL simultaneously activates a predetermined write word line WWLN[k] and read word line RWLN[k]. Consequently, the write selection line WCP and read selection line RCP are simultaneously activated during the period from time t13 to t14.

[0116] In this example, the read enable signal RDEN is at an assert level during the period from time t12 to t14. The disturb test circuit DTBR outputs a high impedance to the read bit line RBL during the high impedance period TzR, which is the assert period of the read enable signal RDEN. On the other hand, the disturb test circuit DTBR precharges the read bit line RBL during the precharge period TpR, which is the negate period of the read enable signal RDEN.

[0117] The data input / output circuit IOC receives an "H" level external input data D[i] at time t10, prior to time t12. Accordingly, the disturb data setting circuit DTBD generates an "H" level positive-sequence input data DT and an "L" level negative-sequence input data DN at time t10. The disturb test circuit DTBR precharges the read bit line RBL to an "L" level at time t10 based on the "H" level positive-sequence input data DT and the negate level read enable signal RDEN. This "L" level precharge is maintained until time t12, when the high-impedance period TzR begins.

[0118] Furthermore, in this example, the write enable signal WTEN is at the assert level during the period from time t11 to t15. Time t11 is between time t10, when the external input data D[i] is determined, and time t12, when the test clock signal TCLK rises. Time t15 is after time t14, when the write selection line WCP is deactivated, and before time t16, when the next rising edge of the test clock signal TCLK occurs.

[0119] At time t11, the data input / output circuit IOC latches the external input data D[i] at the "H" level in response to the rising edge of the write enable signal WTEN. Then, the data input / output circuit IOC drives the write bit line WBLN to the "L" level via the write driver WDV.

[0120] Furthermore, as shown in Figure 7, the inverting memory node SNb pre-stores an "H" level. Then, at time t13, the inverting memory node SNb is connected to the write bit line WBLN, which is driven to an "L" level. In a stable latch cell LC, the inverting memory node SNb transitions from the "H" level to the "L" level. On the other hand, in an unstable latch cell LC, the inverting memory node SNb cannot fully transition to the "L" level due to interference from the read bit line RBL, which is pre-charged to the "L" level.

[0121] Figure 11 shows the state of the data input / output circuit IOC during the period from time t10 to time t12 in Figure 10. The external input data D[i] and the positive-sequence input data DT[i] are at the "H" level. The write bit line WBLN[i] is at the "L" level. The disturb test circuit DTBR receives the "L" level read enable signal RDEN and the "H" level positive-sequence input data DT[i]. As a result, the disturb test circuit DTBR precharges the read bit line RBL[i] to the "L" level via two test nMOS transistors MNt2 and MNt1, which are turned on.

[0122] <Details of the Disturb Readout Test> Figure 12 is a timing chart showing an example of a disturb readout test operation using the two disturb test circuits DTBR and DTBW shown in Figure 9. Figure 13 is a schematic diagram to supplement the explanation of the precharge operation by the two disturb test circuits DTBR and DTBW in Figure 12. In Figure 12, the disturb readout test described in Figure 8 is performed. Figure 13 shows the on / off state of each transistor and the state of each signal line in the data input / output circuit IOC shown in Figure 9 during the precharge periods TpR and TpW shown in Figure 12.

[0123] The time intervals t20-t26 in Figure 12 are the same as the time intervals t10-t16 in Figure 10. In Figure 12, there are three differences from the case in Figure 10. The first difference is that both test mode signals TMR and TMW are controlled to the assert level. Consequently, both test mode switches TSW1 and TSW2 are controlled to be ON. The second difference is that at time t20, an external input data D[i] of the "L" level is input, the opposite of the case in Figure 11. Consequently, the disturb data setting circuit DTBD generates a positive-sequence input data DT of the "L" level and a negative-sequence input data DN of the "H" level.

[0124] A third difference is that the bit write mask selection line BW is controlled to be in an active state. Consequently, the write driver WDV shown in Figure 9 outputs a high impedance to the write bit line WBLN. As a result, the voltage level of the write bit line WBLN is controlled by the disturb test circuit DTBW.

[0125] The disturb test circuit DTBW outputs a high impedance to the write bit line WBLN during the assertion period of the write enable signal WTEN, from time t21 to t25. In other words, the period from time t21 to t25 is the high impedance period TzW of the write bit line WBLN. On the other hand, the disturb test circuit DTBW precharges the write bit line WBLN during the period excluding the negate period of the write enable signal WTEN, from time t21 to t25. In other words, the period excluding time t21 to t25 is the precharge period TpW of the write bit line WBLN.

[0126] In detail, the disturb test circuit DTBW precharges the write bit line WBLN to the "L" level at time t20 based on the "H" level inverted input data DN and the negate level write enable signal WTEN. This "L" level precharge is maintained until time t21, when the write bit line WBLN transitions to the high impedance period TzW.

[0127] Meanwhile, the disturb test circuit DTBR precharges the read bit line RBL to an "H" level at time t20 based on the "L" level positive-sequence input data DT and the negate level read-enable signal RDEN. This "H" level precharge is maintained until time t22, when the read bit line RBL transitions to a high-impedance period TzR.

[0128] Furthermore, as shown in Figure 8, the non-inverting memory node SNt pre-stores the "L" level. Then, at time t23, the non-inverting memory node SNt is connected to the read bit line RBL, which holds the "H" level. In a stable latch cell LC, the read bit line RBL transitions from the "H" level to the "L" level. On the other hand, in an unstable latch cell LC, the read bit line RBL cannot sufficiently transition to the "L" level due to interference from the write bit line WBLN, which is pre-charged to the "L" level.

[0129] For example, the read latch circuit QLT shown in Figure 9 latches the read data at the falling edge of the read enable signal RDEN during the "L" level period of the read enable signal RDEN. If the transition of the read bit line RBL to the "L" level is insufficient at time t24 when the read enable signal RDEN falls, the read latch circuit QLT may mistakenly latch the "H" level.

[0130] Figure 13 shows the state of the data input / output circuit IOC during the period from time t20 to time t21 in Figure 12. The external input data D[i] and the positive-sequence input data DT[i] are at the "L" level. The negative-sequence input data DN[i] is at the "H" level. In addition, the write driver WDV outputs a high impedance to the write bit line WBLN[i] in conjunction with the "H" level of the bit write mask enable signal BWE.

[0131] In this state, the disturb test circuit DTBW receives a "L" level write enable signal WTEN and a "H" level inverted input data DN[i]. This causes the disturb test circuit DTBW to precharge the write bit line WBLN[i] to the "L" level via two ON test nMOS transistors MNt4 and MNt3. Meanwhile, the disturb test circuit DTBR receives a "L" level read enable signal RDEN and a "L" level positive input data DT[i]. This causes the disturb test circuit DTBR to precharge the read bit line RBL[i] to the "H" level via two ON test pMOS transistors MPt1 and MPt2.

[0132] <Manufacturing method for semiconductor devices> Figure 14 is a flowchart showing an example of a semiconductor device manufacturing method according to one embodiment. Figure 15 is a flowchart showing an example of a disturb write test (step S102a) in Figure 14. Figure 16 is a flowchart showing an example of a disturb read test (step S102b) in Figure 14. The manufacturing method shown in Figure 14 comprises a wafer processing step (step S101), a wafer testing step (step S102), a packaging step (step S103), and a final testing step (step S104).

[0133] In the wafer processing step (step S101), various semiconductor manufacturing equipment forms multiple semiconductor devices on a semiconductor wafer. Each of the multiple semiconductor devices has a memory MEM formed on it, which includes two disturb test circuits DTBR and DTBW, as shown in Figures 1, 3, and 9.

[0134] In the wafer testing process (step S102), for example, a probe testing device electrically tests multiple semiconductor devices, and consequently memory MEM, formed on a semiconductor wafer. The wafer testing process includes a disturb write test (step S102a) and a disturb read test (step S102b), as shown in Figures 15 and 16.

[0135] In the packaging process (step S103), various assembly devices assemble semiconductor devices that were determined to be good in the wafer testing process into packages. In the final testing process (step S104), for example, a semiconductor tester electrically tests the semiconductor devices assembled in the packages. Then, semiconductor devices that are determined to be good in the final testing process are shipped to the market.

[0136] Here, manufacturing variations in the wafer processing process can result in both stable and unstable latch cell LCs against the aforementioned inter-port interference. It is desirable that unstable latch cell LCs be detected in the wafer testing process. This can reduce the failure rate of semiconductor devices in the final testing process and in the market. Furthermore, if the memory MEM shown in Figure 1 is equipped with a rescue latch cell LC, a latch cell LC determined to be defective can be replaced with the rescue latch cell LC. This can improve the yield in the wafer testing process. In addition, detecting unstable latch cell LCs at an early stage can reduce unnecessary costs that may arise later, such as the assembly costs for defective products.

[0137] However, as mentioned above, simply supplying a normal external signal to the memory MEM with a probe testing device may not be sufficient to reproduce the worst-case scenarios shown in Figures 7 and 8. Therefore, tests such as those shown in Figures 15 and 16 are performed using two disturb test circuits, DTBR and DTBW. This allows for the detection of unstable latch cells LC during the wafer testing process, thus achieving the various effects described above.

[0138] First, let's explain the disturb write test (step S102a) shown in Figure 15. In step S201, the probe test device writes an "H" level to the inverted storage node SNb in the target latch cell LC. That is, the probe test device performs a normal write to the target latch cell LC using the write clock signal CLKW and the "L" level external input data D[i].

[0139] Next, in step S202, the probe testing device asserts the test mode signal TMR. Then, the probe testing device performs a "L" level disturb write to the inverting memory node SNb in the target latch cell LC. That is, the probe testing device performs a disturb write to the target latch cell LC using the test clock signal TCLK and the "H" level external input data D[i].

[0140] Next, in step S203, the probe inspection device performs a normal read from the target latch cell LC using the read clock signal CLKR. Then, in step S204, the probe inspection device determines whether or not it was able to read an "H" level from the target latch cell LC. That is, the probe inspection device determines whether the "L" level disturb write to the inverting storage node SNb in step S202 passed or failed.

[0141] If the judgment result in step S204 is fail, in step S209 the target latch cell LC is replaced with a replacement latch cell LC through a predetermined remediation procedure. If the target latch cell LC cannot be remediated, the semiconductor device containing the target latch cell LC is removed as a defective product. On the other hand, if the judgment result in step S204 is pass, the probe inspection device proceeds to step S205.

[0142] In step S205, the probe testing device writes the "L" level to the inverted memory node SNb of the target latch cell LC, the opposite to the case in step S201. Note that the processing in step S205 may be omitted in some cases due to the processing in step S202. Subsequently, in steps S206-S208, the same processing as in steps S202-S204 described above is performed using the inverted phase data. If the determination result in step S208 is a failure, the processing in step S209 is performed.

[0143] Next, the disturb read test (step S102b) shown in Figure 16 will be described. In step S301, the probe test device writes an "L" level to the non-inverting storage node SNt and an "H" level to the inverting storage node SNb in the target latch cell LC. That is, the probe test device performs a normal write to the target latch cell LC using the write clock signal CLKW and the "L" level external input data D[i].

[0144] Next, in step S302, the probe testing device asserts both test mode signals TMR and TMW. Then, the probe testing device performs a disturb readout from the target latch cell LC. That is, the probe testing device performs a disturb readout from the target latch cell LC using the test clock signal TCLK and the “L” level external input data D[i].

[0145] Then, in step S303, the probe inspection device determines whether or not it was able to read an "L" level from the target latch cell LC. That is, the probe inspection device determines whether the disturb read of the "L" level from the non-inverting storage node SNt in step S302 was a pass or a fail.

[0146] If the judgment result in step S303 is fail, in step S307 the target latch cell LC is replaced with a replacement latch cell LC through a predetermined remediation procedure. If the target latch cell LC cannot be remediated, the semiconductor device containing the target latch cell LC is removed as a defective product. On the other hand, if the judgment result in step S303 is pass, the probe inspection device proceeds to step S304.

[0147] In step S304, the probe testing device, contrary to step S301, writes an "H" level to the non-inverting memory node SNt and an "L" level to the inverting memory node SNb in the target latch cell LC. Then, in steps S305 and S306, the same processing as in steps S302 and S303 described above is performed using the inverted phase data. If the determination result in step S306 is a failure, the processing in step S307 is performed.

[0148] In this example, the probe testing device performed write, read, and judgment operations by supplying various external signals to the memory MEM. Alternatively, a BIST (Built-in Self Test) circuit may perform write, read, and judgment operations by supplying various external signals to the memory MEM. That is, a semiconductor device according to one embodiment may include a BIST circuit that performs tests as shown in Figures 15 and 16. This allows for a reduction in test time, for example, because the number of simultaneous measurements in the wafer testing process is not limited by the resources of the probe testing device.

[0149] <Main effects of one embodiment> In the method described above, each latch cell LC constituting the D-latch macro is composed of 12 MOS transistors. To test the effects of inter-port interference, a disturb test circuit DTBR, DTBW is provided within the D-latch macro to reproduce the worst-case inter-port interference condition. This allows for the detection of unstable latch cells LC that would fail under the worst-case conditions during the wafer testing process, thereby reducing the failure rate of semiconductor devices in the market.

[0150] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0151] BW, BWB Bitlight Mask Selection Line CDC1, CDC2 Charge / discharge circuit CSW1, CSW2 CMOS switches D[i] External input data DLT Program Latch Circuit DTBR, DTBW Disturb Test Circuit LC latch cell MN1-MN6 nMOS transistors MNt1-MNt4 Test nMOS Transistors MP1-MP6 pMOS transistors MPt1-MPt4 Test pMOS Transistors ND1, ND2 intermediate nodes Nvd High-potential power node Nvs low-potential power node QLT read latch circuit RBL Read Bit Line RCP, RCPN Readout Selection Line SNb inverted memory node SNt non-inverted memory node TSW1, TSW2 Test Mode Switches VDD High-potential power supply voltage VSS Low-potential power supply voltage WBLN write bit line WCP, WCPN write selection line WDV Light Driver

Claims

1. During the write operation, it is activated and is a pair of complementary signal lines, which are the write selection lines, Activated during readout operations, a pair of readout selection lines, which are complementary signal lines, A plurality of latch cells connected to the pair of write selection lines and the pair of read selection lines, Multiple read bit lines for transferring read data from the multiple latch cells, Multiple write bit lines for transferring write data to the multiple latch cells, When a high-impedance write operation is performed on any of the aforementioned latch cells, multiple pairs of bit write mask selection lines, which are complementary signal lines, are activated. A plurality of first test circuits connected to the plurality of read bit lines, It has, Each of the aforementioned plurality of latch cells is A first storage node and a second storage node that store complementary data, A first nMOS transistor is connected between the first memory node and the first intermediate node, and its gate is connected to the second memory node. A second nMOS transistor is connected between the second memory node and a low-potential power supply node to which a low-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third nMOS transistor is connected between the first intermediate node and the low-potential power supply node and controlled by the pair of write selection lines, A first pMOS transistor is connected between the first memory node and the second intermediate node, and its gate is connected to the second memory node. A second pMOS transistor is connected between the second memory node and a high-potential power supply node to which a high-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of write selection lines, A first CMOS switch controlled by the pair of write selection lines comprises a fourth nMOS transistor and a fourth pMOS transistor that, when controlled to be ON, connect a predetermined write bit line among the plurality of write bit lines to the first storage node, A second CMOS switch is configured, controlled by the pair of read selection lines, and when controlled to be ON, a fifth nMOS transistor and a fifth pMOS transistor connect the second storage node to a predetermined read bit line among the plurality of read bit lines, A sixth nMOS transistor connected between the first intermediate node and the low-potential power supply node, and controlled by a pair of bit write mask selection lines which are any of the plurality of pairs of bit write mask selection lines, A sixth pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of bit write mask selection lines, Equipped with, With the first CMOS switch and the second CMOS switch controlled to be ON for overlapping periods of time, a test to rewrite the first memory node from a first logical level to a second logical level that is in the opposite phase to the first logical level is performed as a disturb write test. The plurality of first test circuits precharge the plurality of read bit lines to the second logic level before the second CMOS switch is controlled to turn on when performing the disturb write test. Semiconductor equipment.

2. In the semiconductor device described in claim 1, Multiple external input data that define multiple write data are input from an external source, Each of the aforementioned plurality of first test circuits is A first charge / discharge circuit that charges or discharges the predetermined read bit line based on predetermined external input data among the plurality of external input data during the off period of the second CMOS switch, When performing the aforementioned disturb write test, a first test mode switch connects the first charge / discharge circuit to the predetermined read bit line, Equipped with, Semiconductor equipment.

3. In the semiconductor device described in claim 2, The first charge / discharge circuit is, A first test pMOS transistor and a second test pMOS transistor are connected in series between the high-potential power supply node and the predetermined read bit line via the first test mode switch, A first test nMOS transistor and a second test nMOS transistor are connected in series between the low-potential power supply node and the predetermined read bit line via the first test mode switch, Equipped with, The on / off states of the first test pMOS transistor and the first test nMOS transistor are controlled complementaryly based on the predetermined external input data. The second test pMOS transistor and the second test nMOS transistor are controlled to be ON during the OFF period of the second CMOS switch. Semiconductor equipment.

4. In the semiconductor device described in claim 1, Furthermore, it includes a plurality of second test circuits connected to the plurality of write bit lines, With the first storage node storing the first logical level, the first CMOS switch and the second CMOS switch are controlled to be turned ON for overlapping periods of time, and a test of reading the second logical level from the second storage node via the second CMOS switch is performed as a disturb read test. The plurality of first test circuits precharge the plurality of read bit lines to the first logic level before the second CMOS switch is controlled to turn ON when performing the disturb read test. The plurality of second test circuits precharge the plurality of write bit lines to the second logic level before the first CMOS switch is controlled to turn on when performing the disturb read test. Semiconductor equipment.

5. In the semiconductor device according to claim 4, further, Multiple write latch circuits that latch multiple external input data from an external source as multiple write data, Multiple write drivers are connected between the multiple write latch circuits and the multiple write bit lines, and consist of a tristate circuit that corresponds to the high-impedance write operation, and output high impedance during the disturb read test, Equipped with, Each of the first test circuits is: A first charge / discharge circuit that charges or discharges the predetermined read bit line based on predetermined external input data among the plurality of external input data during the off period of the second CMOS switch, When performing the disturb read test, a first test mode switch connects the first charge / discharge circuit to the predetermined read bit line, Equipped with, Each of the aforementioned plurality of second test circuits is A second charge / discharge circuit that charges or discharges the predetermined write bit line based on the predetermined external input data during the off period of the first CMOS switch, When performing the aforementioned disturb read test, a second test mode switch connects the second charge / discharge circuit to the predetermined write bit line, Equipped with, Semiconductor equipment.

6. In the semiconductor device described in claim 5, The first charge / discharge circuit is, A first test pMOS transistor and a second test pMOS transistor are connected in series between the high-potential power supply node and the predetermined read bit line via the first test mode switch, A first test nMOS transistor and a second test nMOS transistor are connected in series between the low-potential power supply node and the predetermined read bit line via the first test mode switch, Equipped with, The on / off states of the first test pMOS transistor and the first test nMOS transistor are controlled complementaryly based on the predetermined external input data. The second test pMOS transistor and the second test nMOS transistor are controlled to be ON during the OFF period of the second CMOS switch. The second charge / discharge circuit is, A third test pMOS transistor and a fourth test pMOS transistor are connected in series between the high-potential power supply node and the predetermined write bit line via the second test mode switch, A fourth test nMOS transistor and a fourth test nMOS transistor are connected in series between the low-potential power supply node and the predetermined write bit line via the second test mode switch, Equipped with, The on / off states of the third test pMOS transistor and the third test nMOS transistor are controlled complementaryly based on the predetermined external input data. The fourth test pMOS transistor and the fourth test nMOS transistor are controlled to be turned ON during the off period of the first CMOS switch. Semiconductor equipment.

7. In the semiconductor device described in claim 5, When the predetermined external input data is input to the first charge / discharge circuit, the second charge / discharge circuit is configured to receive data that is in the opposite phase of the predetermined external input data. Semiconductor equipment.

8. In the semiconductor device described in claim 1, Furthermore, the system includes a read latch circuit that inputs and latches the read data transferred to the plurality of read bit lines without going through a sense amplifier. Semiconductor equipment.

9. During the write operation, it is activated and is a pair of complementary signal lines, which are the write selection lines, Activated during readout operations, a pair of readout selection lines, which are complementary signal lines, A plurality of latch cells connected to the pair of write selection lines and the pair of read selection lines, Multiple read bit lines for transferring read data from the multiple latch cells, Multiple write bit lines for transferring write data to the multiple latch cells, When a high-impedance write operation is performed on any of the aforementioned latch cells, multiple pairs of bit write mask selection lines, which are complementary signal lines, are activated. A plurality of first test circuits connected to the plurality of read bit lines, Multiple second test circuits connected to the multiple write bit lines, It has, Each of the aforementioned plurality of latch cells is A first storage node and a second storage node that store complementary data, A first nMOS transistor is connected between the first memory node and the first intermediate node, and its gate is connected to the second memory node. A second nMOS transistor is connected between the second memory node and a low-potential power supply node to which a low-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third nMOS transistor is connected between the first intermediate node and the low-potential power supply node and controlled by the pair of write selection lines, A first pMOS transistor is connected between the first memory node and the second intermediate node, and its gate is connected to the second memory node. A second pMOS transistor is connected between the second memory node and a high-potential power supply node to which a high-potential power supply voltage is supplied, and whose gate is connected to the first memory node. A third pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of write selection lines, A first CMOS switch controlled by the pair of write selection lines comprises a fourth nMOS transistor and a fourth pMOS transistor that, when controlled to be ON, connect a predetermined write bit line among the plurality of write bit lines to the first storage node, A second CMOS switch is configured, controlled by the pair of read selection lines, and when controlled to be ON, a fifth nMOS transistor and a fifth pMOS transistor connect the second storage node to a predetermined read bit line among the plurality of read bit lines, A sixth nMOS transistor connected between the first intermediate node and the low-potential power supply node, and controlled by a pair of bit write mask selection lines which are any of the plurality of pairs of bit write mask selection lines, A sixth pMOS transistor is connected between the second intermediate node and the high-potential power supply node and controlled by the pair of bit write mask selection lines, Equipped with, With the first memory node storing the first logical level, the first CMOS switch and the second CMOS switch are controlled to be turned ON for overlapping periods of time, and a test is performed to read a second logical level, which is in the opposite phase to the first logical level, from the second memory node via the second CMOS switch, as a disturb read test. The plurality of first test circuits precharge the plurality of read bit lines to the first logic level before the second CMOS switch is controlled to turn ON when performing the disturb read test. The plurality of second test circuits precharge the plurality of write bit lines to the second logic level before the first CMOS switch is controlled to turn on when performing the disturb read test. Semiconductor equipment.

10. In the semiconductor device described in claim 9, further, Multiple write latch circuits that latch multiple external input data from an external source as multiple write data, Multiple write drivers are connected between the multiple write latch circuits and the multiple write bit lines, and consist of a tristate circuit that corresponds to the high-impedance write operation, and also output high impedance during the disturb read test, Equipped with, Each of the aforementioned plurality of first test circuits is A first charge / discharge circuit that charges or discharges the predetermined read bit line based on predetermined external input data among the plurality of external input data during the off period of the second CMOS switch, When performing the disturb read test, a first test mode switch connects the first charge / discharge circuit to the predetermined read bit line, Equipped with, Each of the aforementioned plurality of second test circuits is A second charge / discharge circuit that charges or discharges the predetermined write bit line based on the predetermined external input data during the off period of the first CMOS switch, When performing the aforementioned disturb read test, a second test mode switch connects the second charge / discharge circuit to the predetermined write bit line, Equipped with, Semiconductor equipment.

11. In the semiconductor device according to claim 10, The first charge / discharge circuit is, A first test pMOS transistor and a second test pMOS transistor are connected in series between the high-potential power supply node and the predetermined read bit line via the first test mode switch, A first test nMOS transistor and a second test nMOS transistor are connected in series between the low-potential power supply node and the predetermined read bit line via the first test mode switch, Equipped with, The on / off states of the first test pMOS transistor and the first test nMOS transistor are controlled complementaryly based on the predetermined external input data. The second test pMOS transistor and the second test nMOS transistor are controlled to be ON during the OFF period of the second CMOS switch. The second charge / discharge circuit is, A third test pMOS transistor and a fourth test pMOS transistor are connected in series between the high-potential power supply node and the predetermined write bit line via the second test mode switch, A fourth test nMOS transistor and a fourth test nMOS transistor are connected in series between the low-potential power supply node and the predetermined write bit line via the second test mode switch, Equipped with, The on / off states of the third test pMOS transistor and the third test nMOS transistor are controlled complementaryly based on the predetermined external input data. The fourth test pMOS transistor and the fourth test nMOS transistor are controlled to be turned ON during the off period of the first CMOS switch. Semiconductor equipment.

12. In the semiconductor device according to claim 10, When the predetermined external input data is input to the first charge / discharge circuit, the second charge / discharge circuit is configured to receive data that is in the opposite phase of the predetermined external input data. Semiconductor equipment.

13. In the semiconductor device described in claim 9, Furthermore, the system includes a read latch circuit that inputs and latches the read data transferred to the plurality of read bit lines without going through a sense amplifier. Semiconductor equipment.

Images