Polarized superjunction field-effect transistors and electrical equipment

Abstract

To provide a polarization superjunction field effect transistor capable of significantly reducing the gate leakage current that flows when a positive voltage is applied to the gate electrode. 【Solution means】This field effect transistor includes a first undoped GaN layer 11, Al x , x , 1-x , x , 1-x , x , 1-x , 1-y , 1-x , 1-x , y Ga 1-x N layer 12 (0.17 ≤ x ≤ 0.35), a second undoped GaN layer 13, a p-type GaN layer 15, Al x Ga 1-x An intermediate layer 14 between the Al x Ga 1-x N layer and the second undoped GaN layer, a source electrode 18 and a drain electrode 19 on the Al x Ga 1-x N layer, and a gate electrode 17 on the p-type GaN layer. The intermediate layer is a graded Al x Ga 1-x N layer (x ≤ y < 0.5) in which the bandgap increases continuously and / or stepwise from the bandgap of the Al y Ga 1-y N layer at the interface between the N layer and the intermediate layer towards the interface between the second undoped GaN layer and the intermediate layer, and has a thickness such that carriers do not substantially move due to the tunneling effect.

Description

[Technical Field]

[0001] This invention relates to a polarized superjunction field-effect transistor and an electrical device using this polarized superjunction field-effect transistor. [Background technology]

[0002] Conventionally, polarization superjunction (PSJ) GaN-based field-effect transistors (FETs) are known as power transistors (see Patent Documents 1 and 2). These polarization superjunction GaN-based field-effect transistors consist of an undoped GaN layer and Al x Ga 1-x It has a polarization superjunction region that includes a structure in which N layers and undoped GaN layers are sequentially stacked. This polarization superjunction GaN-based field-effect transistor enables high voltage resistance, high power output, high efficiency, and high-speed operation, which are difficult to achieve with silicon (Si)-based power transistors.

[0003] In recent years, polarized superjunction GaN-based field-effect transistors have been proposed that suppress current collapse and improve sheet carrier concentration (see Patent Document 3). These polarized superjunction GaN-based field-effect transistors are characterized by having a first intermediate layer between the lower undoped GaN layer and the AlGaN layer, and a second intermediate layer between the upper undoped GaN layer and the AlGaN layer. These first and second intermediate layers are sufficiently thin, and it is believed that carriers (electrons and holes) can move in the thickness direction of these layers by tunneling. Typically, AlN layers are used as these first and second intermediate layers. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 5828435 [Patent Document 2] Patent No. 5669119 [Patent Document 3] Japanese Patent Publication No. 2022-119335 [Patent Document 4] Patent No. 6941903 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, according to findings independently obtained by the inventors, it has been found that conventional polarized superjunction GaN-based field-effect transistors exhibit a gate leakage current greater than expected when a positive voltage is applied to the gate electrode. Therefore, a reduction in this gate leakage current is desirable.

[0006] Therefore, the problem that this invention aims to solve is to provide a polarized superjunction field-effect transistor that can significantly reduce the gate leakage current that flows when a positive voltage is applied to the gate electrode, and a high-performance electrical device using this polarized superjunction field-effect transistor. [Means for solving the problem]

[0007] To solve the above problems, this invention provides: The first semiconductor layer and A second semiconductor layer is located above the first semiconductor layer mentioned above, A third semiconductor layer having an island-like shape, located above the second semiconductor layer, The fourth semiconductor layer is located above the third semiconductor layer mentioned above, An intermediate layer between the second semiconductor layer and the third semiconductor layer, The source electrode and drain electrode on the second semiconductor layer described above, A gate electrode electrically connected to the above fourth semiconductor layer, It has, The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the intermediate layer are all group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first and third semiconductor layers. The intermediate layer is a graded layer in which the bandgap increases continuously and / or stepwise from the interface between the second semiconductor layer and the intermediate layer toward the interface between the third semiconductor layer and the intermediate layer, starting from the bandgap of the second semiconductor layer, and has a thickness such that carriers do not substantially move due to the tunnel effect. The first semiconductor layer and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer, which is a polarization superjunction field effect transistor.

[0008] The group III nitride semiconductor layer generally consists of at least one group III element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In), and at least one group V element selected from the group consisting of N (nitrogen), phosphorus (P), and arsenic (As). The group III nitride semiconductor layer most commonly consists of Al p B q Ga 1-p-q-r In r N (where 0 ≤ p ≤ 1, 0 ≤ q ≤ 1, 0 ≤ r ≤ 1, 0 ≤ p + q + r < 1), and typically consists of Al p Ga 1-p-r In r N (where 0 ≤ p ≤ 1, 0 ≤ r ≤ 1, 0 ≤ p + r < 1). Most typically, the first semiconductor layer and the third semiconductor layer are undoped GaN layers, the second semiconductor layer is an Al p Ga 1-p [[ID=​​​​​​​​​​​​​​​N-layer, for example, Si-doped n-type Al p Ga 1-p N layers may also be used. Graded Al t Ga 1-t The N layer is also Al p Ga 1-p It is similar to the N layer. s Ga 1-s The In composition s and thickness u of the N layer are typically chosen to satisfy approximately s × u ≤ 0.20 × 5 [nm]. t Ga 1-t The thickness of the N layer is selected as needed, taking into consideration the Al composition t, etc., but is, for example, 3 nm or more, preferably 3.5 nm or more, and more preferably 4 nm or more.

[0009] In this polarized superjunction field-effect transistor, when not in operation, a two-dimensional electron gas (2DEG) is formed in the first semiconductor layer near the heterointerface between the first and second semiconductor layers, and a two-dimensional hole gas (2DHG) is formed in the third semiconductor layer near the heterointerface between the third semiconductor layer and the intermediate layer.

[0010] This polarized superjunction field-effect transistor is most typically configured as in the following invention.

[0011] In other words, this invention is The first undoped GaN layer, Al above the first undoped GaN layer x Ga 1-x N layers (0.17 ≤ x ≤ 0.35), The above Al x Ga 1-x A second undoped GaN layer having an island-like shape, located above the N layer, The p-type GaN layer above the second undoped GaN layer described above, The above Al x Ga 1-x An intermediate layer between the N layer and the second undoped GaN layer, The above Al x Ga 1-x Source electrode and drain electrode on the N layer, The above p-type GaN layer and the electrically connected gate electrode, It has, The above intermediate layer is Al x Ga 1-x The band gap from the interface between the N layer and the intermediate layer toward the interface between the second undoped GaN layer and the intermediate layer is Al x Ga 1-x Graded Al, which increases continuously and / or stepwise from the band gap of the N layer y Ga 1-y This is a polarized superjunction field-effect transistor with an N-layer (x≦y<0.5) and a thickness such that carriers do not substantially move due to the tunneling effect.

[0012] If this polarized superjunction field-effect transistor has a structure similar to that of Patent Document 1, the polarized superjunction region is a first undoped GaN layer in the portion where the p-type GaN layer does not exist, Al x Ga 1-x N-layer, graded aluminum y Ga 1-y It consists of an N layer and a second undoped GaN layer. The thickness of the first undoped GaN layer, the thickness of the second undoped GaN layer, etc., are typically selected in accordance with Patent Document 1. If this polarized superjunction field-effect transistor has a structure similar to that of Patent Document 2, the polarized superjunction region consists of a first undoped GaN layer and an Al layer. x Ga 1-x N-layer, graded aluminum y Ga 1-y The structure consists of an N layer, a second undoped GaN layer, and a p-type GaN layer. The thickness of the first undoped GaN layer, the thickness of the second undoped GaN layer, the thickness of the p-type GaN layer, and the impurity concentration are typically selected in accordance with Patent Document 2.

[0013] Furthermore, this invention, It has at least one transistor, The aforementioned transistor, The first semiconductor layer and A second semiconductor layer is located above the first semiconductor layer mentioned above, A third semiconductor layer having an island-like shape, located above the second semiconductor layer, The fourth semiconductor layer is located above the third semiconductor layer mentioned above, An intermediate layer between the second semiconductor layer and the third semiconductor layer, The source electrode and drain electrode on the second semiconductor layer described above, A gate electrode electrically connected to the above fourth semiconductor layer, It has, The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the intermediate layer are all group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first and third semiconductor layers. The above-mentioned intermediate layer is a graded layer in which the band gap increases continuously and / or stepwise from the band gap of the second semiconductor layer toward the interface between the second semiconductor layer and the intermediate layer toward the interface between the third semiconductor layer and the intermediate layer, and has a thickness such that carriers do not substantially move due to the tunneling effect. The first semiconductor layer and the third semiconductor layer are undoped semiconductor layers. The above-mentioned fourth semiconductor layer is a p-type semiconductor layer, and the electrical device is a polarized superjunction field-effect transistor.

[0014] Furthermore, this invention, It has at least one transistor, The aforementioned transistor, The first undoped GaN layer, Al above the first undoped GaN layer x Ga 1-x N layers (0.17 ≤ x ≤ 0.35), The above Al x Ga 1-x A second undoped GaN layer having an island-like shape, located above the N layer, The p-type GaN layer above the second undoped GaN layer described above, The above Al x Ga 1-x An intermediate layer between the N layer and the second undoped GaN layer, The above Alx Ga 1-x Source electrode and drain electrode on the N layer, The above p-type GaN layer and the electrically connected gate electrode, It has, The above intermediate layer is Al x Ga 1-x The band gap from the interface between the N layer and the intermediate layer toward the interface between the second undoped GaN layer and the intermediate layer is Al x Ga 1-x Graded Al, which increases continuously and / or stepwise from the band gap of the N layer y Ga 1-y This electrical device is a polarized superjunction field-effect transistor with an N-layer structure (x ≤ y < 0.5) and a thickness such that carriers do not substantially move due to the tunneling effect.

[0015] In the above invention of electrical equipment, "electrical equipment" includes virtually all devices that use electricity, regardless of their purpose, function, or size, but examples include electronic devices, mobile devices, power devices, construction machinery, and machine tools. Electronic devices include robots, computers, game consoles, in-vehicle devices, household electrical appliances (such as air conditioners), industrial products, mobile phones, mobile devices, IT equipment (such as servers), power conditioners used in solar power generation systems, and power transmission systems. Mobile devices include railway vehicles, automobiles (such as electric vehicles), motorcycles, aircraft, rockets, and spacecraft. For anything not listed above, the explanations related to the above invention of the polarized superjunction field-effect transistor apply, as long as they do not contradict their nature. [Effects of the Invention]

[0016] According to this invention, the intermediate layer between the second semiconductor layer and the third semiconductor layer or Al x Ga 1-x An intermediate layer between the N layer and the second undoped GaN layer allows carriers to move between the second and third semiconductor layers or Al when a positive voltage is applied to the gate electrode. x Ga 1-xBecause current flow is reduced between the N layer and the second undoped GaN layer, the gate leakage current that flows when a positive voltage is applied to the gate electrode can be significantly reduced. Furthermore, by using this polarized superjunction field-effect transistor, high-performance electronic devices can be realized. [Brief explanation of the drawing]

[0017] [Figure 1] This is a cross-sectional view showing a polarization superjunction GaN-based FET according to the first embodiment of this invention. [Figure 2] This is a schematic diagram showing the energy band diagram of the region directly beneath the gate electrode of a polarization superjunction GaN-based FET according to the first embodiment of this invention. [Figure 3] This is a cross-sectional view showing an example of the configuration of a graded Aly Ga1-y N layer in a polarized superjunction GaN-based FET according to the first embodiment of this invention. [Figure 4] This is a schematic diagram showing the energy band diagram of the region directly beneath the gate electrode when a graded Aly Ga1-y N layer is used in a polarization superjunction GaN-based FET according to the first embodiment of this invention, as shown in Figure 3. [Figure 5] This is a schematic diagram showing the energy band diagram of the region directly below the gate electrode when a positive voltage is applied to the gate electrode in a polarization superjunction GaN-based FET according to the first embodiment of this invention. [Figure 6] This is a schematic diagram showing the energy band diagram of the region directly below the gate electrode of a polarized superjunction GaN-based FET, as a comparative example for comparison with the first embodiment of this invention. [Figure 7] This schematic diagram shows the energy band diagram of the region directly below the gate electrode when a positive voltage is applied to the gate electrode in a comparative example of a polarized superjunction GaN-based FET, for comparison with the first embodiment of this invention. [Figure 8]This schematic diagram shows the energy band diagram of the region directly beneath the gate electrode of a polarization superjunction GaN-based FET according to the first embodiment of this invention, obtained by simulation based on a one-dimensional model. [Figure 9] This schematic diagram shows the energy band diagram of the region directly beneath the gate electrode of a polarized superjunction GaN-based FET, obtained by simulation based on a one-dimensional model, as a comparative example for comparison with the first embodiment of this invention. [Figure 10] This is a cross-sectional view showing a polarization superjunction GaN-based FET according to a second embodiment of the present invention. [Figure 11] This is a cross-sectional view showing a polarization superjunction GaN-based FET according to a third embodiment of the present invention. [Figure 12] This is a schematic diagram showing the measurement results of the gate voltage-gate current characteristics of a polarized superjunction GaN-based FET according to an example. [Modes for carrying out the invention]

[0018] The following describes embodiments for carrying out the invention. <First Embodiment> [Polarized Superjunction GaN-based FET]

[0019] As shown in Figure 1, in the polarization superjunction GaN-based FET according to the first embodiment, an undoped GaN layer 11 and an Al layer are provided on the substrate 10 via a buffer layer (not shown). x Ga 1-x N-layer 12, graded aluminum y Ga 1-y An N layer 13 and an undoped GaN layer 14 are sequentially stacked. The substrate 10 is preferably a substrate on which GaN-based semiconductors are grown on the C plane, such as a C-plane sapphire substrate, a Si substrate, or a SiC substrate. The buffer layer is made of, for example, polycrystalline or amorphous GaN, AlN, AlGaN, or even an AlGaN / GaN superlattice. x Ga 1-xThe N layer 12 is typically undoped, but may be an n-type or p-type Al doped with a donor (n-type impurity) or an acceptor (p-type impurity). x Ga 1-x It may also be an N layer. Al x Ga 1-x The Al composition x of the N layer 12 is in the range of 0.17 ≤ x ≤ 0.35. Graded Al y Ga 1-y The Al composition y of the N layer 13 is x ≤ y < 0.5. Graded Al y Ga 1-y The N layer 13 has a thickness such that carriers (electrons and holes) do not move substantially due to the tunneling effect, for example, a thickness of 4 nm or more. Graded Al y Ga 1-y Details of the structure of the N layer 13 will be described later. Graded Al y Ga 1-y The N layer 13 and the undoped GaN layer 14 have an island shape, and the Al x Ga 1-x N layer 12 is exposed on both sides. A p-type GaN layer 14 is laminated on the entire surface of the undoped GaN layer 13. The thickness of one side portion of the p-type GaN layer 14 on the drain electrode 19 side, which will be described later, is smaller than the thickness of one side portion on the source electrode 18 side, which will be described later. The portion of the p-type GaN layer 15 with a small thickness corresponds to the polarization super-junction region (PSJ region). On the p-type GaN layer 15 with a large thickness, a p + -type GaN layer 16 is laminated on the entire surface. The p-type GaN layer 15 and the p + -type GaN layer 16 are doped with magnesium (Mg) as an acceptor. [[ID=​​​​​​​​​​​Ga 1-y N layer 13, an undoped GaN layer 14, a p-type GaN layer 15, and a p + type GaN layer 16, a source electrode 18 is provided on the p-type GaN layer 15 and p + type GaN layer 16 side portion, and a drain electrode 19 is provided on the opposite side portion. As will be described later, the source electrode 18 and the drain electrode 19 are made of a metal having a small work function, typically titanium (Ti), so as to be able to make an ohmic contact with the 2DEG formed in the undoped GaN layer 11 in the vicinity of the heterointerface between the undoped GaN layer 11 and Al x Ga 1-x N layer 12. The source electrode 18 and the drain electrode 19 may be composed of a laminated film in which an aluminum (Al) film, a nickel (Ni) film, a gold (Au) film, etc. are laminated on a Ti film.

[0021] In this polarization superjunction GaN-based FET, a portion of the p-type GaN layer 15 having a small thickness, the undoped GaN layer 14 directly below this portion, the graded Al y Ga 1-y N layer 13, Al x Ga 1-x N layer 12, and the undoped GaN layer 11 constitute a psj region. The p + type GaN layer 16, the p-type GaN layer 15 in the portion directly below it, the undoped GaN layer 14, the graded Al y Ga 1-y N layer 13, Al x Ga 1-x N layer 12, and the undoped GaN layer 11 constitute a gate electrode contact region.

[0022] In this polarization superjunction GaN-based FET, due to the piezoelectric polarization and the spontaneous polarization, positive fixed charges are induced in the Al x Ga 1-x N layer 12 in the vicinity of the heterointerface between the undoped GaN layer 11 on the substrate 10 side and Al x Ga 1-x N layer 12, and graded Al y Ga1-y N layer 13 and Al x Ga 1-x Graded Al in the vicinity of the heterointerface between the N layer 12 and the undoped GaN layer 14 y Ga 1-y N layer 13 and Al x Ga 1-x A negative fixed charge is induced in the N layer 12. Therefore, in this polarized superjunction GaN-based FET, when non-operating (thermal equilibrium state), graded Al y Ga 1-y N layer 13 and Al x Ga 1-x 2DHG20 is formed in the undoped GaN layer 14 near the heterointerface between the N layer 12 and the undoped GaN layer 14, and Al x Ga 1-x 2DEG21 is formed in the undoped GaN layer 11 near the heterointerface with the N layer 12. In the non-operating state (thermal equilibrium state), 2DEG21 is formed in the portion directly below the gate electrode 17, so this polarized superjunction GaN-based FET is normally-on type.

[0023] Graded Al y Ga 1-y In the N layer 13, the Al composition is y, and therefore the band gap is Al x Ga 1-x N-layer 12 and this graded aluminum y Ga 1-y The undoped GaN layer 14 and this graded Al at the interface between the N layer 13 and this layer 13 y Ga 1-y Al toward the interface between the N layer 13 x Ga 1-x It increases continuously and / or stepwise from layer N 12. This graded Al y Ga 1-y The Al composition y of layer N 13 is x ≤ y < 0.5, therefore this graded Al y Ga 1-y The maximum band gap of layer N13 is Al at y=0.5 y Ga 1-yIt is less than the bandgap of the N layer. Typically, it is selected to be y ≦ 0.4, but it is not limited to this. In FIG. 2, the graded Al y Ga 1-y FIG. 4 shows the energy band diagram of the region directly under the gate electrode 20 when the bandgap of the graded Al c Ga v N layer 13 continuously increases. In FIG. 2, the vertical axis is the electron energy, E f is the energy at the lower end of the conduction band, E y Ga 1-y When the Al composition y of the graded Al y Ga 1-y N layer 13, and thus the bandgap, increases stepwise, the graded Al y1 Ga 1-y1 N layer 13 consists of n layers of Al y2 Ga 1-y2 N layer 13-1, Al ... y(n-1) Ga 1-y(n-1) N layer 13-(n-1) and Al yn Ga 1-yn N layer 13-n, where x < y1 < y2 <,..., < y(n-1) < yn. In FIG. 4, an example of the energy band diagram of the region directly under the gate electrode 17 when the bandgap of the graded Al y Ga 1-y N layer 13 increases stepwise is shown.

[0024] Now, in a polarization superjunction GaN-based FET having an energy band as shown in FIG. 2, FIG. 5 shows the energy band diagram when a positive voltage V is applied to the gate electrode 17. For comparison, FIG. 6 shows the energy band diagram of the region directly under the gate electrode 17 of a comparative example of a polarization superjunction GaN-based FET that is only different in that the graded Al y Ga 1-y N layer 13 is not provided. Also, FIG. 7 shows the energy band diagram when a positive voltage V is applied to the gate electrode 17 of this comparative example of a polarization superjunction GaN-based FET. As shown in FIG. 7, the graded Aly Ga 1-y In a comparative example of a polarization superjunction GaN-based FET without an N layer 13, when a positive voltage V is applied to the gate electrode 17, Al x Ga 1-x Carriers (electrons (e) pass through layer N 12) - ) and holes (h + )) flows easily. In contrast, as shown in Figure 5, graded Al y Ga 1-y In a polarization superjunction GaN-based FET provided with an N layer 13, graded Al y Ga 1-y Al x Ga 1-x Because the conduction band is raised and the valence band is lowered from the N layer 12, when a positive voltage V is applied to the gate electrode 17, the carriers are Al x Ga 1-x Current flow through layer N12 is significantly reduced. Therefore, a substantial reduction in gate leakage current can be achieved.

[0025] [Manufacturing method for polarized superjunction GaN-based FETs] First, on the substrate 10, for example, using a conventionally known MOCVD (metal-organic chemical vapor deposition) method, a buffer layer, an undoped GaN layer 11, and Al are formed using TMG (trimethylgallium) as the Ga raw material, TMA (trimethylaluminum) as the Al raw material, NH3 (ammonia) as the nitrogen raw material, and N2 gas and H2 gas as carrier gases. x Ga 1-x N-layer 12, graded aluminum y Ga 1-y N layer 13, undoped GaN layer 14, p-type GaN layer 15 and p + The GaN layer 16 is grown sequentially. Undoped GaN layer 11, Al x Ga 1-x N-layer 12, graded aluminum y Ga 1-y The growth temperature of the N layer 13, the undoped GaN layer 14, and the p-type GaN layer 15 is, for example, around 1100°C. y Ga 1-yWhen growing the N layer 13, the flow rates of TMG, TMA, and NH3 are changed continuously or stepwise. As the substrate 10, a sapphire substrate (e.g., a C-plane sapphire substrate), a Si substrate, a SiC substrate, etc., can be used. For the buffer layer, a GaN layer, an AlN layer, an AlGaN layer, an AlGaN / GaN superlattice layer, etc., can be used. When using a GaN layer as the buffer layer, for example, it is grown at a low temperature of about 530°C. p-type GaN layer 15 and p + Biscyclopentadienylmagnesium (Cp2Mg) is used as the p-type dopant for the growth of the GaN layer 16, and hydrogen (H2) and nitrogen (N2) are used as carrier gases for their growth.

[0026] Next, p + After forming a mask such as a resist pattern with a shape corresponding to the device formation region on the GaN layer 16, this mask is used to p + p-type GaN layer 16, p-type GaN layer 15, undoped GaN layer 14, graded Al y Ga 1-y N layer 13, Al x Ga 1-x Element isolation is achieved by sequentially etching the N layer 12 and the undoped GaN layer 11 to an intermediate depth in the thickness direction of the undoped GaN layer 11 and patterning them into a predetermined shape. After this, the mask is removed.

[0027] Next, p + On the type GaN layer 16, the p shown in Figure 1 + After forming a mask such as a resist pattern with a shape corresponding to the planar shape of the GaN layer 16, this mask is used to p + The p-type GaN layer 16 and the p-type GaN layer 15 are sequentially etched to a depth intermediate in the thickness direction of the p-type GaN layer 15 to pattern them into a predetermined shape. After this, the mask is removed.

[0028] Next, p +After forming a mask such as a resist pattern with a shape corresponding to the planar shape of the undoped GaN layer 14 shown in Figure 1, covering the p-type GaN layer 16 and the p-type GaN layer 15, this mask is used to cover the p-type GaN layer 15, the undoped GaN layer 14, and the graded Al y Ga 1-y N layer 13 is Al x Ga 1-x The N layer 12 is etched until it is exposed and then patterned into the desired shape. After this, the mask is removed.

[0029] Next, exposed Al x Ga 1-x After forming the source electrode 18 and drain electrode 19 on the N layer 12, p + A gate electrode 17 is formed on the GaN layer 16.

[0030] Based on the above, the target polarization superjunction GaN-based FET shown in Figure 1 is manufactured.

[0031] For this polarized superjunction GaN-based FET, an energy band diagram was created by simulation based on a one-dimensional model of the depth direction (stack direction) of the region directly beneath the gate electrode 17. The results are shown in Figure 8. Here, the thickness of each layer of this polarized superjunction GaN-based FET is 800 nm for the undoped GaN layer 11, and Al x Ga 1-x N-layer 12 is 40nm, graded aluminum y Ga 1-y The N layer 13 was 3 nm, the undoped GaN layer 14 was 65 nm, and the p-type GaN layer 15 was 60 nm. x Ga 1-x The Al composition x of layer N12 was set to 0.21. Graded Al y Ga 1-y The Al composition y of the N layer 13 was continuously increased from 0.21 to 0.35. The acceptor concentration of the p-type GaN layer 15 was 5 × 10⁻¹⁰. 19 cm -3 The simulation was performed assuming a uniform temperature of 300K throughout the entire FET. y Ga 1-ySimilarly, an energy band diagram was created by simulation for a polarization superjunction GaN-based FET using a comparative example that does not include the N layer 13. The results are shown in Figure 9.

[0032] As described above, according to this first embodiment, Al x Ga 1-x A graded aluminum layer is placed between the N layer 12 and the undoped GaN layer 14. y Ga 1-y The presence of the N layer 13 significantly reduces the gate leakage current that flows when a positive voltage is applied to the gate electrode 17.

[0033] <Second Embodiment> [Polarized Superjunction GaN-based FET]

[0034] As shown in Figure 10, the polarization superjunction GaN-based FET according to the second embodiment differs from the polarization superjunction GaN-based FET according to the first embodiment in that, similar to Patent Document 1, there is no p-type GaN layer 15 in the polarization superjunction region. Other aspects are the same as those of the polarization superjunction GaN-based FET according to the first embodiment.

[0035] [Manufacturing method for polarized superjunction GaN-based FETs] This method for manufacturing a polarized superjunction GaN-based FET is the same as the method for manufacturing a polarized superjunction GaN-based FET according to the first embodiment, except that a p-type GaN layer 15 is not ultimately formed on the undoped GaN layer 14 in the polarized superjunction region.

[0036] According to this second embodiment, the same advantages as the first embodiment can be obtained.

[0037] <Third Embodiment> [Polarized Superjunction GaN-based FET]

[0038] As shown in Figure 11, in the polarization superjunction GaN-based FET according to the third embodiment, p is present on the p-type GaN layer 15 in the thicker portion. + Instead of the p-type GaN layer 16, p-type Inz Ga 1-z The difference from the polarization superjunction GaN-based FET according to the first embodiment is that the N layer 22 is stacked. z Ga 1-z The N layer 22 is doped with Mg as a p-type impurity. z Ga 1-z The In composition z and thickness t of the N layer 22 are selected as needed, but the In composition z is typically selected to be 0.20 or less. The In composition z and thickness t are typically selected to satisfy approximately y × t ≤ 0.20 × 5 [nm]. For example, when y = 0.10, t is generally selected to be 10 nm or less. Other aspects are the same as for the polarization superjunction GaN-based FET according to the first embodiment.

[0039] In this polarized superjunction GaN-based FET, p-type In z Ga 1-z Due to the polarization effect of the N layer 22, the conduction band is raised, and in the non-operating state (thermal equilibrium state), 2DEG21 is not formed in the portion directly below the gate electrode 17 (p-type In z Ga 1-z For details on the effects of using the N layer 19, see, for example, Patent Document 4). In other words, this polarized superjunction GaN-based FET has a gate threshold voltage V th >0, and it is a normally-off type. In order to form 2DEG21 in the part directly below the gate electrode 17, V th Larger positive gate voltage V g It is necessary to apply it.

[0040] [Manufacturing method for polarized superjunction GaN-based FETs] The manufacturing method for this polarized superjunction GaN-based FET is p + Instead of the p-type GaN layer 16, p-type In z Ga 1-z The method for manufacturing a polarization superjunction GaN-based FET is the same as the method according to the first embodiment, except for forming the N layer 22.

[0041] According to this third embodiment, the same advantages as in the first embodiment can be obtained in a normally-off type polarization superjunction GaN-based FET.

[0042] (Examples) A polarized superjunction GaN-based FET with a structure similar to that of the second embodiment was fabricated. This polarized superjunction GaN-based FET was manufactured as follows: A C-plane sapphire substrate was used as the substrate 10, and on it, a 30 nm thick GaN low-temperature buffer layer, an 800 nm thick undoped GaN layer 11, and a 40 nm thick Al layer with x=0.21 were fabricated by MOCVD. x Ga 1-x N-layer 12, 4.4nm thick graded aluminum y Ga 1-y N layer 13, undoped GaN layer 14 with a thickness of 65 nm, Mg concentration [Mg] = 5 × 10⁻¹⁶ 19 cm -3 In the p-type GaN layer 15 and with a thickness of 5 nm, the Mg concentration [Mg] = 1 × 10⁻¹⁰ 20 cm -3 p + The GaN layer 16 was sequentially epitaxially grown. y Ga 1-y N layer 13 is made of Al with a thickness of 1.5 nm. 0.25 Ga 0.75 N-layer, 1.5 nm thick Al 0.3 Ga 0.7 N layer and 1.4 nm thick Al 0.35 Ga 0.65 It has a three-layer structure with N layers. Undoped GaN layer 11, Al x Ga 1-x N-layer 12, graded aluminum y Ga 1-y N layer 13, undoped GaN layer 14, p-type GaN layer 15 and p + The growth temperature for the GaN layer 16 was set to 1100°C. H2 and N2 were used as carrier gases during growth.

[0043] Next, the gate electrode contact region was masked and etched until the undoped GaN layer 14 was reached. At this point, the p-type GaN layer 15 other than the gate electrode contact region was completely removed. Next, the gate electrode contact region and the psj region were masked and etched down to the undoped GaN layer 13. x Ga 1-x Layer N-12 was exposed.

[0044] Next, the surface of the area excluding the parts where the source electrode 18 and drain electrode 19 are formed is masked with an SiO2 film. Then, a Ti / Al / Ni / Au multilayer film is formed in the source electrode formation area and the drain electrode formation area by vacuum deposition to form the source electrode 18 and drain electrode 19. After that, an ohmic alloy treatment is performed in N2 at 800°C for 60 seconds.

[0045] Next, the SiO2 film in the area where the gate electrode 17 is formed is removed, p + After forming a gate electrode 17 by vacuum deposition on a GaN layer 16, an ohmic alloy treatment was performed by rapid thermal annealing (RTA) at 550°C for 300 seconds in air.

[0046] Subsequently, using polyimide as a mask, approximately 2 μm of Au was layered onto the source electrode 18 and drain electrode 19 by electroplating.

[0047] Graded Al y Ga 1-y A polarized superjunction GaN-based FET without the N layer 13 was fabricated in the same manner as described above.

[0048] The source electrode 18 and drain electrode 19 of the polarized superjunction GaN FETs fabricated as described above, both in the embodiment and the comparative example, are grounded, and a positive voltage is applied to the gate electrode 17 as the gate voltage to obtain a gate voltage (V g )-Gate current (I gThe characteristics were measured. The measurement results are shown in Figure 12. As shown in Figure 12, the gate current of the polarized superjunction GaN-based FET according to the example is significantly reduced to about 1 / 4 or less compared to the gate current of the polarized superjunction GaN-based FET according to the comparative example. In other words, graded Al y Ga 1-y It is clear that the introduction of the N layer 13 can significantly reduce gate leakage current.

[0049] Although embodiments of this invention have been described in detail above, this invention is not limited to the embodiments described above, and various modifications based on the technical idea of ​​this invention are possible.

[0050] For example, the numerical values, structures, shapes, and materials mentioned in the above-described embodiments are merely examples, and different numerical values, structures, shapes, and materials may be used as needed. [Explanation of Symbols]

[0051] 10...Substrate, 11...Undoped GaN layer, 12...Al x Ga 1-x N layer, 13... Graded Al y Ga 1-y N layer, 14...undoped GaN layer, 15...p-type GaN layer, 16...p + GaN layer, 17...gate electrode, 18...source electrode, 19...drain electrode, 20...2DHG, 21...2DEG, 22...p-type In z Ga 1-z N layer

Claims

1. The first semiconductor layer, A second semiconductor layer is located above the first semiconductor layer mentioned above, A third semiconductor layer having an island-like shape, located above the second semiconductor layer, The fourth semiconductor layer is located above the third semiconductor layer mentioned above, An intermediate layer between the second semiconductor layer and the third semiconductor layer, The source electrode and drain electrode on the second semiconductor layer described above, A gate electrode electrically connected to the above fourth semiconductor layer, It has, The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the intermediate layer are all group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first and third semiconductor layers. The above-mentioned intermediate layer is a graded layer in which the band gap increases continuously and / or stepwise from the band gap of the second semiconductor layer toward the interface between the second semiconductor layer and the intermediate layer toward the interface between the third semiconductor layer and the intermediate layer, and has a thickness such that carriers do not substantially move due to the tunneling effect. The first semiconductor layer and the third semiconductor layer are undoped semiconductor layers. The above-mentioned fourth semiconductor layer is a p-type semiconductor layer in a polarized superjunction field-effect transistor.

2. The first undoped GaN layer, Al above the first undoped GaN layer x Ga 1-x N layers (0.17 ≤ x ≤ 0.35) and The above Al x Ga 1-x A second undoped GaN layer, having an island-like shape, located above the N layer, The p-type GaN layer above the second undoped GaN layer, The above Al x Ga 1-x An intermediate layer between the N layer and the second undoped GaN layer, The above Al x Ga 1-x Source electrode and drain electrode on the N layer, The above p-type GaN layer and the electrically connected gate electrode, It has, The intermediate layer is the above Al x Ga 1-x N layer and the band gap increases continuously and / or stepwise from the interface between the x GaN layer and the intermediate layer toward the interface between the second undoped GaN layer and the intermediate layer, from the band gap of the x Al x Ga 1-x N layer, and is a graded x Al y Ga 1-y N layer (x ≦ y < 0.5), and has a thickness such that carriers do not substantially move due to the tunneling effect, a polarization superjunction field effect transistor.

3. The above Al y Ga 1-y The polarization superjunction field-effect transistor according to claim 2, wherein the thickness of the N-graded layer is 3 nm or more.

4. It has at least one transistor, The aforementioned transistor, The first semiconductor layer, A second semiconductor layer is located above the first semiconductor layer mentioned above, A third semiconductor layer having an island-like shape, located above the second semiconductor layer, The fourth semiconductor layer is located above the third semiconductor layer mentioned above, An intermediate layer between the second semiconductor layer and the third semiconductor layer, The source electrode and drain electrode on the second semiconductor layer described above, A gate electrode electrically connected to the above fourth semiconductor layer, It has, The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the intermediate layer are all group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first and third semiconductor layers. The above-mentioned intermediate layer is a graded layer in which the band gap increases continuously and / or stepwise from the band gap of the second semiconductor layer toward the interface between the second semiconductor layer and the intermediate layer toward the interface between the third semiconductor layer and the intermediate layer, and has a thickness such that carriers do not substantially move due to the tunneling effect. The first semiconductor layer and the third semiconductor layer are undoped semiconductor layers. The above-mentioned fourth semiconductor layer is a p-type semiconductor layer, and the electrical device is a polarized superjunction field-effect transistor.

5. It has at least one transistor, The aforementioned transistor, The first undoped GaN layer, Al above the first undoped GaN layer x Ga 1-x N layers (0.17 ≤ x ≤ 0.35) and The above Al x Ga 1-x A second undoped GaN layer, having an island-like shape, located above the N layer, The p-type GaN layer above the second undoped GaN layer, The above Al x Ga 1-x An intermediate layer between the N layer and the second undoped GaN layer, The above Al x Ga 1-x Source electrode and drain electrode on the N layer, The above p-type GaN layer and the electrically connected gate electrode, It has, The above intermediate layer is Al x Ga 1-x The band gap from the interface between the N layer and the intermediate layer toward the interface between the second undoped GaN layer and the intermediate layer is Al x Ga 1-x Graded Al, which increases continuously and / or stepwise from the band gap of the N layer y Ga 1-y An electrical device that is a polarized superjunction field-effect transistor having an N-layer (x ≤ y < 0.5) and a thickness such that carriers do not substantially move due to the tunneling effect.

Images