Memory system

Abstract

For example, this provides a memory system that can improve the increase in write time and write amount caused by using an SLC buffer. [Solution] According to the embodiment, the memory system comprises a non-volatile memory and a controller. The controller is connectable to a host and controls the non-volatile memory. The controller is configured to write data to the non-volatile memory using multiple write types with different data writing speeds based on information provided by the host, and to determine the write ratio of the multiple write types.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a memory system. [Background technology]

[0002] NAND flash memory typically supports multiple write types. For example, NAND flash memory that supports TLC (triple level cell) supports data writing using SLC (single level cell) in addition to TLC.

[0003] Writing using TLC allows for the storage of more data than writing using SLC. On the other hand, the data writing speed using TLC is slower than that of SLC. Thus, when writing to NAND flash memory, there is a trade-off between the amount of data written and the writing speed depending on the writing method.

[0004] Furthermore, even when writing data of the same number of bits to a single memory cell, there are differences between the Foggy-Fine method and the Full Sequence method. In the Foggy-Fine method, the same data is written to the memory cell through multiple write operations. In the Full Sequence method, data is written to the memory cell in a single write operation. The Foggy-Fine method is slower in writing speed and writes a larger amount of data than the Full Sequence method. The amount of data written to a single memory cell using the Foggy-Fine method is the same as the amount of data written using the Full Sequence method, but because multiple write operations are performed, the amount of data written using the Foggy-Fine method is greater than that written using the Full Sequence method.

[0005] Furthermore, there are times when high write speeds are not necessary while using a storage device. For example, when a storage device is downloading data to be written from the network, the network communication speed may be excessively slower than the storage device's write speed. In this case, the storage device's write speed is excessively fast.

[0006] One technique for improving the write speed of NAND flash memory is a mechanism called an SLC buffer. This mechanism temporarily improves the write speed by writing data using SLC instead of a slower write type such as TLC. The data temporarily written to the SLC buffer needs to be written back using a write type that has a larger data capacity per memory cell, such as TLC, during the storage device's idle time.

[0007] In this situation, the write speed of the storage device to the SLC buffer may be excessively fast compared to the communication speed when receiving the data from the host device. At this point, the storage device's write speed is excessively fast.

[0008] Furthermore, when writing data larger than the available capacity of the SLC buffer, it becomes necessary to rewrite the data in the SLC buffer to the normal storage area in order to create more free space than the insufficient capacity in the SLC buffer. For this reason, the write time when writing large amounts of data increases compared to when writing data smaller than the available capacity of the SLC buffer. Also, the write time when writing large amounts of data increases compared to when writing data to the normal storage area using TLC. Thus, if writing continues when the capacity of the SLC buffer is less than the amount of data to be written, the write speed will be slower and the write time will increase compared to writing using only the normal storage area.

[0009] Furthermore, NAND flash memory has a rewrite lifespan. The rewrite lifespan is the period until the number of data rewrites reaches its upper limit. Therefore, using an SLC buffer, which increases the amount of data written, shortens the lifespan of NAND flash memory. One indicator of NAND flash memory lifespan is called WAF (Write Amplification Factor). This is an amplification factor that shows how much data is actually written in the NAND flash memory relative to the amount of data instructed to be written from the host device.

[0010] Data written to the SLC buffer is migrated and written to the normal storage area. At this time, the data is written to match the number of bits stored per memory cell in the destination. Taking this into account, the WAF (Write-Aid Function) when data is written from the host device to the SLC buffer and finally migrated to the normal storage area to which TLC is applied is 4. For example, when writing 3 GiB of data via the SLC buffer to a normal storage area with a TLC block size of 3 GiB, the data is first written to 3 blocks in the SLC buffer. Then, the data is rewritten to 1 block in the normal storage area. Therefore, a total of 4 blocks are written. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0401341 [Patent Document 2] U.S. Patent Application Publication No. 2022 / 0057956 [Patent Document 3] U.S. Patent Application Publication No. 2015 / 0019801 [Patent Document 4] Japanese Patent Publication No. 2022-030146 [Overview of the project] [Problems that the invention aims to solve]

[0012] One embodiment of the present invention provides a memory system that can improve the write time and write amount, for example, by using an SLC buffer.

Means for Solving the Problems

[0013] According to an embodiment, a memory system includes a non-volatile memory and a controller. The controller is connectable to a host and controls the non-volatile memory. The controller is configured to write data to the non-volatile memory using a plurality of write types with different data write speeds based on information given from the host, and determine the write ratio of the plurality of write types.

Brief Description of the Drawings

[0015] The embodiments will be described below with reference to the drawings.

[0016] (First Embodiment) First, the first embodiment will be described.

[0017] Figure 1 shows an example configuration of the memory system 1 of the first embodiment. Figure 1 also shows an example configuration of an information processing system including the memory system 1 and a host 2 connected to the memory system 1. The host 2 is an information processing device such as a server or a personal computer.

[0018] The memory system 1 comprises a controller 11 and a flash memory 12. The flash memory 12 is a NAND flash memory that supports multiple write types.

[0019] Here, we show an example where the flash memory 12 supports two write types. A high-speed write type such as SLC is designated as Type A, and a slower write type compared to SLC, such as TLC, is designated as Type B. The Type A area 31 shown in Figure 1 conceptually represents an area where data has been written using the Type A write type, and the Type B area 32 conceptually represents an area where data has been written using the Type B write type.

[0020] Furthermore, the flash memory 12 may support not only two write types, but three or more. Also, the combination of write types A and B is not limited to a combination of SLC and TLC, but may be any two combination from among SLC, MLC (multi-level cell), TLC, QLC (quadruple-level cell), PLC (penta-level cell), etc. In other words, any storage device that uses a primary buffer to perform writing with a second number of storage bits per memory cell, which is smaller than the first number of storage bits per memory cell, in addition to an area where writing is performed with a first number of storage bits per memory cell with multiple values, in order to optimize the writing speed, can be applied as the memory system 1. The primary buffer is a storage area that has a faster writing speed than the storage area where the data is to be written, and is provided for temporarily writing data.

[0021] Furthermore, the combination of write types A and B may be such that both have the same number of memory bits per memory cell, with one being a Foggy-Fine write and the other a Full Sequence write. In other words, a storage device that uses both Foggy-Fine and Full Sequence writes as a primary buffer can also be applied as memory system 1.

[0022] In other words, various storage devices that support multiple write types with different speeds can be applied as the memory system 1 of the first embodiment.

[0023] The controller 11 is a device that writes data to and reads data from the flash memory 12 in response to commands from the host 2. The controller 11 can also configure the operation settings of the memory system 1 in response to commands from the host 2. The controller 11 is implemented, for example, as a SoC (system on a chip).

[0024] The controller 11 includes a processor 111, a host interface unit 112, and a memory interface unit 113.

[0025] The processor 111 executes various processes that the controller 11 should perform by running a program called firmware. These processes include writing data to the flash memory 12, reading data from the flash memory 12, and configuring the operation of the memory system 1, as mentioned above. In addition, the write ratio control unit 21 is one of the processing units realized by the processor 111 executing the firmware. The write ratio control unit 21 is a module that controls the write ratio of type A and type B write types to the flash memory 12 based on information provided by the host 2.

[0026] In this example, various processes that the controller 11 should perform are realized by the processor 111 executing firmware, but these may also be realized by dedicated hardware built into the controller 11, such as electrical circuits.

[0027] The host interface unit 112 controls communication with the host 2 in accordance with a predetermined communication standard. The memory interface unit 113 controls writing data to the flash memory 12 and reading data from the flash memory 12.

[0028] The memory system 1 of the first embodiment, having the configuration described above, performs writing to the flash memory 12 by mixing Type A write types and Type B write types in a ratio corresponding to the performance level when a parameter specifying the performance level is attached to the write command received from the host 2. In other words, the memory system 1 of the first embodiment enables the host 2 to specify the performance level when issuing a write command. The performance level is a value that indicates, for example, which stage out of a predetermined number of stages the writing speed requested from the memory system 1 is at. This parameter may be attached to the write command using, for example, one of a set of parameters prepared in advance. The vendor can arbitrarily define the use of the set of parameters. The ratio of write types according to the performance level specified by the host 2 is controlled by the write ratio control unit 21.

[0029] In the memory system 1 of the first embodiment, the write ratio for each write type corresponding to each performance level is pre-set at the time of shipment. The write ratio is stored in the write ratio control unit 21. When the controller 11 receives a write command from the host 2, it determines whether or not a parameter indicating the performance level is attached to the write command. If a parameter indicating the performance level is attached, the write control unit 21 references the write ratio corresponding to the performance level from the volatile memory. The controller 11 writes to the flash memory 12 using the ratio referenced by the write ratio control unit 21. If a parameter indicating the performance level is not attached to the write command, the controller 11 writes to the flash memory 12 with a predetermined write type.

[0030] In the memory system 1 of the first embodiment, the write ratio between type A write type and type B write type is predetermined for each performance level that can be specified by the host 2. The write ratio between type A write type and type B write type corresponding to each performance level must be determined based on the average write speed when writing to the flash memory 12 by mixing type A write type and type B write type. Here, for example, a method for calculating the average write speed when writing to the flash memory 12 by mixing type A write type and type B write type, which is tried during the design of the memory system 1, will be described.

[0031] For example, consider a case where the write ratio is set to Type A:Type B = 2:1 for a certain performance level k. In this case, the controller 11 controls the writing to the flash memory 12 so that 2 / 3 of the amount of data written by the write command is written with Type A write type and 1 / 3 is written with Type B write type. Let L be the amount of data to be written, and v be the write speed for Type A. a The write speed of Type B is v b Let α and β be the proportions of writing for each writing type. The writing speed v at this time is:

[0032]

number

[0033] The ratios α and β have the relationship α + β = 1 and β = 1 - α. Also, α and β are numbers between 0 and 1 (inclusive). Substituting these into the above equation,

[0034]

number

[0035] Based on the average write speed calculated as described above, the memory system 1 is configured with a write ratio between Type A write type and Type B write type, corresponding to each performance level.

[0036] The controller 11 writes data to the flash memory 12 by mixing Type A write types and Type B write types at a set ratio. At this time, it is preferable that the writing by Type A and writing by Type B are performed based on the size of the area managed by the controller 11 in the flash memory 12.

[0037] For example, when writing 9 MiB of data, if the controller 11 manages a size of 1 MiB and the write ratio is SLC buffer:normal storage (TLC) = 2:1, then the first 2 MiB of data is written to the SLC buffer. The next 1 MiB of data is written to normal storage. Then the next 2 MiB of data is written to the SLC buffer. Ultimately, 9 MiB of data is written alternately using each write type. In other words, the size of the flash memory 12 area managed by the controller 11 is the smallest unit in which the controller 11 changes the write type. In this way, data is written alternately to the area of ​​the flash memory 12 corresponding to each write type.

[0038] Furthermore, when the memory system 1 performs a mix of Type A and Type B write operations to the flash memory 12, it writes the data to the flash memory 12 via the controller 11's cache memory. At this time, the controller 11 alternately writes data of a size corresponding to the size of the cache memory to the respective areas of the flash memory 12 corresponding to each write operation. If the cache memory is small, the controller 11 alternately writes small data. Alternately writing small data can complicate data management within the controller 11. A more ideal average write speed can be achieved by increasing the size of the controller 11's cache memory. The controller 11's cache memory may be built into the controller 11 as SRAM (static RAM [random access memory]) or provided externally as DRAM (dynamic RAM) or similar. However, increasing the cache memory also increases the cost of the memory system 1, so it is necessary to set an appropriate size for the cache memory.

[0039] In the first embodiment, host 2 cannot calculate the average write speed of memory system 1 from the performance level. Therefore, host 2 estimates the average write speed from the past operating results of memory system 1 and specifies the performance level. Alternatively, host 2 may specify the performance level by setting the average write speed of memory system 1 as design information during the design of host 2.

[0040] Next, we will describe the WAF in the case where the memory system 1 of the first embodiment provides a flash memory area 12 corresponding to the type A write type for type B write types as a primary buffer, and there is a sufficient primary buffer.

[0041] When data is written using a primary buffer without utilizing the write ratio, and the data is ultimately migrated to normal storage, the WAF (Web Application Firewall) is w a Let's assume that the WAF is w when the data is ultimately migrated to normal storage using the write ratio. The write speed Va of type A in [Equation 1] is the write speed of the primary buffer, and the write speed V of type B is... b If we substitute the write speed of normal storage, the WAFw when using the write ratio will be expressed using the symbol in [Equation 1],

[0042]

number

[0043]

number

[0044] 1≧α≧0, w a Since ≥1, w a ≥w. WAFw when using the write ratio is WAFw when not using the write ratio. a It will be less than that.

[0045] Figure 2 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the first embodiment.

[0046] Host 2 sends a write command to memory system 1 with parameter a1 specifying the performance level (1). When the controller 11 of memory system 1 receives the write command with parameter a1 specifying the performance level, it determines the write ratio of type A writes to type B writes based on the specified performance level (2).

[0047] Based on the determined write ratio, the controller 11 of the memory system 1 performs two write operations to the flash memory 12: a write operation of type A (3-1) and a write operation of type B (3-2). Once the writing to the flash memory 12 is complete, the controller 11 of the memory system 1 sends a response to the write command to the host 2 (4).

[0048] Figure 3 is a flowchart showing the operation flow of the memory system 1 in the first embodiment when a write command is received.

[0049] The controller 11 determines whether or not a write command has been received from the host 2 (S101). If no write command has been received (S101: NO), the controller 11 terminates its operation related to the reception of the write command. If a write command has been received (S101: YES), the controller 11 determines whether or not a parameter specifying the performance level has been attached to the write command (S102).

[0050] If no parameter specifying the performance level is attached to the write command (S102: NO), the controller 11 performs a write to the flash memory 12 using a predetermined write type (S103). The predetermined write type may be a single predetermined write type, or it may be multiple write types with predetermined write ratios.

[0051] On the other hand, if a parameter specifying the performance level is attached to the write command (S102:YES), the controller 11 determines the ratio of write types based on the specified performance level (S104). The ratio of write types determined here may include cases where the ratio of one write type is 100%.

[0052] The controller 11 executes writes to the flash memory 12 using one or more write types based on the determined write ratio (S105).

[0053] As described above, in the memory system 1 of the first embodiment, writing is performed at a write ratio that sufficiently satisfies the performance level specified by the host 2, thereby suppressing writing of low-capacity write types. This suppresses migration processing from low-capacity write types to high-capacity write types during writing, and shortens the final write completion time. In addition, since the amount of data written is reduced by suppressing migration processing, the number of rewrite cycles of the flash memory 12 is reduced, and its lifespan can be improved.

[0054] Furthermore, the memory system 1 of the first embodiment optimizes the write speed by writing at a write ratio that sufficiently satisfies the performance level specified by the host 2. This eliminates situations where, for example, the write speed becomes excessive in relation to the host 2's requests.

[0055] (Second Embodiment) Next, a second embodiment will be described. It is assumed that the memory system 1 of the second embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0056] In the second embodiment, unlike the first embodiment, no parameter specifying the performance level is attached to the write command. The memory system 1 of the second embodiment operates based on a pre-specified performance level for all received write commands.

[0057] The memory system 1 of the second embodiment has the same write control as the memory system 1 of the first embodiment. The memory system 1 of the second embodiment performs writing with one or more write types at a write ratio corresponding to a pre-specified performance level.

[0058] Similar to the memory system 1 of the first embodiment, the memory system 1 of the second embodiment can be applied to various storage devices that, as a write type, use a primary buffer in addition to an area where a first number of storage bits per memory cell with multiple values, such as MLC, TLC, QLC, and PLC, is written, and an area where a second number of storage bits per memory cell, such as SLC, MLC, TLC, and QLC, is written, which is less than the first number of storage bits per memory cell. The combination of the number of storage bits per memory cell is not limited. Furthermore, even when the number of storage bits per memory cell is the same, the memory system 1 of the second embodiment can be applied to any storage device that uses multiple write types with different speeds, such as a storage device that uses both Foggy-Fine and Full Sequence methods.

[0059] Figure 4 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the second embodiment.

[0060] Prior to sending a write command to memory system 1, host 2 sends a configuration command b1 to memory system 1 with a parameter b2 specifying the performance level (1). When memory system 1's controller 11 receives configuration command b1 with the parameter b2 specifying the performance level, it determines and sets the write ratio between type A writes and type B writes based on the specified performance level (2). Once the write ratio setting is complete, memory system 1's controller 11 sends a response to the configuration command to host 2 (3).

[0061] After sending the configuration command b1 to memory system 1, host 2 sends a write command to memory system 1 (4). The write command does not include any parameters specifying the performance level.

[0062] When the controller 11 of memory system 1 receives a write command, it performs two actions based on the write ratio set when it received the setting command b1: writing data to the flash memory 12 with type A write (5-1) and writing data to the flash memory 12 with type B write (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of memory system 1 sends a response to the write command to the host 2 (6).

[0063] Figure 5 is a flowchart showing the operation flow of the memory system 1 in the second embodiment when a write command is received.

[0064] The controller 11 determines whether or not a performance level setting command has been received from the host 2 (S201). If a setting command has been received (S201:YES), the controller 11 determines and sets the ratio of write types based on the specified performance level (S202). If a setting command has not been received (S201:NO), the controller 11 skips the processing in step S202.

[0065] Next, the controller 11 determines whether or not a write command has been received from the host 2 (S203). If a write command has been received (S203: YES), the controller 11 executes data writing to the flash memory 12 with one or more write types based on the configured write ratio (S204). If a write command has not been received (S203: NO), the controller 11 terminates its operation related to the reception of a write command.

[0066] As described above, in the memory system 1 of the second embodiment, the processing related to the write ratio for each write command is reduced by specifying the performance level in advance. This makes it possible to optimize the write speed.

[0067] (Third embodiment) Next, a third embodiment will be described. It is assumed that the memory system 1 of the third embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0068] In the third embodiment, instead of the performance level in the first embodiment, a parameter specifying the ratio of write types is added to the write command.

[0069] Host 2 adds a parameter to the write command that specifies the write ratio. The controller 11 of memory system 1 writes the received data to the flash memory 12 for each write type at the specified write ratio.

[0070] In other words, in the third embodiment, the host 2 directly specifies the write ratio for each write command. By directly specifying the write ratio, the host 2 can explicitly control the usage of the flash memory 12.

[0071] For example, writing using SLC consumes three times the capacity of the flash memory 12 compared to writing using TLC. In the third embodiment, by enabling the host 2 to be aware of this physical capacity consumption, writing can be performed while considering the performance degradation of the memory system 1. Similar to the first embodiment, the combination of writing types is not limited to the combination of SLC and TLC, but various combinations of writing types can be applied.

[0072] Figure 6 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the third embodiment.

[0073] Host 2 sends a write command to memory system 1 with parameter c1 specifying the ratio of write types (1). When the controller 11 of memory system 1 receives a write command with parameter c1 specifying the ratio of write types, it performs two actions based on the specified ratio: writing data to flash memory 12 with type A write type (2-1) and writing data to flash memory 12 with type B write type (2-2).

[0074] Once the data has been written to the flash memory 12, the controller 11 of the memory system 1 sends a response to the write command to the host 2 (3).

[0075] Figure 7 is a flowchart showing the operation flow of the memory system 1 in the third embodiment when a write command is received.

[0076] The controller 11 determines whether or not a write command has been received from the host 2 (S301). If no write command has been received (S301: NO), the controller 11 terminates its operation related to the reception of the write command. If a write command has been received (S301: YES), the controller 11 determines whether or not a parameter specifying the ratio of write types has been added to the write command (S302).

[0077] If no parameter specifying the ratio of write types is attached to the write command (S302: NO), the controller 11 executes the writing of data to the flash memory 12 using the default write type (S303). The default write type may be a single predetermined write type, or it may be multiple write types with predetermined write ratios.

[0078] On the other hand, if a parameter specifying the ratio of write types is attached to the write command (S302:YES), the controller 11 executes data writing to the flash memory 12 with one or more write types based on the specified write ratio (S304).

[0079] As described above, in the memory system 1 of the third embodiment, the host 2 can understand and control the amount of data that can be written by specifying the write ratio.

[0080] (Fourth Embodiment) Next, a fourth embodiment will be described. It is assumed that the memory system 1 of the fourth embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0081] In the fourth embodiment, instead of the performance level in the second embodiment, a ratio of write types is specified in the setting command. The memory system 1 in the fourth embodiment operates based on the pre-specified ratio of write types for all received write commands.

[0082] In the fourth embodiment, the host 2 first sets the write ratio for the memory system 1. Thereafter, the memory system 1 performs writing at the specified write ratio.

[0083] In the fourth embodiment, the host 2 directly specifies the write ratio for each write type. This makes it easier for the host 2 to understand the remaining capacity of the memory system 1.

[0084] Figure 8 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the fourth embodiment.

[0085] Prior to sending a write command to memory system 1, host 2 sends a configuration command d1 to memory system 1 with a parameter d2 specifying the ratio of write types (1). When memory system 1's controller 11 receives configuration command d1 with the parameter d2 specifying the ratio of write types, it sets the specified write ratio (2). Once the write ratio setting is complete, memory system 1's controller 11 sends a response to the configuration command to host 2 (3).

[0086] After sending the configuration command d1 to memory system 1, host 2 sends a write command to memory system 1 (4). The write command does not include any parameters specifying the ratio of write types.

[0087] When the controller 11 of memory system 1 receives a write command, it performs two actions based on the write ratio set when it received the setting command d1: writing data to the flash memory 12 using type A write (5-1) and writing data to the flash memory 12 using type B write (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of memory system 1 sends a response to the write command to the host 2 (6).

[0088] Figure 9 is a flowchart showing the operation flow of the memory system 1 in the fourth embodiment when a write command is received.

[0089] The controller 11 determines whether or not a command to set the ratio of write types has been received from the host 2 (S401). If a setting command has been received (S401: YES), the controller 11 sets the specified ratio of write types (S402). If a setting command has not been received (S401: NO), the controller 11 skips the processing in step S402.

[0090] Next, the controller 11 determines whether or not a write command has been received from the host 2 (S403). If a write command has been received (S403: YES), the controller 11 executes data writing to the flash memory 12 with one or more write types based on the configured write ratio (S404). If a write command has not been received (S403: NO), the controller 11 terminates its operation related to the reception of a write command.

[0091] As described above, in the memory system 1 of the fourth embodiment, in addition to the effects of the memory system 1 of the third embodiment, the processing related to the write ratio for each write command is reduced, so that the write speed can be optimized.

[0092] (Fifth embodiment) Next, a fifth embodiment will be described. It is assumed that the memory system 1 of the fifth embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0093] In the fifth embodiment, instead of the performance level in the first embodiment, a parameter specifying throughput is added to the write command.

[0094] Host 2 sends a write command to memory system 1 with a parameter specifying the desired throughput. Throughput refers to the amount of data that controller 13 writes to flash memory 12 per unit time. Based on the specified throughput, controller 11 of memory system 1 determines the write ratio, taking into account the write speed of each write type.

[0095] In the fifth embodiment, the following formula is used to convert the write rate to the average write speed, and, contrary to the first embodiment, the average write speed v is given, and the write rate α for type A writes and the write rate β for type B writes are determined.

[0096] v a v ≥ v ≥ v b In the case of, [Equation 1] can be transformed as follows.

[0097]

Equation

[0098]

Equation

[0099] Since the writing ratio of each writing type is determined by the above equation, the controller 11 performs writing according to the writing ratio, similar to the first embodiment.

[0100] However, it may be difficult to perform this calculation for each write command. In such a case, at the time of starting up the memory system 1, the throughput and performance level are made to correspond between the memory system 1 and the host 2. Thereafter, for each write command, the host 2 may specify the throughput corresponding to the performance level. Thereby, the calculation load for each write command can be reduced.

[0101] ​In the fifth embodiment, the required write speed can be directly specified on the host 2 side, increasing the convenience of the memory system 1. Furthermore, the impact of the throughput of each write type can be hidden from the host 2 side on the memory system 1 side. As a result, the host 2 does not need to consider information about each write type of the memory system 1.

[0102] Figure 10 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the fifth embodiment.

[0103] Host 2 sends a write command to memory system 1 with parameter e1 specifying throughput (1). When the controller 11 of memory system 1 receives the write command with parameter e1 specifying throughput, it calculates the write ratio of type A writes to type B writes based on the specified throughput (2).

[0104] Based on the calculated write ratio, the controller 11 of the memory system 1 performs two write operations to the flash memory 12: a write operation of type A (3-1) and a write operation of type B (3-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of the memory system 1 sends a response to the write command to the host 2 (4).

[0105] Figure 11 is a flowchart showing the operation flow of the memory system 1 in the fifth embodiment when a write command is received.

[0106] The controller 11 determines whether or not a write command has been received from host 2 (S501). If no write command has been received (S501: NO), the controller 11 terminates its operation related to the reception of the write command. If a write command has been received (S501: YES), the controller 11 determines whether or not a parameter specifying throughput has been added to the write command (S502).

[0107] If no parameter specifying throughput is attached to the write command (S502: NO), the controller 11 executes data writing to the flash memory 12 using a predetermined write type (S503). The predetermined write type may be a single predetermined write type, or it may be multiple write types with predetermined write ratios.

[0108] On the other hand, if a parameter specifying throughput is attached to the write command (S502:YES), the controller 11 calculates the ratio of write types based on the specified throughput (S504). The ratio of write types calculated here may include cases where the ratio of one write type is 100%.

[0109] The controller 11 executes data writing to the flash memory 12 using one or more write types based on the calculated write ratio (S505).

[0110] As described above, in the memory system 1 of the fifth embodiment, the host 2 can write data to the memory system 1 simply by specifying the throughput, without having to consider the write speed of each type of write operation of the memory system 1.

[0111] (Sixth Embodiment) Next, a sixth embodiment will be described. It is assumed that the memory system 1 of the sixth embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0112] In the sixth embodiment, throughput is specified in the configuration command instead of the performance level as in the second embodiment. The memory system 1 of the sixth embodiment calculates and sets the ratio of write types according to the specified throughput and operates based on the pre-configured ratio of write types for all received write commands.

[0113] In the sixth embodiment, the host 2 first sets the throughput for the memory system 1. The memory system 1 calculates and sets the write ratio corresponding to the specified throughput using the formula described above. Thereafter, the memory system 1 writes data to the flash memory 12 at the set write ratio.

[0114] The sixth embodiment, like the fourth embodiment, is a mechanism that makes it easy for the host 2 to set a desired write speed for the memory system 1.

[0115] Figure 12 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the sixth embodiment.

[0116] Prior to sending a write command to memory system 1, host 2 sends a configuration command f1 to memory system 1 with a parameter f2 specifying throughput (1). When memory system 1's controller 11 receives configuration command f1 with the throughput parameter f2 attached, it calculates and sets the write ratio between type A writes and type B writes based on the specified throughput (2). Once the write ratio setting is complete, memory system 1's controller 11 sends a response to the configuration command to host 2 (3).

[0117] After sending the configuration command f1 to memory system 1, host 2 sends a write command to memory system 1 (4). The write command does not include any parameters specifying throughput.

[0118] When the controller 11 of memory system 1 receives a write command, it performs two actions based on the write ratio set when it received the setting command f1: writing data to the flash memory 12 with type A write (5-1) and writing data to the flash memory 12 with type B write (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of memory system 1 sends a response to the write command to the host 2 (6).

[0119] Figure 13 is a flowchart showing the operation flow of the memory system 1 in the sixth embodiment when a write command is received.

[0120] The controller 11 determines whether or not a throughput setting command has been received from the host 2 (S601). If a setting command has been received (S601: YES), the controller 11 calculates and sets the ratio of write types based on the specified throughput (S602). If a setting command has not been received (S601: NO), the controller 11 skips the processing in step S602.

[0121] Next, the controller 11 determines whether or not a write command has been received from the host 2 (S603). If a write command has been received (S603: YES), the controller 11 executes data writing to the flash memory 12 with one or more write types based on the configured write ratio (S604). If a write command has not been received (S603: NO), the controller 11 terminates its operation related to the reception of a write command.

[0122] As described above, in the memory system 1 of the sixth embodiment, in addition to the effects of the memory system 1 of the fifth embodiment, the processing related to the write ratio for each write command is reduced, so that the write speed can be optimized.

[0123] (Seventh Embodiment) Next, the seventh embodiment will be described. It is assumed that the memory system 1 of the seventh embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0124] In the first to sixth embodiments, write control is performed using instantaneous write speed as an indicator. In the seventh embodiment, information on the amount to be written is transmitted in advance from the host 2 to the memory system 1, and the memory system 1 controls the write time to be minimized based on that information.

[0125] In the seventh embodiment, first, the amount of data expected to be written from the host 2 to the memory system 1 within a certain period is set. This period is, for example, roughly until the writing from the host 2 is completed and the memory system 1 has an opportunity to perform background processing for its own maintenance.

[0126] The controller 11 of the memory system 1 calculates the write ratio that allows data to be written in the shortest time based on the usage status of the flash memory 12.

[0127] When the estimated amount of data is set by the host 2, the controller 11 calculates the maximum usable primary buffer size. If e is the free capacity in the flash memory 12, L is the amount of data to be written, and i is the capacity ratio, which is the ratio of the amount of data written to one memory cell by a slow write type to the amount of data written to one memory cell by a high-speed write type, then the relationship shown in [Equation 7] holds.

[0128]

number

[0129] Furthermore, the maximum usable primary buffer size s can be obtained by rearranging [Equation 7] and using the formula [Equation 8].

number

[0130] To calculate the write ratios α and β for each write type, you can do so as follows.

[0131]

number

[0132] For example, when calculating the write ratio between SLC and TLC, the calculation can be performed using the formulas [Equation 7], [Equation 8], and [Equation 9], where e is the free space in the flash memory 12 converted assuming normal writing to storage (writing with TLC), and i is 3, which is the capacity ratio between SLC and TLC.

[0133] The controller 11 secures the SLC buffer size according to the ratio in the above formula and writes data in the same manner as in the second embodiment. The average writing speed at this time can be estimated by [Equation 1]. Furthermore, the combination of a high-speed writing type and a low-speed writing type is not limited to the combination of SLC and TLC. Similar to the second embodiment, combinations of writing types other than SLC and TLC are also applicable.

[0134] Figure 14 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the seventh embodiment.

[0135] Prior to sending a write command to memory system 1, host 2 sends a configuration command g1 to memory system 1 with a parameter g2 specifying the total amount to be written (1). When memory system 1's controller 11 receives configuration command g1 with the parameter g2 specifying the total amount to be written, it calculates and sets the write ratio between type A writes and type B writes based on the specified total amount to be written (2). Once the write ratio setting is complete, memory system 1's controller 11 sends a response to the configuration command to host 2 (3).

[0136] After sending the configuration command g1 to memory system 1, host 2 sends a write command to memory system 1 (4). The write command does not include a parameter specifying the total amount to be written.

[0137] When the controller 11 of memory system 1 receives a write command, it performs two actions based on the write ratio set when it received the setting command g1: writing data to the flash memory 12 using type A write (5-1) and writing data to the flash memory 12 using type B write (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of memory system 1 sends a response to the write command to the host 2 (6).

[0138] Figure 15 is a flowchart showing the operation flow when a write command is received by the memory system 1 of the seventh embodiment.

[0139] The controller 11 determines whether or not a command to set the total amount of writes has been received from the host 2 (S701). If a setting command has been received (S701: YES), the controller 11 calculates and sets the ratio of write types based on the specified total amount of writes (S702). If a setting command has not been received (S701: NO), the controller 11 skips the processing in step S702.

[0140] Next, the controller 11 determines whether or not a write command has been received from the host 2 (S703). If a write command has been received (S703: YES), the controller 11 writes data to the flash memory 12 with one or more write types based on the configured write ratio (S704). If a write command has not been received (S703: NO), the controller 11 terminates its operation related to the reception of the write command.

[0141] For example, in the memory system 1 of the second embodiment, migration processing is performed when a larger amount of data than expected is written, which may result in the expected effect not being achieved. In the memory system 1 of the seventh embodiment, the occurrence of data being written in excess of what was expected is mitigated, and the effects of the memory system 1 of the second embodiment can be obtained more reliably.

[0142] Furthermore, in the memory system 1 of the seventh embodiment, the controller 11 performs write control considering the usage status of the flash memory 12, thereby achieving the shortest possible write time.

[0143] (Eighth embodiment) Next, the eighth embodiment will be described. It is assumed that the memory system 1 of the eighth embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0144] In the eighth embodiment, the write time is specified by a setting command instead of the performance level as in the second embodiment. The memory system 1 of the eighth embodiment calculates the throughput when writing data for the specified time based on the usage status of the flash memory 12. The memory system 1 of the eighth embodiment further calculates and sets the ratio of write types according to the calculated throughput, and operates based on the set ratio of write types for all received write commands.

[0145] Let's consider using up the free space e in flash memory 12 within a time t specified by host 2. We allocate e between the primary buffer and normal storage, and let L be the amount of data that can be written from host 2 as a result of this allocation. Here, L is a value that indicates how much data size can be written from host 2, similar to [Equation 7]. e is the free space in flash memory 12 converted assuming writing to normal storage. Based on the above, the relationship between e, t, and s is given by equation [Equation 10].

[0146]

number

[0147] From equation [Equation 10], the size of the primary buffer s when e is written completely in t can be calculated. Similarly, considering equation [Equation 7], the write ratio can be calculated as follows.

[0148]

number

[0149] By writing at the write ratio calculated in this way, e is used up within the specified time. After securing the primary buffer size s calculated by formula [Equation 10], data is written in the same manner as in the second embodiment. The write type when writing data to the primary buffer may be SLC, and the write type when writing data to the normal storage may be TLC. Furthermore, the combination of write types that can be written to the primary buffer and write types that are written to the normal storage is not limited to the combination of SLC and TLC. As in the second embodiment, combinations of write types other than SLC and TLC are also applicable.

[0150] Figure 16 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the eighth embodiment.

[0151] Prior to sending a write command to memory system 1, host 2 sends a configuration command h1 to memory system 1 with a parameter h2 specifying the write time (1). When memory system 1's controller 11 receives configuration command h1 with the parameter h2 specifying the write time, it calculates and sets the write ratio between type A writes and type B writes based on the specified write time (2). Once the write ratio setting is complete, memory system 1's controller 11 sends a response to the configuration command to host 2 (3).

[0152] After sending the configuration command h1 to memory system 1, host 2 sends a write command to memory system 1 (4). The write command does not include a parameter specifying the write time.

[0153] When the controller 11 of memory system 1 receives a write command, it performs two actions based on the write ratio set when the setting command h1 was received: writing data to the flash memory 12 using type A write (5-1) and writing data to the flash memory 12 using type B write (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of memory system 1 sends a response to the write command to the host 2 (6).

[0154] Figure 17 is a flowchart showing the operation flow of the memory system 1 in the eighth embodiment when a write command is received.

[0155] The controller 11 determines whether or not a write time setting command has been received from the host 2 (S801). If a setting command has been received (S801: YES), the controller 11 calculates and sets the ratio of write types based on the specified write time (S802). If a setting command has not been received (S801: NO), the controller 11 skips the processing in step S802.

[0156] Next, the controller 11 determines whether or not a write command has been received from the host 2 (S803). If a write command has been received (S803: YES), the controller 11 executes data writing to the flash memory 12 with one or more write types based on the configured write ratio (S804). If a write command has not been received (S803: NO), the controller 11 terminates its operation related to the reception of the write command.

[0157] As described above, in the memory system 1 of the eighth embodiment, in addition to the effects of the memory system 1 of the second embodiment, the scheduling of command issuance processing on the host 2 can be made easier by specifying the write time.

[0158] (Ninth Embodiment) Next, the ninth embodiment will be described. The ninth embodiment shows an example of the behavior of the memory system 1 when the performance level (first embodiment) and throughput (fifth embodiment) are specified by parameters of a write command from multiple hosts 2.

[0159] Figure 18 shows an example configuration of an information processing system including a memory system 1 according to the ninth embodiment and a host 2 connected to the memory system 1.

[0160] As shown in Figure 18, the controller 11 of the memory system 1 in the ninth embodiment can receive commands from multiple hosts 2. Here, we will proceed with an example where write commands with parameters specifying the performance level are received from multiple hosts 2 (referred to as host[1] and host[2]).

[0161] In the ninth embodiment, when the controller 11 of the memory system 1 receives write commands from multiple hosts 2 with parameters specifying the performance level, it increases the performance level within the memory system 1 to satisfy all performance requests from the multiple hosts 2. The controller 11 sequentially decreases the performance level within the memory system 1 as each write command is completed.

[0162] For example, if a first write command from host [1] specifies performance level 1 and a second write command from host [2] specifies performance level 3, the controller 11 sets the internal performance level of the memory system 1 to performance level 4. The controller 11 writes the data from the first write command and the data from the second write command to the flash memory 12 at a write ratio corresponding to performance level 4.

[0163] When controller 11 completes the execution of a write command with performance level 1 specified, it reduces the performance level within the memory system 1 from performance level 4 to performance level 3. That is, when controller 11 completes the writing of the data for the first write command, it reduces the performance level to 3. At performance level 3, controller 11 writes the data for the second write command to the flash memory 12.

[0164] As another example, if a third write command from host[1] specifies a throughput of 1 GiB / s and a fourth write command from host[2] specifies a throughput of 2 GiB / s, the controller 11 will operate memory system 1 with a throughput of 3 GiB / s. Once the controller 11 has finished executing the third write command specifying a throughput of 1 GiB / s, it will operate memory system 1 with a throughput of 2 GiB / s.

[0165] As a result, the memory system 1 of the ninth embodiment can fully obtain the effects of the memory system 1 of the first embodiment and the fifth embodiment, even when performance levels and throughput are specified by multiple hosts 2.

[0166] (Tenth embodiment) Next, the tenth embodiment will be described. The tenth embodiment shows an example of the behavior of the memory system 1 when the performance level (second embodiment), throughput (sixth embodiment), total write amount (seventh embodiment), and write time (eighth embodiment) are specified by setting commands from multiple hosts 2.

[0167] Similar to the memory system 1 of the ninth embodiment, the controller 11 of the memory system 1 of the tenth embodiment can receive commands from multiple hosts 2. Here, we will proceed with an example where a configuration command with parameters specifying the performance level is received from multiple hosts 2.

[0168] In the tenth embodiment, when the controller 11 of the memory system 1 receives a configuration command from multiple hosts 2 with parameters specifying the performance level, it increases the performance level within the memory system 1 so that all performance requests from the multiple hosts 2 can be met. Based on the increased performance level, the controller 11 determines and sets the write ratios for multiple write types.

[0169] Furthermore, in response to instructions from each host 2 to deactivate the performance level setting, the controller 11 reduces the performance level within the memory system 1. Based on the reduced performance level, the controller 11 determines and sets the write ratios for multiple write types.

[0170] For example, if host [1] specifies performance level 1 by a first configuration command and host [2] specifies performance level 3 by a second configuration command, the controller 11 sets the performance level inside the memory system 1 to performance level 4. The controller 11 writes the data of the write command from host 2 to the flash memory 12 at a write ratio corresponding to performance level 4.

[0171] If the host [1] instructs the controller 11 to deactivate performance level 1, the controller 11 reduces the performance level within the memory system 1 from performance level 4 to performance level 3.

[0172] As a result, the memory system 1 of the 10th embodiment can fully obtain the effects of the memory systems 1 of the 2nd, 6th, 7th, and 8th embodiments, even when performance levels, throughput, total write volume, and write time are specified by multiple hosts 2.

[0173] (11th embodiment) Next, the 11th embodiment will be described. It is assumed that the memory system 1 of the 11th embodiment has the same configuration as the memory system 1 of the first embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0174] The eleventh embodiment is an example in which the memory system 1 has a performance information output mechanism so that the host 2 can determine the performance level, the ratio of write types, throughput, write time, etc. Here, we will proceed with the explanation using the case in which the host 2 specifies the performance level to the memory system 1 as an example.

[0175] Before specifying a performance level, Host 2 queries Memory System 1 for performance information. This performance information includes the throughput corresponding to the performance level, the generation information of Flash Memory 12, the upper and lower limits of the throughput that Memory System 1 can achieve, and the percentage increase in the amount of writes to the primary buffer. Performance information refers to all the information necessary to determine the performance level. In response to the query from Host 2, Memory System 1 sends the performance information to Host 2.

[0176] Host 2 determines which performance level to use in which situation based on the performance information obtained from memory system 1. Memory system 1 operates as memory system 1 in the first and second embodiments based on the performance level specified by host 2.

[0177] Figure 19 is a sequence diagram showing the operation procedure for writing data in an information processing system including the memory system 1 of the 11th embodiment.

[0178] Prior to sending a write command to memory system 1, host 2 queries memory system 1 for performance information (1). Upon receiving this query, the controller 11 of memory system 1 sends the performance information of memory system 1 to host 2 (2).

[0179] Host 2 determines the performance level based on the performance information received from memory system 1 and sends a write command to memory system 1 with parameter a1 specifying the determined performance level (3).

[0180] When the controller 11 of the memory system 1 receives a write command with parameter a1 specifying the performance level, it determines the write ratio of type A write type to type B write type based on the specified performance level (4). Based on the determined write ratio, the controller 11 of the memory system 1 performs two write operations: writing data to the flash memory 12 using type A write type (5-1) and writing data to the flash memory 12 using type B write type (5-2). Once the writing of data to the flash memory 12 is complete, the controller 11 of the memory system 1 sends a response to the write command to the host 2 (6).

[0181] Figure 20 is a flowchart showing the operation flow of the memory system 1 in the 11th embodiment when a write command is received.

[0182] The controller 11 determines whether or not it has received a query for performance information from the host 2 (S901). If it has received a query (S901: YES), the controller 11 sends the performance information of the memory system 1 to the host 2 (S902). If it has not received a query (S901: NO), the controller 11 skips the processing in step S902.

[0183] Furthermore, the controller 11 determines whether or not a write command has been received from the host 2 (S903). If no write command has been received (S903: NO), the controller 11 terminates its operation related to the reception of the write command. If a write command has been received (S903: YES), the controller 11 determines whether or not a parameter specifying the performance level has been added to the write command (S904).

[0184] If no parameter specifying the performance level is attached to the write command (S904: NO), the controller 11 performs a write to the flash memory 12 using a predetermined write type (S905). The predetermined write type may be a single predetermined write type, or it may be multiple write types with predetermined write ratios.

[0185] On the other hand, if a parameter specifying the performance level is attached to the write command (S904:YES), the controller 11 determines the ratio of write types based on the specified performance level (S906). The ratio of write types determined here may include cases where the ratio of one write type is 100%.

[0186] The controller 11 executes data writing to the flash memory 12 using one or more write types based on the determined write ratio (S907).

[0187] As described above, in the memory system 1 of the 11th embodiment, the host 2 can determine the characteristics of the connected memory system 1 and then cause the memory system 1 to perform an operation that provides the effects of any of the memory systems 1 from the first to the tenth embodiment.

[0188] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0189] 1...Memory system, 2...Host, 11...Controller, 12...Flash memory, 21...Write ratio control unit, 31...Type A area, 32...Type B area, 111...Processor, 112...Host interface unit, 113...Memory interface unit.

Claims

1. Non-volatile memory and A controller that can connect to a host and controls the non-volatile memory, It is equipped with, The controller writes data to the non-volatile memory using multiple write types with different data writing speeds, based on information provided by the host. The settings are configured to determine the write ratio of the aforementioned multiple write types. Memory system.

2. The aforementioned controller, Upon receiving a first write command specifying the writing of the first data, The system is configured to write the first data to the non-volatile memory by mixing two or more of the aforementioned plurality of write types. The memory system according to claim 1.

3. The information provided by the host is information regarding the write speed, The controller is configured to, upon receiving a write command from the host with a parameter specifying information regarding the write speed, determine the write ratio of the multiple write types according to the information regarding the write speed, and write data to the non-volatile memory by mixing the multiple write types at the determined ratio. The memory system according to claim 1.

4. The controller includes volatile memory, The controller is configured to write data to the non-volatile memory by mixing the multiple write types at the write ratio that was stored in the volatile memory before receiving the write command, if the parameter is not attached to the write command. The memory system according to claim 3.

5. The information regarding the aforementioned write speed is a performance level. The memory system according to claim 3.

6. The aforementioned controller, It can connect to multiple hosts, When multiple write commands, each with a parameter specifying a performance level, are received from each of the multiple hosts, the system is configured to calculate a total performance level by summing the performance levels specified by the parameters attached to the write commands received from each of the multiple hosts, determine the write ratio according to the calculated performance level, and write data to the non-volatile memory by mixing the multiple write types at the determined ratio. The memory system according to claim 5.

7. The information relating to the writing speed is throughput. The memory system according to claim 3.

8. The aforementioned controller, It can connect to multiple hosts, When multiple write commands, each with a parameter specifying throughput, are received from each of the multiple hosts, the system is configured to calculate the total throughput by summing the throughputs specified by the parameters attached to the write commands received from each of the multiple hosts, determine the write ratio according to the calculated throughput, and then mix the multiple write types at the determined ratio to write data to the non-volatile memory. The memory system according to claim 7.

9. The controller is configured to, upon receiving a write command from the host with the write ratios of the multiple write types attached, to write the data to the non-volatile memory by mixing the multiple write types according to the write ratios. The memory system according to claim 1.

10. The aforementioned controller, When a configuration command with parameters specifying information about the write speed is received from the host, the write ratio is determined according to the information about the write speed. After receiving the aforementioned setting command, if a write command is received from the host, the system is configured to write data to the non-volatile memory using the multiple write types at the determined write ratio. The memory system according to claim 1.

11. The information regarding the aforementioned write speed is a performance level. The memory system according to claim 10.

12. The aforementioned controller, It can connect to multiple hosts, When multiple configuration commands, each with a parameter specifying a performance level, are received from each of the multiple hosts, the system is configured to calculate a total performance level by summing the performance levels specified by the parameters attached to the configuration commands received from each of the multiple hosts, and to determine the write ratio according to the calculated performance level. The memory system according to claim 11.

13. The information regarding the write speed is throughput, which is the amount of data written per unit time. The memory system according to claim 10.

14. The aforementioned controller, It can connect to multiple hosts, When multiple configuration commands, each with a parameter specifying throughput, are received from each of the multiple hosts, the system is configured to calculate the total throughput by summing the throughputs specified by the parameters attached to the configuration commands received from each of the multiple hosts, and to determine the write ratio according to the calculated throughput. The memory system according to claim 13.

15. The information regarding the writing speed is the total amount written. The memory system according to claim 10.

16. The aforementioned controller, It can connect to multiple hosts, When multiple configuration commands, each with a parameter specifying the total amount of writes, are received from each of the multiple hosts, the system is configured to calculate the sum of the total amount of writes specified by the parameters attached to the configuration commands received from each of the multiple hosts, and to determine the write ratio of the multiple write types according to the calculated sum of the total amount of writes. The memory system according to claim 15.

17. The information relating to the writing speed is the writing time. The memory system according to claim 10.

18. The aforementioned controller, It can connect to multiple hosts, When multiple configuration commands, each with a parameter specifying the write time, are received from each of the multiple hosts, the system is configured to calculate the total write time by summing the write times specified by the parameters attached to the configuration commands received from each of the multiple hosts, and to determine the write ratio according to the calculated write time. The memory system according to claim 17.

19. The aforementioned controller, When a configuration command with a parameter specifying the write ratio is received from the host, the write ratio specified by the parameter is set. After receiving the aforementioned setting command, if a write command is received from the host, the system is configured to write data to the non-volatile memory by mixing the multiple write types at the configured write ratio. The memory system according to claim 1.

20. The controller is configured to send performance information of the memory system to the host when it receives an inquiry from the host regarding the performance of the memory system. The memory system according to any one of claims 1 to 18.

Images