Indium gallium nitride structures and devices

Abstract

The present invention provides an indium gallium nitride (InGaN) layer having a substantially relaxed region, and a device fabricated on the InGaN layer. [Solution] An InGaN layer is disclosed, characterized in that its in-plane lattice constant is in the range of 3.19 Å to 3.50 Å. The InGaN layer is grown by accreting InGaN grown on multiple GaN seed regions. This InGaN layer can be used to fabricate optical and electronic devices for use as light sources in lighting and display applications.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 16 / 689,0. It was filed on November 19, 2019.

[0002] This disclosure relates to an indium gallium nitride (InGaN) layer having a substantially relaxed region and a device fabricated on the InGaN layer. The substantially relaxed wurtzite-type (0001) InGaN region has an in-plane, i.e., “a” lattice constant of 3.19 Å or more. The substantially relaxed InGaN region is grown on a plurality of group III nitride seed regions such as a GaN, InGaN, AlGaN, or AlN seed region. During growth, the InGaN grown on the seed region relaxes and coalesces to provide a substantially relaxed InGaN region that can be used as a growth surface for other semiconductor materials. This InGaN layer can be used to fabricate optical and electronic devices for use as light sources in lighting and display applications systems.

Background Art

[0003] Compound semiconductor materials are typically deposited or grown on a growth substrate and lattice-matched at the atomic level to avoid the occurrence of growth defects such as dislocations. In some cases, it is desirable to change the lattice constant of the compound semiconductor material to provide a material and / or device and / or system having specific characteristics.

[0004] InGaN is currently a preferred material for the active layer of GaN-based optoelectronic devices, such as blue or violet light-emitting diodes (LEDs), which form the basis of most currently commercialized lighting and display systems using LEDs, or violet light-emitting laser diodes (LDs), which form the basis of the Blu-ray® industry. Currently, such devices are manufactured using an InGaN active layer grown with pseudo-lattice mismatch on a gallium nitride (GaN) epitaxial layer. However, because the crystalline atomic lattice constant of InGaN is larger than that of GaN, serious distortion occurs in InGaN grown on GaN (InGaN / GaN), and the material quality deteriorates significantly as the InN mole fraction or thickness increases. This limits the performance of InGaN / GaN-based optoelectronic devices, such as LEDs and LDs.

[0005] Attempts to grow high-quality, planar, and relaxed InGaN for device applications have not yet reached commercialization. The technique of inclined layers used in certain III-V material systems has been attempted for InGaN using low-temperature molecular beam epitaxy (MBE). However, this relaxation mechanism is accompanied by the emergence of high densities of dislocations, stacking defects, and threading dislocations, resulting in poor material quality. A similar approach using commercially preferred metalorganic chemical vapor deposition (MOCVD) on c-plane InGaN has the drawback that there is no sliding system for (polar) c-plane growth, and when attempting to utilize nonpolar and semipolar growth surfaces, materials with high defect densities are obtained. Hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers for the purpose of reducing crystal defects, but this technique has limitations in terms of achievable InN mole fraction and can only be applied to N-polar surfaces, making it not ideal for low-cost manufacturing. There have been attempts to grow strained InGaN layers that can be lifted off and bonded to a corresponding carrier to facilitate relaxation, but as a result of this method, lattice expansion is limited and a non-planar, trench-like surface occurs. Using nanocolumn or nanorod device structures designed to avoid the strain limitations of conventional heteroepitaxy results in a non-planar device shape that is not very suitable for manufacturing and may exhibit low optical quality.

[0006] The use of patterning and regrowth has been used to grow high-quality lattice-mismatched heteroepitaxy for single-element (e.g., Ge on Si) semiconductors and binary III-V (e.g., GaAs on Si) zinc blende semiconductors. However, similar approaches to wurtzite semiconductors and / or ternary alloys such as InGaN have not been successful. SUMMARY OF THE INVENTION

[0007] According to the present invention, a group III nitride semiconductor structure comprises (a) In x Ga 1-xA seed region including N(0≦x<1) and a wurtzite-type group III nitride crystal structure; (b) A first plane parallel to the (0001) plane of the wurtzite-type group III nitride structure and intersecting the seed region, wherein the intersection of the first plane and the first edge of the seed region is In x Ga 1-x N / In y Ga 1-y N heterointerface, where 0<y≦1 and y>x; In x Ga 1-x N / In y Ga 1-y N heterointerface is coplanar with the first crystallographic plane of the seed region, the first plane; (c) Any second plane parallel to the (0001) plane of the wurtzite-type group III nitride crystal structure and intersecting the second edge of the seed region, which is the position of the group III nitride heterointerface, and the group III nitride heterointerface is coplanar with the second crystallographic plane of the seed region, the second plane; (d) A (0001) InGaN region overlapping the seed region, characterized by an in-plane a lattice constant greater than 3.19 Å, and each of the first crystallographic plane and the second crystallographic plane is crystallographically equivalent, the (0001) InGaN region, and including.

[0008] According to the present invention, a semiconductor device includes a III-V semiconductor structure according to the present invention.

[0009] According to the present invention, an illumination system includes a semiconductor device according to the present invention.

[0010] According to the present invention, a display system includes a semiconductor device according to the present invention.

[0011] Those skilled in the art will understand that the drawings described herein are for illustrative purposes only. The drawings are not intended to limit the scope of the present disclosure.

Brief Description of the Drawings

[0012] [Figure 1A-1E]Figures 1A to 1E show an example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by this disclosure.

[0013] [Figure 2A-2E] Figures 2A-2E show an example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by this disclosure.

[0014] [Figure 3A-3E] Figures 3A to 3E show an example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by this disclosure.

[0015] [Figure 4A-4E] Figures 4A to 4E show an example of a process flow for fabricating an InGaN layer having a relaxed InGaN region provided by this disclosure.

[0016] [Figure 5] Figure 5 shows an example of a positive etch mask with various shapes, dimensions, and orientations with respect to the crystallographic directions (1-100) and (11-20) of a group III nitride wurtzite-type material.

[0017] [Figure 6] Figure 6 shows examples of negative etch masks with various shapes, dimensions, and orientations with respect to the crystallographic directions (1-100) and (11-20) of GaN group III nitride wurtzite type materials.

[0018] [Figure 7] Figure 7 shows the transition from an InGaN lattice (solid circle) characterized by a lattice constant "a" similar to that of GaN, to a more relaxed InGaN lattice constant (hatched circle) characterized by a lattice constant "a'".

[0019] [Figure 8]Figure 8 shows an example of an LED incorporating the group III nitride semiconductor structure provided by this disclosure.

[0020] [Figures 9A-9D] Figures 9A–9D show examples of LEDs incorporating the group III nitride semiconductor structure provided by this disclosure.

[0021] [Figure 10] Figure 10 shows an example of a laser diode (LD) incorporating a group III nitride semiconductor structure provided by this disclosure.

[0022] [Figure 11] Figure 11 shows examples of lighting devices and lighting systems that can incorporate the LEDs provided by this disclosure.

[0023] [Figure 12] Figure 12 shows examples of display devices and display systems that can incorporate the LEDs provided by this disclosure.

[0024] [Figure 13] Figure 13 shows a cross-sectional view of an example of a group III nitride semiconductor structure provided by this disclosure.

[0025] [Figure 14A-14B] Figures 14A and 14B show the range of InN mole fractions and a-lattice constants in the relaxed (0001) InGaN region, respectively, depending on the peak emission wavelength.

[0026] [Figures 15A-15F] Figures 15A to 15F show an example of a process flow for fabricating the InGaN layer provided by this disclosure.

[0027] [Figures 16A-16F] Figures 16A to 16F show an example of a process flow for fabricating the InGaN layer provided by this disclosure.

[0028] [Figures 17A-17B] Figures 17A and 17B show cross-sectional views of examples of group III nitride semiconductor structures provided by this disclosure.

[0029] [Figure 18A-18C] Figures 18A-18C show an example of gradually growing InGaN on a (10-11) facet of a group III nitride semiconductor to fill the "v-pit" structure.

[0030] [Figure 19] Figure 19 shows the provision of a relaxed InGaN region by gradually growing InGaN on a (10-11)GaN seed facet.

[0031] [Figure 20] Figure 20 shows an example of gradually growing InGaN on a (10-11)GaN seed facet to provide a relaxed InGaN region. [Modes for carrying out the invention]

[0032] "Substantially uniform lattice constants" refers to semiconductor layers characterized by local lattice constants that exhibit variations of less than 1% relative to the average lattice constant, such as less than 0.5% or less than 0.1% relative to the average lattice constant.

[0033] "Defect density" refers to the density of extended defects, such as dislocations, on a planar diagram in a semiconductor layer. Defect density can be determined, for example, by etching (and counting of etch pit density EPD), cathodoluminescence for observing and counting scotoma, and atomic force microscopy (AFM) for observing and counting small pits.

[0034] Lattice constants can be determined by X-ray diffraction (XRD) and reciprocal lattice space mapping (RSM) analysis. Using high-angle XRD, i.e., near glazing incidence, it is possible to determine the lattice constants of the upper layers in a structure, where the lattice constant may vary as a function of depth.

[0035] "III-V group materials" refer to compound semiconductor materials that contain at least one group III element and at least one group V element from the periodic table.

[0036] The term "growth surface" refers to a plane parallel to the deposition surface of a material on a planar surface, such as the deposition surface of a conventional substrate growth surface.

[0037] Furthermore, "substantially perpendicular to the growth surface" refers to a surface that forms an angle with respect to the growth surface that is approximately 90 degrees, such as between 88 and 92 degrees.

[0038] Wurtzite-type GaN is characterized by a wurtzite-type crystal structure with a and c lattice constants of 3.189 Å and 5.185 Å, respectively, at room temperature. The crystal plane normal to the c lattice constant direction ("c direction") is the c plane, which has the Ga plane (0001) and the N plane (000-1). The plane containing the c direction and perpendicular to the a lattice constant direction ("a direction") is the (11-20) plane, or "a plane". The plane containing the c direction and rotated 30 degrees with respect to the a direction is the (1-100) plane, or "m plane".

[0039] In x Ga 1-x N has the same crystal structure as wurtzite-type GaN, but contains a non-zero InN mole fraction x, forming a ternary compound with a specific fraction of group III column atoms as In and the remainder as Ga. InN has a and c lattice constants of 3.545 Å and 5.703 Å at room temperature, respectively. x Ga 1-x N has a and c lattice constants between those of GaN and InN at room temperature, and depending on the mole fraction, these constants are relative to those of InN.

[0040] Although this specification focuses on the growth of (0001)InGaN on a GaN seed surface, this method is applicable to other wurtzite-type materials, such as InGaN on AlN, AlGaN on AlN, and AlGaN on GaN. Furthermore, the present invention is applicable to non-basal wurtzite structures, such as so-called nonpolar and semipolar GaN and related materials. Finally, the present invention is also applicable to other compound semiconductor systems, including zincblende materials such as InGaAs on GaAs, InGaSb on GaSb, and group II-VI compound semiconductor systems.

[0041] "Relaxed InGaN" refers to InGaN material that exhibits an in-plane lattice constant equal to or nearly equal to that of fully relaxed InGaN material. For example, wurtzite-type relaxed InGaN has an a-plane lattice constant at room temperature greater than 3.189 Å (0% InN) and up to 3.545 Å (100% InN). This is in contrast to strained InGaN material, such as InGaN grown with pseudo-lattice mismatch on GaN, which thus exhibits an in-plane lattice constant equal to or nearly equal to that of GaN (i.e., ~3.189 Å), regardless of the InN mole fraction. Such strained InGaN material is referred to as InGaN / GaN.

[0042] The "in-plane lattice constant" refers to the spacing of the crystal lattice within the growth plane. In the case of (0001) materials, the in-plane lattice constant is the a-lattice constant.

[0043] "Lateral growth" refers to growth in directions other than the normal to the growth surface, including directions parallel to the growth surface.

[0044] The following describes in detail specific embodiments of materials, semiconductor structures, optoelectronic devices, and methods. The disclosed embodiments are not intended to limit the scope of the claims. Rather, the claims are intended to cover all alternatives, modifications, and equivalents.

[0045] This invention teaches the formation of a large-area, planar, coherent, at least partially but substantially uniformly relaxed compound semiconductor material layer for use in optical and / or electronic devices. Large area refers to 1 cm². 2 Larger ranges such as 1mm 2 This refers to a larger area. Planar refers to a semiconductor layer that is substantially flat and exhibits at least one surface with little significant thickness variation over a large area. For example, a planar semiconductor layer may have an RMS roughness of less than 1 nm, as determined by atomic force microscopy. A planar semiconductor layer may have a thickness of, for example, within ±10% of the average thickness. Coherent refers to a material that is substantially crystalline rather than amorphous. Relaxed refers to a material whose in-plane lattice constant is approximately that of a self-supporting, coherent, 100% relaxed material. Substantially relaxed refers to a material whose in-plane lattice constant is within 30% of that of a self-supporting, coherent, 100% relaxed material. Uniform refers to a material whose in-plane lattice constant is substantially unchanging over a large area on which optical device structures and / or electronic device structures can be constructed. In addition, the present invention is applicable to a wide range of semiconductor crystal systems, including wurtzite crystal structures, and to higher-order alloys, including ternary and quaternary alloys. Finally, the present invention is suitable for structures grown by multiple growth methods, but more specifically by metal-organic chemical vapor deposition (MOCVD).

[0046] Specifically, the present invention teaches the formation of large-area, planar, coherent, at least partially but substantially uniformly relaxed indium gallium nitride (InGaN) material layers for use as substrates in optical and / or electronic devices. Various compositions (i.e., InN mole fractions) are feasible. Coherent means that the InGaN material is substantially crystalline rather than amorphous. Relaxed means that the lattice constant of the InGaN material is approximately that of a self-supporting, coherent, 100% relaxed InGaN material of the same composition. Uniformly relaxed means that the in-plane lattice constant is largely unchanged over most of a large area in the plane including the growth surface. Such relaxed InGaN material is referred to in the present invention as relaxed InGaN, for example, native InGaN (Native InGaN®).

[0047] The present invention further teaches the formation of optical and / or electrical devices, as well as optical and / or electrical systems, using relaxed InGaN, which may include other InGaN layers grown in a pseudo-lattice mismatch on the relaxed InGaN (i.e., InGaN / InGaN), such as native InGaN®.

[0048] Other features and aspects of the present invention will become apparent from the following description and accompanying drawings. Specifically, the teachings of the present invention are applicable to other compound semiconductor device materials, such as aluminum gallium nitride, aluminum gallium indium nitride, Group III As, Group III P, Group III Sb, etc.

[0049] This invention discloses the use of a semiconductor seed material deposited on a substrate to register the crystal growth of a compound semiconductor material. This seed material has multiple edged seed regions, which are planar seed surface portions, and the normals to each of these planar seed surface portions have crystallographically equivalent orientations that are not parallel to the large-area normals of the substrate. The crystallographically equivalent orientations of a limited number (preferably one) of exposed planar seed surfaces ensure uniform relaxation and compositional control of the InGaN material grown thereon. As a result, when InGaN growth exhibits variations in seed surface orientations simultaneously, competing growth modes and problems associated with uncontrolled compositional control, such as non-uniform InN incorporation and rough surfaces, are avoided. The dimensions of the seed surface portions are limited to allow for the seeding of additional compound semiconductor material and to allow for easy relaxation towards its relaxed lattice constant during growth. The resulting "relaxed" compound semiconductor material is then grown and coalesced to form a large-area (i.e., 1 × 1 mm²) 2 Larger, preferably 1 x 1 cm 2 It forms a film (with a larger surface area). This large-area relaxed compound semiconductor material film serves as a template for growing improved optical and / or electronic device structures.

[0050] Specifically, the present invention discloses the use of a GaN seed region having a seed surface portion to register the crystal growth of InGaN. The dimensions of the GaN seed surface and its associated geometric shape are limited to such an extent that InGaN material can be used as a seed and that it can be easily relaxed towards its relaxed lattice constant during growth. The crystallographic orientation, characterized by a normal to the planar seed surface portion, may be a nonpolar direction, e.g., (11-20) or (1-100), or a plane rotated between them, or a semipolar direction, e.g., (1-101). The (relaxed) InGaN layers are then grown and coalesced to form a planar, large-area film. This large-area relaxed InGaN film serves as a template for the growth of improved optical and / or electronic device structures using InGaN.

[0051] An example of a method for growing a relaxed InGaN region is shown in Figures 1A to 1E.

[0052] As shown in Figure 1A, the GaN (or AlN) layer 102, primarily on the (0001) plane, i.e., the c-plane, can be grown on the substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include engineering substrates such as silicon-on-insulators (SOI). The GaN layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. The GaN layer 102 can be covered with a masking layer 103 of a material that slowly promotes the nucleation of the group III nitride material. Suitable masking materials include dielectrics such as silicon nitride, silicon oxide, and aluminum oxide. The masking layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography, such as using nanolithography and wet and / or dry etching techniques, to provide the desired pattern, as shown in Figure 1B. The etched area 104 from which the mask and GaN material have been removed exposes the GaN seed surface 102a. The seed surface can be substantially perpendicular to the GaN(0001)c plane. As shown in Figure 1C, the GaN seed surface 102a can be used for at least lateral growth of InGaN 105 to form an InGaN / GaN heterojunction that is not coplanar with the substrate 101. Each exposed GaN seed surface can have an equivalent crystallographic orientation. For example, the GaN seed surface can have a plane that is mainly (1-100), i.e., the m plane, or mainly (11-20), i.e., the a plane, or a plane rotated between the m plane and the a plane. Furthermore, the seed surface 102a can be intentionally oriented to promote favorable and uniform growth characteristics, for example. Figure 1E shows a plane 108a that passes through the relaxed InGaN region and is coplanar with surface 107, a plane 108b that bisects the seed region 102, and the InGaN region between the two seed regions 102.The center of the seed region is shown as 108c, and the center of the InGaN region between two seed regions 102 is shown as 108d.

[0053] The orientation of the GaN seed surface can be determined by patterning and during the growth orientation of the GaN layer. The orientation of the seed surface further depends on the angle of the etched GaN layer surface. For example, in the case of nearly perpendicular etching of the (0001) GaN layer, the orientation of the GaN seed surface can vary to approximately (1-100) to (11-20) and any orientation rotated between them. By selecting this orientation, InGaN growth conditions and InGaN material quality can be optimized.

[0054] In the case of InGaN growth on certain GaN seed surfaces, particularly surfaces substantially perpendicular to the main surface of the substrate, it may be desirable to increase lateral growth relative to the vertical by optimizing the growth conditions and / or by selecting a GaN seed surface orientation that promotes a rapid growth rate, in order to facilitate coalescence.

[0055] A small GaN seed surface size promotes relaxation of the InGaN material deposited on it, resulting in a planar crystallographic orientation that facilitates coherent InGaN growth. During growth, the InGaN grows coherently, relaxing toward its relaxed lattice constant and eventually coalescing with adjacent InGaN growth fronts. Referring to Figure 1C, InGaN 105 grows from the GaN seed surface, and in Figure 1D, InGaN 106 grows above the mask layer 103, filling the etched cavity. Continued InGaN growth causes the grown InGaN to coalesce with the GaN seed surface in the adjacent cavity. Subsequently, the relaxed InGaN grows on the masking layer, forming a continuous, planar, relaxed InGaN region, or InGaN template, at the upper InGaN growth surface 107.

[0056] In this InGaN growth method, relaxation occurs primarily laterally, i.e., by twisting, rather than by tilt, which occurs when attempting to relax InGaN directly on the GaN(0001) surface. The latter method leads to a vertical InGaN strain gradient, which becomes problematic during subsequent InGaN growth and coalescence. Instead, the present invention reduces tilt, making it possible to ensure that the final coalescence film is substantially free of strain and / or compositional inhomogeneities, thus providing a high-quality, planar, relaxed InGaN large-area surface for semiconductor growth. Furthermore, since relaxation occurs uniformly at the GaN seed surface, the vertical strain gradient that can occur when a strain layer is first grown with pseudo-lattice mismatch (and then etched and relaxed) is largely avoided.

[0057] In the InGaN growth method provided by this disclosure, InGaN growth will primarily occur on the surface of the GaN seed material, while InGaN growth on other exposed surfaces should be minimized or completely avoided. For this reason, it may be beneficial to etch through the GaN seed material into the underlying substrate to move the substrate growth surface away from the InGaN nucleation region. In addition, the growth conditions of the InGaN layer can be selected to promote growth on one or more GaN seed surfaces, in contrast to InGaN nucleation and growth on the substrate, which may exhibit competitive growth modes. This technique is illustrated in Figures 2A-2E, where both the GaN layer and a portion of the substrate are etched. To make the InGaN to be grown on the substrate non-competitive, the distance between competitive growth (at the substrate surface) and the desired growth at one or more surfaces of the GaN seed material is increased by etching the substrate. Furthermore, the etching of the substrate can play a role in hindering InGaN nucleation and growth, thereby further reducing the possibility of interference in competitive growth modes.

[0058] Figure 2A shows the substrate 201, the GaN layer 202 on top of it, and the mask layer 203 on top of that. In Figure 2B, the mask layer 203, the GaN layer 202, and a portion of the substrate 201 are etched, and the exposed GaN seed surface 202a is provided in the cavity 204. As shown in Figure 2C, InGaN 205 grows laterally on the GaN seed surface 202a, in each cavity 204, and on the substrate 201. As shown in Figure 2D, as the InGaN growth 206 continues, the laterally growing regions merge and grow out of the cavity and above the mask layer 203. A void, a portion 208 of the cavity 204, may occur within the cavity's boundaries between the substrate 201 and the merged InGaN 206. As shown in Figure 2E, as InGaN growth continues, InGaN grown from adjacent cavities coalesces to form a relaxed InGaN surface 207, which can be used for growing a semiconductor layer. Figure 2E shows a plane 208a that passes through the relaxed InGaN region and is coplanar with surface 207, a plane 208b that bisects the seed region 202, and the InGaN region between the two seed regions 202. The center of the seed region is shown as 208c, and the center of the InGaN region between the two seed regions 202 is shown as 208d.

[0059] Figure 13 is a detailed cross-sectional view of a structure obtained from the process flow illustrated in Figures 2A-2E. A substrate 1301, e.g., (0001) sapphire, includes optionally etched regions 1306 extending within the substrate 1301. A GaN (or AlN) seed layer material 1302, characterized by an in-plane a-lattice constant a1, is superimposed on the substrate 1301 in the non-etched regions and beneath a masking layer 1303. InGaN 1305 nucleates at the edge of the seed layer material 1302 on the GaN seed surface 1307, forming an InGaN / GaN heterojunction 1307 (i.e., the heterojunction is located at the interface between the InGaN region and the GaN seed region), and its normal shares an equivalent crystallographic direction that is not parallel to the main surface of the substrate 1301. The InGaN material 1305 grows at least partially transversely in the InGaN regions between the GaN seed surfaces, relaxing toward the relaxed in-plane a-lattice constant a2 of the InGaN. The plane 1308b, parallel to the main surface of the substrate 1301 and bisecting the GaN seed surface 1307, features different in-plane a-lattice constants at different locations within the cross-section. For example, at the center point within the GaN seed region, the lattice constant along plane 1308b is characterized by a1, which is commensurate with that of GaN, and at the center point 1305 between the GaN seed surfaces 1307, the lattice constant along plane 1308b is approximately a2, which is commensurate with that of at least partially relaxed InGaN, and is determined by epitaxial growth conditions, in particular, such as temperature and the relative flow rate of organometallic precursors, such as trimethylindium (TMI) compared to trimethylgallium (TMG) in MOCVD, according to the average mole fraction of InN in the InGaN layer. In the region between these two central points, the lattice constant along plane 1308b is characterized by an in-plane a lattice constant greater than a1 and less than a2, because a2 > a1. In the plan view (not shown), the variation in the in-plane a lattice constant within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figures 5 and 6).

[0060] The InGaN material coalesces on the masking layer 1303 to form a relaxed InGaN region 1304 having a planar InGaN surface 1305c. A plane 1308a located within the relaxed InGaN region 1304, parallel to the main surface of the original growth substrate, is primarily characterized by an in-plane a-lattice constant a2. Specifically, at the center point 1305 between the GaN seed surfaces, the InGaN lattice constant along plane 1308a is characterized by a2, while at the center point on the GaN seed surface, the InGaN a-lattice constant along plane 1308a is slightly smaller than a2. In a plan view (not shown), the variation in the in-plane a-lattice constant within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figures 5 and 6). The variation in the in-plane a-lattice constant in the case of InGaN can be detected, for example, using XRD and RSM, and can be resolved on a sub-micrometer scale and on the upper surface using glazing incidence technique. Note that the midpoint of plane 1308b within a seed region is shown as 1308c, and the midpoint of plane 1308b between two seed regions is shown as 1308d.

[0061] The GaN seed region 1302 has an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed region 1302 can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302, for example, the width of the GaN seed region 1302 can be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 can be, for example, 0.01 μm to 1 μm, 0.02 μm to 0.8 μm, 0.05 μm to 0.5 μm, or 0.1 μm to 0.4 μm.

[0062] Figures 3A-3E show an example process flow for fabricating relaxed InGaN using an SOI substrate. In this embodiment, as is well known in the case of GaN growth on Si, it may be desirable to control wafer warpage by including a strain-controlled intermediate layer, such as GaN, AlGaN, or AlInGaN, within the semiconductor structure (not shown).

[0063] Figure 3A shows the substrate 301, the oxide layer 301a and silicon layer 301b, the seed layer 302, and the mask layer 303. Figure 3B shows the cavity 304 after etching down to the silicon layer 301b, which forms the seed region from the seed layer 302. Figure 3C shows the lateral growth of InGaN from the seed layer 302 within the cavity 304 on the edge surface of the seed region. This InGaN growth has a sufficiently high mole fraction of InN to induce strain relaxation. In Figure 3D, the InGaN growth 306 from the seed layer 302 grows and coalesces to fill the cavity and extends further above the mask 303. As shown in Figure 3E, continued InGaN growth provides a planar relaxed InGaN layer 307. Figure 3E shows a plane 308a that passes through the relaxed InGaN region and is coplanar with surface 307, a plane 308b that bisects the seed region 302, and the InGaN region between the two seed regions 302. The center of the seed region is shown as 308c, and the center of the InGaN region between the two seed regions 302 is shown as 308d.

[0064] Figures 4A–4E show another example of a process flow for fabricating a relaxed InGaN layer using an SOI substrate. This example is similar to Figures 3A–3E, with the addition that the top silicon layer 401b and the embedded oxide layer 401a of the SOI substrate are removed by etching (in region 404) to minimize competitive growth of InGaN on the silicon substrate and to promote InGaN growth on the seed surface.

[0065] Figure 4A shows the SOI substrate 401, the oxide layer 401a and silicon layer 401b, the seed layer 402, and the mask layer 403 superimposed on top. Figure 4B shows the cavity 404 obtained as a result of etching down to the substrate 401, which forms the seed region from the seed layer 402. In Figure 4C, the lateral InGaN growth 405 extends from the edge surface of the seed layer 402 into the cavity 404. This InGaN growth has a sufficiently high mole fraction of InN to induce strain relaxation. As shown in Figure 4D, as the InGaN growth 406 continues, the InGaN grown from the opposite seed surface coalesces, grows vertically, fills the top of the cavity, and extends above the mask layer 403. Due to the preferential growth from the seed surface compared to growth on the substrate, a space 408, or void, is created between the substrate 401 and the InGaN layer 406. As shown in Figure 4E, continued InGaN growth provides a planar, relaxed InGaN layer 407. Figure 4E shows a plane 408a that passes through the relaxed InGaN region and is coplanar with surface 407, a plane 408b that bisects the seed region 402, and the InGaN region between the two seed regions 402. The center of the seed region is shown as 408c, and the center of the InGaN region between the two seed regions 402 is shown as 408d.

[0066] Figure 5 shows examples of mask patterns for etching seed material, including stripes, rectangles, triangles, and hexagons. For wurtzite materials such as Group III nitride materials, including InGaN, preferred pattern features are those with edges sharing equivalent crystallographic orientations, such as hexagons or triangles. Other shapes and other relative dimensions can be used. The narrowest dimension of the mask pattern can be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern can be aligned with a specific crystal plane. For example, in the case of wurtzite material with a (0001) main growth plane, aligning the mask edges with the (1-100) plane, the (11-20) plane, or any orientation in between can facilitate the growth of a high-quality, relaxed InGaN layer.

[0067] Figure 6 shows an alternative set of mask patterns, which is the negative version of the one shown in Figure 5, but otherwise similar.

[0068] Figure 7 shows a conceptual plan view cross-section of a patterned GaN seed material with lattice constant a, on which lateral heteroepitaxy is performed to grow an InGaN layer that can be relaxed via twist to a relaxed lattice constant a'. For sufficiently small dimensions, the deformation is perfectly elastic and no defects are formed. For larger dimensions, some plastic deformation may occur, but this may be acceptable if the final defect density of the subsequently deposited and stacked semiconductor layer is sufficiently low. For example, the expanded defect density in the subsequently deposited semiconductor layer is 5E9cm². 2 Less than, for example, 5E8cm 2 Less than 5E7cm 2 It is preferable that it be less than [value]. The lateral InGaN growth and coalescence method provided by this disclosure facilitates the annihilation of threading dislocations in group III nitride materials.

[0069] Further control over the thickness and compositional uniformity of relaxed InGaN growth may be achieved by growing multilayer structures rather than by using bulk InGaN layers. For example, a 25% bulk InGaN layer, for instance, with 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of InN. 0.5 Ga 0.5 Alternating layers with N may be used. The thickness of individual layers can be, for example, in the range of 0.5 nm to 100 nm, or 1 nm to 30 nm. The multilayer structure is not limited to the substrate layer, but may be used throughout the entire epitaxial stack, including semiconductor device layers such as n-type, p-type, and active layers that overlap the relaxed InGaN layer, or in the layers between the relaxed InGaN substrate layer and the device layer.

[0070] Compared to InGaN / GaN, the increased lattice constant of the relaxed InGaN layer allows for the growth of subsequent semiconductor layers at much higher temperatures than in the case of InGaN / GaN. For example, InGaN with an a-lattice constant of 3.205 Å has been shown to incorporate approximately 7% InN, compared to approximately 4% in the case of InGaN / GaN. Since the incorporation of InN mole fraction into GaN is inversely proportional to the growth temperature in MOCVD, this suggests that increasing the a-lattice constant of InGaN from approximately 0.015 to 0.020 can raise the useful growth temperature by approximately 50°C. Further increases in the a-lattice constant of InGaN may even enable higher temperatures at the same InN mole fraction. This effect can be utilized not only in realizing higher quality semiconductor layers grown on relaxed InGaN, achieved by reducing point defect formation at higher temperatures, but also in reducing or eliminating pits that occur at the locations of through-dislocations on the surface of the InGaN film. Ideally, the growth temperature of the InGaN layer should be kept sufficiently high to eliminate pits or limit them to a diameter of at least much smaller than 1 μm, e.g., less than 200 nm or less than 50 nm. Small pits can be "filled" with a thin, high-temperature GaN or AlGaN layer grown above the InGaN film containing the pits.

[0071] The method provided by this disclosure may include iteration, which may be useful for obtaining large lattice constant changes. For example, a relaxed InGaN layer may be used as a seed layer to provide a seed surface for growing a layer with an even higher InN mole fraction. The resulting new relaxed InGaN layer may then be used as a seed layer in another cycle or the like. This method may be useful in obtaining a relaxed InGaN layer with a very high InN mole fraction, which may be suitable as a substrate for growing an active semiconductor layer that emits at long wavelengths, for example, beyond red to deep red and even infrared emission, in the range of 700 nm to 1.6 μm.

[0072] The relaxed InGaN layers provided by this disclosure can serve as templates and / or support structures for growing optical and / or electrical devices. Very large-area wafers, including wafers with diameters of 150 mm, 200 mm or more, are possible, thereby facilitating the mass and low-cost manufacturing of these devices.

[0073] As an example, Figure 8 shows an LED structure formed by growing an n-type layer 806 (e.g., doped with Si or Ge) on the relaxed InGaN surface of an InGaN layer 804, followed by an InGaN-containing active region 807, an optional p-type electron blocking layer 808 containing, for example, GaN, AlGaN, or InGaN (or a multilayer containing an alloy thereof), and then a p-type layer 809 such as a p-type GaN or InGaN layer. A highly doped, e.g., Mg-doped, p-type contact layer 810, e.g., containing GaN or InGaN, overlaps the p-type layer 809 to provide ohmic contact to the p-side device. As shown in Figure 8, the semiconductor structure beneath the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. Within the range of refractive index contrasts that exist between these various features, the presence of these features may help improve light extraction from the device. The resulting semiconductor wafer can undergo a series of process steps, such as lithography, etching, and semiconductor deposition, to form isolated LED regions with suitable electrical contact materials for n-type and p-type layers. Such contact materials may have suitable optical properties, such as high light reflectivity and / or transparency. Electrode metallization 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned, and electrical connections can be obtained, for example, using wire bonds. Various transparent conductive oxide (TCO) materials (not shown), such as indium tin oxide (ITO), can be used to facilitate the current spreading layer 811, particularly in the case of a resistive p-type layer. After the semiconductor structure is fabricated, the wafer can be diced to provide individual devices, which can be mounted in suitable packages by various means, including, among others, epoxy die attachment or soldering. Electrical contacts can be formed between the p-type and n-type layers, for example, using wire bonds, to form a functional device, which can ultimately be powered.The device may further include a luminescent down-conversion material and / or a sealing material such as silicone to provide desired light output characteristics, including white light for lighting applications. This device may be used in lighting systems and / or display applications.

[0074] As shown in Figures 9A to 9D, various flip-chip (FC) LED architectures are possible, including (a) a standard one, (b) a thin-film flip-chip (TFFC) in which the initial growth substrate is removed but the mask and seed layer portions are retained, (c) a TFFC in which the mask and seed layer portions are removed and the exposed InGaN layer is textured (for light extraction purposes) by photolithography and / or chemical etching techniques.

[0075] The semiconductor structure shown in Figures 9A to 9D includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and an initial InGaN growth region 905, an n-type layer 906, an InGaN-containing active region 907, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization 911, and an n-side electrode metallization 912. In Figure 9B, the substrate is removed; in Figure 9C, the growth region and mask region are removed; and in Figure 9D, a portion of the relaxed InGaN region 904 is removed and / or roughened 904a, for example, to enhance specific optical properties of the device.

[0076] Figure 10 shows a laser diode structure grown on top of a relaxed InGaN layer. As shown in Figure 10, the relaxed InGaN layer 1004, including the initial InGaN region 1005, overlaps the mask region 1003, the seed region 1002, and the substrate 1001. The laser diode can be formed by growing an n-type photoconfinement ("cladding") layer 1007 on top of the relaxed InGaN material 1004 and the n-type contact layer 1006, then growing an InGaN-based active region including waveguide regions containing waveguide layers 1008 and 1010 on both sides of the InGaN-containing active layer 1009), and then growing a p-type photoconfinement ("cladding") layer 1011. Layers 1012 and 1013 overlap the p-cladding layer 1011. Wafer fabrication for laser diodes is similar to that for LEDs, except that the devices are formed in stripes to form the laser cavity. Following dicing and the formation of etched or cleaved mirror facets, high-reflection dielectric coatings and anti-reflection dielectric coatings can be deposited on the rear and front facets, respectively (not shown). Depending on the material selection and application details, the laser diode can be mounted in a suitable package with the epitaxial side down or the substrate side down. Electrical contacts can be formed on the high-density p-type contact layer 1014 and n-type contact layer 1006 via electrode metallizations 1015a and 1015b, respectively, to form a functional device to which power can be supplied. This laser diode is used in lighting systems and / or display applications.

[0077] The relaxed InGaN layer provided by this disclosure is applicable to a wide range of compound semiconductor devices that affect the performance of a broad range of system solutions for various applications, including lighting devices and lighting systems (Figure 11) and display devices and display systems (Figure 12).

[0078] The target composition of the relaxed InGaN layer can be selected depending on the intended device, application, and performance requirements. In the case of conventional InGaN light-emitting diodes lattice-matched to GaN, the best-performing devices emit light in the violet wavelength range. At these wavelengths, the strain state of the InGaN quantum wells relative to the GaN substrate is approximately 1% to 2%. The corresponding compositional difference is sufficiently high that very high quantum efficiency devices can be obtained through bandgap design, while the strain state is sufficiently low that the relatively thick InGaN quantum well (QW) layer can reduce the carrier density and mitigate non-emissive Auger recombination (also known as "droop"). Applying this acceptable range of strain states to other emission wavelengths, the preferred composition range of the relaxed InGaN substrate provided by this disclosure can be calculated for various light-emitting devices, ranging from blue (approximately 450 nm) to infrared (approximately 1.3 μm) wavelengths. The preferred ranges are listed in Tables 1 and 2. TIFF2026050367000002.tif141170 TIFF2026050367000003.tif144170

[0079] Figures 14A and 14B graphically illustrate preferred ranges for InN mole fraction and a lattice constant depending on the peak emission wavelength, for a relaxed InGaN layer of (0001) used as a template for fabricating light-emitting diodes and laser diodes, and are consistent with the parameters shown in Tables 1 and 2. For example, as a function of the peak emission wavelength λ, relaxed In x Ga 1-x The InN mole fraction x for the N base layer is given by condition x. min ≤x ≤x max It is desirable that the following conditions be met, where X min and X max These are EQN.1 and EQN.2, respectively: x min = -6.046E-07λ 2 + 1.837E-03λ - 6.917E-01, (λ ≥ 440 nm) EQN.1 x max = -6.152E-07λ 2 + 1.847E-03λ - 6.142E-01, (λ ≥ 440 nm) EQN.2 It is defined as follows.

[0080] Similarly, as a function of the peak emission wavelength λ, relaxed In x Ga 1-x The in-plane lattice constant a of the N base layer is a min ≦a≦a max It is desirable to satisfy the following conditions, where a min and a max These are EQN.3 and EQN.4, respectively: a min = -2.067E-07λ 2 + 6.366E-04λ - 2.951, (λ ≧ 440 nm) EQN.3 a max = -2.190E-07λ 2 + 6.575E-04λ - 2.970, (λ ≧ 440 nm) EQN.4 It is defined as follows.

[0081] The methods and semiconductor structures provided herein can be adapted for the fabrication of vertical cavity surface-emitting layers (VCSELs). The selection of relaxed InGaN substrate compositions for LDs or VCSELs is the same as that for LEDs, as shown in Tables 1 and 2.

[0082] Figures 15A–15F illustrate a method for fabricating a relaxed InGaN layer on the edge surface of a faceted GaN seed region. This method provides a (0001)GaN or AlN seed layer 1502 on a substrate 1501. Figure 15A shows the substrate 1501, the seed layer 1502 superimposed thereon, and the mask layer 1503 superimposed thereon. The GaN seed layer can have a thickness of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. Referring to the process flow illustrated in Figures 15A–15F, the seed layer 1502 can be covered with a masking layer 1503 containing a material that slowly promotes GaN nucleation. The masking layer 1503 can be patterned and etched using any suitable photolithography, such as nanolithography and etching techniques (wet, dry, or a combination thereof), to create the various patterns described above. The exposed GaN within the openings in the mask 1504 created by etching can then be used to nucleate a GaN seed material 1506, which can be grown from the openings in the mask and, by appropriate selection of growth conditions, as shown in Figures 15C and 15D, to form a seed region having edges that are triangular facets with a hexagonal base. For example, the structure may have six sides with a hexagonal base and triangular facets that are equivalent planes of {1-10¹}. Once the facets are fully formed, as shown in Figure 15D, the surface 1507 of the triangular facets can be used as a seed surface for at least lateral growth of InGaN, forming a heterojunction that is not coplanar with the substrate surface. The small dimensions of the GaN seed surface (facet) and the selection of the InGaN target composition facilitate the relaxation of overgrown InGaN as the InGaN thickness increases, while simultaneously providing a flat and crystallographically equivalent orientation to ensure coherence. InGaN1508 grows coherently and relaxes toward its relaxed lattice constant, forming a hexagonal structure with triangular facets, which is relaxed InGaN, as shown in Figure 15E.These InGaN facets can be further grown and eventually coalesced with adjacent InGaN growth fronts of other planar seed facets. As shown in Figure 15F, the coalesced InGaN is then grown on a masking layer and seed region, and growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous planar, relaxed InGaN layer or template 1509 as the upper region of the structure. This method has the advantage that it does not require etching the GaN (or InGaN, AlGaN, or AlN) seed material to provide a seed surface portion for InGaN nucleation. Furthermore, this method is very suitable when the growth substrate is a group III nitride material, such as a GaN or AlN substrate. Thus, this method allows for low dislocation density (e.g., 5E7cm⁻¹ on a GaN substrate) for long-life operation (>10,000 hours). -2 This facilitates the fabrication of LD devices where a value less than (Illegible) is preferable.

[0083] Figures 16A–16F illustrate another method for fabricating a relaxed InGaN layer on a faceted GaN surface. This method is similar to the method illustrated in Figures 15A–15F, except that the GaN seed material is nucleated on the substrate. This method can provide a substrate 1601 suitable for GaN nucleation, such as sapphire, SiC, sapphire, AlN, or GaN. Referring to Figure 16A, the substrate 1601 can be coated with a masking layer 1602 of a material that slowly promotes GaN nucleation. As shown in Figure 16B, the masking layer 1602 is patterned and etched using photolithography, such as nanolithography and etching techniques (wet, dry, or a combination thereof), to create various patterns 1604. Next, the substrate 1603 exposed within the openings of the mask created by etching can be used to nucleate a GaN seed material 1605, as shown in Figure 16C. This material grows from the openings in the mask, and by appropriately selecting the growth conditions, it is possible to form a GaN seed region having triangular facets and a hexagonal base. For example, the seed region may be hexaplane and have triangular facets that are crystallographically equivalent planes of {1-10¹}. As shown in Figure 16D, after the seed region is fully formed, the surface 1607 of the triangular facets is used as a seed surface for at least lateral growth of InGaN, forming six heterojunctions in a crystallographically equivalent plane that is not coplanar with the substrate. The small size of the GaN seed surface and the selection of a target composition of the grown InGaN material promote relaxation of the InGaN grown on the seed surface. Furthermore, each seed surface provides a flat and crystallographically equivalent orientation that ensures the coherence of the entire grown InGaN material. InGaN grows coherently and relaxes toward its relaxed lattice constant, forming facet 1608, which is relaxed InGaN, as shown in Figure 16E. These facets grow further and eventually merge with adjacent InGaN growth fronts that grew from other seed regions.As shown in Figure 16F, the bonded InGaN is then grown on a masking layer, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN region 1609 or template across the entire substrate. This method has the advantage of not requiring etching of the GaN (or AlN) material to provide a seed surface for InGaN nucleation. Another advantage of this method is that the entire process can be provided in a single epitaxial growth step. Furthermore, this method is particularly suitable when the growth substrate is a group III nitride material, such as a GaN or AlN substrate.

[0084] Figure 17A provides a detailed cross-sectional view of the structure obtained from the process flow of Figures 15A-15F. The substrate 1701, for example (0001) sapphire, serves as the main growth substrate for the GaN (or InGaN, AlGaN, or AlN) seed layer 1702, characterized by an in-plane lattice constant a1. The GaN seed layer 1702 grows between masked regions 1703, forming a GaN seed region 1702a having exposed edges of crystallographically equivalent planar GaN seed surfaces. InGaN material is nucleated on the triangular GaN seed surface of the GaN seed region, forming a heterojunction 1707 that is not parallel to the main surface of the original growth substrate 1701. The heterojunction 1707 may be formed on a stable crystallographically equivalent facet of the GaN seed region, for example, on a crystallographically equivalent facet of {1-101}. The InGaN material grows at least partially transversely in the region 1705 between the GaN seed surfaces, so as to relax toward the relaxed in-plane a-lattice constant a2 of the InGaN. A plane 1708b, parallel to the main surface of the original growth substrate and bisecting the GaN seed material, features different in-plane a-lattice constants at different locations along the plane. Specifically, at the center point within the GaN seed region 1702a, this plane features a lattice constant a1, and at the center point 1705 between the GaN seed regions 1702a, the lattice constant is approximately a2. In the GaN region between these two center points, the in-plane a-lattice constant is greater than a1 and less than a2, because a2 > a1. In a plan view (not shown), the variation in the GaN in-plane a-lattice constant within the plane 1708b is characterized by a two-dimensional mask pattern applied to the GaN seed layer material (see Figures 5 and 6).

[0085] As shown in Figures 17A and 17B, plane 1708b intersects with the edge of seed region 1702a, and the interface between InGaN region 1704 and the seed region is the location of heterojunction 1709b. The heterojunction is coplanar with the first crystallographic plane of the seed region. Any plane, such as plane 1708b, which is parallel to the main growth surface and intersects both the InGaN region (such as 1708c) and the seed region 1702a, intersects with the edge of seed region 1702a, and the interface between the InGaN region and the seed region, which is coplanar with the second crystallographic plane of the seed region, is the location of heterojunction 1709c. As shown in Figures 17A and 17B, the first and second crystallographic planes are identical. The first and second crystallographic planes can be crystallographically equivalent crystallographic planes.

[0086] The InGaN material coalesces on the masking layer 1703 to form a relaxed InGaN layer 1704 having a planar surface 1705c. Plane 1708a, located within the InGaN layer 1704 parallel to the main surface of the original growth substrate and near surface 1705c, is primarily characterized by an InGaN in-plane a-lattice constant a2. At the center point 1705 between GaN seed regions, the InGaN lattice constant is a2, while at the center point within a GaN seed region, the in-plane a-lattice constant is slightly less than a2. In a plan view (not shown), the variation in the in-plane a-lattice constant within plane 1708b is characterized by a two-dimensional mask pattern applied to the seed layer material (see Figures 5 and 6). The variation in the in-plane a-lattice constant is detectable by measurement techniques such as XRD and RSM and can be resolved on a sub-micrometer scale. The midpoint along plane 1708b within seed region 1702a is shown as 1708c, and the midpoint between two seed regions 1702a is shown as 1708d.

[0087] The GaN seed region 1702a may have an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed region 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask material 1703 may be, for example, 0.01 μm to 1 μm. Figure 17B provides a detailed cross-sectional view of the structure obtained from the process flow of Figures 16A to 15F. This structure is similar to the structure in Figure 17A, with similar components identified so that they have the same numbering. However, in the structure of Figure 17B, there is no planar starting GaN (or AlN) seed layer 1702. Instead, the GaN (or AlN) seed material is nucleated directly onto the substrate 1701 within the openings between the mask regions 1703. The substrate may be, among other things, sapphire, GaN, AlN, or silicon.

[0088] The group III nitride semiconductor structure is (a)In x Ga 1-x (b) a seed region comprising N(0≦x<1) and a wurtzite-type group III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite-type group III nitride structure and intersecting the seed region; the intersection of the first plane and the first edge of the seed region is In x Ga 1-x N / In y Ga 1-y This becomes the position of the N heterojunction, 0<y≦1かつy> x is; In x Ga 1-x N / In y Ga 1-yThe material may include: (c) a first plane in which the N heterojunction is coplanar with the first crystallographic plane of the seed region; (d) a second plane which is parallel to the (0001) plane of the wurtzite-type group III nitride crystal structure and intersects the second edge of the seed region, and which is the location of the group III nitride heterojunction, and in which the group III nitride heterojunction is coplanar with the second crystallographic plane of the seed region; and (e) a (0001)InGaN region which overlaps the seed region, and the (0001)InGaN region is characterized by an in-plane a lattice constant greater than 3.19 Å, where each of the first and second crystallographic planes is crystallographically equivalent.

[0089] The first parallel plane can intersect with two facets of the seed region. The facets of the seed region are parallel to the crystallographic plane of the seed region, for example, the crystallographic plane of the wurtzite crystal structure. The facets of the seed region can be crystallographically equivalent facets. The intersection of the first parallel plane and the facets of the seed region is In x Ga 1-x N / In y Ga 1-y This is the position of a heterojunction such as N, where 0 ≤ x < 1, 0<y≦1、かつy> x is the answer.

[0090] The location of the group III nitride heterojunction is a second plane that is parallel to the {0001} plane of the wurtzite-type group III nitride crystal structure and intersects the seed region. The second plane may intersect the same facets as the first plane. The second plane may intersect the facets of the seed region that are coplanar with the crystallographic plane of the seed region. Each of the crystallographic planes may be a crystallographically equivalent plane. Each of the seed regions may be characterized by facets parallel to the crystallographic plane of the seed region, such as the crystallographic plane of the wurtzite-type crystal structure. Each of the crystallographic planes may be a crystallographically equivalent plane. Each of the crystallographic planes may be crystallographically equivalent to the {10-11} plane. Each of the crystallographic planes may be crystallographically equivalent to the {1-100} plane. Each of the crystallographic planes may be crystallographically equivalent to the {11-20} plane. Each of the crystallographic planes can be either a (1-100) plane or a (11-20) plane.

[0091] The InGaN region is located between seed regions. At least a portion of the InGaN region, or the InGaN region between seed regions, can be a partially relaxed InGaN region. The InGaN region can include multiple InGaN layers, each having a different elemental composition. The InGaN region (0001) can be superimposed on a seed region. The InGaN region (0001) can be a fully relaxed InGaN region and can have an in-plane a-lattice constant greater than 3.19 Å, for example, in the range of 3.20 Å to 3.50 Å.

[0092] A seed region can have two or more facets, for example, 2, 3, 4, 5, or 6 facets. A seed region can have 3 or 6 facets. A seed region can have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. A seed region can have a triangular base or a hexagonal base.

[0093] Each seed region may contain, for example, GaN, and may have, for example, a lattice constant of about 3.189 Å. Each seed region may contain, In x Ga 1-x N / In y Ga 1-y Both the N heterojunction and the group III nitride heterojunction are GaN-InGaN heterojunctions.

[0094] Figures 18 to 20 illustrate embodiments of the present invention. Figures 18A, 18B, and 18C show schematic plan views of so-called "v-pit" structures that can be formed during the growth of group III nitrides on the basal plane. Specifically, in the case of group III nitride materials grown at low temperatures, for example, GaN grown using MOCVD at temperatures below 800°C, the dynamics of the adsorbed atoms are such that the semiconductor material does not tend to fill the area near the dislocation core, causing pits to form from a stable (10-11) plane with a dislocation core at the center. If growth continues under low-temperature conditions, the pits become larger (Figure 18B) and collide (Figure 18C). As the pits become larger, the total surface area of ​​the exposed (10-11) facets becomes equal to or greater than the total surface area of ​​the exposed (0001) surface. The presence of these large surface area (10-11) facets, each of which is crystallographically equivalent, provides an opportunity to form high-quality, relaxed InGaN on a (10-11) seed surface, for example, on GaN, as devised in this invention.

[0095] For example, as shown in Figure 19, GaN can be nucleated at low temperatures on a suitable substrate, such as GaN, sapphire, Si, SiC, AlN, etc. Once a reasonably high-quality GaN epitaxial film is achieved, for example, by growing the GaN epitaxial film at a high temperature (e.g., above 900°C), the growth conditions can be changed again, for example, by growing GaN at a temperature of 800°C or lower to form v-pits. After that, growth is stopped, the GaN structure is removed from the MOCVD reactor, and SiO2 or SiN xA suitable growth mask layer, such as a dielectric layer, can be selectively deposited on the (0001) surface and not on the (10-11) surface. This can be achieved by various means, such as high-angle sputtering or deposition, or by selective deposition of photoresist in the v-pits followed by deposition and lift-off. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. Subsequently, InGaN, optionally preceding the deposition of a thin layer of GaN, can be selectively grown on the exposed GaN seed region material on the (10-11) facet. A target value for the InN mole fraction can be set so that as the thickness of the InGaN layer increases, large strains are induced, and as a result, relaxation is induced. The InGaN growth can continue to grow and coalesce above the mask region, providing a planar, high-quality, relaxed InGaN (0001) region, which can serve as a template for device fabrication as described in this disclosure. InGaN layers can be grown at temperatures higher than typical for InGaN / GaN growth, such as above 900°C, because relaxed InGaN material incorporates In much more readily than InGaN that is pseudo-lattice-matched to GaN. Increasing the growth temperature allows for filling v-pit defects and obtaining a coalesced, planar film. Controlling the morphology and compositional uniformity of relaxed InGaN growth can be easily achieved by growing a multilayer structure rather than by using a bulk InGaN layer. For example, a 25% bulk InGaN layer can be grown with 3nm GaN and 1nm InN, or 2nm GaN and 2nm InN. 0.5 Ga 0.5 Alternating layers of N can be used as substitutes. The thickness of individual layers can range, for example, from 0.5 nm to 100 nm, or from 1 nm to 30 nm. Multiperiodic multilayer structures of this kind, for example, 2 to 10 layers, 2 to 100 layers, or more than 100 layers, may also be used.

[0096] In another example, the masking step can be eliminated, and the entire process can be completed in situ within the growth chamber. For example, as shown in Figure 20, GaN can be nucleated on a suitable substrate, such as GaN, sapphire, Si, AlN, etc. After a reasonably high-quality GaN epitaxial film is achieved by growing it at a high temperature, for example (more than 900°C), the growth conditions can be changed again to form v-pits by growing GaN at a temperature of, for example, 800°C or lower. The v-pits can be grown such that the exposed surface area of ​​the equivalent {10-11} facet is greater than the exposed surface area of ​​(0001)GaN. Preferably, the exposed surface area of ​​the (10-11) facet is greater than twice the exposed surface area of ​​(0001)GaN, and more preferably 10 times the exposed surface area of ​​(0001)GaN. Then, InGaN can be selectively grown on the seed region (10-11) facet. The target value of the InN composition can be set such that increasing the thickness of the InGaN layer induces greater strain, and consequently, relaxation. The InGaN can continue to grow and coalesce, providing a planar, high-quality, relaxed InGaN(0001) region, which can serve as a template for device fabrication as described in this disclosure.

[0097] (0001) Since the growth surface area is smaller than the (10-11) growth surface area, the latter growth mode is dominant, and InGaN can be relaxed and become the dominant growth surface as the film thickness increases. Growing the InGaN layer at a higher temperature than is typical for InGaN / GaN growth may be useful because the relaxed InGaN material can incorporate In more easily than InGaN which is pseudo-lattice matched with GaN. Increasing the growth temperature makes it possible to fill v-pit defects and obtain a coalesced, planar film. Controlling the morphology and compositional uniformity of relaxed InGaN growth can be easily done by growing a multilayer structure rather than by using a bulk InGaN layer. For example, a 25% bulk InGaN layer can be grown with 3 nm of GaN and 1 nm of InN, or 2 nm of GaN and 2 nm of In 0.5 Ga 0.5 Alternating layers of N may be used as a substitute. The thickness of individual layers can be, for example, in the range of 0.5 nm to 100 nm, or 1 nm to 30 nm. Such multi-period multilayer structures can be used, with 2 to 10 layers, 2 to 100 layers, or more than 100 layers.

[0098] As an example, a c-plane (0001) sapphire substrate can be loaded into an MOCVD reactor capable of supplying at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be obtained, followed by high-temperature GaN growth that may involve the formation of three-dimensional islands followed by coalescence into a two-dimensional (0001) GaN film. This transition from three-dimensional to two-dimensional helps to redirect threading dislocations laterally and also helps to reduce the overall threading dislocation density on the growth surface, which is 1E9cm -2 It can be reduced to less than 1E8cm in a planar GaN layer. -2This can be achieved in terms of dislocation density. Next, by lowering the growth temperature (for example, to below 800°C), a v-pit structure can be formed at the dislocation core, which is characterized by inclined (10-11) planes. These planes can form an angle of approximately 63 degrees with respect to the (0001) growth surface. The height of the v-pit is controlled by the thickness of the low-temperature layer, which is increased by growth such that the total surface area of ​​the exposed {10-11} facets is greater than the surface area of ​​(0001), as shown in Table 3 for this specific example. TIFF2026050367000004.tif34170

[0099] For example, if the dislocation density is 1E8cm -2 In this case, the target v-pit height can be set to 0.14 μm or more.

[0100] After achieving the target surface area ratio between the (10-11) material and the (0001) material, TMI is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed region to induce strain relaxation. The InGaN layers can be periodic alternating layers with the GaN layers. For example, each InGaN layer can have a thickness of 0.5 nm to 100 nm, e.g., 1 nm to 30 nm, and can be sandwiched between GaN layers of similar thickness. To induce strain relaxation, it is desirable that the average composition of the strain relaxation layer be moderately high; for example, the average InN content can be greater than 5%. By increasing the growth temperature after or before strain relaxation has started, the growth can be planarized, which helps to achieve a planar, uniform, relaxed (0001)InGaN layer for device fabrication.

[0101] Although the above discussion focuses on GaN seed regions, it is also possible to utilize InGaN (or AlGaN) seed regions, provided that this material is pseudo-lattice-matched to one of the underlying GaN layers, such as a GaN nucleation layer and / or buffer layer. The seed region is the region near the InGaN-GaN (or InGaN-InGaN) heterojunction that ultimately induces relaxation. Seed material below these regions is referred to as seed material rather than seed region.

[0102] The relaxed InGaN layer and semiconductor structures comprising the relaxed InGaN layer provided by this disclosure can be used to fabricate electronic and optoelectronic devices, including InGaN-based optoelectronic devices such as LEDs and LDs (and VCSELs). LEDs and LDs comprising the relaxed InGaN layer provided by this disclosure can be used in lighting systems and display systems. Specifically, in the case of LEDs, the device may be formed on a relaxed InGaN substrate layer on a substrate. The substrate can be thinned by techniques such as grinding, lapping, or etching, and can be diced by means known in the art, such as sawing, scribe and break, or laser scribe and break, to provide individual LED chips or dies. The dimensions of the LED chip or die may be, for example, 250 μm. 2 From 10mm 2This can be done. Then, individual LED chips can be mounted to a suitable package component, which provides leads for making electrical contact with the device and acting as a heat sink. Die attachment can be performed using any preferred method, such as epoxy or silicone attachment or soldering. The electrical connection between the chip and the package can be completed by using bond wires, such as Au or Ag wires, to connect the anode and cathode leads in the package to the respective contact metallizations, i.e., electrodes, on the LED chip. In the case of a flip-chip device, electrical contact can be formed through an intermediate submount located between the LED chip and the package. The chip electrodes can be attached to the submount carrier by means of soldering or gold bumping. After dicing, the submount carrier can be mounted to the package by any preferred method.

[0103] The desired emission color from a packaged LED device can be obtained by fabricating and providing LEDs using relaxed InGaN having a desired peak emission wavelength. Multiple such LED chips with arbitrarily different peak emission wavelengths can be included in separate packages or combined together in a multi-chip package. For example, a single package may contain red, green, and blue LED chips, which may be placed in the circuit and electrically coupled to a driver circuit, either in-package or out-of-package, for operating the LEDs. By selecting the circuit details and drivers, different colored LEDs can be operated separately or together to provide a wide range of emission characteristics, including white emission for use in lighting applications or emission for use as a backlight in liquid crystal display (LCD) devices, such as television displays, computer monitors, mobile phone displays, and wearable display devices.

[0104] One or more LED chips can be combined with an luminescent down-conversion material to provide a desired emission spectrum. Such luminescent down-conversion materials may include phosphors, semiconductor nanoparticles such as quantum dots, or perovskite materials. Multiple luminescent down-conversion materials can also be combined within a single package. By selecting the emission wavelength of the LED chip to excite the luminescent down-conversion material, the emission from the package can be made a combination of direct emission from the LED chip and emission from the luminescent down-conversion material, or the emission can be made primarily from the luminescent down-conversion material so that the LED chip light is completely absorbed by the luminescent down-conversion material or blocked or filtered from escaping from the package. Packaged LEDs using luminescent down-conversion materials can be used to produce white light useful for lighting applications. Such devices can be electrically coupled to a driver circuit, powered from an external power source such as a mains power supply or battery power supply, thermally coupled to a heatsink, and optically coupled to various optical components or lenses to provide lighting devices such as LED lamps or LED lighting fixtures.

[0105] Even smaller LED chips may be fabricated using the present invention. Specifically, 1 μm 2 From 50 μm 2Devices having the dimensions of a microLED, so-called "microLEDs," can be fabricated. In the case of microLEDs, conventional dicing techniques are not very suitable, so other means of separating the devices are often employed. For example, dicing may be possible by forming LEDs of the desired dimensions on a substrate, then coupling the top surface of the LEDs to a carrier, such as a blue tape or submount carrier, and then removing the substrate. Individual devices may then be selected and arranged in a package component for a display using microLEDs, or on a backplane. Advanced die handling techniques, as known in the art, can be used to handle microLED devices. Specifically, red-emitting, green-emitting, and blue-emitting LEDs according to the present invention can be formed and arranged as microLEDs to provide a microLED display that can be incorporated into systems such as televisions, computer monitors, tablets, mobile phones, and wearable devices.

[0106] LDs incorporating the relaxed InGaN layer provided herein can also be incorporated into a variety of systems. The LD package is similar to the LED package described herein, except that means are provided for managing even higher power density in the LD device from a thermal standpoint, and means are provided for optically utilizing the laser facets. Multiple emission color LDs may be provided in separate packages or combined into a single package. The LDs may also be coupled with an emission down-conversion material to provide a desired emission spectrum. The LDs are useful in applications requiring very high light density, such as automotive forward lighting systems or projection displays, where projection displays may include optical modulation means such as rastering optics, micromirror devices, or LCD modulators.

[0107] Examples of lighting and display systems are shown in Figures 11 and 12.

[0108] Embodiments of the Invention The present invention can be further defined by the following embodiments.

[0109] Embodiment 1. A group III nitride semiconductor structure comprising an InGaN region comprising a relaxed (0001)InGaN region; wherein the relaxed (0001)InGaN region has an in-plane a-lattice constant characterized by periodicity in at least one direction.

[0110] Embodiment 2. The semiconductor structure according to Embodiment 1, wherein the relaxed InGaN region is characterized by a c-plane growth orientation.

[0111] Embodiment 3. The semiconductor structure according to any one of Embodiments 1 to 2, wherein the relaxed InGaN region is characterized by an average in-plane a-lattice constant greater than 3.19 Å.

[0112] Embodiment 4. The semiconductor structure according to any one of Embodiments 1 to 3, wherein the relaxed InGaN region has a thickness of less than 3 μm.

[0113] Embodiment 5. The semiconductor structure according to any one of Embodiments 1 to 4, wherein the relaxed InGaN region has a thickness of 20 nm to 1 μm.

[0114] Embodiment 6. The relaxed InGaN region is 5E9cm 2 A semiconductor structure according to any one of embodiments 1 to 5, having a defect density of less than .

[0115] Embodiment 7. The semiconductor structure according to any one of Embodiments 1 to 6, wherein the relaxed InGaN region includes an InGaN-GaN superlattice.

[0116] Embodiment 8. A semiconductor structure according to any one of embodiments 1 to 7, further comprising: a plurality of mask regions located beneath a first portion of the relaxed InGaN region; and a plurality of unmasked regions located beneath a second portion of the relaxed InGaN region.

[0117] Embodiment 9. The semiconductor structure according to Embodiment 8, wherein each of the plurality of mask regions includes a dielectric material.

[0118] Embodiment 10. The semiconductor structure according to Embodiment 9, wherein the dielectric material comprises silicon nitride, silicon oxide, or aluminum oxide.

[0119] Embodiment 11. The semiconductor structure according to any one of Embodiments 8 to 10, wherein each of the plurality of mask regions has a thickness of 20 nm to 2 μm.

[0120] Embodiment 12. The semiconductor structure according to any one of Embodiments 8 to 10, wherein each of the plurality of mask regions has a thickness of less than 2 μm.

[0121] Embodiment 13. The semiconductor structure according to any one of Embodiments 8 to 12, wherein the maximum in-plane dimension of each of the plurality of non-mask regions is less than 1 μm.

[0122] Embodiment 14. The semiconductor structure according to any one of Embodiments 8 to 13, further comprising seed regions located beneath each of the plurality of mask regions.

[0123] Embodiment 15. The semiconductor structure according to Embodiment 14, wherein the seed region comprises GaN, AlN, or AlGaN.

[0124] Embodiment 16. The semiconductor structure according to any one of Embodiments 14 to 15, wherein the seed region has a thickness of 20 nm to 2 μm.

[0125] Embodiment 17. The semiconductor structure according to any one of Embodiments 14 to 16, wherein the seed region has a thickness of less than 2 μm.

[0126] Embodiment 18. The semiconductor structure according to any one of Embodiments 14 to 17, wherein the seed region includes a horizontal interface and a seed interface, the horizontal interface is substantially coplanar with the (0001)InGaN crystallographic plane, and the seed interface includes a planar seed portion that is not parallel to the horizontal interface.

[0127] Embodiment 19. The semiconductor structure according to Embodiment 18, wherein the planar seed portion includes an a-plane, an m-plane, or a plane between the a-plane and the m-plane.

[0128] Embodiment 20. The semiconductor structure according to Embodiment 19, wherein the horizontal interface is characterized by a c-plane orientation; and the planar seed portion is not coplanar with the horizontal interface.

[0129] Embodiment 21. The semiconductor structure according to any one of Embodiments 19 to 20, wherein the planar seed portion includes a heterojunction.

[0130] Embodiment 22. The semiconductor structure according to Embodiment 21, wherein the heterojunction is a GaN-InGaN heterojunction.

[0131] Embodiment 23. The semiconductor structure according to Embodiment 22, wherein the seed region comprises GaN; the planar seed portion comprises a GaN / InGaN heterojunction; and the GaN / InGaN heterojunction is substantially parallel to a GaN(1-100) crystal plane, a GaN(11-20) crystallographic plane, or a crystallographic plane between the GaN(1-100) crystallographic plane and the GaN(11-20) crystallographic plane.

[0132] Embodiment 24. The semiconductor structure according to any one of Embodiments 8 to 23, wherein the plurality of non-mask regions include InGaN.

[0133] Embodiment 25. The semiconductor structure according to any one of Embodiments 8 to 24, wherein the plurality of non-mask regions are characterized by a pattern.

[0134] Embodiment 26. The semiconductor structure according to any one of Embodiments 8 to 25, wherein the plurality of non-mask regions are characterized by at least one-dimensional non-mask region periodicity.

[0135] Embodiment 27. The semiconductor structure according to Embodiment 26, wherein the periodicity of the in-plane a-lattice constant of the relaxed InGaN region corresponds to the periodicity of the non-masked region.

[0136] Embodiment 28. The semiconductor structure according to any one of Embodiments 8 to 27, wherein the plurality of non-mask regions are characterized by the shape of an array.

[0137] Embodiment 29. The semiconductor structure according to Embodiment 28, wherein the shape includes an edge oriented with respect to the crystallographic plane of InGaN.

[0138] Embodiment 30. The semiconductor structure according to Embodiment 29, wherein the edge is oriented with respect to the a-plane or m-plane of InGaN at a deviation of ±1°.

[0139] Embodiment 31. The semiconductor structure according to any one of Embodiments 29 to 30, wherein the edge is oriented parallel to the (1-100)InGaN crystallographic plane.

[0140] Embodiment 32. The semiconductor structure according to any one of Embodiments 29 to 31, wherein the edge is oriented parallel to the (11-20)InGaN crystallographic plane.

[0141] Embodiment 33. The semiconductor structure according to any one of Embodiments 29 to 31, wherein the edge is oriented in a direction that is not parallel to the (1-100)InGaN crystallographic plane and not parallel to the (11-20)InGaN crystallographic plane.

[0142] Embodiment 34. The semiconductor structure according to any one of embodiments 8 to 33, further comprising a substrate in each of the plurality of non-masked regions and a substrate beneath each of the plurality of masked regions.

[0143] Embodiment 35. The semiconductor structure according to Embodiment 34, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[0144] Embodiment 36. The semiconductor structure according to any one of Embodiments 8 to 35, further comprising a substrate located beneath each of the plurality of non-masked regions, and a cavity located within the non-masked region and above a portion of the substrate.

[0145] Embodiment 37. The III-V semiconductor structure has an area defined by its width and length, and the area is 0.1 mm². 2 A larger semiconductor structure according to any one of embodiments 1 to 36.

[0146] Embodiment 38. The semiconductor structure according to Embodiment 37, characterized by the periodicity, wherein the period is less than at least 10 times the width and / or less than 10 times the length.

[0147] Embodiment 39. The semiconductor structure according to any one of Embodiments 37 to 38, characterized in that the number of non-masked regions within the area is greater than 10.

[0148] Embodiment 40. A semiconductor structure according to any one of Embodiments 1 to 39, wherein the in-plane a-lattice constant fluctuates between a minimum and maximum value around an average in-plane a-lattice constant of less than approximately 1% within a range of one period related to the periodicity.

[0149] Embodiment 41. A semiconductor structure according to any one of Embodiments 1 to 40, further comprising a plurality of seed regions located beneath a first portion of the relaxed InGaN region, wherein each of the plurality of seed regions comprises a plurality of planar seed portions; and each of the plurality of planar seed portions is not a coplanar (0001)InGaN crystallographic plane.

[0150] Embodiment 42. The semiconductor structure according to Embodiment 41, wherein the planar seed portion forms at least a portion of a pyramidal shape having a hexagonal base.

[0151] Embodiment 43. The semiconductor structure according to any one of Embodiments 41 to 42, wherein each of the plurality of planar seed portions is characterized by a (1-10¹) crystallographic plane.

[0152] Embodiment 44. A semiconductor structure according to any one of embodiments 41 to 43, further comprising a plurality of mask regions located below a second portion of the relaxed InGaN region, wherein each of the plurality of seed portions extends over the plurality of mask regions.

[0153] Embodiment 45. The semiconductor structure according to Embodiment 44, further comprising a seed layer located beneath each of the plurality of mask regions and beneath each of the plurality of seed regions.

[0154] Embodiment 46. The semiconductor structure according to Embodiment 45, wherein the seed layer and each of the plurality of seed regions are continuous.

[0155] Embodiment 47. The semiconductor structure according to Embodiment 46, further comprising a substrate located beneath the seed layer.

[0156] Embodiment 48. The semiconductor structure according to any one of embodiments 44 to 47, further comprising a substrate located beneath each of the plurality of seed regions and located beneath each of the plurality of mask regions.

[0157] Embodiment 49. A semiconductor structure according to any one of Embodiments 1 to 48, wherein the in-plane a-plane lattice constant is greater than 3.19 Å in a plane parallel to the c-plane of InGaN and passing through the relaxed InGaN region.

[0158] Embodiment 50. A semiconductor structure according to any one of Embodiments 1 to 49, further comprising a plurality of unmasked regions located beneath a portion of the relaxed InGaN region, wherein the periodicity of the lattice constant of the relaxed InGaN region corresponds to the periodicity of the plurality of unmasked regions.

[0159] Embodiment 51. A semiconductor structure according to any one of Embodiments 1 to 50, further comprising a plurality of seed regions located beneath a portion of the relaxed InGaN region, wherein each of the plurality of seed regions is characterized by an in-plane a-lattice constant a1; the relaxed InGaN region is characterized by an in-plane a-lattice constant a2; and a2 is greater than a1.

[0160] Embodiment 52. A semiconductor structure according to any one of Embodiments 1 to 51, further comprising a plurality of seed regions located beneath a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is not parallel to the growth plane of the seed region and the relaxed InGaN region.

[0161] Embodiment 53. A semiconductor structure according to any one of Embodiments 1 to 52, further comprising a plurality of seed regions located beneath a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is perpendicular to the c-plane of the relaxed InGaN region.

[0162] Embodiment 54. A semiconductor structure according to any one of Embodiments 1 to 53, further comprising a plurality of seed regions located beneath a portion of the relaxed InGaN region, wherein the relaxed InGaN region and the plurality of seed regions form a plurality of heterojunctions; and each of the plurality of heterojunctions is parallel to the a-plane of InGaN, parallel to the m-plane of InGaN, or forms an angle between the a-plane and the m-plane of InGaN.

[0163] Embodiment 55. A semiconductor structure according to any one of Embodiments 1 to 54, further comprising a plurality of seed regions located beneath a portion of the relaxed InGaN region, wherein the plurality of seed regions are characterized by periodicity in at least one direction; and the periodicity of the in-plane a-lattice constant of the relaxed InGaN region corresponds to the periodicity of the plurality of seed regions.

[0164] Embodiment 56. The semiconductor structure according to Embodiment 55, wherein the periodicity of the in-plane a-lattice constant of the relaxed InGaN region is the same as the periodicity of the plurality of seed regions.

[0165] Embodiment 57. The semiconductor structure according to any one of Embodiments 1 to 56, further comprising an n-doped semiconductor layer, an active semiconductor layer, and a p-doped semiconductor layer on the relaxed InGaN region.

[0166] Embodiment 58. The semiconductor structure according to any one of Embodiments 1 to 57, further comprising a plurality of semiconductor epitaxial layers on the relaxed InGaN region.

[0167] Embodiment 59. A group III nitride semiconductor structure comprising: an InGaN region including a relaxed (0001)InGaN region; a plurality of mask regions located beneath a first portion of the relaxed InGaN region; a plurality of unmasked regions located beneath a second portion of the relaxed InGaN region; and seed regions located beneath each of the mask regions.

[0168] Embodiment 60. The semiconductor structure according to Embodiment 59, wherein the seed regions contain GaN; and the unmasked regions between the seed regions and below the second portion of the InGaN region contain InGaN.

[0169] Embodiment 61. The semiconductor structure according to any one of Embodiments 59 to 60, wherein, in a plane parallel to the c-plane of the relaxed InGaN region and bisecting the seed region, the in-plane a-lattice constant within the seed region is smaller than the in-plane a-lattice constant between the seed regions and below the second portion of the InGaN region.

[0170] Embodiment 62. A semiconductor device comprising the III-V semiconductor structure described in any one of Embodiments 1 to 61.

[0171] Embodiment 63. The semiconductor device according to Embodiment 62, comprising an optoelectronic device.

[0172] Embodiment 64. The semiconductor device according to Embodiment 62, comprising a light-emitting diode or a laser diode.

[0173] Embodiment 65. The semiconductor device according to Embodiment 64, further comprising a peak emission wavelength.

[0174] Embodiment 66. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 440 nm and 460 nm, and the in-plane a-lattice constant is between 3.196 Å and 3.214 Å.

[0175] Embodiment 67. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 520 nm and 540 nm, and the in-plane a-lattice constant is between 3.235 Å and 3.253 Å.

[0176] Embodiment 68. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 580 nm and 600 nm, and the in-plane a-lattice constant is between 3.260 Å and 3.282 Å.

[0177] Embodiment 69. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 620 and 640 nm, and the in-plane a-lattice constant is between 3.282 Å and 3.296 Å.

[0178] Embodiment 70. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 690 and 710 nm, and the in-plane a-lattice constant is between 3.303 Å and 3.324 Å.

[0179] Embodiment 71. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 840 nm and 870 nm, and the in-plane a-lattice constant is between 3.346 Å and 3.367 Å.

[0180] Embodiment 72. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 940 nm and 980 nm, and the in-plane a-lattice constant is between 3.374 Å and 3.392 Å.

[0181] Embodiment 73. The semiconductor device according to Embodiment 65, wherein the peak emission wavelength is between 1300 nm and 1350 nm, and the in-plane a-lattice constant is between 3.435 Å and 3.456 Å.

[0182] Embodiment 74. A lighting system comprising a semiconductor device according to any one of Embodiments 62 to 73.

[0183] Embodiment 75. A display system including a semiconductor device according to any one of Embodiments 62 to 73.

[0184] Finally, it is desirable to note that alternative ways of implementing the embodiments disclosed herein exist. Therefore, these embodiments are considered illustrative and not restrictive, and the claims may be modified within their scope and equivalents, without being limited to the details given herein.

Claims

1. (a) In ｘ Ga １－ｘ A seed region containing N (0 ≤ x < 1) and a wurtzite-type group III nitride crystal structure; (b) A first plane parallel to the (0001) plane of the wurtzite-type group III nitride structure and intersecting the seed region; The intersection of the first plane and the first edge of the seed region is, In ｘ Ga １－ｘ N / In ｙ Ga １－ｙ This is the position of an N heterojunction, where 0 < y ≤ 1 and y > x; The In ｘ Ga １－ｘ N / In ｙ Ga １－ｙ A first plane, in which the InGaN hetero-junction is coplanar with a first crystallographic plane of the seed region; (c) Any second plane parallel to the (0001) plane of the wurtzite-type group III nitride crystal structure and intersecting the second edge of the seed region, which is the location of the group III nitride heterojunction, and which is coplanar with the second crystallographic plane of the seed region; (d) A (0001)InGaN region overlapping the seed region, characterized by an in-plane a-lattice constant greater than 3.19 Å, Includes The first crystallographic plane and the second crystallographic plane are crystallographically equivalent. Group III nitride semiconductor structure.

2. The semiconductor structure according to claim 1, wherein the first edge and the second edge are different edges.

3. The semiconductor structure according to claim 1, wherein the first edge and the second edge are the same edge.

4. The semiconductor structure according to any one of claims 1 to 3, wherein the first crystallographic plane and the second crystallographic plane are different crystallographic planes.

5. The semiconductor structure according to any one of claims 1 to 3, wherein the first crystallographic plane and the second crystallographic plane are the same crystallographic plane.

6. The semiconductor structure according to any one of claims 1 to 5, wherein each of the seed regions is characterized by three to six planar seed facets.

7. The semiconductor structure according to any one of claims 1 to 6, wherein each of the seed regions is characterized by a triangular base or a hexagonal base.

8. The semiconductor structure according to any one of claims 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {10-11} plane.

9. The semiconductor structure according to any one of claims 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {1-100} plane.

10. The semiconductor structure according to any one of claims 1 to 6, wherein each of the crystallographic planes is a crystallographically equivalent {11-20} plane.

11. The semiconductor structure according to any one of claims 1 to 6, wherein each of the crystallographic planes is a (1-100) plane and a (11-20) plane.

12. The semiconductor structure according to any one of claims 1 to 11, wherein the region at the midpoint between seed regions is an InGaN region.

13. The semiconductor structure according to claim 12, wherein the InGaN region is at least a partially relaxed seed region.

14. The semiconductor structure according to any one of claims 12 to 13, wherein the InGaN region comprises a plurality of InGaN layers, and each InGaN layer has a different element content.

15. The semiconductor structure according to any one of claims 1 to 14, wherein each of the seed regions contains GaN and has a lattice constant of about 3.189 Å.

16. The semiconductor structure according to any one of claims 1 to 15, wherein the in-plane a-lattice constant is 3.20 Å to 3.50 Å.

17. Each seed region contains GaN, The aforementioned In ｘ Ga １－ｘ N / In ｙ Ga １－ｙ The semiconductor structure according to any one of claims 1 to 16, wherein each of the N heterojunction and the group III nitride heterojunction is a GaN-InGaN heterojunction.

18. A semiconductor structure according to any one of claims 1 to 17, comprising an array including a plurality of seed regions.

19. A semiconductor structure according to any one of claims 1 to 17, further comprising a substrate and a mask region, wherein the seed region overlaps a first portion of the substrate and the mask region overlaps a second portion of the substrate.

20. The semiconductor structure according to claim 19, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

21. A semiconductor device comprising a group III nitride semiconductor structure according to any one of claims 1 to 20.

22. The aforementioned semiconductor device is: The n-type group III nitride layer on the (0001) InGaN region; The (0001) p-type group III nitride layer on the InGaN region; The InGaN-containing active region between the n-type III nitride layer and the p-type III nitride layer; A first electrical contact metallization process to form an electrical contact with the p-type group III nitride layer; A second electrical contact metallization process to form an electrical contact with the n-type group III nitride layer, A semiconductor device according to claim 21, including the above.

23. A lighting system or display system comprising a semiconductor device according to any one of claims 21 to 22.

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