Memory device, method for testing a memory device, and method for manufacturing a memory device.

Abstract

To improve the yield of memory devices. [Solution] A memory device according to one embodiment comprises a first chip, a second chip stacked on the first chip, and a switching circuit. The second chip includes a substrate, a memory cell array configured to store data nonvolatilously, and a first via, a second via, and a third via, each passing through the substrate in the stacking direction and connected to the first chip. The switching circuit is configured to switch between a first state in which a first signal is communicated between the first chip and the second chip via the first via and a second signal is communicated via the second via, a second state in which a first signal is communicated via the third via and a second signal is communicated via the second via, and a third state in which a first signal is communicated via the first via and a second signal is communicated via the third via.

Description

Technical Field

[0001] The embodiments relate to a memory device, a method for testing a memory device, and a method for manufacturing a memory device.

Background Art

[0002] A memory system including a NAND flash memory as a memory device and a memory controller for controlling the memory device is known. The memory device includes a plurality of core chips and an interface chip. Each of the plurality of core chips stores data non-volatilely. The interface chip controls communication between the memory controller and the plurality of core chips.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the yield of the memory device.

Means for Solving the Problems

[0005] The memory device of the embodiment comprises a first chip, a second chip, and a switching circuit. The second chip is stacked on the first chip and includes a substrate, a memory cell array configured to store data nonvolatilously, and a first via, a second via, and a third via, each passing through the substrate in the stacking direction and connected to the first chip. The switching circuit is configured to switch between a first state in which a first signal is communicated between the first chip and the second chip via the first via and a second signal is communicated via the second via, a second state in which the first signal is communicated between the first chip and the second chip via the third via and a second signal is communicated via the second via, and a third state in which the first signal is communicated between the first chip and the second chip via the first via and a second signal is communicated via the third via. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the functional configuration of a memory device according to the first embodiment and its connection to a memory controller. [Figure 3] A circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to the first embodiment. [Figure 4] A circuit diagram showing a second implementation example of the TSV switching circuit included in the memory device according to the first embodiment. [Figure 5] A diagram showing an example of the relationship between signals transmitted by the TSV switching circuit according to the first embodiment. [Figure 6] A circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to a first modification of the first embodiment. [Figure 7] A circuit diagram showing a second implementation example of a TSV switching circuit included in a memory device according to a first modification of the first embodiment. [Figure 8] A circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to a second modification of the first embodiment. [Figure 9] Circuit diagram showing a second implementation example of the TSV switching circuit included in the memory device according to the second modification of the first embodiment. [Figure 10] Circuit diagram showing an implementation example of the TSV switching circuit included in the memory device according to the third modification of the first embodiment. [Figure 11] Circuit diagram showing an implementation example of the TSV switching circuit included in the memory device according to the fourth modification of the first embodiment. [Figure 12] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the second embodiment. [Figure 13] Flowchart showing an example of the test processing in the memory device according to the second embodiment. [Figure 14] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the modification of the second embodiment. [Figure 15] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the third embodiment. [[ID=二十一]] [Figure 16] [[ID=二十二]]Flowchart showing an example of the test processing in the memory device according to the third embodiment. [Figure 17] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the fourth embodiment. [Figure 18] Flowchart showing an example of the test processing regarding redundant vias in the memory device according to the fourth embodiment. [Figure 19] Flowchart showing an example of the test processing regarding default vias in the memory device according to the fourth embodiment. [Figure 20] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the modification of the fourth embodiment. [Figure 21] Block diagram showing an example of the functional configuration regarding the test processing of the memory device according to the fifth embodiment. [Figure 22] Flowchart showing an example of the test processing in the memory device according to the fifth embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. When distinguishing a plurality of components having a common reference numeral, a suffix is added to the common reference numeral for distinction. When no distinction is required for a plurality of components, only the common reference numeral is given to the plurality of components, and no suffix is added.

[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Information Processing System The configuration of the information processing system according to the first embodiment will be described.

[0009] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3. The host 2 and the memory system 3 are connected via a host bus HB. The host bus HB conforms to, for example, SD TM interface, M-PHY TM , SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), or PCIe TM (Peripheral Component Interconnect express).

[0010] The host 2 is, for example, a server in a data center, a personal computer, or a mobile terminal. The host 2 performs information processing using the data stored in the memory system 3.

[0011] The memory system 3 is a storage device configured to be connected to the host 2. The memory system 3 is, for example, SD TMThe memory system is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 3 performs data writing, reading, and erasing operations in response to requests from the host 2.

[0012] 1.1.2 Memory System Next, referring to Figure 1, the internal configuration of the memory system 3 will be described. As shown in Figure 1, the memory system 3 includes a memory controller 4 and a memory device 5.

[0013] The memory controller 4 is comprised of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 4 may be composed of multiple semiconductor chips. The memory controller 4 controls the memory device 5 based on requests from the host 2.

[0014] Specifically, for example, the memory controller 4 executes a write operation to write data to the memory device 5 based on a write command from the host 2. The memory controller 4 also executes a read operation to read the data written by the write operation from the memory device 5 based on a read command from the host 2.

[0015] The memory device 5 is, for example, a semiconductor package that functions as NAND flash memory. The memory device 5 includes an interface chip (IF chip) 10, and a plurality of core chips 20-1, 20-2, 20-3, and 20-4. In the example shown in Figure 1, four core chips 20-1 to 20-4 are shown, but any number of core chips can be implemented in the memory device 5.

[0016] The IF chip 10 is a semiconductor chip that manages communication between the memory controller 4 and the multiple core chips 20-1 to 20-4. The IF chip 10 is connected to the memory controller 4 via the memory bus MB. The memory bus MB conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0017] Multiple core chips 20-1, 20-2, 20-3, and 20-4 are semiconductor chips that store data nonvolatilely. The multiple core chips 20-1, 20-2, 20-3, and 20-4 are stacked on top of the IF chip 10 in this order, for example.

[0018] The core chip 20-1 includes a plurality of vias V1 and a plurality of wirings W1. Each of the plurality of vias V1 is a TSV (through silicon via) that penetrates the semiconductor substrate SUB1 constituting the core chip 20-1. Each of the plurality of vias V1 electrically connects the IF chip 10 to the corresponding wiring W1. In other words, the core chip 20-1 communicates with the IF chip 10 via the vias V1.

[0019] The core chip 20-2 includes multiple vias V2 and multiple wirings W2. Each of the multiple vias V2 is a TSV that penetrates the semiconductor substrate SUB2 that constitutes the core chip 20-2. Each of the multiple vias V2 electrically connects the corresponding wiring W1 in the core chip 20-1 to the corresponding wiring W2 in the core chip 20-2. In other words, the core chip 20-2 communicates with the IF chip 10 via vias V2 and V1.

[0020] The core chip 20-3 includes a plurality of vias V3 and a plurality of wirings W3. Each of the plurality of vias V3 is a TSV that penetrates the semiconductor substrate SUB3 that constitutes the core chip 20-3. Each of the plurality of vias V3 electrically connects the corresponding wiring W2 in the core chip 20-2 to the corresponding wiring W3 in the core chip 20-3. That is, the core chip 20-3 communicates with the IF chip 10 via vias V3, V2, and V1.

[0021] The core chip 20-4 includes a plurality of vias V4 and a plurality of wirings W4. Each of the plurality of vias V4 is a TSV that penetrates the semiconductor substrate SUB4 that constitutes the core chip 20-4. Each of the plurality of vias V4 electrically connects the corresponding wiring W3 in the core chip 20-3 to the corresponding wiring W4 in the core chip 20-4. That is, the core chip 20-4 communicates with the IF chip 10 via vias V4, V3, V2, and V1.

[0022] In the following, vias V1-V4 and wiring W1-W4 that are connected to each other may be considered as a single via. In this case, vias V1-V4 and wiring W1-W4 considered as a single via will simply be called via V.

[0023] 1.1.3 Memory Devices Figure 2 is a block diagram showing an example of the functional configuration of a memory device according to the first embodiment and its connection to a memory controller. As shown in Figure 2, the IF chip 10 includes an input / output control circuit 11, a logic control circuit 12, a ready / busy control circuit 13, a register 14, a sequencer 15, a voltage generation circuit 16, and a fuse circuit 17. The core chip 20-1 includes a memory cell array 21, a low decoder module 22, and a sense amplifier module 23. Although not shown in Figure 2, each of the core chips 20-2, 20-3, and 20-4 includes a configuration equivalent to that of the core chip 20-1.

[0024] Furthermore, a TSV switching circuit 30-1 is provided so as to span logically the IF chip 10 and the core chip 20-1. A TSV switching circuit 30-2 is provided so as to span core chip 20-1 and core chip 20-2. A TSV switching circuit 30-3 is provided so as to span core chip 20-2 and core chip 20-3. A TSV switching circuit 30-4 is provided so as to span core chip 20-3 and core chip 20-4. Physically, the TSV switching circuit 30-1 can be placed anywhere inside the IF chip 10, and inside each of the core chips 20-1, 20-2, 20-3, and 20-4.

[0025] The input / output control circuit 11, the logic control circuit 12, and the ready / busy control circuit 13 transmit and receive various signals to and from the memory controller 4 via the memory bus MB. The signals transmitted and received by the input / output control circuit 11 include, for example, signals DQ<7:0>, DQS, and DQSn. The signals received by the logic control circuit 12 include, for example, signals CEn<3:0>, CLE, ALE, WEn, RE, and REn. The ready / busy control circuit 13 transmits the signal RBn<3:0>. In this specification, the suffix n in the name of a signal means that the signal is asserted when it is at a low level. Hereinafter, signals transmitted from the memory controller 4 to the memory device 5 are referred to as input signals. Signals transmitted from the memory device 5 to the memory controller 4 are referred to as output signals.

[0026] Signal DQ<7:0> is an 8-bit signal. Signal DQ<7:0> is a bidirectional signal and represents the data transmitted and received between the memory device 5 and the memory controller 4. Hereinafter, when transmitted from the memory controller 4 to the memory device 5, signal DQ<7:0> is called input data DQ<7:0>. When transmitted from the memory device 5 to the memory controller 4, signal DQ<7:0> is called output data DQ<7:0>. Input data DQ<7:0> includes, for example, write data, address information, and commands. Output data DQ<7:0> includes, for example, read data.

[0027] Signals DQS and DQSn are bidirectional signals and are strobe signals for signal DQ<7:0>. Signal DQSn is the inverse signal of signal DQS. Signals DQS and DQSn are output signals when signal DQ<7:0> is an output signal, and input signals when signal DQ<7:0> is an input signal.

[0028] Signal CEn<3:0> is an input signal for enabling core chips 20-1, 20-2, 20-3, and 20-4. For example, the signals CEn that make up signal CEn<3:0> <0> , CEn <1> , CEn <2> , and CEn <3> These correspond to core chips 20-1, 20-2, 20-3, and 20-4, respectively.

[0029] Signals CLE and ALE are input signals that notify memory device 5 that input signal DQ<7:0> is command and address information, respectively.

[0030] The signal WEn is an input signal used to input data DQ<7:0> into the memory device 5.

[0031] Signals RE and REn are input signals for reading output data DQ<7:0> from memory device 5. Signal REn is the inverted signal of signal RE.

[0032] Signal RBn<3:0> is an output signal that indicates whether core chips 20-1, 20-2, 20-3, and 20-4 are ready or busy. For example, the signals RBn that make up signal RBn<3:0> <0> RBn <1> RBn <2> , and RBn <3> These correspond to core chips 20-1, 20-2, 20-3, and 20-4, respectively. The ready state is when core chip 20 is able to receive instructions from memory controller 4. The busy state is when core chip 20 is unable to receive instructions from memory controller 4. A low-level signal RBn<3:0> indicates the busy state.

[0033] The input / output control circuit 11 receives input data DQ<7:0> from the memory controller 4. The input / output control circuit 11 extracts address information, commands, and write data from the input data DQ<7:0> and sends them to the register 14. The input / output control circuit 11 reads the read data from the register 14 and outputs it to the memory controller 4 as output data DQ<7:0>. The logic control circuit 12 receives signals CEn<3:0>, CLE, ALE, WEn, RE, and REn from the memory controller 4. The ready / busy control circuit 13 sends the signal RBn<3:0> received from the sequencer 15 to the memory controller 4.

[0034] Register 14 temporarily stores address information, commands, write data, and read data for each of the core chips 20-1, 20-2, 20-3, and 20-4. The address information includes, for example, column addresses, block addresses, and page addresses. The sequencer 15 controls the operation of the entire memory device 5 based on the commands stored in register 14. The voltage generation circuit 16 generates various voltages used in write, read, and erase operations. The address information and write data stored in register 14, the control signals generated by the sequencer 15, and the various voltages generated by the voltage generation circuit 16 are supplied to the memory cell arrays 21, row decoder modules 22, and sense amplifier modules 23 of each of the multiple core chips 20-1, 20-2, 20-3, and 20-4 via TSV switching circuits 30-1, 30-2, 30-3, and 30-4. The read data from each of the memory cell arrays 21 of the multiple core chips 20-1, 20-2, 20-3, and 20-4, read by the sense amplifier module 23, is stored in register 14 via TSV switching circuits 30-1, 30-2, 30-3, and 30-4.

[0035] The fuse circuit 17 is a circuit that stores the settings of the TSV switching circuits 30-1, 30-2, 30-3, and 30-4, which will be described later. The fuse circuit 17 may, for example, melt a metal component to store the settings, or it may be an electronic fuse.

[0036] The memory cell array 21 includes a plurality of blocks, a plurality of bit lines, and a plurality of word lines. A block is, for example, a unit of data erasure in an erasure process. Each of the plurality of blocks includes a plurality of memory cells. A memory cell is, for example, a unit of element that stores data non-volatilely. Each of the plurality of memory cells is associated with a set of bit lines and word lines.

[0037] The row decoder module 22 selects one block in the corresponding memory cell array 21 based on the block address in register 14. The row decoder module 22 further selects a word line in the selected block based on the page address in register 14.

[0038] The sense amplifier module 23 selects a bit line based on the column address in register 14. During the write operation, the sense amplifier module 23 transfers the write data to the memory cell array 21 via the selected bit line. During the read operation, the sense amplifier module 23 senses the threshold voltage of the memory cell via the selected bit line. Then, the sense amplifier module 23 generates read data based on the sense result and sends the generated read data to register 14.

[0039] The TSV switching circuit 30-1 has the function of switching the TSV used for the communication of a predetermined signal between the IF chip 10 and the core chip 20-1 among a plurality of vias V1. The TSV switching circuit 30-2 has the function of switching the TSV used for the communication of a predetermined signal between the core chip 20-1 and the core chip 20-2 among a plurality of vias V2. The TSV switching circuit 30-3 has the function of switching the TSV used for the communication of a predetermined signal between the core chip 20-2 and the core chip 20-3 among a plurality of vias V3. The TSV switching circuit 30-4 has the function of switching the TSV used for the communication of a predetermined signal between the core chip 20-3 and the core chip 20-4 among a plurality of vias V4.

[0040] In the following explanation, it is assumed that a predetermined TSV is pre-assigned to the communication of a given signal. The predetermined TSV assigned to a given signal is also called the "default via". The TSV used to switch from the default via for the communication of a given signal is also called the "redundant via". The TSV used for other communications (for example, control signals used for via switching) is also called the "control via". The control via may be either the default via or the redundant via.

[0041] Furthermore, when switching from a default via to a redundant via occurs during the communication of signals transmitted and received between the IF chip 10 and the core chip 20-4, it is sufficient for at least one of vias V1, V2, V3, and V4 to actually be switched. In the first and second implementation examples of the first embodiment described below, for the sake of explanation, it is assumed that when switching from a default via to a redundant via occurs, all of vias V1, V2, V3, and V4 are switched.

[0042] 1.1.4 TSV Switching Circuit Referring to Figures 3 to 11, an example of the implementation of the TSV switching circuit in the memory device according to the first embodiment will be described. Figures 3 to 11 mainly show an example of the implementation of the TSV switching circuit 30-1 for unidirectional signals transmitted from the IF chip 10, but the TSV switching circuit 30-1 for unidirectional signals transmitted from the core chip 20-2 is configured similarly. For an example of the implementation of the TSV switching circuit 30-1 for bidirectional signals transmitted and received between the IF chip 10 and the core chip 20-1, the differences from the implementation example for unidirectional signals will be mainly described. In addition, each of the TSV switching circuits 30-2, 30-3, and 30-4 has a configuration equivalent to the TSV switching circuit 30-1 shown in Figures 3 to 11.

[0043] Figure 3 is a circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to the first embodiment. Figure 3 shows a TSV switching circuit 30-1 for a 1-bit signal SIG transmitted from the IF chip 10, and a part of the TSV switching circuit 30-2.

[0044] As shown in Figure 3, the IF chip 10 includes internal circuit C0, and the core chip 20-1 includes internal circuits C1 and C2. Regarding the signal SIG, the TSV switching circuit 30-1 in the core chip 20-1 includes a default via dV1, a redundant via rV1, and switches dSW1 and rSW1. The TSV switching circuit 30-2 in the core chip 20-2 includes a default via dV2 and a redundant via rV2. Regarding the signal SIG transmitted from the internal circuit C0 of the IF chip 10, the internal circuit C0 of the IF chip 10 and the internal circuit C1 of the core chip 20-1 are connected via the TSV switching circuit 30-1 and wiring W1. In the core chip 20-1, internal circuit C2 generates the signal SIG output to the core chip 20-2.

[0045] The default via dV1 has a first terminal to which the signal SIG is input, and a second terminal connected to the first terminal of switch dSW1. Switch dSW1 has a second terminal connected to wiring W1.

[0046] The redundant via rV1 has a first terminal to which the signal SIG is input, and a second terminal connected to the first terminal of switch rSW1. Switch rSW1 has a second terminal connected to wiring W1. Wiring W1 is further connected to the default via dV2 and the redundant via rV2.

[0047] Each of switches dSW1 and rSW1 is logically a two-terminal switch. When switch dSW1 is ON, switch rSW1 is OFF. When switch dSW1 is OFF, switch rSW1 is ON. The physical implementation of each of switches dSW1 and rSW1 can be any implementation that logically realizes a two-terminal switch. For example, if the default via dV1 is used for unidirectional signal transmission, each switch may be implemented as a tristate buffer where one of them is exclusively ON, or as a bus switch where the ON / OFF function is implemented by a MOSFET. If the default via dV1 is used for bidirectional signal transmission and reception, each switch may be implemented as four tristate buffers where at most one is ON. The same applies to the other default vias and redundant vias described below.

[0048] With the above configuration, when switch dSW1 is ON, the signal SIG can be communicated between the IF chip 10 and the core chip 20-1 via the default via dV1 and without using the redundant via rV1. Also, when switch rSW1 is ON, the signal SIG can be communicated between the IF chip 10 and the core chip 20-1 via the redundant via rV1 and without using the default via dV1.

[0049] Thus, in the implementation example of the TSV switching circuit 30-1 for unidirectional signals transmitted from the IF chip 10, the internal circuit C0 of the IF chip 10 and the internal circuit C1 of the core chip 20-1 function as a transmit circuit and a receive circuit, respectively. In the implementation example of the TSV switching circuit 30-1 for unidirectional signals transmitted from the core chip 20-1, the internal circuit C0 of the IF chip 10 and the internal circuit C1 of the core chip 20-1 function as a receive circuit and a transmit circuit with a tristate buffer, respectively. In the implementation example of the TSV switching circuit 30-1 for bidirectional signals transmitted and received between the IF chip 10 and the core chip 20-1, the internal circuit C0 of the IF chip 10 and the internal circuit C1 of the core chip 20-1 function as a transmit / receive circuit with a tristate buffer and a transmit / receive circuit with a tristate buffer, respectively.

[0050] Figure 4 is a circuit diagram showing a second implementation example of the TSV switching circuit included in the memory device according to the first embodiment. As shown in Figure 4, the core chip 20-1 includes internal circuits C1 and C2. The TSV switching circuit 30-1 in the IF chip 10 includes inverters IV1 and IV2, a logical AND circuit AND1, and a negative logical AND circuit NAND1. The TSV switching circuit 30-1 in the core chip 20-1 includes a default via dV1, a redundant via rV1, a control via cV1, an inverter IV3, and negative logical AND circuits NAND2, NAND3, and NAND4. The TSV switching circuit 30-2 in the core chip 20-1 includes inverters IV4 and IV5, a logical AND circuit AND2, and a negative logical AND circuit NAND5. The TSV switching circuit 30-2 in the core chip 20-2 includes a default via dV2, a redundant via rV2, and a control via cV2.

[0051] Signal SEL is a 1-bit control signal supplied from fuse circuit 17. Signal SEL is used to switch vias related to signal SIG in TSV switching circuits 30-1, 30-2, 30-3, and 30-4. Signal SEL is supplied to core chip 20-1 via control via cV1 and further supplied to core chip 20-2 via control via cV2. When signal SEL is "0", default via dV1 is selected, and when signal SEL is "1", redundant via rV1 is selected. When signal SEL is "0", default via dV2 is selected, and when signal SEL is "1", redundant via rV2 is selected.

[0052] Inverter IV1 includes an input terminal to which the signal SEL is input, and an output terminal to which the result of the negation operation of the input signal is output.

[0053] The AND1 logic AND circuit includes a first input terminal to which the signal SIG is input, a second input terminal connected to the output terminal of inverter IV1, and an output terminal that outputs the result of the logic AND operation of each input signal to the first terminal of default via dV1.

[0054] The NAND1 negative AND circuit includes a first input terminal to which the signal SIG is input, a second input terminal to which the signal SEL is input, and an output terminal to output the result of the negative AND operation of each input signal.

[0055] Inverter IV2 includes an input terminal connected to the output terminal of the negative AND circuit NAND1, and an output terminal that outputs the result of the negative operation of the input signal to the first terminal of the redundant via rV1.

[0056] Inverter IV3 includes an input terminal to which the signal SEL is input via control via cV1, and an output terminal to which the result of the negation operation of the input signal is output.

[0057] The NAND2 negative AND circuit includes a first input terminal connected to the second terminal of the default via dV1, a second input terminal connected to the output terminal of inverter IV3, and an output terminal that outputs the result of the negative AND operation of each input signal.

[0058] The NAND3 negative AND circuit includes a first input terminal connected to the second terminal of a redundant via rV1, a second input terminal to which the signal SEL is input via a control via cV1, and an output terminal that outputs the result of the negative AND operation of each input signal.

[0059] The negative AND circuit NAND4 includes a first input terminal connected to the output terminal of the negative AND circuit NAND2, a second input terminal connected to the output terminal of the negative AND circuit NAND3, and an output terminal that outputs the result of the negative AND operation of each input signal to wiring W1.

[0060] Internal circuit C1 receives signal SIG from IF chip 10 via wiring W1. Internal circuit C1 uses signal SIG for internal processing in core chip 20-1.

[0061] Internal circuit C2 is a circuit that generates the signal SIG within the core chip 20-1. Internal circuit C2 outputs the signal SIG to the AND gate AND2 and the NAND gate NAND5.

[0062] Inverter IV4 includes an input terminal to which the signal SEL is input via control via cV1, and an output terminal to which the result of the negation operation of the input signal is output.

[0063] The AND2 logic AND circuit includes a first input terminal to which the signal SIG is input from the internal circuit C2, a second input terminal connected to the output terminal of inverter IV4, and an output terminal that outputs the result of the logic AND operation of each input signal to the first terminal of default via dV2.

[0064] The NAND5 negative AND circuit includes a first input terminal to which the signal SIG is input from the internal circuit C2, a second input terminal to which the signal SEL is input via the control via cV1, and an output terminal to output the result of the negative AND operation of each input signal.

[0065] Inverter IV5 includes an input terminal connected to the output terminal of the NAND5 negative AND circuit, and an output terminal that outputs the result of the negative operation of the input signal to the first terminal of the redundant via rV2.

[0066] Figure 4 is a circuit diagram showing an example implementation of a selection circuit used for a unidirectional signal output from the IF chip 10. It shows the selection circuit from when the signal SIG is output from the internal circuit C0 of the IF chip 10 to when it is input to the internal circuit C1 of the core chip 20-1. When the signal SIG is a bidirectional signal, a tristate buffer is implemented between the final stage of the transmission circuit in both the internal circuit C0 of the IF chip 10 and the internal circuit C1 of the core chip 20-1 and the default via. The same applies to redundant vias.

[0067] Figure 5 shows an example of the relationship between signals transmitted by the TSV switching circuit according to the first embodiment. In Figure 5, the values ​​at the default via dV1, redundant via rV1, the output terminals of the negative AND circuits NAND2 and NAND3, and the wiring W1 are shown for each pair of signal values ​​SEL and SIG.

[0068] <If default via dV1 is selected> First, let's explain the case where the default via dV1 is selected. In this case, the fuse circuit 17 outputs "0" as the signal SEL.

[0069] In this case, the second input terminal of the AND1 circuit and the second input terminal of the NAND2 circuit are both input to "1". Therefore, the value at default via dV1 corresponds to the value of signal SIG. Also, the value at the output terminal of the NAND2 circuit is the inverted value of the value at default via dV1 (i.e., signal SIG).

[0070] On the other hand, the second input terminal of the negative AND circuit NAND1 and the second input terminal of the negative AND circuit NAND3 are both input to "0". Therefore, the value at the redundant via rV1 will be "0" regardless of the value of the signal SIG. Also, the value at the output terminal of the negative AND circuit NAND3 will be "1" regardless of the value at the redundant via rV1 (i.e., even if the value at the redundant via rV1 changes to "1" due to some abnormality).

[0071] Therefore, the value at the output terminal of the negative AND circuit NAND4, i.e., the value at wiring W1, will be the value corresponding to the signal SIG, regardless of whether the redundant via rV1 is functioning correctly, provided that the default via dV1 is functioning correctly.

[0072] <If redundant via rV1 is selected> Next, we will describe the case where the redundant via rV1 is selected. In this case, the fuse circuit 17 outputs "1" as the signal SEL.

[0073] In this case, "0" is input to the second input terminal of the AND1 logic AND circuit and the second input terminal of the NAND2 logic AND circuit. Therefore, the value at default via dV1 will be "0" regardless of the value of signal SIG. Also, the value at the output terminal of the NAND2 logic AND circuit will be "1" regardless of the value at default via dV1 (i.e., even if the value at default via dV1 changes to "1" due to some abnormality).

[0074] On the other hand, the second input terminal of the negative AND circuit NAND1 and the second input terminal of the negative AND circuit NAND3 are both input with a "1". Therefore, the value in the redundant via rV1 corresponds to the value of the signal SIG. Also, the value at the output terminal of the negative AND circuit NAND3 is the inverted value of the value in the redundant via rV1 (i.e., the signal SIG).

[0075] Therefore, the value at the output terminal of the negative AND circuit NAND4, i.e., the value at wiring W1, will be the value corresponding to the signal SIG, regardless of whether the default via dV1 is functioning correctly, provided that the redundant via rV1 is functioning correctly.

[0076] With the above configuration, when signal SEL is "0", signal SIG can be communicated between the IF chip 10 and the core chip 20-1 via the default via dV1, regardless of whether the redundant via rV1 is functioning correctly. Also, when signal SEL is "1", signal SIG can be communicated between the IF chip 10 and the core chip 20-1 via the redundant via rV1, regardless of whether the default via dV1 is functioning correctly.

[0077] 1.2 Effects according to the first embodiment According to the first embodiment, the TSV switching circuit 30-1 is configured to switch between a state in which the signal SIG is communicated between the IF chip 10 and the core chip 20-1 via the default via dV and a state in which the signal SIG is communicated via the redundant via rV.

[0078] For example, in the first implementation example, by turning switch dSW1 ON and switch rSW1 OFF, communication via the default via dV becomes possible. By turning switch dSW1 OFF and switch rSW1 ON, communication via the redundant via rV becomes possible.

[0079] Furthermore, in the second implementation example, for example, the control signal SEL can be used to select whether to communicate via the default via dV or the redundant via rV. This allows the redundant via rV to be used even if the default via dV has a connection failure. As a result, chip failure can be avoided, and the yield of the memory device 5 can be improved.

[0080] 1.3 Modifications of the First Embodiment Various modifications can be applied to the first embodiment described above.

[0081] 1.3.1 First Modification of the First Embodiment The first embodiment described above describes a case where one redundant via is assigned to one default via, but it is not limited to this. For example, one redundant via may be assigned to multiple default vias. The following mainly describes configurations that differ from the first embodiment. Configurations equivalent to the first embodiment will be omitted from the description as appropriate.

[0082] Figure 6 is a circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to a first modification of the first embodiment. The configuration shown in Figure 6 corresponds to the configuration in the first embodiment shown in Figure 3.

[0083] As shown in Figure 6, the IF chip 10 has an internal circuit C0 <0> and C0 <1> Including the core chip 20-1, the internal circuit C1 <0> , C1 <1> , C2 <0> , and C2 <1> Includes the signal SIG. <0> and SIG <1> Regarding this, the TSV switching circuit 30-1 is driver D0 in the IF chip 10. <0> and D0 <1> , and switch dSW0a <0> dSW0a <1> , and rSW0a are included. The TSV switching circuit 30-1 is the default via dV1 in the core chip 20-1. <0> and dV1 <1> , redundant via rV1, and switch dSW1b <0> dSW1b <1> , and rSW1b included. Default via dV1 <0> This is an example of the first via. Default via dV1 <1> This is an example of a second via. Redundant via rV1 is an example of a third via. Switch rSW0a is an example of a first switch. Switch dSW1b <0> This is an example of a second switch. Switch dSW1b <1> This is an example of a third switch. Switch rSW1b is an example of a fourth switch.

[0084] The TSV switching circuit 30-2 is located in the core chip 20-1 and driver D1 <0> and D1 <1> , and switch dSW1a <0> dSW1a <1> , and rSW1a are included. The TSV switching circuit 30-2 is the default via dV2 in the core chip 20-2. <0> and dV2 <1> , and also includes redundant via rV2. Internal circuit C0 of IF chip 10 <0> The signal transmitted from SIG <0> Regarding the internal circuit C0 of IF chip 10, <0> and the internal circuit C1 of the core chip 20-1 <0> This is the TSV switching circuit 30-1 and wiring W1 <0> It is connected via the internal circuit C0 of the IF chip 10. <1> The signal transmitted from SIG <1> Regarding the internal circuit C0 of IF chip 10, <1> and the internal circuit C1 of the core chip 20-1 <1> This is the TSV switching circuit 30-1 and wiring W1 <1> It is connected via wiring W1. <0> and W1 <1> Each of these is the internal circuit C1 of the core chip 20-1. <0> and C1 <1> The connection is established.

[0085] Driver D0 <0> The signal is SIG <0> It has an input terminal to which a signal is received and an output terminal. Driver D0 <1> The signal is SIG <1> It has an input terminal to which a signal SIG is input, and an output terminal. <0> SIG <1> If it is a bidirectional signal, driver D0 <0> and driver D0 <1> This is implemented using a tristate buffer.

[0086] Switch dSW0a <0> and dSW0a <1> Each of these is a two-terminal switch. Switch dSW0a <0> Driver D0 <0> The first terminal is connected to the output terminal, and the default via dV1 <0> Switch dSW0a has a second end connected to the first end. <1> Driver D0 <1> The first terminal is connected to the output terminal, and the default via dV1 <1> It has a second end connected to the first end of the first end.

[0087] Switch rSW0a is a 4-terminal switch. Switch rSW0a is driver D0 <0> The first terminal is connected to the output terminal of driver D0 <1> It has a second terminal connected to the output terminal, a third terminal connected to the first terminal of redundant via rV1, and a fourth terminal that is grounded. When switch rSW0a is ON, the third terminal is connected to either the first or second terminal. When switch rSW0a is OFF, the third terminal is connected to the fourth terminal.

[0088] Switch dSW1b <0> and dSW1b <1> Each of these is a two-terminal switch. Switch dSW1b <0> The default via is dV1 <0> The first end is connected to the second end, and wiring W1 <0> It has a second end connected to and a switch dSW1b <1> The default via is dV1 <1> The first end is connected to the second end, and wiring W1 <1> It has a second end connected to and

[0089] Switch rSW1b is a 4-terminal switch. Switch rSW1b is connected to the first terminal which is connected to the second terminal of redundant via rV1, and to wiring W1 <0> The second end is connected to the wiring W1 <1> It has a third end connected to the switch and a fourth end that is grounded. When switch rSW1b is ON, the first end is connected to either the second or third end. When switch rSW1b is OFF, the first end is connected to the fourth end.

[0090] Driver D1 <0> This is the internal circuit C2 <0> Driver D1 has an input terminal connected to the output terminal and an output terminal. <1> This is the internal circuit C2 <1> It has an input terminal connected to the output terminal and an output terminal. Signal SIG <0> SIG <1> If it is a bidirectional signal, driver D1 <0> and driver D1 <1> This is implemented using a tristate buffer.

[0091] Internal circuit C1 <0> Wiring W1 <0> Through the internal circuit C0 of the IF chip 10 <0> From signal SIG <0> Receives. Internal circuit C1 <1> Wiring W1 <1> Through the internal circuit C0 of the IF chip 10 <1> From signal SIG <1> Receives. Internal circuit C1 <0> and C1 <1> These are the signals SIG <0> and SIG <1> This is used for internal processing in the core chip 20-1.

[0092] Internal circuit C2 <0> and C2 <1> Each of these is a signal SIG within the core chip 20-1. <0> and SIG <1> This is a circuit that generates [something]. Internal circuit C2 <0> Driver D1 <0> The input terminal has a signal SIG <0> Outputs the following: Internal circuit C2 <1> Driver D1 <1> The input terminal has a signal SIG <1> Outputs.

[0093] Switch dSW1a <0> and dSW1a <1> Each of these is a two-terminal switch. Switch dSW1a <0> Driver D1 <0> The first terminal is connected to the output terminal, and the default via dV2 <0> Switch dSW1a has a second end connected to the first end. <1> Driver D1 <1> The first terminal is connected to the output terminal, and the default via dV2 <1> It has a second end connected to the first end of the first end.

[0094] Switch rSW1a is a 4-terminal switch. Switch rSW1a is driver D1 <0> The first terminal is connected to the output terminal of driver D1 <1> It has a second terminal connected to the output terminal, a third terminal connected to the first terminal of the redundant via rV2, and a fourth terminal that is grounded. When switch rSW1a is ON, the third terminal is connected to either the first or second terminal. When switch rSW1b is OFF, the third terminal is connected to the fourth terminal.

[0095] In Figure 6, the internal circuit C0 <0> The signal SIG generated by <0> The default via is dV1 <0> Wiring via W1 <0> It is sent to the internal circuit C0 <1> The signal SIG generated by <1> Wiring W1 via redundant via rV1 <1> It is sent to the internal circuit C2 <0> The signal SIG generated by <0> The default via is dV2 <0> It is transmitted to and internal circuit C2 <1> The signal SIG generated by <1> This shows the case where it is sent to the redundant via rV2. In this case, switch dSW0a <0> dSW1b <0> , and dSW1a <0> This will turn on. Switch dSW0a <1> dSW1b <1> , and dSW1a <1> This will be turned off. In switches rSW0a and rSW1a, the second terminal and the third terminal are connected. In switch rSW1b, the first terminal and the third terminal are connected. Note that driver D0 <0> and D0 <1> This is the signal SIG from IF chip 10. <0> and SIG <1> The system turns on when the output is displayed, and off otherwise. Driver D1 <0> and D1 <1> This is the signal SIG from core chip 20-1. <0> and SIG <1> The system turns on when the output is displayed, and off otherwise.

[0096] Meanwhile, internal circuit C0 <0> The signal SIG generated by <0> Wiring W1 via redundant via rV1 <0> It is sent to the internal circuit C0 <1> The signal SIG generated by <1> The default via is dV1 <1> Wiring via W1 <1> It is sent to the internal circuit C2 <0> The signal SIG generated by <0> The data is sent to the redundant via rV2, and the internal circuit C2 <1> The signal SIG generated by <1> The default via is dV2 <1> When a signal is sent, each switch will be in the following state: namely, switch dSW0a <0> dSW1b <0> , and dSW1a <0> This will turn off. Switch dSW0a <1> dSW1b <1> , and dSW1a <1> This is turned ON. In switches rSW0a and rSW1a, the first terminal and the third terminal are connected. In switch rSW1b, the first terminal and the second terminal are connected. Note that driver D0 <0> and D0 <1> This is the signal SIG from IF chip 10. <0> and SIG <1> The system turns on when the output is displayed, and off otherwise. Driver D1 <0> and D1 <1> This is the signal SIG from core chip 20-1. <0> and SIG <1> The system turns on when the output is displayed, and off otherwise.

[0097] With the above configuration, the signal SIG <0> and SIG <1> Any one of these communication paths can be switched to a single redundant via rV1.

[0098] Figure 7 is a circuit diagram showing a second implementation example of the TSV switching circuit included in a memory device according to a first modification of the first embodiment. The configuration shown in Figure 7 corresponds to the configuration in the first embodiment shown in Figure 4.

[0099] As shown in Figure 7, the core chip 20-1 has an internal circuit C1 <0> , C1 <1> , C2 <0> , and C2 <1> This includes the TSV switching circuit 30-1, which in the IF chip 10 controls inverter IV1 <0> and IV1 <1> AND1 logic circuit <0> AND1 <1> , and the negated AND circuit NAND1 <0> NAND1 <1> , and NAND1r. The TSV switching circuit 30-1 is located in the core chip 20-1, with default via dV1 <0> and dV1 <1> , redundant via rV1, control via cV1 <0> and cV1 <1> Inverter IV3 <0> and IV3 <1> , and also the negative AND circuit NAND2 <0> NAND2 <1> NAND3 <0> NAND3 <1> NAND4 <0> , and NAND4 <1> The TSV switching circuit 30-2 includes inverter IV4 in the core chip 20-1. <0> and IV4 <1> AND2 logic circuit <0> AND2 <1> , and also the negated AND circuit NAND5 <0> NAND5 <1> , and NAND5r. The TSV switching circuit 30-2 is located in the core chip 20-2, with default via dV2 <0> and dV2 <1> , redundant via rV2, and control via cV2 <0> and cV2 <1> Includes.

[0100] Inverter IV1 <0> This is an example of the first inverter. Inverter IV1 <1> This is an example of a second inverter. AND1 logic circuit. <0> This is an example of a first logic AND circuit. (AND1 logic AND circuit) <1> This is an example of a second logical AND circuit. Negated logical AND circuit NAND1 <0> This is an example of a first-generation NAND gate. NAND gate (NAND1) <1> This is an example of a second negative AND gate. The negative AND gate NAND1r is an example of a third negative AND gate. Inverter IV3 <0> This is an example of a third inverter. Inverter IV3 <1> This is an example of a fourth inverter. (NAND2) <0> This is an example of a fourth-order negated AND gate. (NAND2) <1> This is an example of a fifth-order negated AND gate. (NAND3) <0> This is an example of a sixth negative AND gate. (NAND3) <1> This is an example of a 7th negated AND gate. NAND4 negated AND gate <0> This is an example of an 8th negated AND gate. NAND4 negated AND gate <1> This is an example of a 9th negated AND circuit.

[0101] Signal SEL <0> and SEL <1> Each of these is a 1-bit control signal supplied from the fuse circuit 17. Signal SEL <0> and SEL <1> These are the signals SIG in the TSV switching circuits 30-1, 30-2, 30-3, and 30-4, respectively. <0> and SIG <1> Used for switching vias related to the signal SEL. <0> This is the control via cV1 <0> It is supplied to the core chip 20-1 via control via cV2 <0> The signal is further supplied to the core chip 20-2 via the SEL. <1> This is the control via cV1 <1> It is supplied to the core chip 20-1 via control via cV2 <1> The signal is further supplied to the core chip 20-2 via the SEL. <0> If it is "0", then the signal SIG <0> The default via is selected for the signal SEL. <0> If it is "1", then the signal SIG <0> A redundant via is selected for the signal SEL. <1> If it is "0", then the signal SIG <1> The default via is selected for the signal SEL. <1> If it is "1", then the signal SIG <1> A redundant via is selected for the signal SEL. <0> and SEL <1> The system is controlled so that none of the values ​​become "1".

[0102] Inverter IV1 <0> The signal SEL <0> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output. Inverter IV1 <1> The signal SEL <1> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output.

[0103] AND1 (Logical AND Circuit) <0> The signal is SIG <0> The first input terminal to which the input is received, and inverter IV1 <0> The second input terminal is connected to the output terminal, and the result of the logical AND operation of each input signal is set to default via dV1. <0> The output terminal that outputs to the first terminal of the AND gate includes the AND gate. <1> The signal is SIG <1> The first input terminal to which the input is received, and inverter IV1 <1> The second input terminal is connected to the output terminal, and the result of the logical AND operation of each input signal is set to default via dV1. <1> It includes an output terminal that outputs to the first end of the .

[0104] Negative AND gate (NAND1) <0> The signal is SIG <0> The first input terminal to which the signal SEL is input, and <0> It includes a second input terminal to which a signal is input, and an output terminal that outputs the result of the negative AND operation of each input signal. Negative AND circuit NAND1 <1> The signal is SIG <1> The first input terminal to which the signal SEL is input, and <1> It includes a second input terminal to which the input signal is received, and an output terminal that outputs the result of the negated logical AND operation of each input signal.

[0105] The negative AND gate NAND1r is a negative AND gate NAND1 <0> The first input terminal is connected to the output terminal of the NAND gate, and the negative AND gate is connected to the output terminal of the NAND gate. <1> It includes a second input terminal connected to the output terminal of and an output terminal that outputs the result of the negated logical AND operation of each input signal to the first terminal of redundant via rV1.

[0106] Inverter IV3 <0> This is the control via cV1 <0> The signal SEL is transmitted via <0> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output. Inverter IV3 <1> This is the control via cV1 <1> The signal SEL is transmitted via <1> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output.

[0107] Negative AND gate (NAND2) <0> The default via is dV1 <0> The first input terminal is connected to the second terminal of the inverter IV3 <0> It includes a second input terminal connected to the output terminal of the first input and an output terminal that outputs the result of the negative AND operation of each input signal. (NAND2 circuit) <1> The default via is dV1 <1> The first input terminal is connected to the second terminal of the inverter IV3 <1> It includes a second input terminal connected to the output terminal of the first input, and an output terminal that outputs the result of the negated logical AND operation of each input signal.

[0108] NAND3 (Negative AND gate) <0> This includes the first input terminal connected to the second terminal of redundant via rV1, and the control via cV1 <0> The signal SEL is transmitted via <0> It includes a second input terminal to which a signal is input, and an output terminal that outputs the result of the negative AND operation of each input signal. Negative AND circuit NAND3 <1> This includes the first input terminal connected to the second terminal of redundant via rV1, and the control via cV1 <1> The signal SEL is transmitted via <1> It includes a second input terminal to which the input signal is received, and an output terminal that outputs the result of the negated logical AND operation of each input signal.

[0109] NAND4 (Negative AND gate) <0> This is a NAND2 (negative AND gate) circuit. <0> The first input terminal is connected to the output terminal of the NAND3 circuit, and the negative AND gate is connected to the output terminal of the NAND3 circuit. <0> The second input terminal is connected to the output terminal of and the result of the negated logical AND operation of each input signal is wired to W1. <0> It includes an output terminal that outputs to the following. Negative AND gate NAND4 <1> This is a NAND2 (negative AND gate) circuit. <1> The first input terminal is connected to the output terminal of the NAND3 circuit, and the negative AND gate is connected to the output terminal of the NAND3 circuit. <1> The second input terminal is connected to the output terminal of and the result of the negated logical AND operation of each input signal is wired to W1. <1> It includes an output terminal that outputs to the following.

[0110] Internal circuit C1 <0> Wiring W1 <0> The signal SIG is transmitted from the IF chip 10 via this signal. <0> Receives. Internal circuit C1 <1> Wiring W1 <1> The signal SIG is transmitted from the IF chip 10 via this signal. <1> Receives. Internal circuit C1 <0> and C1 <1> These are the signals SIG <0> and SIG <1> This is used for internal processing in the core chip 20-1.

[0111] Internal circuit C2 <0> and C2 <1> Each of these is a signal SIG within the core chip 20-1. <0> and SIG <1> This is a circuit that generates [something]. Internal circuit C2 <0> The signal is SIG <0> AND gate <0> and the negated AND circuit NAND5 <0> Outputs to internal circuit C2. <1> The signal is SIG <1> AND gate <1> and the negated AND circuit NAND5 <1> Output to [this location].

[0112] Inverter IV4 <0> This is the control via cV1 <0> The signal SEL is transmitted via <0> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output. Inverter IV4 <1> This is the control via cV1 <1> The signal SEL is transmitted via <1> It includes an input terminal to which a signal is input and an output terminal to which the result of the negation operation of the input signal is output.

[0113] AND2 (Logical AND Circuit) <0> This is the internal circuit C2 <0> From signal SIG <0> The first input terminal to which the input is received, and inverter IV4 <0> The second input terminal is connected to the output terminal, and the result of the logical AND operation of each input signal is via default via dV2. <0> The output terminal that outputs to the first end of the circuit includes AND2. <1> This is the internal circuit C2 <1> From signal SIG <1> The first input terminal to which the input is received, and inverter IV4 <1> The second input terminal is connected to the output terminal, and the result of the logical AND operation of each input signal is via default via dV2. <1> It includes an output terminal that outputs to the first end of the .

[0114] NAND5 (negated AND gate) <0> This is the internal circuit C2 <0> From signal SIG <0> The first input terminal to which the signal is received, and the control via cV1 <0> The signal SEL is transmitted via <0> It includes a second input terminal to which a signal is input, and an output terminal that outputs the result of the negative AND operation of each input signal. Negative AND circuit NAND5 <1> This is the internal circuit C2 <1> From signal SIG <1> The first input terminal to which the signal is received, and the control via cV1 <1> The signal SEL is transmitted via <1> It includes a second input terminal to which the input signal is received, and an output terminal that outputs the result of the negated logical AND operation of each input signal.

[0115] The negative AND gate NAND5r is a negative AND gate NAND5 <0> The first input terminal is connected to the output terminal of the NAND5 circuit, and the negative AND gate is connected to the output terminal of the NAND5 circuit. <1> It includes a second input terminal connected to the output terminal of and an output terminal that outputs the result of the negated logical AND operation of each input signal to the first terminal of a redundant via rV2.

[0116] With the above configuration, the signal SEL <0> and SEL <1> If both are "0", then regardless of whether the redundant via rV1 is normal or not, the default via dV1 <0> and dV1 <1> The signal SIG is transmitted via this signal. <0> and SIG <1> They can communicate with each other. Signal SEL <0> If it is "1" and the signal SEL <1> If it is "0", the default via dV1 <0> Regardless of whether it is normal or not, the signal SIG is transmitted via redundant via rV1. <0> While communicating, default via dV1 <1> The signal SIG is transmitted via this signal. <1> It can communicate with the SEL signal. <0> If it is "0" and the signal SEL <1> If it is "1", the default via dV1 <1> Regardless of whether it is normal or not, the signal SIG is transmitted via redundant via rV1. <1> While communicating, default via dV1 <0> The signal SIG is transmitted via this signal. <0> It can communicate.

[0117] In the examples in Figures 6 and 7, we described a case where one redundant via is assigned to two default vias, but the number of default vias may be three or more, and the number of redundant vias may be two or more. In addition, the second implementation example shown in Figure 7 has a one-hot configuration where at most one of the control signals SEL<1:0> is "1", but other implementation methods are also possible. For example, the control signal SEL<1:0> may consist of an enable signal EN and an encoded selection signal. This is also true for subsequent implementation examples.

[0118] According to the first modification of the first embodiment, the TSV switching circuit 30-1 switches between the IF chip 10 and the core chip 20-1 via default via dV <0> The signal SIG is transmitted via this signal. <0> While communicating, default via dV <1> The signal SIG is transmitted via this signal. <1> The first state communicates with the signal SIG via redundant via rV. <0> While communicating, default via dV <1> The signal SIG is transmitted via this signal. <1> The second state for communication and the default via dV <0> The signal SIG is transmitted via this signal. <0> While communicating, the signal SIG is transmitted via redundant via rV. <1> It is configured to switch between a third state that communicates with and another state.

[0119] For example, in the first implementation example, switch dSW0a <0> dSW0a <1> dSW1b <0> , and dSW1b <1> The first state is achieved by turning on switch dSW0a, connecting the third and fourth terminals of switch rSW0a, and turning off switch rSW1b. <1> and dSW1b <1> Turn on switch dSW0a <0> and dSW1b <0> The second state is achieved by turning off switch dSW0a, connecting the first and third terminals of switch rSW0a, and connecting the first and second terminals of switch rSW1b. <0> and dSW1b <0> Turn on switch dSW0a <1> and dSW1b <1> The third state is achieved by turning off the switch, connecting the second and third terminals of switch rSW0a, and connecting the first and third terminals of switch rSW1b.

[0120] Furthermore, for example, in the second implementation example, the signal SEL <0> and SEL <1> By setting both to "0", the first state is achieved. Signal SEL <0> and SEL <1> The second state is achieved by setting these values ​​to "1" and "0" respectively. Signal SEL <0> and SEL <1> By setting these values ​​to "0" and "1" respectively, the third state is realized.

[0121] This allows the redundant via rV to be replaced by the default via dV. <0> and dV <1> It can be used as a substitute for any of the following.

[0122] 1.3.2 Second Modification of the First Embodiment The first modification of the first embodiment described above describes a case in which a signal passing through either the default via or a redundant via is transmitted to the wiring within the core chip, but it is not limited to this. Below, we will mainly describe configurations that differ from the first modification of the first embodiment. Configurations equivalent to the first modification of the first embodiment will be omitted from the description as appropriate.

[0123] Figure 8 is a circuit diagram showing a first implementation example of a TSV switching circuit included in a memory device according to a second modification of the first embodiment. The configuration shown in Figure 8 corresponds to the configuration in the first modification of the first embodiment shown in Figure 6.

[0124] As shown in Figure 8, the first implementation example of the TSV switching circuit 30-1 in the second modified example of the first embodiment is equivalent to the first implementation example in the first modified example of the first embodiment. In this circuit configuration, in Figure 8, the internal circuit C0 <0> The signal SIG generated by <0> The default via is dV1 <0> Wiring via W1 <0> It is sent to the internal circuit C0 <1> The signal SIG generated by <1> The default via is dV1 <1> Wiring W1 via both redundant via rV1 and redundant via rV1 <1> It is sent to the internal circuit C2 <0> The signal SIG generated by <0> The default via is dV2 <0> It is transmitted to and internal circuit C2 <1> The signal SIG generated by <1> The default via is dV2 <1> This indicates that the data is sent to both the and redundant via rV2. In this case, switch dSW0a <0> dSW0a <1> dSW1b <0> dSW1b <1> dSW1a <0> , and dSW1a <1> This is turned ON. In switches rSW0a and rSW1a, the second terminal and the third terminal are connected. In switch rSW1b, the first terminal and the third terminal are connected. Note that driver D0 <0> and D0 <1> This is the signal SIG from IF chip 10. <0> and SIG <1> If this is output, it will be in the ON state; otherwise, it will be in the OFF state. Driver D1 <0> and D1 <1> This is the signal SIG from core chip 20-1. <0> and SIG <1> If this is output, it will be in the ON state; otherwise, it will be in the OFF state.

[0125] Meanwhile, internal circuit C0 <0> The signal SIG generated by <0> The default via is dV1 <0> Wiring W1 via both redundant via rV1 and redundant via rV1 <0> It is sent to the internal circuit C0 <1> The signal SIG generated by <1> The default via is dV1 <1> Wiring via W1 <1> It is sent to the internal circuit C2 <0> The signal SIG generated by <0> The default via is dV2 <0> It is transmitted to both and redundant via rV2, and internal circuit C2 <1> The signal SIG generated by <1> The default via is dV2 <1> When a signal is sent, each switch will be in the following state: namely, switch dSW0a <0> dSW0a <1> dSW1b <0> dSW1b <1> dSW1a <0> , and dSW1a <1> This is turned ON. In switches rSW0a and rSW1a, the first terminal and the third terminal are connected. In switch rSW1b, the first terminal and the second terminal are connected. Note that driver D0 <0> and D0 <1> This is the signal SIG from IF chip 10. <0> and SIG <1> If this is output, it will be in the ON state; otherwise, it will be in the OFF state. Driver D1 <0> and D1 <1> This is the signal SIG from core chip 20-1. <0> and SIG <1> If this is output, it will be in the ON state; otherwise, it will be in the OFF state.

[0126] With the above configuration, two default vias dV1 are used for transmitting one signal SIG. <0> and dV1 <1> Any one of these and one redundant via rV1 can be used simultaneously.

[0127] Figure 9 is a circuit diagram showing a second implementation example of the TSV switching circuit included in a memory device according to a second modification of the first embodiment. The configuration shown in Figure 9 corresponds to the configuration in the first modification of the first embodiment shown in Figure 7.

[0128] As shown in Figure 9, the TSV switching circuit 30-1 in the second modified example of the first embodiment has an inverter IV1 in the IF chip 10. <0> and IV1 <1> Instead, a negative AND gate, NAND1m <0> and NAND1m <1> This includes the following. In the second modified example of the first embodiment, the TSV switching circuit 30-1 is located in the core chip 20-1, and the negative AND circuit NAND2 of the TSV switching circuit 30-1 in the first modified example of the first embodiment <0> NAND2 <1> NAND3 <0> NAND3 <1> NAND4 <0> , and NAND4 <1> Instead, the tristate buffer TS <0> and TS <1> Includes. Negative AND gate NAND1m <0> This is an example of a 10th negated AND gate. Negated AND gate NAND1m <1> This is an example of an 11th negated AND circuit. Tristate buffer TS <0> This is an example of a first tristate buffer. Tristate buffer TS <1> This is an example of a second tristate buffer.

[0129] The signal MODE is a 1-bit control signal supplied from the fuse circuit 17. The signal MODE is a control signal used to select whether or not to share a redundant via and a default via for a given signal SIG. When the signal MODE is "0", the redundant via and the default via are shared for the signal SIG corresponding to the signal SEL, which is "1". Therefore, when the signal MODE is "0", the signal SEL <0> and SEL <1> Either one of them becomes "1" (i.e., signal SEL) <0> and SEL <1> (These are controlled so that none of them become "0" or none of them become "1"). Also, when the signal MODE is "1", either a redundant via or a default via is used for all signals SIG (i.e., signal SEL <0> and SEL <1> (The values ​​are controlled so that none of them become "1".)

[0130] Negative AND gate (NAND1m) <0> The signal SEL <0> The first input terminal receives the signal MODE, the second input terminal receives the signal MODE, and the AND1 logic circuit <0> It has an output terminal connected to the second input terminal. Negated AND gate NAND1m <1> The signal SEL <1> The first input terminal receives the signal MODE, the second input terminal receives the signal MODE, and the AND1 logic circuit <1> It has an output terminal connected to the second input terminal of and

[0131] Tristate buffer TS <0> Inverter IV3 <0> The input terminal is connected to the output terminal, and wiring W1 <0> The output terminal is connected to the control via cV1. <0> The signal SEL is transmitted via <0> It has a control terminal to which the signal SEL is input. <0> If it is "1", the tristate buffer TS <0> This inverts the signal at the input terminal and conducts it to the output terminal. Signal SEL <0> If it is "0", the tristate buffer TS <0> This isolates the input terminal from the output terminal.

[0132] Tristate buffer TS <1> Inverter IV3 <1> The input terminal is connected to the output terminal, and wiring W1 <1> The output terminal is connected to the control via cV1. <1> The signal SEL is transmitted via <1> It has a control terminal to which the signal SEL is input. <1> If it is "1", the tristate buffer TS <1> This inverts the signal at the input terminal and conducts it to the output terminal. Signal SEL <1> If it is "0", the tristate buffer TS <1> This isolates the input terminal from the output terminal.

[0133] Internal circuit C1 <0> Wiring W1 <0> via default via dV1 <0> The second end of and the tristate buffer TS <0> It is connected to the output terminal of the internal circuit C1. <0> Wiring W1 <0> The signal SIG received from the IF chip 10 via the IF chip 10 <0> This is used for internal processing in the core chip 20-1. Internal circuit C1 <1> Wiring W1 <1> via default via dV1 <1> The second end of and the tristate buffer TS <1> It is connected to the output terminal of the internal circuit C1. <1> Wiring W1 <1> The signal SIG received from the IF chip 10 via the IF chip 10 <1> This is used for internal processing in the core chip 20-1.

[0134] With the above configuration, in addition to the mode in which the default via is switched to a redundant via (MODE="1"), the signal SIG can be transmitted in a mode in which the default via and the redundant via are shared (MODE="0").

[0135] According to a second modification of the first embodiment, the TSV switching circuit 30-1 has a first state, a second state, and a third state, in addition to a default via dV <0> and signal SIG via redundant via rV <0> While communicating, default via dV <1> The signal SIG is transmitted via this signal. <1> The fourth state for communication and the default via dV <0> The signal SIG is transmitted via this signal. <0> While communicating, default via dV <1> and signal SIG via redundant via rV <1> It is configured to switch between a fifth state that communicates with and another state.

[0136] For example, in the first implementation example, switch dSW0a <0> dSW0a <1> dSW1b <0> , and dSW1b <1> The fourth state is achieved by turning on switch dSW0a, connecting the first and third terminals of switch rSW0a, and connecting the first and second terminals of switch rSW1b. <0> dSW0a <1> dSW1b <0> , and dSW1b <1> The fifth state is achieved by turning on the switch, connecting the second and third terminals of switch rSW0a, and connecting the first and third terminals of switch rSW1b.

[0137] Furthermore, for example, in the second implementation example, the signal SEL <0> SEL <1> The first state is achieved by setting , and MODE to "0", "0", and "1" respectively. Signal SEL <0> SEL <1> The second state is achieved by setting and MODE to "1", "0", and "1" respectively. Signal SEL <0> SEL <1> The third state is achieved by setting MODE to "0", "1", and "1" respectively. Signal SEL <0> SEL <1> The fourth state is achieved by setting MODE to "1", "0", and "0" respectively. Signal SEL <0> SEL <1> The fifth state is achieved by setting MODE to "0", "1", and "0" respectively.

[0138] This means that if the default via dV is usable but its resistance increases, the resistance can be reduced by sharing a redundant via rV.

[0139] 1.3.3 Third Modification of the First Embodiment In the first embodiment described above, the case in which the signal SEL read from the fuse circuit 17 in the IF chip 10 is directly input to the TSV switching circuits 30-1 and 30-2 was described, but the invention is not limited to this. For example, the signal SEL read from the fuse circuit 17 may be stored in a register provided on each chip. The following mainly describes configurations that differ from the first embodiment. Configurations equivalent to the first embodiment will be omitted from the description as appropriate.

[0140] Figure 10 is a circuit diagram showing an example of the implementation of a TSV switching circuit in a memory device according to a third modified example of the first embodiment. The configuration shown in Figure 10 corresponds to the configuration in the first embodiment shown in Figure 4.

[0141] As shown in Figure 10, the IF chip 10 further includes a TSV control register 18. The core chip 20-1 further includes a TSV control register 24. Although not shown in Figure 10, core chips 20-2, 20-3, and 20-4 have the same configuration as core chip 20-1.

[0142] The TSV control register 18 stores information about the signal SEL stored in the fuse circuit 17, for example, when the memory device 5 is started. The TSV control register 24 receives and stores the information about the signal SEL stored in the TSV control register 18 via the control via cV1, for example.

[0143] With the above configuration, when transmitting signal SIG, it is possible to omit the transmission of signal SEL from IF chip 10 to core chip 20-1. In addition, the information stored in TSV control register 18 can be transferred to TSV control register 24 using one control via cV1, regardless of the number of signal SELs. For example, when the memory device 5 is started, the sequencer 15 of IF chip 10 writes the information stored in fuse circuit 17 to TSV control register 18. The sequencer 15 then serially transfers this information to each core chip 20 using control via cV1, and writes this information to TSV control register 24. The sequencer 15 may write different information to TSV control register 24 for each core chip 20. This allows different settings to be used for each core chip 20.

[0144] This configuration allows for a reduction in the number of TSVs compared to using multiple control vias cV1 depending on the number of signal SELs.

[0145] 1.3.4 Fourth Modification of the First Embodiment In the third modification of the first embodiment described above, the case in which information regarding the signal SEL is stored in the fuse circuit 17 within the IF chip 10 was explained, but the invention is not limited to this. For example, the fuse circuit may be provided outside the IF chip 10. Below, configurations different from the third modification of the first embodiment will be mainly described. Configurations equivalent to the third modification of the first embodiment will be omitted from the description as appropriate.

[0146] Figure 11 is a circuit diagram showing an example of the implementation of a TSV switching circuit in a memory device according to a fourth modification of the first embodiment. The configuration shown in Figure 11 corresponds to the configuration in the third modification of the first embodiment shown in Figure 10.

[0147] As shown in Figure 11, the fuse circuit 6 is located outside the IF chip 10. The TSV control register 18, as in the third modification described with reference to Figure 10, for example, is written by the sequencer 15 to the TSV control registers of the IF chip 10 and each core chip 20 via the pad 19, which is an external input terminal of the IF chip 10, when the memory device 5 is started up.

[0148] As configured as described above, the number of TSVs can be reduced compared to the case where multiple control vias cV1 are used depending on the number of signal SELs, similar to the third modification of the first embodiment. In addition, since the area for placing the fuse circuit on the IF chip 10 can be reduced, the constraints on the layout of the IF chip 10 can be relaxed.

[0149] 2. Second Embodiment Next, a memory device according to the second embodiment will be described. The second embodiment includes a configuration that performs a test process to test whether the TSV is normal or not. The following description will mainly focus on configurations and operations that differ from the first embodiment. Configurations and operations that are the same as those of the first embodiment will be omitted as appropriate.

[0150] 2.1 Functional configuration for memory device testing Figure 12 is a block diagram showing an example of a functional configuration for a test process of a memory device according to the second embodiment. As shown in Figure 12, the IF chip 10 further includes a pad 19A and a selector 51. The core chip 20-4 further includes a pad 25A.

[0151] Pad 19A is a terminal for connecting to a tester 40, which is an external device of the memory device 5, during the test process. During the test process, the IF chip 10 receives a test signal SIGt from the tester 40 via pad 19A. The test signal SIGt is, for example, a data pattern in which 1-bit data is arranged in a time series.

[0152] The test signal SIGt is input to selector 51. The signal SIG is also input to selector 51. Based on the signal MODE_T, which is a 1-bit control signal, selector 51 selects either signal SIG or test signal SIGt as the signal to be transmitted from IF chip 10 to core chip 20-1 via via V. Signal MODE_T may be an internal signal controlled by a command from the host bus HB, or it may be a control signal from a tester input from a pad provided separately from SIGt. For example, if signal MODE_T is "1", selector 51 selects the test signal SIGt. If signal MODE_T is "0", selector 51 selects the signal SIG. Modifications of the second embodiment, the third embodiment, and the fourth embodiment, and their modifications are similar.

[0153] When the memory device 5 operates in normal mode, performing normal operations such as writing and reading, the signal SIG is selected. On the other hand, when the memory device 5 operates in test mode, performing test operations, the test signal SIGt is selected. The test signal SIGt output from selector 51 passes through TSV switching circuits 30-1, 30-2, 30-3, 30-4 and pad 25A, which is an external output terminal of the core chip 20-4, and is then input to the tester 40 as a return signal SIGr.

[0154] The tester 40 checks for the consistency between the test signal SIGt and the return signal SIGr. If the test signal SIGt and the return signal SIGr match, the TSV set selected by the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 is determined to be normal. On the other hand, if the test signal SIGt and the return signal SIGr do not match, the TSV set selected by the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 is determined to be abnormal. By performing this test process, the memory device 5 can determine whether or not TSV switching is necessary in the TSV switching circuits 30-1, 30-2, 30-3, and 30-4.

[0155] 2.2 Test Processing Figure 13 is a flowchart showing an example of a test process in a memory device according to the second embodiment.

[0156] As shown in Figure 13, when the signal MODE_T is set to "1" and the memory device 5 enters test mode (start), the tester 40 sends the test signal SIGt to the IF chip 10 (S1).

[0157] The IF chip 10 transmits the test signal SIGt to the core chip 20-4 via a set of TSVs configured by the TSV switching circuits 30-1, 30-2, 30-3, and 30-4. The core chip 20-4 transmits the received test signal SIGt as a return signal SIGr to the tester 40. The tester 40 then receives the return signal SIGr (S2).

[0158] The tester 40 determines whether the return signal SIGr received in step S2 matches the test signal SIGt transmitted in step S1 (S3).

[0159] If the return signal SIGr matches the test signal SIGt (S3; yes), the tester 40 determines that the TSV set used when transmitting the test signal SIGt is normal (S4).

[0160] If the return signal SIGr does not match the test signal SIGt (S3; no), the tester 40 determines that the TSV set used when transmitting the test signal SIGt is abnormal (S5).

[0161] After the processing in step S4, or after the processing in step S5, the test process ends (end).

[0162] As described above, if an abnormality is determined in the TSV during the processing of step S5, a TSV switching process may be performed after the test processing. Specifically, for example, the default via dV <0> and default via dV <1> In response to the determination that it is normal, the TSV switching circuit 30-1 is set so that the first state is selected. Default via dV <0> It is determined that the default via dV is abnormal. <1> In response to the determination that the condition is normal, the TSV switching circuit 30-1 is set to select either the second or fourth state. Default via dV <0> It is determined to be normal and the default via dV <1> In response to the determination that the condition is abnormal, the TSV switching circuit 30-1 is set to select either the third state or the fifth state.

[0163] 2.3 Effects according to the second embodiment According to the second embodiment, during the test process, the tester 40 transmits a test signal SIGt from the IF chip 10 to the core chip 20-4 via a via. Based on the test signal SIGt that has passed through the via, the tester 40 determines whether the via is normal or abnormal. This allows the fuse circuit 17 to store information for switching a default via dV that has been determined to be abnormal to a redundant via rV that has been determined to be normal, before shipment. Therefore, even if some of the default vias dV are abnormal, the memory device 5 can be shipped as a normal product.

[0164] 2.4 Modified Examples of the Second Embodiment In the second embodiment described above, a test process was performed using one set of test signal SIGt and return signal SIGr for one signal SIG, but the invention is not limited to this. For example, a test process using one set of test signal SIGt and return signal SIGr may be performed for multiple signal SIGs. Below, the configurations and operations that differ from the second embodiment will be mainly described. Configurations and operations equivalent to those in the second embodiment will be omitted as appropriate.

[0165] Figure 14 is a block diagram showing an example of a functional configuration related to the test processing of a memory device according to a modified example of the second embodiment. The configuration shown in Figure 14 corresponds to the configuration in the second embodiment shown in Figure 12. As shown in Figure 14, the IF chip 10 replaces the selector 51 with a selector 51. <0> and 51 <1> The core chip 20-4 further includes a selector 26.

[0166] The test signal SIGt is selected by selector 51. <0> It is input to selector 51. <0> The signal SIG <0> The following is input. Selector 51 <0> This is the MODE_T signal, which is a 1-bit control signal. <0> Based on this, the signal SIG is transmitted from the IF chip 10 to the core chip 20-1 via via V. <0> Select either the signal MODE_T or the test signal SIGt. For example, select the signal MODE_T <0> If it is "1", selector 51 <0> Select the test signal SIGt. Signal MODE_T <0> If it is "0", selector 51 <0> The signal is SIG <0> Select this option.

[0167] The test signal SIGt is selected by selector 51. <1> It is input to selector 51. <0> The signal SIG <1> The following is input. Selector 51 <1> This is the MODE_T signal, which is a 1-bit control signal. <1> Based on this, the signal SIG is transmitted from the IF chip 10 to the core chip 20-1 via via V. <1> Select either the signal MODE_T or the test signal SIGt. For example, select the signal MODE_T <1> If it is "1", selector 51 <1> Select the test signal SIGt. Signal MODE_T <1> If it is "0", selector 51 <1> The signal is SIG <1> Select this option.

[0168] When memory device 5 operates in normal mode, performing normal operations such as write and read operations, the signal SIG is activated. <0> and SIG <1> This is selected. On the other hand, when the memory device 5 operates in test mode to perform test processing, the test signal SIGt is selected. Selector 51 <0> and 51 <1> The test signals SIGt output from each of these devices pass through TSV switching circuits 30-1, 30-2, 30-3, and 30-4 before being input to selector 26 in the core chip 20-4.

[0169] Selector 26 is for the signal MODE_T <0> and MODE...T <1> Based on this, select the signal to input to pad 25A. For example, the signal MODE_T <0> is "1" and signal MODE_T <1> If it is "0", selector 26 is selector 51 <0> Select the test signal SIGt input from MODE_T. <0> is "0" and signal MODE_T <1> If it is "1", selector 26 is selector 51 <1> The test signal SIGt input from selector 26 is selected. The test signal SIGt output from selector 26 is input to tester 40 as a return signal SIGr via pad 25A.

[0170] According to a modification of the second embodiment, the memory device 5 shares an interface with the tester 40 for transmitting a test signal SIGt to multiple vias. This reduces the number of pads 19A and 25A, allowing test processing to be performed on more vias even when there is insufficient mounting area for pads 19A and 25A.

[0171] 3. Third Embodiment Next, a memory device according to the third embodiment will be described. The third embodiment can perform test processing in units of multiple TSVs.

[0172] 3.1 Functional configuration for memory device testing Figure 15 is a block diagram showing an example of the functional configuration for the test processing of a memory device according to the third embodiment. As shown in Figure 15, the IF chip 10 includes a test pattern generation circuit 52, a latch 53, 32 selectors 54<31:0>, and a determination circuit 55. The core chip 20-4 includes a comparator 60.

[0173] Furthermore, the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 of this embodiment shown in Figure 15 are configured to switch between 32 default vias dV<31:0> and 4 redundant vias rV<3:0>, for example, with the same configuration as the first and second modified examples of the first embodiment shown in Figures 6 to 9.

[0174] The test pattern generation circuit 52 generates a test pattern as a test signal SIGt<3:0> synchronized with the clock signal CLK. The test pattern is, for example, a data sequence of several bits. Specifically, the test pattern generation circuit 52 can generate four types of test patterns, “0000”, “1111”, “0101”, and “1010”, as test signals SIGt<3:0>.

[0175] The latch 53 receives the test signal SIGt<3:0> from the test pattern generation circuit 52, synchronizes it with the clock signal CLK, and sends it to the four wires.

[0176] The 32 selectors 54<31:0> are classified into 4 selectors 54<3:0>, 4 selectors 54<7:4>, ..., and 4 selectors 54<31:28>. The test signal SIGt<3:0> is input to the redundant via rV<3:0> and the 4 selectors 54<4k+3:4k> (0≦k≦7). Additionally, the signal SIG<4k+3:4k> is input to each of the 4 selectors 54<4k+3:4k>. Each of the 4 selectors 54<4k+3:4k> selects either the signal SIG<4k+3:4k> or the test signal SIGt<3:0> as the signal to be transmitted from the IF chip 10 to the core chip 20-1 via the default via dV<4k+3:4k> based on the signal MODE_T.

[0177] For example, when signal MODE_T is "1", selector 54<4k+3:4k> selects test signal SIGt<3:0> respectively. When signal MODE_T is "0", selector 54<4k+3:4k> selects signal SIG<4k+3:4k> respectively.

[0178] With the above configuration, when operating in test mode, the test signal SIGt <0> This is a redundant via rV <0> , and default via dV <0> ,dV <4> , ..., and dV <28> The test signal SIGt is input to this. <1> This is redundant via rV <1> , and default via dV <1> ,dV <5> , ..., and dV <29> The test signal SIGt is input to this. <2> This is a redundant via rV <2> , and default via dV <2> ,dV <6> , ..., and dV <30> The test signal SIGt is input to this. <3> This is redundant via rV <3> , and default via dV <3> ,dV <7> , ..., and dV <31> The test signal SIGt<3:0>, having passed through the redundant via rV<3:0> and the default via dV<31:0>, is input to the comparator 60 in the core chip 20-4.

[0179] The comparator 60 includes a latch 61, 32 exclusive OR circuits 62<31:0>, an error detection circuit 63, and a tristate buffer 64.

[0180] The latch 61 receives the test signal SIGt<3:0>, which has passed through both the redundant via rV<3:0> and the default via dV<31:0>. The latch 61 captures the input test signal SIGt<3:0> in synchronization with the clock signal CLK.

[0181] Each of the exclusive OR circuits 62<4k+3:4k> has a first input terminal to which a test signal SIGt<3:0>, which has passed through a redundant via rV<3:0> and been taken into the latch 61, is input; a second input terminal to which a test signal SIGt<3:0>, which has passed through a default via dV<4k+3:4k> and been taken into the latch 61, is input; and an output terminal to output the result of the exclusive OR operation of each input signal.

[0182] The error detection circuit 63 determines, based on the output from the exclusive OR circuit 62<4k+3:4k>, whether the test signal SIGt<3:0> that has passed through the redundant via rV<3:0> matches the test signal SIGt<3:0> that has passed through the default via dV<4k+3:4k>. Specifically, for example, if the output from the exclusive OR circuit 62<4k+3:4k> is "0" for all cycles, the error detection circuit 63 outputs a signal of "0" as a 1-bit determination result indicating normality (i.e., the test has passed) to the control terminal of the tristate buffer 64. If the output from the exclusive OR circuit 62<4k+3:4k> contains even one "1", the error detection circuit 63 outputs a signal of "1" as a 1-bit determination result indicating abnormality (i.e., the test has failed) to the control terminal of the tristate buffer 64.

[0183] The tristate buffer 64 has a grounded input terminal, a control terminal to which the output signal from the error detection circuit 63 is input, and an output terminal connected to a control via cV. When the error detection circuit 63 outputs "0", the output of the tristate buffer 64 becomes low (strong low) level. On the other hand, when the error detection circuit 63 outputs "1", the output of the tristate buffer 64 becomes high impedance (Hi-Z).

[0184] In the example shown in Figure 15, a single tristate buffer 64 is connected to the error detection circuit 63, but this is not the only case. For example, a logical OR circuit may be provided to which the output from the exclusive OR circuit 62<4k+3:4k> is input. In this case, by providing eight tristate buffers, each receiving the output from eight logical OR circuits, the same functionality as the configuration in Figure 15 can be achieved.

[0185] The control via cV is connected to the power supply VT via resistor R in the IF chip 10. The power supply VT weakly drives the control via cV to a high (weak high) level. Therefore, when the output of the tristate buffer 64 is low level, the control via cV is driven to a low level. On the other hand, when the output of the tristate buffer 64 is high impedance, the control via cV is no longer low level (i.e., it becomes high level).

[0186] The determination circuit 55 is connected to the control via cV in the IF chip 10. The determination circuit 55 receives the voltage level of the control via cV as a return signal SIGr and determines the result of the test process. Specifically, if all return signals SIGr in the test process are low level, the determination circuit 55 determines that all vias subject to the test process are normal. If all return signals SIGr in the test process are high level, the determination circuit 55 determines that the redundant via rV<3:0> is abnormal. If both low-level and high-level return signals SIGr are present, the determination circuit 55 determines that the default via dV<4k+3:4k> corresponding to the high-level return signal SIGr is abnormal.

[0187] With the above configuration, the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 can switch the default via dV<4k+3:4k> which has been determined to be abnormal, to the normal redundant via rV<3:0> based on the determination result from the determination circuit 55.

[0188] 3.2 Test Processing Figure 16 is a flowchart showing an example of a test process in a memory device according to the third embodiment.

[0189] As shown in Figure 16, when the signal MODE_T is set to "1" and the memory device 5 enters test mode (start), the test pattern generation circuit 52 and latch 53 transmit the test signal SIGt<3:0> according to the clock signal CLK (S11).

[0190] Test signal SIGt <0> This is redundant via rV <0> , and default via dV <0> ,dV <4> , ..., and dV <28> The test signal SIGt is stored in latch 61 via each of the following. <1> This is redundant via rV <1> , and default via dV <1> ,dV <5> , ..., and dV <29> The test signal SIGt is stored in latch 61 via each of the following. <2> This is redundant via rV <2> , and default via dV <2> ,dV <6> , ..., and dV <30> The test signal SIGt is stored in latch 61 via each of the following. <3> This is redundant via rV <3> , and default via dV <3> ,dV <7> , ..., and dV <31> Each of these is stored in latch 61.

[0191] Comparator 60 selects four default vias dV<4k+3:4k> as the default via set, corresponding to the unselected variable k (0≦k≦7) (S12).

[0192] The exclusive OR circuit 62<4k+3:4k> compares the test signal SIGt<3:0> that has passed through the redundant via rV<3:0> with the test signal SIGt<3:0> that has passed through the default via dV<4k+3:4k> selected in step S12 (S13).

[0193] The error detection circuit 63 determines whether the test signals SIGt<3:0> that were compared in step S13 match (S14).

[0194] If the comparison results match (S14; yes), the determination circuit 55 receives a return signal SIGr indicating normal operation (S15). Specifically, the error detection circuit 63 outputs a signal of "0" indicating normal operation. As a result, the tristate buffer 64 drives the control via cV to a low level. Therefore, the determination circuit 55 receives a low-level return signal SIGr indicating normal operation.

[0195] If the comparison results do not match (S14; no), the determination circuit 55 receives a return signal SIGr indicating an abnormality (S16). Specifically, the error detection circuit 63 outputs a signal of "1" indicating an abnormality. As a result, the tristate buffer 64 becomes high impedance. Consequently, the control via cV is driven to a high level. Therefore, the determination circuit 55 receives a high-level return signal SIGr indicating an abnormality.

[0196] The memory device 5 determines whether all sets of default vias have been selected (S17).

[0197] If there are any unselected default via pairs (S17; no), the comparator 60 selects four default vias dV<4k+3:4k> corresponding to the unselected variable k as the default via pair (S12). Then, the subsequent steps S13 to S17 are executed. In this manner, steps S12 to S17 are executed until all default via pairs are selected.

[0198] If all default via sets have been selected (S17; yes), the determination circuit 55 determines whether all return signals SIGr indicate normal status (S18).

[0199] If all return signals SIGr indicate normality (S18; yes), the determination circuit 55 determines that all vias subject to the test process (i.e., redundant via rV<3:0> and default via dV<31:0>) are normal (S19).

[0200] If there is a return signal SIGr indicating an abnormality (S18; no), the determination circuit 55 determines whether all return signals SIGr indicate an abnormality or not (S20).

[0201] If both a normal return signal SIGr and an abnormal return signal SIGr are included (S20; no), the determination circuit 55 determines that the default via dV<4k+3:4k> corresponding to the abnormal return signal SIGr is abnormal (S21).

[0202] If all return signals SIGr indicate an abnormality (S20; yes), the determination circuit 55 determines that the redundant via rV<3:0> is abnormal (S22).

[0203] After the processing in step S19, step S21, or step S22, the test process ends (end).

[0204] If an abnormality is detected in the TSV during the processing in step S16, a TSV switching process may be performed after the test process. Specifically, for example, the default via dV <0> and default via dV <1> In response to the determination that it is normal, the TSV switching circuit 30-1 is set so that the first state is selected. Default via dV <0> It is determined that the default via dV is abnormal. <1> In response to the determination that the condition is normal, the TSV switching circuit 30-1 is set to select either the second or fourth state. Default via dV <0> It is determined to be normal and the default via dV <1> In response to the determination that the condition is abnormal, the TSV switching circuit 30-1 is set to select either the third state or the fifth state.

[0205] 3.3 Effects of the Third Embodiment According to the third embodiment, the error detection circuit 63 performs a first to eighth process (0≦k≦7) to determine the consistency between the test signal SIGt<3:0> that has passed through each redundant via rV<3:0> and the test signal SIGt<3:0> that has passed through each default via dV<4k+3:4k>. The determination circuit 55 determines that if the results of the first to eighth processes all show a match, the redundant via <3:0> and the default via dV<31:0> are all normal. The determination circuit 55 determines that if the results of the first to eighth processes all show a mismatch, the redundant via <3:0> is abnormal and the default via dV<31:0> is normal. For example, if the result of the first process shows a mismatch, the determination circuit 55 determines that the default via dV<3:0> corresponding to the first process that showed a mismatch is abnormal, and that the redundant via rV<3:0> and the default via dV<31:4> are normal. Furthermore, if the result of the second process shows a mismatch, the determination circuit 55 determines that the default via dV<7:4> corresponding to the second process that showed a mismatch is abnormal, and that the redundant via rV<3:0> and the default vias dV<31:8> and dV<3:0> are normal. This allows the test process to be simplified when the failure rate of the TSV can be considered to be very low.

[0206] Furthermore, the process for determining the consistency described above is performed in synchronization with the clock signal CLK. This allows for the detection of an abnormality if the signal cannot be transmitted at a shorter period than the clock signal CLK due to an increase in the via's resistance. Therefore, the test process can detect not only open-circuit failures but also resistance value failures.

[0207] 4. Fourth Embodiment Next, a memory device according to the fourth embodiment will be described. In the fourth embodiment, a 1-bit test pattern is used to sequentially test all vias.

[0208] 4.1 Functional configuration for memory device testing Figure 17 is a block diagram showing an example of the functional configuration for the test processing of a memory device according to the fourth embodiment. As shown in Figure 17, the IF chip 10 includes a test pattern generation circuit 52, 32 selectors 54<31:0>, and a determination circuit 55. The core chip 20-4 includes a comparator 70.

[0209] The test pattern generation circuit 52 generates a 1-bit test signal SIGt. Such a test signal SIGt is used to check the continuity of a via. The test signal SIGt is, for example, "1". The test pattern generation circuit 52 outputs the generated test signal SIGt synchronized with the clock signal CLK.

[0210] The test signal SIGt is input to the redundant via rV<3:0> and 32 selectors 54<31:0>. Additionally, the signal SIG<31:0> is input to each of the 32 selectors 54<31:0>. Each of the 32 selectors 54<31:0> selects either the signal SIG<31:0> or the test signal SIGt as the signal to be transmitted from the IF chip 10 to the core chip 20-1 via the default via dV<31:0>, based on the signal MODE_T.

[0211] For example, when signal MODE_T is "1", each of selector 54<31:0> selects the test signal SIGt. When signal MODE_T is "0", each of selector 54<31:0> selects the signal SIG<31:0>. With this configuration, when operating in test mode, the test signal SIGt is input to the redundant via rV<3:0> and the default via dV<31:0>. After passing through each of the redundant via rV<3:0> and the default via dV<31:0>, the test signal SIGt is input to the comparator 70 in the core chip 20-4.

[0212] The comparator 70 includes selectors 71 and 72, an error detection circuit 73, and a tristate buffer 74.

[0213] Selector 71 receives the test signal SIGt that has passed through the redundant via rV<3:0>. Selector 71 outputs one predetermined test signal SIGt selected by the memory device 5 from among the four received test signals SIGt.

[0214] Selector 72 receives the test signal SIGt that has passed through the default via dV<31:0>. Selector 72 outputs a predetermined test signal SIGt selected by the memory device 5 from among the 32 received test signals SIGt.

[0215] The error detection circuit 73 determines whether each of the redundant vias rV<3:0> is normal or not based on the clock signal CLK and the test signal SIGt output from the selector 71. Specifically, if the test signal SIGt input from the selector 71 is "1", the error detection circuit 73 outputs a signal of "0" to the control terminal of the tristate buffer 74 as a result of the determination, indicating that the corresponding redundant via rV is normal. If the test signal SIGt input from the selector 71 is "0", the error detection circuit 73 outputs a signal of "1" to the control terminal of the tristate buffer 74 as a result of the determination, indicating that the corresponding redundant via rV is abnormal.

[0216] Furthermore, the error detection circuit 73 determines whether each of the default vias dV<31:0> is normal or not based on the clock signal CLK and the test signals SIGt output from selectors 71 and 72. Specifically, if the test signal SIGt input from selector 72 matches the test signal SIGt input from selector 71, the error detection circuit 73 outputs a "0" signal to the control terminal of the tristate buffer 74 as a result of the determination, indicating that the corresponding default via dV is normal. If the test signal SIGt input from selector 72 does not match the test signal SIGt input from selector 71, the error detection circuit 73 outputs a "1" signal to the control terminal of the tristate buffer 74 as a result of the determination, indicating that the corresponding default via dV is abnormal. Note that the test signal SIGt output from selector 71 for this determination is the test signal SIGt that has passed through the redundant via rV that has been determined to be normal.

[0217] The tristate buffer 74 has a grounded input terminal, a control terminal to which the output signal from the error detection circuit 73 is input, and an output terminal connected to a control via cV. When the error detection circuit 73 outputs "0", the output of the tristate buffer 74 becomes low level. On the other hand, when the error detection circuit 73 outputs "1", the output of the tristate buffer 74 becomes high impedance.

[0218] The control via cV is connected to the power supply VT via resistor R in the IF chip 10. The power supply VT weakly drives the control via cV to a high level. Therefore, when the output of the tristate buffer 74 is low level, the control via cV is driven to a low level. On the other hand, when the output of the tristate buffer 74 is high impedance, the control via cV is no longer low level (i.e., it becomes high level).

[0219] The determination circuit 55 is connected to the control via cV in the IF chip 10. The determination circuit 55 receives the voltage level of the control via cV as a return signal SIGr and determines the result of the test process. Specifically, in the continuity check of the redundant via rV (test process related to the redundant via rV), the determination circuit 55 determines that the corresponding redundant via rV is normal if the return signal SIGr is low level, and determines that the corresponding redundant via rV is abnormal if the return signal SIGr is high level. In the consistency check between the redundant via rV and the default via dV (test process related to the default via dV), the determination circuit 55 determines that the corresponding default via dV is normal if the return signal SIGr is low level, and determines that the corresponding default via dV is abnormal if the return signal SIGr is high level.

[0220] With the above configuration, the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 can switch the default via dV, which has been determined to be abnormal, to a normal redundant via rV based on the determination result from the determination circuit 55.

[0221] 4.2 Test Processing 4.2.1 Testing process for redundant vias Figure 18 is a flowchart showing an example of a test process for redundant vias in a memory device according to the fourth embodiment.

[0222] As shown in Figure 18, when the signal MODE_T is set to "1" and the memory device 5 enters test mode (start), selector 71 selects one of the redundant vias rV<3:0> (S31). In this case, selector 72 does not select any of the default vias dV<31:0>.

[0223] The test pattern generation circuit 52 transmits a test signal SIGt according to the clock signal CLK (S32). The selector 71 transmits the test signal SIGt, which has passed through the redundant via rV selected in step S31, to the error detection circuit 73.

[0224] The error detection circuit 73 checks for continuity of the test signal SIGt that has passed through the redundant via rV selected in step S31, based on the clock signal CLK and the test signal SIGt received from the selector 71 (S33).

[0225] The error detection circuit 73 determines whether the test signal SIGt passed the continuity check. (S34)

[0226] If the continuity check is passed (S34; yes), the determination circuit 55 determines that the redundant via rV selected in step S31 is normal (S35). Specifically, the error detection circuit 73 outputs a signal of "0" indicating normality. As a result, the tristate buffer 74 drives the control via cV to a low level. The determination circuit 55 receives a low-level return signal SIGr indicating normality and determines that the corresponding redundant via rV is normal.

[0227] If the continuity check fails (S34; no), the determination circuit 55 determines that the redundant via rV selected in step S31 is abnormal (S36). Specifically, the error detection circuit 73 outputs a signal of "1" indicating an abnormality. As a result, the tristate buffer 74 becomes high impedance. As a result, the control via cV is driven to a high level. The determination circuit 55 receives a high-level return signal SIGr indicating an abnormality and determines that the corresponding redundant via rV is abnormal.

[0228] The memory device 5 determines whether all redundant vias rV have been selected (S37).

[0229] If there are any unselected redundant vias rV (S37; no), selector 71 selects the unselected redundant vias rV (S31). Then, the subsequent steps S32 to S37 are executed. In this way, steps S31 to S37 are executed until all redundant vias rV are selected.

[0230] If all redundant vias rV have been selected (S37; yes), the testing process for redundant vias rV is complete (end).

[0231] 4.2.2 Test processing for default vias Figure 19 is a flowchart showing an example of a test process for the default via in a memory device according to the fourth embodiment.

[0232] As shown in Figure 19, after the test process for the redundant via rV (start), selectors 71 and 72 select one pair from the normal redundant via rV and the default via dV<31:0> (S41).

[0233] The test pattern generation circuit 52 transmits a test signal SIGt according to the clock signal CLK (S42). Selector 71 transmits the test signal SIGt that has passed through the normal redundant via rV selected in step S41 to the error detection circuit 73. Selector 72 transmits the test signal SIGt that has passed through the default via dV selected in step S41 to the error detection circuit 73.

[0234] The error detection circuit 73 compares the test signals SIGt that have passed through the redundant via rV and default via dV selected in step S41, based on the clock signal CLK and the test signals SIGt received from selectors 71 and 72, respectively (S43).

[0235] The error detection circuit 73 determines whether the test signals SIGt that were compared in step S43 match (S44).

[0236] If the comparison results do not match (S44; no), the determination circuit 55 determines that the default via dV selected in step S41 is abnormal (S45). Specifically, the error detection circuit 73 outputs a signal of "1" indicating an abnormality. As a result, the tristate buffer 74 becomes high impedance. As a result, the control via cV is driven to a high level. The determination circuit 55 receives a high-level return signal SIGr indicating an abnormality and determines that the corresponding default via dV is abnormal.

[0237] After the processing in step S45, the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 switch from the default via dV, which was determined to be abnormal in the processing in step S45, to a normal redundant via rV (S46).

[0238] Specifically, for example, default via dV <0> and default via dV <1> In response to the determination that it is normal, the TSV switching circuit 30-1 is set so that the first state is selected. Default via dV <0> It is determined that the default via dV is abnormal. <1> In response to the determination that the condition is normal, the TSV switching circuit 30-1 is set to select either the second or fourth state. Default via dV <0> It is determined to be normal and the default via dV <1> In response to the determination that the condition is abnormal, the TSV switching circuit 30-1 is set to select either the third state or the fifth state.

[0239] After the processing in step S46, the test pattern generation circuit 52 transmits a test signal SIGt according to the clock signal CLK (S42). Then, the subsequent processing in steps S43 and S44 is performed. In this way, the processing in steps S42 to S46 is performed until the comparison results match.

[0240] If the comparison results show a match (S44; yes), the determination circuit 55 determines that the default via dV selected in step S41 is normal (S47). Specifically, the error detection circuit 73 outputs a signal of "0" indicating normality. As a result, the tristate buffer 74 drives the control via cV to a low level. The determination circuit 55 receives a low-level return signal SIGr indicating normality and determines that the corresponding default via dV is normal.

[0241] After processing in step S47, the memory device 5 determines whether all default vias dV have been selected (S48).

[0242] If there are unselected default vias dV (S48; no), selectors 71 and 72 select a pair of a normal redundant via rV and an unselected default via dV (S41). Then, the subsequent steps S42 to S48 are executed. In this way, the processes from steps S41 to S48 are executed until all default vias dV are selected.

[0243] If all default vias (dV) are selected (S48; yes), the test process for the default vias (dV) is completed (end).

[0244] 4.3 Effects of the Fourth Embodiment According to the fourth embodiment, the memory device 5 first determines whether each of the redundant vias rV<3:0> is good or bad. Next, the memory device 5 determines the consistency between the test signal SIGt that passed through the redundant via rV determined to be normal and the test signal SIGt that passed through the default via dV. This enables efficient switching to a normal redundant via rV when an abnormality is detected in the default via dV.

[0245] Furthermore, the matching determination process is performed using a 1-bit test signal SIGt. This simplifies the test pattern generation circuit 52.

[0246] 4.4 Modified Version of the Fourth Embodiment In the fourth embodiment described above, a case was described in which a test signal SIGt is generated within the IF chip 10 and a determination is made based on the return signal SIGr, but this is not limited to this case. For example, the generation of the test signal SIGt and the determination based on the return signal SIGr may be performed by the tester 40. Below, we will mainly describe configurations and operations that differ from the fourth embodiment. Descriptions of configurations and operations equivalent to the fourth embodiment will be omitted as appropriate.

[0247] Figure 20 is a block diagram showing an example of a functional configuration for a memory device test process according to a modified version of the fourth embodiment. The configuration shown in Figure 20 corresponds to the configuration in the fourth embodiment shown in Figure 17. As shown in Figure 20, the IF chip 10 includes pads 19B and 19C, but does not include the test pattern generation circuit 52. The core chip 20-4 includes pads 25B and 25C, but does not include the error detection circuit 73 and the tristate buffer 74.

[0248] Pads 19B and 19C are terminals for connecting the IF chip 10 and the tester 40. During the test process, the IF chip 10 receives test signals SIGt1 and SIGt2 from the tester 40 via pads 19B and 19C, respectively. Test signal SIGt1, input via pad 19B, passes through redundant via rV<3:0> and is transmitted to selector 71. Test signal SIGt2, input via pad 19C, passes through default via dV<31:0> and is transmitted to selector 72. Each of the test signals SIGt1 and SIGt2 is, for example, a 1-bit signal.

[0249] Pads 25B and 25C are terminals for connecting the core chip 20-4 and the tester 40. Selector 71 sends test signal SIGt1 corresponding to the selected redundant via rV to the tester 40 via pad 25B. Selector 72 sends test signal SIGt2 corresponding to the selected default via dV<31:0> to the tester 40 via pad 25C.

[0250] Tester 40 receives the signals output from pads 25B and 25C of the core chip 20-4 as return signals SIGr1 and SIGr2, respectively. Based on the test signal SIGt1 and the return signal SIGr1, Tester 40 performs test processing on the redundant via rV. Based on the test signals SIGt1 and SIGt2, as well as the return signals SIGr1 and SIGr2, Tester 40 performs test processing on the default via dV.

[0251] According to a modification of the fourth embodiment, the test signal SIGt is generated and the via is judged to be good or bad by the tester 40. This reduces the amount of circuitry that needs to be implemented on the IF chip 10 and the core chip 20-4.

[0252] 5. Fifth Embodiment Next, a memory device according to the fifth embodiment will be described. In the fifth embodiment, test processing is performed on all vias to be tested at once.

[0253] 5.1 Functional configuration for memory device testing Figure 21 is a block diagram showing an example of the functional configuration for the test processing of a memory device according to the fifth embodiment. As shown in Figure 21, the IF chip 10 includes a test pattern generation circuit 52, a latch 53, 32 selectors 54, and a determination circuit 55. The core chip 20-4 includes a comparator 80.

[0254] The test pattern generation circuit 52 generates a 1-bit test signal SIGt. Such a test signal SIGt is used to check the continuity of a via. The test signal SIGt is, for example, "1". The test pattern generation circuit 52 transmits the generated test signal SIGt to the latch 53.

[0255] Latch 53 synchronizes the test signal SIGt with the clock signal CLK and sends it out as the test signal SIGt<35:0> to the 36 wires.

[0256] The test signal SIGt<35:32> is input to the redundant via rV<3:0> respectively. The test signal SIGt<31:0> is input to the 32 selectors 54<31:0> respectively. In addition, the signal SIG<31:0> is input to each of the 32 selectors 54<31:0>. Each of the 32 selectors 54<31:0> selects either the signal SIG<31:0> or the test signal SIGt<31:0> as the signal to be transmitted from the IF chip 10 to the core chip 20-1 via the default via dV<31:0> based on the signal MODE_T.

[0257] For example, when the signal MODE_T is "1", each of the selectors 54<31:0> selects the test signal SIGt<31:0>. When the signal MODE_T is "0", each of the selectors 54<31:0> selects the signal SIG<31:0>. With this configuration, when operating in test mode, the test signal SIGt<35:0> is input to the redundant via rV<3:0> and the default via dV<31:0>. The test signal SIGt<35:0>, having passed through each of the redundant via rV<3:0> and the default via dV<31:0>, is input to the comparator 80 in the core chip 20-4.

[0258] The comparator 80 includes a latch 81, an error detection circuit 82, and 36 tristate buffers 83<35:0>.

[0259] The latch 81 receives the test signal SIGt<35:0>, which has passed through the redundant via rV<3:0> and the default via dV<31:0>, respectively. The latch 81 captures the input test signal SIGt<35:0> in synchronization with the clock signal CLK.

[0260] The error detection circuit 82 determines whether each of the redundant vias rV<3:0> and default vias<31:0> is normal or not based on the test signal SIGt<35:0> input from the latch 81. Specifically, if the test signal SIGt that has passed through a certain redundant via rV or default via dV is "1", the determination result outputs a signal of "0" to the control terminal of the corresponding tristate buffer 83, indicating that the redundant via rV or default via dV is normal. If the test signal SIGt that has passed through a certain redundant via rV or default via dV is "0", the determination result outputs a signal of "1" to the control terminal of the corresponding tristate buffer 83, indicating that the redundant via rV or default via dV is abnormal.

[0261] Each of the tristate buffers 83<35:0> has a grounded input terminal, a control terminal to which the output signal from the error detection circuit 82 is input, and an output terminal. The output terminals of each tristate buffer 83<35:0> are connected to the control via cV<35:0>. The default via dV is connected to the error detection circuit 82. If a "0" signal is output for this, the tristate buffer 83 The output will be low level (0≦i≦35). Redundant via rV from error detection circuit 82. <j>If a "0" signal is output for this, the output of the tristate buffer 83<32+j> will be low level (0≦j≦3). Meanwhile, the default via dV is output from the error detection circuit 82. If "1" is output for this, then the tristate buffer 83 The output will be high impedance. A redundant via rV is accessed from the error detection circuit 82. <j>If "1" is output for this, the output of the tristate buffer 83<32+j> will be high impedance.

[0262] Each of the control vias cV<35:0> is connected to the power supply VT via a resistor R in the IF chip 10. The power supply VT weakly drives each of the control vias cV<35:0> to a high level. Therefore, when the output of a certain tristate buffer 83 is low level, the corresponding control via cV is driven to a low level. On the other hand, when the output of a certain tristate buffer 83 is high impedance, the corresponding control via cV is no longer low level (i.e., it becomes high level).

[0263] The determination circuit 55 is connected to each of the control vias cV<35:0> in the IF chip 10. The determination circuit 55 determines the result of the test process by receiving the voltage levels of each control via cV<35:0> as return signals SIGr<35:0>. Specifically, the determination circuit 55 receives the return signals SIGr If it is low level, the corresponding default via dV The system determines that it is normal and returns the SIGr signal. If it is at a high level, the corresponding default via dV The determination circuit 55 determines that the system is abnormal. If the return signal SIGr<32+j> is low level, the corresponding redundant via rV <j>If it is determined to be normal and the return signal SIGr<32+j> is high level, the corresponding redundant via rV <j>It is determined that there is an abnormality.

[0264] With the above configuration, the TSV switching circuits 30-1, 30-2, 30-3, and 30-4 can switch the default via dV determined to be abnormal to the normal redundant via rV based on the determination result by the determination circuit 55.

[0265] 5.2 Test Processing FIG. 22 is a flowchart showing an example of test processing in the memory device according to the fifth embodiment.

[0266] As shown in FIG. 22, when the signal MODE_T is set to "1" and the memory device 5 enters the test mode (start), the test pattern generation circuit 52 transmits the test signal SIGt according to the clock signal CLK (S51). The latch 81 transmits the test signal SIGt that has passed through each of the redundant vias rV<3:0> and the default via dV<31:0> to the error detection circuit 82 in synchronization with the clock signal CLK.

[0267] The error detection circuit 82 checks the conduction of the test signal SIGt that has passed through each of the redundant vias rV<3:0> and the default via dV<31:0> (S52).

[0268] The determination circuit 55 determines that the redundant via rV or the default via dV through which the test signal SIGt that has passed the conduction check in step S52 has passed is normal (S53).

[0269] Specifically, the default via dV If the test signal SIGt that has passed through passes the continuity check, the error detection circuit 82 sends a signal of "0" indicating normal operation to the tristate buffer 83. Output to the tristate buffer 83. This is the corresponding control via cV The signal is driven to a low level. The judgment circuit 55 receives a low-level return signal SIGr indicating normal operation. By receiving the corresponding default via dV This is judged as normal.

[0270] Also, redundant via rV <j>If the test signal SIGt passes the continuity check, the error detection circuit 82 outputs a "0" signal indicating normal to the tristate buffer 83<32+j>. As a result, the tristate buffer 83<32+j> drives the corresponding control via cV<32+j> to a low level. The determination circuit 55 receives the low-level return signal SIGr<32+j> indicating normal and determines the corresponding redundant via rV <j>This is judged as normal.

[0271] The determination circuit 55 determines that the redundant via rV or default via dV through which the test signal SIGt, which failed to confirm continuity in step S52, passed is abnormal (S54).

[0272] Specifically, default via dV If the test signal SIGt that has passed through fails to confirm continuity, the error detection circuit 82 sends a signal of "1" indicating an abnormality to the tristate buffer 83. Output to the tristate buffer 83. This results in high impedance. This causes the corresponding control via cV It is driven to a high level. The judgment circuit 55 receives a high-level return signal SIGr indicating an abnormality. By receiving the corresponding default via dV This is judged as abnormal.

[0273] Also, redundant via rV <j>If the test signal SIGt that has passed through fails to confirm continuity, the error detection circuit 82 outputs a "1" signal indicating an abnormality to the tristate buffer 83<32+j>. As a result, the tristate buffer 83<32+j> becomes high impedance. As a result, the corresponding control via cV<32+j> is driven to a high level. The judgment circuit 55, upon receiving the high-level return signal SIGr<32+j> indicating an abnormality, determines the corresponding redundant via dV <j>This is judged as abnormal.

[0274] After the processing in step S53 and step S54, the test process ends (end). In the example shown in Figure 22, the processing in steps S53 and S54 are executed in series, but this is not the only way. The processing in steps S53 and S54 may be executed in parallel.

[0275] If an abnormality is detected in the TSV during the processing in step S54, a TSV switching process may be performed after the test process. Specifically, for example, the default via dV <0> and default via dV <1> In response to the determination that it is normal, the TSV switching circuit 30-1 is set so that the first state is selected. Default via dV <0> It is determined that the default via dV is abnormal. <1> In response to the determination that the condition is normal, the TSV switching circuit 30-1 is set to select either the second or fourth state. Default via dV <0> It is determined to be normal and the default via dV <1> In response to the determination that the condition is abnormal, the TSV switching circuit 30-1 is set to select either the third state or the fifth state.

[0276] 5.3 Effects of the Fifth Embodiment According to the fifth embodiment, the memory device 5 performs continuity checks for redundant vias rV<3:0> and default vias dV<31:0> in a single operation. This reduces the time required for the test process.

[0277] 6. Others In the second, third, fourth, and fifth embodiments described above, the functional configuration of core chip 20-4 among core chips 20-1, 20-2, 20-3, and 20-4 was described as a functional configuration related to test processing. However, core chips 20-1, 20-2, and 20-3 may also have a configuration equivalent to that of core chip 20-4. This allows core chips 20-1, 20-2, 20-3, and 20-4 to be manufactured using the same process, thereby suppressing an increase in manufacturing costs.

[0278] In the absence of configuration differences between core chips, in the third, fourth, and fifth embodiments, the tristate buffers provided by each of the core chips 20-1, 20-2, and 20-3 can be connected to a control via cV. In this configuration, the outputs of the tristate buffers provided by each of the core chips 20-1, 20-2, and 20-3 are controlled, for example, to be high impedance.

[0279] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0280] 1… Information processing system 2… Host 3…Memory System 4…Memory controller 5…Memory devices 10…IF chip 11…Input / Output Control Circuit 12…Logic control circuits 13…Lady Busy Control Circuit 14…Register 15… Sequencer 16…Voltage generation circuit 6,17…Fuse circuit 18, 24…TSV control registers 19, 19A, 19B, 19C, 25A, 25B, 25C… pads 20-1, 20-2, 20-3, 20-4… Core chips 21…Memory cell array 22… Raw Decoder Module 23...Sense Amp Module 30-1, 30-2, 30-3, 30-4… TSV switching circuit 40… Tester 26, 51, 54, 71, 72… Selector 52… Test pattern generation circuit 53, 61, 81… Latch 55… Judgment circuit 60, 70, 80… Comparator 62… Exclusive OR circuit 63, 73, 82… Error detection circuit 64, 74, 83… Tri-state buffer< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. The first chip and, A second chip stacked on the first chip, comprising a substrate, a memory cell array configured to store data non-volatilely, and a first via, a second via, and a third via, each passing through the substrate in the stacking direction and connected to the first chip, A first state in which a first signal is communicated between the first chip and the second chip via the first via and a second signal is communicated via the second via, A second state in which the first signal is communicated between the first chip and the second chip via the third via and the second signal is communicated via the second via, and A third state in which the first signal is communicated between the first chip and the second chip via the first via and the second signal is communicated via the third via, A switching circuit configured to switch between, A memory device equipped with the following features.

2. The switching circuit is, The first chip includes a first switch, The second chip includes a second switch, a third switch, and a fourth switch, The first switch has a first terminal to which the first signal is input, a second terminal to which the second signal is input, a third terminal connected to the first terminal of the third via, and a fourth terminal that is grounded. The second switch has a first end connected to the first end of the first via, The third switch has a first end connected to the first end of the second via, The fourth switch has a first end connected to the second end of the third via, a second end connected to the second end of the second switch, and a third end connected to the second end of the third switch. The memory device according to claim 1.

3. The switching circuit is, In the first state, the second switch and the third switch are turned ON, and the third and fourth ends of the first switch are connected. In the second state, the third switch is turned ON, the second switch is turned OFF, the first and third ends of the first switch are connected, and the first and second ends of the fourth switch are connected. In the third state, the second switch is turned ON, the third switch is turned OFF, the second and third ends of the first switch are connected, and the first and third ends of the fourth switch are connected. It was further configured in the following way: The memory device according to claim 2.

4. The switching circuit is, The first chip includes a first inverter, a second inverter, a first AND circuit, a second AND circuit, a first negated AND circuit, a second negated AND circuit, and a third negated AND circuit. The second chip includes a third inverter, a fourth inverter, a fourth negative AND circuit, a fifth negative AND circuit, a sixth negative AND circuit, a seventh negative AND circuit, an eighth negative AND circuit, and a ninth negative AND circuit. Each of the first inverter and the third inverter has an input terminal to which a first control signal is input, Each of the second inverter and the fourth inverter has an input terminal to which the second control signal is input, The first AND circuit has a first input terminal into which the first signal is input, a second input terminal connected to the output terminal of the first inverter, and an output terminal connected to the first terminal of the first via. The second AND circuit has a first input terminal into which the second signal is input, a second input terminal connected to the output terminal of the second inverter, and an output terminal connected to the first terminal of the second via. The first negative AND circuit has a first input terminal into which the first signal is input, and a second input terminal into which the first control signal is input, The second negative AND circuit has a first input terminal into which the second signal is input, and a second input terminal into which the second control signal is input, The third negative AND circuit has a first input terminal connected to the output terminal of the first negative AND circuit, a second input terminal connected to the output terminal of the second negative AND circuit, and an output terminal connected to the first terminal of the third via. The fourth negative AND circuit has a first input terminal connected to the second terminal of the first via and a second input terminal connected to the output terminal of the third inverter, The fifth negative AND circuit has a first input terminal connected to the second terminal of the second via and a second input terminal connected to the output terminal of the fourth inverter, The sixth negative AND circuit has a first input terminal to which the first control signal is input, and a second input terminal connected to the second terminal of the third via, The seventh negative AND circuit has a first input terminal to which the second control signal is input, and a second input terminal connected to the second terminal of the third via, The eighth negative AND circuit has a first input terminal connected to the output terminal of the fourth negative AND circuit, and a second input terminal connected to the output terminal of the sixth negative AND circuit. The ninth negative AND circuit has a first input terminal connected to the output terminal of the fifth negative AND circuit, and a second input terminal connected to the output terminal of the seventh negative AND circuit. The memory device according to claim 1.

5. The switching circuit is, In the first state, the first control signal and the second control signal are set to a first value. In the second state, the first control signal is set to a second value different from the first value, and the second control signal is set to the first value. In the third state, the first control signal is set to the first value, and the second control signal is set to the second value. It was further configured in the following way: The memory device according to claim 4.

6. The switching circuit is, The first state, The second state described above, The third state, A fourth state in which the first signal is communicated between the first chip and the second chip via the first via and the third via, and the second signal is communicated via the second via, A fifth state in which the first signal is communicated between the first chip and the second chip via the first via, and the second signal is communicated via the second via and the third via. Further configured to switch, The memory device according to claim 1.

7. The switching circuit is, The first chip includes a first switch, The second chip includes a second switch, a third switch, and a fourth switch, The first switch has a first terminal to which the first signal is input, a second terminal to which the second signal is input, a third terminal connected to the first terminal of the third via, and a fourth terminal that is grounded. The second switch has a first end connected to the first end of the first via, The third switch has a first end connected to the first end of the second via, The fourth switch has a first end connected to the second end of the third via, a second end connected to the second end of the second switch, and a third end connected to the second end of the third switch. The memory device according to claim 6.

8. The switching circuit is, In the first state, the second switch and the third switch are turned ON, and the third and fourth ends of the first switch are connected. In the second state, the third switch is turned ON, the second switch is turned OFF, the first and third ends of the first switch are connected, and the first and second ends of the fourth switch are connected. In the third state, the second switch is turned ON, the third switch is turned OFF, the second and third ends of the first switch are connected, and the first and third ends of the fourth switch are connected. In the fourth state, the second switch and the third switch are turned ON, the first and third ends of the first switch are connected, and the first and second ends of the fourth switch are connected. In the fifth state, the second switch and the third switch are turned ON, the second and third ends of the first switch are connected, and the first and third ends of the fourth switch are connected. It was further configured in the following way: The memory device according to claim 7.

9. The switching circuit is, The first chip includes a first AND circuit, a second AND circuit, a first negated AND circuit, a second negated AND circuit, a third negated AND circuit, a tenth negated AND circuit, and an eleventh negated AND circuit. The second chip includes a third inverter, a fourth inverter, a first tristate buffer, and a second tristate buffer. The tenth negative AND circuit has a first input terminal to which a first control signal is input and a second input terminal to which a third control signal is input, The 11th negated AND circuit has a first input terminal to which a second control signal is input, and a second input terminal to which a third control signal is input, The first AND circuit has a first input terminal into which the first signal is input, a second input terminal connected to the output terminal of the 10th negated AND circuit, and an output terminal connected to the first terminal of the first via. The second AND circuit has a first input terminal into which the second signal is input, a second input terminal connected to the output terminal of the 11th negated AND circuit, and an output terminal connected to the first terminal of the second via. The first negative AND circuit has a first input terminal into which the first signal is input, and a second input terminal into which the first control signal is input, The second negative AND circuit has a first input terminal into which the second signal is input, and a second input terminal into which the second control signal is input, The third negative AND circuit has a first input terminal connected to the output terminal of the first negative AND circuit, a second input terminal connected to the output terminal of the second negative AND circuit, and an output terminal connected to the first terminal of the third via. Each of the third inverter and the fourth inverter has an input terminal connected to the second end of the third via, The first tristate buffer has an input terminal connected to the output terminal of the third inverter, a control terminal to which the first control signal is input, and an output terminal connected to the second terminal of the first via. The second tristate buffer has an input terminal connected to the output terminal of the fourth inverter, a control terminal to which the second control signal is input, and an output terminal connected to the second terminal of the second via. The memory device according to claim 6.

10. The switching circuit is, In the first state, the first control signal and the second control signal are set to a first value, and the third control signal is set to a third value. In the second state, the first control signal is set to a second value different from the first value, the second control signal is set to the first value, and the third control signal is set to the third value. In the third state, the first control signal is set to the first value, the second control signal is set to the second value, and the third control signal is set to the third value. In the fourth state, the first control signal is set to the second value, the second control signal is set to the first value, and the third control signal is set to a fourth value different from the third value. In the fifth state, the first control signal is set to the first value, the second control signal is set to the second value, and the third control signal is set to the fourth value. It was further configured in the following way: The memory device according to claim 9.

11. The first chip includes registers, The switching circuit is configured to receive the first control signal and the second control signal from the register. The memory device according to claim 4.

12. The switching circuit is configured to receive the first control signal and the second control signal from outside the first chip. The memory device according to claim 4.

13. A method for testing a memory device according to claim 1, A test signal is transmitted from the first chip to the second chip via one via selected from the first via, the second via, and the third via. Based on the test signal that has passed through the selected via, it is determined whether the selected via is normal or abnormal. A method for testing memory devices, equipped with the necessary components.

14. If the selected via is determined to be normal, the test signal is transmitted via the via determined to be normal, and vias that have not been determined, selected from the first via, the second via, and the third via. The determination of the consistency between the test signal that passed through the via determined to be normal and the test signal that passed through the via that was not determined, The test method according to claim 13, comprising:

15. The first chip further generates the test signal, The test method according to claim 13.

16. The test signal is further generated by a tester outside the memory device. The test method according to claim 13.

17. A method for testing a memory device according to claim 1, The first chip transmits a test signal to the second chip via the first via and the third via, The first process is performed to determine the consistency between the test signal that has passed through the first via and the test signal that has passed through the third via. The first chip transmits a test signal to the second chip via the second via and the third via, The second process involves determining the consistency between the test signal that has passed through the second via and the test signal that has passed through the third via. A method for testing memory devices, equipped with the necessary components.

18. If the results of the first process and the results of the second process are consistent, it is determined that the first via, the second via, and the third via are normal. If the result of the first process shows a discrepancy and the result of the second process also shows a discrepancy, it is determined that the first via and the second via are normal and the third via is abnormal. If either the result of the first process or the result of the second process shows a match, and the other shows a mismatch, it is determined that the vias corresponding to the matching processes among the first and second vias and the third via are normal, and the vias corresponding to the mismatched processes among the first and second vias are abnormal. It also has the following features: The test method according to claim 17.

19. A method for testing a memory device according to claim 1, The first chip transmits a test signal to the second chip via the first via, the second via, and the third via, The process involves simultaneously determining whether the first via is normal or abnormal based on the test signal that has passed through the first via, determining whether the second via is normal or abnormal based on the test signal that has passed through the second via, and determining whether the third via is normal or abnormal based on the test signal that has passed through the third via. A method for testing memory devices, equipped with the necessary components.

20. A method for manufacturing a memory device according to claim 1, A test signal is transmitted from the first chip to the second chip via one via selected from the first via, the second via, and the third via. Based on the test signal that has passed through the selected via, it is determined whether the selected via is normal or abnormal. The switching circuit is configured such that the first state is selected in response to the determination that the first via and the second via are normal. The switching circuit is configured such that the second state is selected in response to the determination that the first via is abnormal and the second via is normal. The switching circuit is configured such that the third state is selected in response to the determination that the first via is normal and the second via is abnormal. A method for manufacturing a memory device, comprising the following:

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