Error correction device, error correction method, and semiconductor memory system

Abstract

To provide an error correction device, an error correction method, and a semiconductor memory system with improved performance. [Solution] The error correction device according to the embodiment comprises a decoding circuit that reads user data to which an error correction code has been added from a non-volatile memory and performs error correction decoding based on the error correction code for read data of a certain size, and a rewriting circuit that rewrites some bits in the read data of a certain size. Some bits include M consecutive bits or a plurality of bits spaced at N bits apart. M is any natural number greater than or equal to 1, and N is any natural number greater than or equal to 1.

Description

Technical Field

[0001] Embodiments of the present invention relate to an error correction device, an error correction method, and a semiconductor memory system for correcting errors in a NAND flash memory.

Background Art

[0002] Data written to a NAND flash memory may contain errors. In order to correct errors in the read data, an error correction code (hereinafter referred to as ECC) is added to the write data and encoded when writing the data. Whether the read data contains errors can be determined based on the ECC. Even if the data contains errors, up to a certain number of errors can be corrected as a result of decoding.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide an error correction device, an error correction method, and a semiconductor memory system with improved performance.

Means for Solving the Problems

[0005] The error correction device according to this embodiment comprises a decoding circuit that reads user data to which an error correction code has been added from a non-volatile memory and performs error correction decoding based on the error correction code for read data of a certain size, and a rewriting circuit that rewrites some bits in the read data of a certain size. Some bits include M consecutive bits or a plurality of bits spaced at N-bit intervals. M is any natural number greater than or equal to 1, and N is any natural number greater than or equal to 1. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram illustrating an example of an information processing system according to the first embodiment. [Figure 2] A block circuit diagram illustrating an example of error correction and decoding processing using an ECC circuit, an error information investigation circuit, and a data rewriting circuit according to the first embodiment. [Figure 3] A diagram illustrating an example of correct data (expected value) assumed for identifying error patterns according to the first embodiment. [Figure 4] A diagram illustrating an example of read data according to the first embodiment in which random errors occur. [Figure 5] A diagram illustrating an example of read data according to the first embodiment, in which burst errors occur in addition to random errors. [Figure 6] A flowchart illustrating an example of error pattern identification processing according to the first embodiment. [Figure 7] A block diagram illustrating an example of a burst error investigation circuit according to the first embodiment. [Figure 8] A diagram illustrating an example of the operation of a burst error investigation circuit according to the first embodiment. [Figure 9] A diagram illustrating an example of the operation of a data rewriting circuit according to the first embodiment. [Figure 10] A diagram illustrating another example of the operation of the data rewriting circuit according to the first embodiment. [Figure 11]A diagram for explaining an example of the operation of a comparison circuit according to the first embodiment. [Figure 12] A diagram for explaining an example of read data according to the second embodiment in which periodic errors occur in addition to random errors. [Figure 13] A flowchart for explaining an example of a specific process for an error pattern according to the second embodiment. [Figure 14] A block diagram for explaining an example of a periodic error investigation circuit according to the second embodiment. [Figure 15] A diagram for explaining an example of the operation of a periodic error investigation circuit according to the second embodiment. [Figure 16] A diagram for explaining an example of the operation of a periodic error investigation circuit according to the second embodiment. [Figure 17] A diagram for explaining an example of the operation of a periodic error investigation circuit according to the second embodiment. [Figure 18] A diagram for explaining an example of the operation of a periodic error investigation circuit according to the second embodiment. [Figure 19] A diagram for explaining an example of the operation of a data rewrite circuit according to the second embodiment. [Figure 20] A diagram for explaining an example of read data according to the third embodiment in which burst errors and periodic errors occur in addition to random errors. [Figure 21] A diagram for explaining the operation of a data rewrite circuit according to the third embodiment. [Figure 22] A diagram for explaining the operation of a data rewrite circuit according to the third embodiment. [Figure 23] A block circuit diagram for explaining an example of error correction decoding processing by an ECC circuit, an error information investigation circuit, and a data rewrite circuit according to the fourth embodiment. [Figure 24] A diagram for explaining an example of a product code using an XOR code according to the fourth embodiment. [Figure 25] A diagram for explaining an example of error correction by an XOR code according to the fourth embodiment. [Figure 26] A diagram for explaining an example of error correction by an XOR code according to a comparative example. [Figure 27] A diagram for explaining an example of error correction using an XOR code according to a comparative example. [Figure 28] A diagram for explaining an example of error correction using an XOR code according to the fourth embodiment. [Figure 29] A flowchart for explaining an example of a process for specifying an error pattern according to the sixth embodiment. [Embodiments for Carrying Out the Invention]

[0007] Hereinafter, embodiments will be described with reference to the drawings. The following description illustrates devices and methods for embodying the technical idea of the embodiments. However, the technical idea of the embodiments is not limited to the structure, shape, arrangement, material, etc. of the components described below. Modifications that can be easily conceived by those skilled in the art are naturally included in the scope of the disclosure. For the sake of clarity, in the drawings, the size, thickness, planar dimensions, shape, etc. of each element may be changed with respect to the actual element and represented schematically. In a plurality of drawings, there may be elements whose dimensional relationships and ratios to each other are different. In a plurality of drawings, corresponding elements may be assigned the same reference numerals and redundant descriptions may be omitted. In some cases, a plurality of designations may be given to some elements, but these designations are merely examples and do not deny the assignment of other designations to these elements. Nor does it deny the assignment of other designations to elements that do not have a plurality of designations. "Connection" may include not only direct connection but also connection via other elements. When the number of elements is not specified as plural, the element may be a single element or a plurality of elements.

[0008] [First Embodiment] (Information Processing System) FIG. 1 is a block diagram for explaining an example of an information processing system according to the first embodiment. The information processing system 1 includes a host device (hereinafter referred to as a host) 2 and a semiconductor memory system 4.

[0009] Host 2 may be a storage server that stores large amounts of diverse data in a semiconductor memory system 4, or it may be a server or a personal computer.

[0010] Host 2 comprises a central processing unit (CPU) 6 and memory 8. CPU 6 is at least one processor. CPU 6 controls the operation of various components of Host 2. CPU 6 controls communication between Host 2 and the semiconductor memory system 4. CPU 6 sends various commands to the semiconductor memory system 4. Examples of commands sent to the semiconductor memory system 4 are read commands and write commands. Host 2 may also include a control circuit (interface) that controls communication between Host 2 and the semiconductor memory system 4. CPU 6 communicates with the semiconductor memory system 4 via the control circuit.

[0011] Memory 8 is volatile memory. Examples of volatile memory include dynamic random access memory (DRAM) or static random access memory (SRAM). The storage area of ​​memory 8 may be allocated as a buffer area where data is temporarily stored. The buffer area may store data to be written to the semiconductor memory system 4 and data read from the semiconductor memory system 4.

[0012] The semiconductor memory system 4 is a semiconductor storage device configured to write data to and read data from non-volatile memory. An example of the semiconductor memory system 4 is a solid-state drive (hereinafter referred to as SSD). Hereinafter, the semiconductor memory system 4 will be referred to as SSD4. SSD4 can be used as storage for host 2. SSD4 may be built into host 2 or connected to host 2 via cables or a network.

[0013] SSD4 comprises non-volatile memory 12, volatile memory 14, and a controller 16.

[0014] An example of non-volatile memory 12 is NAND flash memory. Hereafter, non-volatile memory 12 will be referred to as NAND flash memory 12. An example of volatile memory 14 is DRAM and SRAM. Hereafter, volatile memory 14 will be referred to as DRAM 14.

[0015] The NAND flash memory 12 includes a plurality of blocks B0, B1, B2, ..., B(m-1). Each of the plurality of blocks B0, B1, B2, ..., Bm-1 includes a plurality of pages P0, ..., Pn-1. In this specification, one unspecified block among the plurality of blocks is referred to as block B. One unspecified page among the plurality of pages is referred to as page P. Block B functions as the smallest unit of data erasure operation. Block B may also be referred to as an erase block or physical block. Each of the plurality of pages P0, ..., Pn-1 includes a plurality of memory cells connected to a single word line. Page P functions as a unit of data write operation and data read operation. A word line may function as a unit of data write operation and data read operation.

[0016] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is called the maximum number of P / E cycles. One P / E cycle for a block includes a data erase operation to erase all memory cells in that block, and a data write operation (program operation) to write data to each page of that block.

[0017] The DRAM14 may be provided with a firmware storage area, a cache area for the logical-physical address translation table, and a buffer area for temporarily storing data.

[0018] The firmware is a program for controlling the operation of the controller 16. The firmware may be loaded from the NAND flash memory 12 into the DRAM 14. An example of firmware is a program for implementing error correction coding and error correction decoding.

[0019] The controller 16 functions as a memory controller configured to control the NAND flash memory 12. For example, the controller 16 controls the writing and reading of the NAND flash memory 12. The controller 16 may be implemented by a circuit such as a System on a Chip (SoC).

[0020] The controller 16 may include a host interface (host I / F) 22, a NAND interface (NAND I / F) 24, a DRAM interface (DRAM I / F) 26, an error correction coding / error correction decoding circuit (hereinafter referred to as ECC circuit) 28, and a CPU 30. These host I / F 22, NAND I / F 24, DRAM I / F 26, ECC circuit 28, and CPU 30 may be connected via a bus 10.

[0021] The host interface 22 functions as a circuit that receives various commands and data from host 2.

[0022] The NAND I / F 24 electrically connects the controller 16 and the NAND flash memory 12. The NAND I / F 24 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI). The NAND I / F 24 functions as a NAND control circuit configured to control the NAND flash memory 12. The NAND I / F 24 may be connected to multiple memory chips within the NAND flash memory 12 via multiple channels. By driving multiple memory chips in parallel, the access to the NAND flash memory 12 can be widened.

[0023] The DRAM I / F26 functions as a DRAM control circuit configured to control access to DRAM14.

[0024] The CPU 30 is a processor configured to control the host I / F 22, NAND I / F 24, DRAM I / F 26, and ECC circuit 28. The CPU 30 performs various processes by executing firmware loaded from the NAND flash memory 12 into the DRAM 14. The firmware is a control program containing a set of instructions that causes the CPU 30 to perform various processes. The CPU 30 can perform command processing and other operations to handle various commands from the host 2. The operation of the CPU 30 is controlled by the firmware executed by the CPU 30.

[0025] The CPU 30 functions as a command receiving circuit 32, a write circuit 34, a read circuit 36, an error information investigation circuit 38, a data rewriting circuit 40, and a comparison circuit 42. The CPU 30 may also function as each of these circuits 32, 34, 36, 38, and 40 by executing firmware.

[0026] Each of the circuits 32, 34, 36, 38, and 40 of the CPU 30 may be implemented by hardware blocks.

[0027] The command reception circuit 32 receives commands transmitted from the host 2. Based on the received commands, the command reception circuit 32 controls the ECC circuit 28, write circuit 34, read circuit 36, error information investigation circuit 38, and data rewriting circuit 40. When the command reception circuit 32 receives a read command, it instructs the read circuit 36 ​​to read data from the NAND flash memory 12 and instructs the ECC circuit 28 to perform error correction decoding of the read data. When the command reception circuit 32 receives a write command, it instructs the ECC circuit 28 to perform error correction encoding of the data to be written and instructs the write circuit 34 to write the error-corrected encoded data to the NAND flash memory 12. The comparison circuit 42 compares the read data and the decoded data and detects the difference. The difference accurately identifies the bit position where the error occurred.

[0028] (Error correction code) One example of an error correction code used by the ECC circuit 28 is the BCH code. In the BCH code, the unit of error is the bit. Errors in the read data from the NAND flash memory 12 are corrected before decoding. However, the ECC circuit 28 may fail to correct the errors, resulting in decoding failure. Possible reasons for decoding failure include non-random error patterns caused by defects in the flash memory that are difficult to correct, or even if the flash memory is in good condition, a large number of error bits being generated randomly due to stress during use.

[0029] CPU30 cannot identify the error pattern when decryption fails. Therefore, CPU30 cannot estimate whether the cause of the error is a malfunction in the flash memory or stress.

[0030] The reason why the error pattern cannot be identified when decoding fails is as follows: When decoding is successful, the ECC circuit 28 outputs the decoded data and the decoding success judgment result. When decoding fails, the ECC circuit 28 outputs only the decoding failure judgment result. When decoding fails, the data is not decoded, so there is no decoded data and it is not output.

[0031] In most cases, the expected value of data written to the flash memory implemented in SSDs is unknown.

[0032] The location of an error bit in the read data can only be determined by comparing the read data with the decoded data or the expected value and detecting the difference between the two. However, if decoded data fails while SSD4 is running, there is no output of decoded data, and the expected value is unknown, so the above comparison cannot be made and the location of the error bit cannot be identified. Therefore, CPU30 does not know whether the error bits are located randomly or not, and cannot identify the error pattern.

[0033] In NAND flash memory 12, the following non-random error patterns are possible:

[0034] • A pattern in which errors occur in multiple consecutive bits: a burst error pattern. • A pattern in which errors occur at regular bit intervals: a periodic error pattern. In the following explanation, the error patterns will be defined as burst error patterns and periodic error patterns.

[0035] The error correction code handled by the ECC circuit 28 according to this embodiment has the following characteristics.

[0036] When attempting to decode a codeword containing error bits, the success or failure of the decoding generally depends on whether the number of error bits exceeds a certain limit. This limit is called the correction limit. • In cases of burst errors, where error bits are densely clustered at consecutive bit positions, or periodic errors, where errors are concentrated at specific intervals, decoding may not be successful even if the number of error bits is well below the correction limit. The above error correction code suffers from reduced correction capability due to burst errors and periodic errors. Therefore, in this embodiment, burst errors and periodic errors occurring in the codeword are detected, and the cause of the error is identified.

[0037] The NAND flash memory 12 according to this embodiment is capable of experiencing 8-bit burst information loss errors and 4-bit periodic information loss errors.

[0038] For burst errors, a series of consecutive bit positions are defined as an interval, and for periodic errors, periodic bit positions located at regular bit intervals are defined as a sequence. In this embodiment, since the expected value is unknown, the details of the error that occurred are unknown at the time of decoding failure.

[0039] The CPU 30 according to this embodiment makes some assumptions about the number of bits mentioned above, rewrites the read data, makes some assumptions about the burst error and period error mentioned above, rewrites the read data, and decodes the rewritten data. If decoding fails, the CPU 30 changes the assumptions, changes the rewritten data, and decodes again, repeating this process.

[0040] The following explanation assumes that the assumptions are correct and that decryption is successful. Even if the assumptions are changed and the decryption process is repeated, decryption may still ultimately fail.

[0041] For the sake of simplicity, the pre-decoded data (data read from the NAND flash memory 12) in this embodiment will satisfy all of the following conditions.

[0042] This includes not only random errors but also burst errors or periodic errors. • In burst error intervals, information loss occurs, and all bits degenerate to either "0" or "1". In a periodic error sequence, information loss occurs, and all bits degenerate to either "0" or "1". • Decoding by the ECC circuit 28 will not succeed as is. If burst errors or periodic errors are eliminated, decoding by the ECC circuit 28 will be successful.

[0043] (Error correction / decryption process) Figure 2 is a block diagram illustrating an example of error correction / decoding processing using the ECC circuit 28, error information investigation circuit 38, and data rewriting circuit 40 according to the first embodiment.

[0044] Error pattern information, error history information, and data read from the NAND flash memory 12 are input to the error information investigation circuit 38. The error information investigation circuit 38 outputs error candidate information.

[0045] Error pattern information includes, for example, information representing an 8-bit burst error pattern or a 4-bit periodic error pattern. Error pattern information related to the NAND flash memory 12, which has been checked in advance before the SSD4 is shipped, is written to the NAND flash memory 12. When the SSD4 is in operation, the error pattern information is read from the NAND flash memory 12 and input to the error information investigation circuit 38. If a new error pattern is detected while the SSD4 is in operation, the error pattern information in the NAND flash memory 12 is updated.

[0046] Error history information is error information that has been determined to be an error from among the error candidate information detected by the error information investigation circuit 38. Error history information and error candidate information represent the type of error pattern and the position of the error bit. Error candidate information is written to and updated in the NAND flash memory 12 when it occurs. Error history information is written to and updated in the NAND flash memory 12 when it is determined to be an error.

[0047] The error information investigation circuit 38 includes a burst error investigation circuit 52, a periodic error investigation circuit 54, an on / off signal generation circuit 56, and an internal state flag 58. The on / off signal generation circuit 56 generates an on signal or an off signal. An on signal turns on the internal state flag 58. When the internal state flag 58 is on, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate. An off signal turns off the internal state flag 58. When the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate.

[0048] Error candidate information and read data are input to the data rewriting circuit 40. The data rewriting circuit either outputs the read data as is, or outputs rewritten data with specific bits of the read data rewritten.

[0049] The data rewriting circuit 40 includes a rewrite bit positioning circuit 62, a rewrite bit value generation circuit 64, an on / off signal generation circuit 66, and an internal state flag 68. The on / off signal generation circuit 66 generates an on signal or an off signal. An on signal turns on the internal state flag 68. When the internal state flag 68 is on, the rewrite bit positioning circuit 62 and the rewrite bit value generation circuit 64 operate. An off signal turns off the internal state flag 68. When the internal state flag 68 is off, the rewrite bit positioning circuit 62 and the rewrite bit value generation circuit 64 do not operate.

[0050] The ECC circuit 28 receives read data or rewrite data as input. The ECC circuit 28 performs error correction decoding of the input data. If decoding is successful, the ECC circuit 28 outputs the decoded data and a success signal indicating decoding success. If decoding fails, the ECC circuit 28 does not output the decoded data and outputs a failure signal indicating decoding failure. The decoded data is written to the NAND flash memory 12. The success / failure signal is input to the error information investigation circuit 38, the data rewriting circuit 40, and the comparison circuit 42.

[0051] The comparison circuit 42 receives the read data, the decoded data, and a success / failure judgment signal. When the comparison circuit 42 receives a judgment signal indicating successful decoding, it compares the read data with the decoded data and outputs difference data indicating the difference in bit values ​​at each bit position. In the difference data, bits where both input data match are normal bits, and their bit value is "0". In the difference data, difference bits where both input data do not match are error bits, and their bit value is "1". Note that the bit value of a normal bit may be "1" and the bit value of an error bit may be "0".

[0052] (Identifying error patterns) The data read from the NAND flash memory 12 is stored in a buffer in the DRAM 14. Data is not read from the NAND flash memory 12 each time the error information investigation circuit 38 processes. Data is not read from the NAND flash memory 12 each time the data rewriting circuit 40 processes.

[0053] Figure 3 is a diagram illustrating an example of correct data (hereinafter referred to as the expected value) assumed for identifying error patterns according to the first embodiment. The data length (1 frame) handled in error correction coding / decoding is assumed to be N bits of data, and the bit positions from the beginning to the end of a frame are called the index. The indices are 0, 1, 2, ..., N-1 in order from the beginning.

[0054] If the ECC circuit 28 fails to decode, the error information investigation circuit 38 examines the read data to narrow down the bit positions where burst errors or periodic errors are suspected. The data rewriting circuit 40 rewrites the bit values ​​at the narrowed bit positions. The ECC circuit 28 attempts to decode the rewritten data again. If the second decoding fails, the bit values ​​are rewritten to different values, and decoding is repeated. If decoding is successful, it is confirmed that the suspected error had occurred. By comparing the data before and after decoding, the exact location of the error bit can also be identified.

[0055] In the first embodiment, it is assumed that the read data (pre-decoded data) from the NAND flash memory 12 contains an 8-bit burst error in addition to random errors.

[0056] Figure 4 illustrates an example of readout data according to the first embodiment in which random errors occur. The random data with indices 4, 9, 21, and 27 (indicated by the bold border) are considered to be errors. Readout data containing only random errors can be decoded by the ECC circuit 28.

[0057] Figure 5 illustrates an example of read data according to the first embodiment, in which burst errors occur in addition to random errors. In the read data, in addition to the random errors shown in Figure 4 (index = 4, 9, 21, 27), a burst error occurs in which the bit value (thick outline) of the consecutive 8-bit interval at index ∈ [11, 18] degenerates to "1" due to information loss. Read data containing burst errors cannot be decoded by the ECC circuit 28 as is. Burst errors also include burst errors in which the bit value degenerates to "0" due to information loss.

[0058] Figure 6 is a flowchart illustrating an example of the error pattern identification process by the error information investigation circuit 38 according to the first embodiment.

[0059] The error information investigation circuit 38 determines whether the judgment signal output by the ECC circuit 28 indicates success or failure (step S12). If the judgment signal indicates failure, the on / off signal generation circuit 56 generates an on signal and turns on the internal state flag 58 (step S14). If the judgment signal indicates success, the on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S16). When the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate. After step S16 is executed, step S12 is executed again.

[0060] If the internal state flag 58 is on (step S14), the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate. The error information investigation circuit 38 is given an 8-bit burst error pattern and a 4-bit periodic error pattern as known error patterns for the NAND flash memory 12. The burst error investigation circuit 52 and the periodic error investigation circuit 54 read the bit values ​​of the read data, determine if the pattern of bit values ​​matches a known error pattern, and save the bit value pattern that matches the known error pattern (step S18).

[0061] Figure 7 is a block diagram illustrating an example of a burst error investigation circuit 52 according to the first embodiment. The burst error investigation circuit 52 includes a read bit position designation circuit 72, a bit value read / comparison circuit 74, a counter for consecutive identical bit values ​​76, and a known pattern matching position / consecutive value storage circuit 78. The initial value of the counter for consecutive identical bit values ​​76 is set to 0.

[0062] Figure 8 is a diagram illustrating an example of the operation of the burst error investigation circuit 52 according to the first embodiment. The read bit position designation circuit 72 designates the indices sequentially starting from 0. The bit value read and compare circuit 74 reads the bit value of each index sequentially starting from 0 and compares the bit value of each index with the bit value of the previous index. The identical bit value consecutive count counter 76 is reset (initialized) when the bit value of each index is different from the bit value of the previous index, that is, when there is one consecutive bit value of "1" or "0" (Step 0 in Figure 8).

[0063] The value of the identical bit value consecutive count counter 76 is incremented by 1 if the bit value of each index is the same as the bit value of the previous index (Step 1 in Figure 8). When the value of the identical bit value consecutive count counter 76 is n, it means that there are (n+1) consecutive bits of the bit value "1" or "0".

[0064] The counter for consecutive identical bit values ​​76 is reset (initialized) when the bit value of each index is different from the bit value of the previous index, that is, when there are one consecutive bits of bit value "1" or "0" (Step 2 in Figure 8).

[0065] When the same bit value appears for 8 consecutive bits, the value of the consecutive identical bit value counter 76 becomes 7 (Step 17 in Figure 8). When the value of the consecutive identical bit value counter 76 becomes 7, the specified burst error pattern (8-bit burst error pattern) is detected.

[0066] The known pattern matching position / continuous value storage circuit 78 stores the currently read index (=17) and bit value (="1"). From the value stored by the storage circuit 78 and the known error pattern of the 8-bit burst error, it can be seen that there are 8 consecutive bits of the bit value "1" at index ∈ [10,17].

[0067] The bit value of the next index (=18) is read (Step 18 in Figure 8). Since the bit value is "1", the value of the identical bit value consecutive count counter 76 becomes 8. At this point, since the state of having 8 consecutive identical bit values ​​continues, the bit value pattern matches a known error pattern. Therefore, the known pattern match position / consecutive value storage circuit 78 stores the index (=18) and bit value (="1") that is currently being read.

[0068] The bit value of the next index (=19) is read (Step 19 in Figure 8). Since the bit value is "0", the counter for consecutive identical bit values ​​76 is reset (initialized).

[0069] Similarly, bit values ​​are read up to index(N-1) (Step(N-1) in Figure 8).

[0070] Returning to the explanation of Figure 6, once the burst error investigation circuit 52 has completed the investigation up to Step (N-1) in Figure 8, it reads the stored values ​​(index: 17, bit value "1" and index: 18, bit value "1") from the storage circuit 78 (step S20 in Figure 6).

[0071] In the first embodiment, the bit value pattern matching the known burst error pattern is found only at index ∈ [10,17] and index ∈ [11,18] in the read data. From this, it is suspected that a burst error occurred at index ∈ [10,17] and index ∈ [11,18]. index ∈ [10,17] and index ∈ [11,18] are candidate intervals where a burst error may occur.

[0072] Similar to the burst error investigation circuit 52, the periodic error investigation circuit 54 also reads the bit values ​​of the read data, determines whether the pattern of bit values ​​matches a known periodic error pattern, and saves the bit value pattern that matches the known error pattern. In the first embodiment, it is assumed that no pattern suspected to be a periodic error was detected. Details of the investigation by the periodic error investigation circuit 54 will be described in the second embodiment.

[0073] The error information investigation circuit 38 inputs the stored value read from the storage circuit 78 to the data rewriting circuit 40 (step S22 in Figure 6). The on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S24). As a result, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate.

[0074] In the data rewriting circuit 40, the on / off signal generation circuit 66 generates an on signal and turns on the internal state flag 68 (step S26). When the internal state flag 68 is on, the rewrite bit position specification circuit 62 and the rewrite bit value generation circuit 64 operate.

[0075] The rewrite bit position designation circuit 62 and the rewrite bit value generation circuit 64 rewrite the bit values ​​in each of the two candidate intervals where an 8-bit burst error is suspected to have occurred, and the ECC circuit 28 attempts to decode the rewritten data (step S28).

[0076] Figure 9 is a diagram illustrating an example of the operation of the data rewriting circuit 40 according to the first embodiment. The rewrite bit position designation circuit 62 first designates the index ∈ [10, 17] section from among two candidate sections in which an 8-bit burst error in the read data is suspected to occur. The rewrite bit value generation circuit 64 generates the 8-bit value of the designated section of the read data. 8 The data is rewritten sequentially in 256 different ways (Steps 0 to 255 in Figure 9). The read data is assumed to contain random errors and burst errors.

[0077] The ECC circuit 28 attempts to decode the rewritten data and supplies a success / failure determination signal to the data rewriting circuit 40. Assume that all 256 possible rewrite data values ​​for the interval index ∈ [10, 17] fail to decode.

[0078] Figure 10 is a diagram illustrating another example of the operation of the data rewriting circuit 40 according to the first embodiment. The rewrite bit position designation circuit 62 designates the following index ∈ [11, 18] as a candidate for the rewrite interval. The rewrite bit value generation circuit 64 generates the 8-bit value of the designated interval of the read data. 8 The data is sequentially rewritten in 256 different ways (Steps 0 to 76 in Figure 10). The read data is assumed to contain random errors and burst errors. In Step 76 of Figure 10, the rewritten data for index ∈ [11, 18] matches the expected value, so decoding is successful. The ECC circuit 28 feeds back the success judgment signal to the data rewriting circuit 40.

[0079] Returning to the explanation of Figure 6, the data rewriting circuit 40 determines whether the judgment signal output by the ECC circuit 28 indicates success or failure (step S30). If the judgment signal indicates success, the on / off signal generation circuit 66 generates an off signal and turns off the internal state flag 68 (step S32). If the internal state flag 68 is off, the rewrite bit position specification circuit 62 and the rewrite bit value generation circuit 64 do not operate.

[0080] If the judgment signal indicates failure, the data rewriting circuit 40 performs error processing (step S34). Examples of error processing include writing the judgment signal to the NAND flash memory 12 and transmitting the judgment signal to a server or the like (not shown).

[0081] It can be seen that a burst error occurred at the point of successful decoding. Depending on the correction capability of the ECC circuit 28, decoding may be successful even in Step 166 of Figure 9, where the burst error section and the inverted section do not exactly coincide. Thus, there are cases where the burst error section cannot be accurately identified.

[0082] To accurately identify burst error intervals, the comparison circuit 42 compares the read data from the NAND flash memory 12 with the decoded data output from the ECC circuit 28 and outputs difference data (step S36).

[0083] Figure 11 is a diagram illustrating an example of the operation of the comparison circuit 42 according to the first embodiment. The comparison circuit 42 creates difference data by performing an exclusive OR (XOR) operation on bit values ​​at bit positions with the same index. The difference data is N bits, where "0" is the value at bit positions where the values ​​match before and after decoding, and "1" is the value at bit positions where the values ​​do not match.

[0084] The CPU 30 can identify the location of the burst error interval in more detail by examining the area around the rewritten bit position in the difference data when decoding is successful. The bit value of the nine consecutive bits at index ∈ [10, 18] is "1", but the bit value at index=10 is not incorrect, while the bit values ​​at index=11 and 18 are incorrect. Therefore, the burst error interval can be identified as index ∈ [11, 18]. Based on the difference data, the CPU 30 can determine one of several error candidate pieces of information as the error history information.

[0085] According to the first embodiment, based on burst error pattern information that may occur in the NAND flash memory 12, some bit values ​​of the read data can be rewritten, and decoding can be attempted again. This makes it possible to identify the location of the burst error in the NAND flash memory 12.

[0086] [Second Embodiment] The circuit configuration of the information processing system according to the second embodiment is the same as in Figure 1, and the circuit configurations of the ECC circuit 28, error information investigation circuit 38, and data rewriting circuit 40 according to the second embodiment are the same as in Figure 2, so they are omitted from the illustration.

[0087] (Identifying error patterns) Figure 12 illustrates an example of read data according to the second embodiment, in which periodic errors occur in addition to random errors. In the read data, in addition to the random errors shown in Figure 4 (index = 4, 9, 21, 27), periodic errors occur in which a 4-bit periodic sequence with index ∈ [4k+2] (where k is an integer) degenerates to "0" due to information loss. Read data containing periodic errors cannot be decoded by the ECC circuit 28 as is. Periodic errors include periodic errors in which bit values ​​degenerate to "0" due to information loss.

[0088] Figure 13 is a flowchart illustrating an example of the error pattern identification process by the error information investigation circuit 38 according to the second embodiment.

[0089] The error information investigation circuit 38 determines whether the judgment signal output by the ECC circuit 28 indicates success or failure (step S52). If the judgment signal indicates failure, the on / off signal generation circuit 56 generates an on signal and turns on the internal state flag 58 (step S54). If the judgment signal indicates success, the on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S56). When the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate. After step S56 is executed, step S52 is executed again.

[0090] When the internal state flag 58 is on, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate. The error information investigation circuit 38 is given an 8-bit burst error pattern and a 4-bit periodic error pattern as known error patterns of the NAND flash memory 12. The burst error investigation circuit 52 and the periodic error investigation circuit 54 read the bit values ​​of the read data, determine whether the pattern of bit values ​​matches a known error pattern, and save the bit value pattern that matches the known error pattern (step S58). In the second embodiment, it is assumed that no pattern of read data suspected of being a burst error was detected as a result of the investigation by the burst error investigation circuit 52.

[0091] Figure 14 is a block diagram illustrating an example of a periodic error investigation circuit 54 according to the second embodiment. The periodic error investigation circuit 54 includes a readout sequence designation circuit 82, a readout bit position designation circuit 84, a bit value readout circuit 86, a "0" counter 88, a "1" counter 90, a sequence bit value ratio calculation circuit 92, and a known pattern matching sequence / degenerate value storage circuit 94.

[0092] The periodic error investigation circuit 54 counts the cumulative number of bit values ​​"0" and "1" in each sequence and calculates the ratio of "0" to "1" within the sequence. The NAND flash memory 12 is designed so that the ratio of bit values ​​"0" to bit values ​​"1" is almost equal throughout, and data is written in a way that prevents bias between bit values ​​"0" and "1". Therefore, if no periodic errors occur, the ratio of bit values ​​"0" to bit values ​​"1" within a sequence will be approximately 1:1. When the ratio of "0" to "1" within a sequence deviates significantly from 1:1, the occurrence of a periodic error is suspected. Criteria for determining whether the ratio has deviated significantly from 1:1 are set in advance.

[0093] Figures 15, 16, 17, and 18 are diagrams illustrating an example of the operation of the period error investigation circuit 54 according to the second embodiment.

[0094] The readout sequence designation circuit 82 first sequentially reads out the bit values ​​of a 4-bit periodic sequence (referred to as sequence 0) starting from index=0 of the readout data (Step0-0 to Step0-(N / 4) in Figure 15). The "0" counter 88 counts the total value of the readout bit values ​​"0". The "1" counter 90 counts the total value of the readout bit values ​​"1".

[0095] Once the investigation of sequence 0 is complete in Step 0 to Step 0-(N / 4) in Figure 15, the ratio of "0" to "1" is calculated from the cumulative number of bit values ​​"0" X0_0 and the cumulative number of bit values ​​"1" X0_1 in sequence 0. In sequence 0, there is no significant bias in the ratio of "0" to "1", and it is determined that the bit value pattern of sequence 0 does not match any known pattern.

[0096] Once the investigation of sequence 0 is complete, the same process is then carried out for the 4-bit periodic sequence starting with index=1 (referred to as sequence 1) (Figure 16). This investigation is repeated for all sequences (Figures 17 and 18). The number of sequences investigated is equal to the period of the sequence. In the second embodiment, the number of sequences investigated is four, from sequence 0 to sequence 3.

[0097] In sequences 0, 1, and 3, the bit value patterns did not match the known patterns. On the other hand, in sequence 2 (Step 2-0 to Step 2-(N / 4) in Figure 17), it was found that all bits were degenerated to "0", and the bit value pattern was determined to match the known pattern. Therefore, the known pattern matching sequence / degenerate value storage circuit 94 stores sequence number: 2 and degenerate value: "0".

[0098] Returning to the explanation of Figure 13, once the periodic error investigation circuit 54 has finished investigating all sequences, it reads the saved value (sequence number: 2, degenerate value: "0") from the storage circuit 94 (step S60 in Figure 13). In the second embodiment, it is assumed that the bit value pattern matching the known periodic error pattern was found only in sequence 2 of the read data. From this, it is suspected that a periodic error occurred in sequence 2. Sequence 2 is a candidate sequence in which a periodic error occurred.

[0099] The error information investigation circuit 38 inputs the value read from the storage circuit 94 to the data rewriting circuit 40 (step S62 in Figure 13). The on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S64). As a result, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate.

[0100] In the data rewriting circuit 40, the on / off signal generation circuit 66 generates an on signal and turns on the internal state flag 68 (step S66). When the internal state flag 68 is on, the rewrite bit position specification circuit 62 and the rewrite bit value generation circuit 64 operate.

[0101] The data rewriting circuit 40 rewrites the bit values ​​in sequence 2, where a 4-bit periodic error is suspected, and the ECC circuit 28 attempts to decode it (step S68).

[0102] Figure 19 is a diagram illustrating an example of the operation of the data rewriting circuit 40 according to the second embodiment. The rewrite bit position specification circuit 62 specifies the bit position of sequence 2 of the read data in which a 4-bit periodic error is suspected to have occurred. The rewrite bit value generation circuit 64 generates the bit value of the sequence of read data by 2 (N / 4) The data is rewritten sequentially according to the format (Step 0 to Step T in Figure 19). The read data is assumed to contain random errors and periodic errors.

[0103] The ECC circuit 28 attempts to decode the rewritten data and supplies a success / failure determination signal to the data rewriting circuit 40. (N / 4) While it is possible that decoding may succeed during the rewriting process, in this embodiment, decoding is considered successful only when the entire sequence 2 has been rewritten to match the expected value (Step T in Figure 19).

[0104] Returning to the explanation of Figure 13, the data rewriting circuit 40 determines whether the judgment signal output by the ECC circuit 28 indicates success or failure (step S70). If the judgment signal indicates success, the on / off signal generation circuit 66 generates an off signal and turns off the internal state flag 68 (step S72). If the internal state flag 68 is off, the rewrite bit position specification circuit 62 and the rewrite bit value generation circuit 64 do not operate.

[0105] If the judgment signal indicates failure, the data rewriting circuit 40 performs error processing (step S74). An example of error processing is the same as the process in step S74.

[0106] It can be seen that a periodic error occurred at the point when decoding was successful. Similar to the first embodiment, in the second embodiment, decoding may be successful even when the entire sequence 2 does not exactly match the expected value. In the second embodiment as well, there may be cases where the period of the periodic error cannot be accurately identified.

[0107] To accurately identify the period of the period error, the comparison circuit 42 compares the read data from the NAND flash memory 12 with the decoded data output from the ECC circuit 28 and outputs difference data (step S76). By examining sequence 2 of the difference data, the occurrence of a period error in sequence 2 can be reliably identified.

[0108] Unlike burst errors, periodic errors do not involve overlapping bit positions between sequences, so it is almost certain that the periodic error sequence is sequence 2 at the time of successful decoding.

[0109] According to the second embodiment, based on periodic error pattern information that may occur in the NAND flash memory 12, some bit values ​​of the read data can be rewritten, and decoding can be attempted again. This makes it possible to identify the period of periodic errors in the NAND flash memory 12.

[0110] [Third Embodiment] The circuit configuration of the information processing system according to the third embodiment is the same as in Figure 1, and the circuit configurations of the ECC circuit 28, error information investigation circuit 38, and data rewriting circuit 40 according to the third embodiment are the same as in Figure 2, so they are omitted from the illustration.

[0111] (Identifying error patterns) Figure 20 is a diagram illustrating an example of readout data according to the third embodiment, in which burst errors and periodic errors occur in addition to random errors. In the readout data, in addition to the random errors shown in Figure 4 (index=4, 9, 21, 27), a burst error occurs in which the bit value of a continuous 8-bit interval at index ∈ [11, 18] degenerates to "1" due to information loss, and a periodic error occurs in which a 4-bit periodic sequence at index ∈ [4k+2] (k is an integer) degenerates to "1" due to information loss. Readout data containing burst errors and periodic errors cannot be decoded by the ECC circuit 28 as is. Burst errors also include errors in which the bit value degenerates to "0" due to information loss. Periodic errors also include errors in which the bit value degenerates to "0" due to information loss.

[0112] Similar to the first and second embodiments, when the ECC circuit 28 outputs a failure determination signal, the burst error investigation circuit 52 and the periodic error investigation circuit 54 start operating to determine whether a known error pattern has occurred in the read data. The investigation of the burst error pattern is the same as the process shown in Figure 6. The investigation of the periodic error pattern is the same as the process shown in Figure 13. As a result, it is suspected that burst errors have occurred in two intervals of the read data, index ∈ [10,17] and index ∈ [11,18], and that periodic errors have occurred in sequence 2. The storage circuit 78 of the burst error investigation circuit 52 stores values ​​related to the candidate burst error intervals. The storage circuit 94 of the periodic error investigation circuit 54 stores values ​​related to the candidate periodic errors.

[0113] When the error investigation circuit 38 transmits the stored values ​​from the storage circuit 78 of the burst error investigation circuit 52 and the stored values ​​from the storage circuit 94 of the periodic error investigation circuit 54 to the data rewriting circuit 40, the burst error investigation circuit 52 and the periodic error investigation circuit 54 stop operating, and the rewrite bit position specification circuit 62 and the rewrite bit value generation circuit 64 start operating.

[0114] Figures 21 and 22 are diagrams illustrating the operation of the data rewriting circuit 40 according to the third embodiment.

[0115] The rewrite bit position designation circuit 62 and the rewrite bit value generation circuit 64 rewrite bit values ​​in the interval index ∈ [10, 17] in a certain sequence of read data in order to identify a burst error. First, the rewrite bit position designation circuit 62 and the rewrite bit value generation circuit 64 determine the first rewrite value in sequence 2 where a 4-bit periodic error is suspected, and then the bit value of index ∈ [10, 17] in the read data is changed twice. 8 The values ​​are rewritten sequentially in 256 different ways (Step0-0 to Step0-255 in Figure 21). If a bit value belongs to both the rewriting interval and the rewriting sequence, the rewriting of the interval takes precedence (e.g., index=10 in Figure 21).

[0116] The ECC circuit 28 attempts to decode the rewritten data and supplies a success / failure determination signal to the data rewriting circuit 40. In the third embodiment, it is assumed that all 256 rewritten data decoding attempts in sequence 2 have failed.

[0117] If decoding of all rewritten data for index ∈ [10, 17] in sequence 2 fails, the rewrite bit positioning circuit 62 and the rewrite bit value generation circuit 64 update the rewritten values ​​of sequence 2 and attempt to rewrite index ∈ [10, 17] again (Step 1-0, ... in Figure 22).

[0118] In the third embodiment, an 8-bit burst interval update cycle is nested within a 4-bit periodic sequence update cycle.

[0119] Because there are overlapping bits in the burst error interval and the periodic error sequence, the burst error and periodic error will be removed by one of the combinations of sequence 2 and index ∈ [10, 17], resulting in successful decoding (Step T'-166 in Figure 22).

[0120] Upon successful decoding, it becomes clear that burst errors and periodic errors had occurred. Similar to the first and second embodiments, the comparison circuit 42 creates pre- and post-decoding difference data to accurately identify the error pattern. The CPU 30 can identify the more detailed locations of the burst error interval and periodic error sequence by examining the area around the rewritten bit position at the time of successful decoding within this difference data.

[0121] In addition to cases where burst errors and periodic errors occur simultaneously, such as in the third embodiment where they occur completely separately and randomly, burst errors can also occur periodically. For example, given known error patterns of 8-bit burst errors and 32-bit periodic errors, an 8-bit burst error may occur with a 32-bit period, such as index∈[0,7], index∈[32,39], index∈[64,71]… In this case as well, errors are suspected in both the burst error investigation circuit 52 and the periodic error investigation circuit 54. If the two types of errors occur separately and randomly, it is considered that burst errors occurred in multiple intervals. If burst errors occur periodically, it is considered that periodic errors occurred in multiple sequences. However, in both cases, the error bit positions point to the same set of bit positions, so the procedure for rewriting them depends on the circuit configuration and settings.

[0122] According to the third embodiment, based on burst error pattern information and periodic error pattern information that may occur in the NAND flash memory 12, some bit values ​​of the read data can be rewritten, and decoding can be attempted again. This makes it possible to identify the location of burst errors and the period of periodic errors in the NAND flash memory 12.

[0123] [Fourth Embodiment] The fourth embodiment determines whether a successful decoding is a misdecoding.

[0124] In the first to third embodiments, if decoding fails, many bit values ​​are rewritten before attempting decoding again. Therefore, there is a risk that the data may be decoded to something different from the expected value. The ECC circuit 28 determines decoding success / failure regardless of whether the decoded data matches or does not match the expected value, so it is not possible to check whether the decoding is correct using only a single code. To check whether the decoding is correct or not, the ECC circuit 28 needs to use a multiplication code such as an XOR code.

[0125] The circuit configuration of the information processing system according to the fourth embodiment is the same as in Figure 1, so it is omitted from the illustration.

[0126] Figure 23 is a block diagram illustrating an example of error correction decoding processing using the ECC circuit 28, error information investigation circuit 38, and data rewriting circuit 40 according to the fourth embodiment. Figure 24 is a diagram illustrating an example of a product code using an XOR code according to the fourth embodiment.

[0127] The data handled in the first to third embodiments corresponds to the horizontal frames in Figure 24. Each horizontal frame consists of a bit value corresponding to the user data and a bit value corresponding to the parity (referred to as horizontal parity in Figure 24 for convenience) added during encoding by the ECC circuit 28. When writing M horizontal frames to the NAND flash memory 12, the ECC circuit 28 performs an XOR operation on identical bit positions in the M horizontal frames and generates the result as XOR parity (referred to as vertical parity in Figure 24 for convenience). The (M+1) bits, which are the M bits after the XOR operation and the 1 bit of vertical parity, are referred to as the vertical frame of the XOR code.

[0128] When an XOR operation is performed on all bit values ​​within a vertical frame, the result is "0" if there are no bit errors within the vertical frame, or if there are even bit errors. If there are errors within the vertical frame, the result is "1". This XOR result is called the XOR code syndrome. When the errors within the vertical frame are mostly 1 bit or less, the XOR code is very effective for checking the accuracy of the decoding.

[0129] The data read from the NAND flash memory 12 consists of multiple horizontal frames and multiple vertical frames. The read data is input to the frame selection circuit 102 (Figure 23). The frame selection circuit 102 selects and outputs one frame from among the multiple horizontal frames and multiple vertical frames. The error information investigation circuit 38 is also input with the selected frame information (vertical / horizontal frame number). The ECC circuit 28 includes a horizontal / vertical frame specification circuit 104. The horizontal / vertical frame specification circuit 104 specifies either a vertical frame or a horizontal frame based on the selected frame information. The data rewriting circuit 40 according to the fourth embodiment includes a rewriting frame / bit position specification circuit 62A instead of the rewriting bit position specification circuit 62 according to the first embodiment.

[0130] Figure 25 is a diagram illustrating an example of error correction using an XOR code according to the fourth embodiment. Correction using the XOR code is performed when decoding of a horizontal frame alone fails. Assume that the ECC circuit 28 attempts to decode horizontal frame 1 and fails. The ECC circuit 28 reads out the M horizontal frames that make up the XOR code and attempts to decode each of them. Assume that as a result, all frames other than horizontal frame 1 are decoded without using the first to third embodiments. Since decoding was successful without rewriting, the risk of misdecoding can be ignored. In this case, the bit positions where the syndrome of the XOR code is "1" inevitably mean that the bit value of horizontal frame 1 is incorrect. Therefore, by rewriting the bit value of the corresponding bit position in horizontal frame 1 to invert it, horizontal frame 1 will be correctly restored.

[0131] Figure 26 illustrates an example of error correction using an XOR code in a comparative example. When decoding fails in multiple horizontal frames, an even number of bit errors may occur in the vertical frame. In this case, the XOR syndrome appears to be "0". Furthermore, even if the bit position where the XOR syndrome is "1" is identified, it is not possible to determine which horizontal frame has the error. In this case, further decoding attempts cannot be made.

[0132] Figure 27 is a diagram illustrating an example of error correction using an XOR code related to the comparative example in Figure 26. Due to its structure, the NAND flash memory 12 may experience burst errors and periodic errors at the same bit positions in multiple horizontal frames, both resulting from the same failure in the NAND flash memory 12. Based on this, the fourth embodiment assumes a case where a burst error occurs in the index ∈ [11, 18] interval of two horizontal frames (horizontal frame 0 and horizontal frame 3). In this case, the comparative example shown in Figure 26 cannot be decoded any further. While executing the processing of the first embodiment on horizontal frame 0 might result in successful decoding, it involves rewriting, thus carrying a risk of incorrect decoding.

[0133] Therefore, when the processing of the first embodiment is performed and horizontal frame 0 is decoded, the correctness of this decoding can be confirmed as shown in Figure 28 by performing the error correction shown in Figure 25.

[0134] Figure 28 is a diagram illustrating an example of error correction using an XOR code according to the fourth embodiment. The data rewriting circuit 40 rewrites the horizontal frame 3 following the error correction shown in Figure 25. When decoding is attempted again on this rewritten horizontal frame 3, the following can be said depending on the result.

[0135] If decoding is successful without any corrections, then all bits in the horizontal frame will have been successfully corrected, and the XOR syndrome of all vertical frames will also be "0," thus indicating that decoding of horizontal frame 0 is correct. If decoding fails or even one bit is corrected, a "1" will appear in the XOR syndrome, indicating that the decoding of horizontal frame 0 was incorrect.

[0136] According to the fourth embodiment, it is possible to determine whether the decoding of the horizontal frame is correct or incorrect, and it is recognized that the risk of misdecoding increases due to rewriting.

[0137] [Fifth Embodiment] In the fifth embodiment, as in the first to fourth embodiments, the CPU 30 writes the type of error and the bit position when decoding is successful to the NAND flash memory 12 as error history information and makes it non-volatile.

[0138] When the error information investigation circuit 38 investigates an error in the future, the CPU 30 can read the non-volatile error history information from the NAND flash memory 12 and supply the error history information to the error information investigation circuit 38.

[0139] The error information investigation circuit 38 according to the first to fourth embodiments investigated burst errors and periodic errors sequentially starting from the bit position index=0, resulting in poor investigation efficiency. However, the error information investigation circuit 38 according to the fifth embodiment can prioritize the investigation of errors of the same type and bit positions as errors that have occurred in the past by referring to error history information, thereby improving investigation efficiency and shortening investigation time.

[0140] [Sixth Embodiment] The sixth embodiment relates to the operation of an on / off signal generation circuit 56 that determines whether or not to operate the burst error investigation circuit 52 and the periodic error investigation circuit 54. In the first to fifth embodiments, the on / off signal generation circuit 56 generates an on signal if the determination signal output from the ECC circuit 28 indicates failure.

[0141] The on / off signal generation circuit 56 according to the sixth embodiment determines whether to generate an on signal or an off signal depending on the cause of the decoding failure. The causes of decoding failure include the occurrence of random errors with a number of bits exceeding the correction limit (hereinafter referred to as cause A) and the occurrence of burst errors or periodic errors (hereinafter referred to as cause B). In the case of decoding failure due to cause B, the on / off signal generation circuit 56 according to the sixth embodiment generates an on signal and activates the burst error investigation circuit 52 and the periodic error investigation circuit 54. In the case of decoding failure due to cause A, the on / off signal generation circuit 56 according to the sixth embodiment does not generate an on signal, but generates an off signal and does not activate the burst error investigation circuit 52 and the periodic error investigation circuit 54. The sixth embodiment reduces the opportunities for the burst error investigation circuit 52 and the periodic error investigation circuit 54 to operate compared to the first to fifth embodiments. This achieves improved operational efficiency of the error information investigation circuit 38.

[0142] Figure 29 is a diagram illustrating an example of the operation of the error information investigation circuit 38 according to the sixth embodiment. The ECC circuit 28 error-corrects and decodes the readout signal of a certain frame (referred to as the target frame) and outputs a determination signal indicating the success or failure of the decoding. The error information investigation circuit 38 determines whether the determination signal output by the ECC circuit 28 indicates success or failure (step S102). If the determination signal indicates success, the on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S104). If the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate. After step S104 is executed, step S102 is executed again.

[0143] If the judgment signal indicates failure, the burst error investigation circuit 52 and the periodic error investigation circuit 54 read data from multiple frames stored in the physical vicinity of the storage location of the target frame in the NAND flash memory 12 and attempt to decode them with the ECC circuit 28 (step S106). This is because the stress conditions are considered to be similar for frames stored in close proximity in the NAND flash memory 12, and therefore the state of frames in the vicinity of the target frame is investigated.

[0144] The burst error detection circuit 52 and the periodic error detection circuit 54 count the number of error bits in the frames that were successfully decoded (step S108). If multiple frames are successfully decoded, the burst error detection circuit 52 and the periodic error detection circuit 54 count the number of error bits in each of the multiple frames that were successfully decoded and calculate the average value of the number of error bits in the multiple frames.

[0145] The burst error investigation circuit 52 and the periodic error investigation circuit 54 determine whether the number of error bits or their average value is near the code correction limit or significantly below the correction limit (step S110). Since the NAND flash memory 12 is under strong stress in the vicinity of the target frame, if the number of error bits or their average value is near the code correction limit, it is considered that the cause of the decoding failure of the target frame is cause A.

[0146] If the number of error bits or their average value is near the code correction limit, the on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58 (step S112). When the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate. After step S112 is performed, step S102 is performed again.

[0147] If the number of error bits or their average value is significantly below the code correction limit, it is unlikely that a strong stress, as in cause A, is being applied only to the target frame, and the cause of the decoding failure of the target frame is likely cause B. Therefore, in this case, the on / off signal generation circuit 56 generates an on signal and turns on the internal state flag 58 (step S114). When the internal state flag 58 is on, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate.

[0148] The burst error investigation circuit 52 and the periodic error investigation circuit 54 rewrite the bit values ​​related to the burst interval and sequence in the read data to determine whether decoding is successful or not, and identify burst errors and periodic errors (step S116).

[0149] According to the sixth embodiment, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate according to the cause of the decoding failure, so the investigation operation is performed efficiently.

[0150] [Seventh Embodiment] Similar to the sixth embodiment, the seventh embodiment also relates to the operation of an on / off signal generation circuit 56 that determines whether or not to operate the burst error investigation circuit 52 and the periodic error investigation circuit 54. The difference between the seventh embodiment and the sixth embodiment is that the ECC circuit 28 according to the seventh embodiment uses a product code, whereas the ECC circuit 28 according to the sixth embodiment handles data corresponding to horizontal frames in the product code, similar to the first to third embodiments.

[0151] In the seventh embodiment, the horizontal frame described in the fourth embodiment is encoded by the product code regardless of the vertical frame. The product code in the seventh embodiment is configured as follows: The ECC circuit 28 first defines the internal code that constitutes the product code (corresponding to the XOR code in the vertical frame of the fourth embodiment). The ECC circuit 28 then arranges the user data to form a matrix, and then encodes each row and column with the internal code to add parity to the user data. As a result, each bit of the user data is double-encoded in the row and column directions.

[0152] The ECC circuit 28 decodes this product code by repeatedly decoding in the row direction and in the column direction. Decoding of the product code is complete when the syndrome becomes "0" in the internal codes of all rows and all columns. If there are rows or columns where the syndrome is not "0" after repeating row-direction decoding or column-direction decoding a predetermined number of times, the decoding of the product code is determined to have failed.

[0153] When attempting to decode the product code, the total number of rows and columns where the syndrome is not "0" can be determined with each iteration of decoding. For example, suppose 64-bit user data is arranged in an 8x8 grid, creating 8 internal codes in the row direction and 8 in the column direction, for a total of 16 internal codes. In the first decoding, suppose a non-zero syndrome occurs in a total of 7 internal codes in a 4x3 grid. In the next decoding, suppose a non-zero syndrome occurs in a total of 3 internal codes in a 2x1 grid. Then, in the following decoding, suppose the syndrome becomes "0" in all rows and all columns, and the product code is successfully decoded. In this case, the number of internal codes with a non-zero syndrome among the 16 internal codes in the 8x8 grid changes from 7, 3, and 0 with each iteration of decoding. The seventh embodiment focuses on this change.

[0154] If an error occurs with a number of bits exceeding the correction limit (Cause A), the number of non-zero syndromes will be larger than that of successfully decoded frames, and it is possible that they will not converge to zero within a predetermined number of attempts. On the other hand, if a burst error or periodic error occurs (Cause B), although the number of non-zero syndromes is not significantly different from that of successfully decoded frames because the number of error bits itself is relatively small, it is possible that the decrease will be slower and they will not converge to zero within a predetermined number of attempts.

[0155] The error information investigation circuit 38 investigates the progression of the number of non-zero syndromes in frames where the product code was successfully decoded, and the progression in cases where it failed, before the SSD4 is shipped, and writes the investigation results to the NAND flash memory 12. Next, if the target frame (data read from the NAND flash memory 12) fails to decode while the SSD4 is running, the error information investigation circuit 38 investigates the progression of the number of non-zero syndromes in the target frame. If the number of non-zero syndromes changes significantly from the initial timing and overlaps with the progression of other decoded failure frames, the cause of the decoded failure of the target frame is considered to be cause A. In this case, the on / off signal generation circuit 56 generates an off signal and turns off the internal state flag 58. When the internal state flag 58 is off, the burst error investigation circuit 52 and the periodic error investigation circuit 54 do not operate.

[0156] On the other hand, if the number of non-zero syndromes is not significantly different from the number of frames that were successfully decoded, the cause of the decoding failure for the target frame is considered to be cause B. In this case, the on / off signal generation circuit 56 generates an on signal and turns on the internal state flag 58. When the internal state flag 58 is on, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate.

[0157] According to the seventh embodiment, even in error correction processing using the product code, the burst error investigation circuit 52 and the periodic error investigation circuit 54 operate according to the cause of the decoding failure, so the investigation operation is performed efficiently.

[0158] (modified version) In each of the above embodiments, the ECC circuit 28 is assumed to encode / decode based on BCH codes or the like, where the unit of error generation is a bit. However, the ECC circuit 28 may also encode / decode based on Reed-Solomon codes or the like, where the unit of error generation is a symbol consisting of multiple bits.

[0159] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0160] 1…Information processing system, 2…Host, 4…SSD, 12…NAND flash memory, 16…Controller, 28…ECC circuit, 30…CPU, 32…Command reception circuit, 34…Write circuit, 36…Read circuit, 38…Error information investigation circuit, 40…Data rewriting circuit, 42…Comparison circuit

Claims

1. A decoding circuit reads user data to which an error correction code has been added from a non-volatile memory and performs error correction decoding based on the error correction code for read data of a certain size, The system comprises a rewriting circuit that rewrites some bits in the aforementioned read data of a fixed size, The aforementioned bits include M consecutive bits or multiple bits spaced at N-bit intervals. M is any natural number greater than or equal to 1, An error correction device where N is any natural number greater than or equal to 1.

2. The error correction device according to claim 1, wherein the aforementioned portion of bits includes the aforementioned M consecutive bits and a plurality of bits spaced at N-bit intervals.

3. The error correction device according to claim 1, wherein the aforementioned part of the bits includes M consecutive bits whose leading bits are spaced at an interval of N bits.

4. The error correction device according to claim 1, further comprising a comparison circuit that compares the read data of a certain size with the output signal of the decoding circuit and detects a pattern of bits that do not match.

5. The decoding circuit is, The error correction decoding is performed on each of the multiple read data of a fixed size. The exclusive OR of the same bit positions of the multiple read data of a fixed size is calculated to generate the exclusive OR data of the fixed size. The exclusive OR of the same bit positions of the multiple read data and the exclusive OR data is calculated to generate the syndrome data of a fixed size. The error correction device according to claim 1, wherein the rewriting circuit determines some of the bits according to the syndrome data.

6. The error correction device according to claim 1, wherein the error correction code includes a BCH code or a Reed-Solomon code.

7. The system further comprises a detection circuit that detects an error pattern in the read data of a fixed size by comparing it with a predetermined bit error pattern data. The error correction device according to claim 1, wherein the rewriting circuit rewrites some of the bits based on the error pattern.

8. The decoding circuit outputs a determination signal if the error correction decoding fails. The detection circuit operates upon receiving the determination signal. The error correction device according to claim 7, wherein the decoding circuit performs the error correction decoding on the read data of a fixed size after rewriting.

9. The detection circuit detects the bits in the read data of a certain size that have lost their bits, The error correction device according to claim 7, wherein the rewriting circuit determines some of the bits according to the bits in which the loss error has occurred.

10. The decoding circuit outputs a determination signal if the error correction decoding fails. The error correction device according to claim 7, wherein the detection circuit operates upon receiving the determination signal.

11. The error correction device according to claim 7, further comprising a write circuit for writing information representing the error pattern detected by the detection circuit to the non-volatile memory.

12. The error correction device according to claim 11, wherein the information representing the error pattern includes information representing that multiple error bits occur consecutively or that multiple error bits occur periodically.

13. The error correction device according to claim 11, wherein the information representing the error pattern includes information representing the rewritten bits when the decoding circuit performs the error correction decoding on the read data of a fixed size after rewriting and the decoding is successful.

14. The error correction device according to claim 11, wherein the information representing the error pattern includes information representing an error pattern different from the predetermined bit error pattern data.

15. If the decoding circuit fails to perform error correction decoding, the system further comprises a determination circuit that determines whether the cause of the failure is a random error or a burst error or periodic error, and outputs a first signal indicating that the cause of the failure is a random error or a second signal indicating that the cause of the failure is a burst error or periodic error. The error correction device according to claim 7, wherein the detection circuit does not operate when it receives the first signal, and operates when it receives the second signal.

16. The decoding circuit counts the number of erroneous bits in a read data of a fixed size that was successfully decoded. The error correction device according to claim 15, wherein the determination circuit outputs the first signal when the number of error bits is near the correction limit of the decoding circuit, and outputs the second signal when the number of error bits is below the correction limit.

17. The error correction device according to claim 15, wherein the decoding circuit performs the error correction decoding based on the product code.

18. Non-volatile memory and A semiconductor memory system comprising a controller for controlling write and read operations of the non-volatile memory, The controller is a semiconductor memory system comprising an error correction device according to any one of claims 1 to 17.

19. Read user data with error correction codes added from non-volatile memory. Error correction decoding is performed on read data of a certain size based on the error correction code. An error correction method for rewriting some bits in the aforementioned read data of a fixed size, The aforementioned bits include M consecutive bits or multiple bits spaced at N-bit intervals. M is any natural number greater than or equal to 1, An error correction method where N is any natural number greater than or equal to 1.

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