RF pulses in pulses for semiconductor RF plasma processing

Abstract

This invention provides systems, apparatus, methods, and computer programs for RF pulses within pulses for semiconductor radio frequency (RF) plasma processing. [Solution] A method for generating a high-frequency (RF) waveform includes the step of defining an ON-OFF pulse train separated by an OFF state that does not have an ON-OFF pulse. The method further includes the step of generating an RF waveform by applying a multilevel pulse waveform that adjusts the magnitude of each ON-OFF pulse. The method includes the step of sending the RF waveform to an electrode.

Description

[Technical Field]

[0001] This embodiment relates to a high-frequency (RF) pulse within a pulse for semiconductor RF plasma processing. [Background technology]

[0002] Plasma systems are used to perform various operations on wafers. A plasma system comprises a radio frequency (RF) generator, an RF match, and a plasma chamber. The RF generator is connected to the RF match via an RF cable, which is connected to the plasma chamber. RF power is supplied to the plasma chamber through the RF cable and RF match, where the wafer is processed. Additionally, one or more gases are supplied to the plasma chamber, and upon receiving RF power, plasma is generated within the plasma chamber. During the supply of one or more gases and RF power, it is desirable that the plasma processing of the wafer be controlled in a desired manner.

[0003] In connection therewith, embodiments described herein arise. [Overview of the project]

[0004] Embodiments of this disclosure provide systems, apparatus, methods, and computer programs for RF pulses within pulses for semiconductor radio frequency (RF) plasma processing. It should be understood that these embodiments can be implemented in many ways, such as processes, or apparatus, or systems, or hardware, or methods, or computer-readable media. Several embodiments are described below.

[0005] Methods and apparatus are described in which, in various embodiments, simultaneous high-speed ON-OFF pulses and low-speed pulses (e.g., inter-level, multi-level, or arbitrary waveform pulses / modulations) are enabled, and the high-speed ON-OFF pulses are always incorporated into the low-speed pulses. A pulsed plasma having one or more pulse frequencies simultaneously is provided. High-speed ON-OFF pulses and low-speed pulses are performed simultaneously in a matchless plasma source.

[0006] In some embodiments, a “pulse within a pulse” is defined as a fast ON-OFF pulse incorporated into a slow pulse. The radio frequency (RF) clock itself operates continuously at the RF frequency. The fast ON-OFF pulses turn the RF clock ON and OFF at the inputs of multiple gate drivers, which may be performed by AND gates prior to the gate driver inputs. The slow pulse or modulation is performed by manipulating the rail voltage of an agile DC rail. A filter formed by an RF antenna or coil together with one or more reactants is a bandpass filter for the RF frequency, converting the square wave at the output of the bridge circuit into a sinusoidal waveform within a rotating range of the RF frequency or RF clock frequency. The RF clock frequency is adjusted during operation so that the plasma load, including the RF antenna and one or more reactants, is completely resistive to the output of the bridge circuit, with or without plasma.

[0007] Several advantages of the systems and methods described herein are provided. Fast ON-OFF pulses, when applied to a trans-coupled plasma (TCP) source or an inductively coupled plasma (ICP) source, generate a cold plasma with a low electron temperature and low plasma potential, thereby forming a small-angle ion energy distribution. This reduces or prevents charging damage in isotropic etching processes. Furthermore, fast ON-OFF pulses, when applied to a TCP or ICP source and combined with an asynchronous bias RF pulse, enable high aspect ratio etching or high aspect ratio deposition. On the other hand, inter-level, multi-level, or arbitrary waveform pulses achieve other improved process performance, such as high selectivity, high etching rate, and excellent uniformity. The methods and apparatus described herein enable simultaneous operation of both fast ON-OFF pulses and slow pulses of inter-level, multi-level, or arbitrary waveform.

[0008] Other embodiments will become apparent from the following embodiments for carrying out the invention, in conjunction with the attached drawings. [Brief explanation of the drawing]

[0009] The embodiments will be understood by referring to the following embodiments for carrying out the invention in conjunction with the attached drawings.

[0010] [Figure 1] A diagram showing an embodiment of a system for performing pulses within pulses.

[0011] [Figure 2A] An explanatory diagram showing an embodiment of a high-frequency (RF) clock signal.

[0012] [Figure 2B] An explanatory diagram showing an embodiment of an ON-OFF pulse signal having a frequency fFast pulse.

[0013] [Figure 2C]Explanatory diagram showing an embodiment of an ON-OFF pulse RF clock signal generated by performing an AND operation between the RF clock signal of FIG. 2A and the ON-OFF pulse signal of FIG. 2B.

[0014] [Figure 3A] Diagram showing an embodiment of a graph representing the transient state of the electron temperature with respect to time t in the plasma chamber when a shaped waveform is generated using the ON-OFF pulse RF clock signal.

[0015] [Figure 3B] Diagram showing an embodiment of a graph representing the plasma potential with respect to time t when a shaped waveform is generated using the ON-OFF pulse RF clock signal.

[0016] [Figure 3C] Diagram showing an embodiment of a graph representing the ion density with respect to time t when a shaped waveform is generated using the ON-OFF pulse RF clock signal.

[0017] [Figure 4A] Diagram showing an embodiment of the RF clock signal in standard display and enlarged display.

[0018] [Figure 4B] Diagram showing an embodiment of the ON-OFF pulse signal in both standard display and enlarged display.

[0019] [Figure 4C] Diagram showing an example of a multi-level pulse waveform executed in conjunction with the RF clock signal of FIG. 4A filtered by the ON-OFF pulse signal of FIG. 4B.

[0020] [Figure 4D] Diagram showing an example of an arbitrary waveform executed in conjunction with the RF clock signal of FIG. 4A filtered by the ON-OFF pulse signal of FIG. 4B.

[0021] [Figure 5A] This diagram illustrates an embodiment of the RF current in the plasma load shown in Figure 1 when the multilevel pulse waveform shown in Figure 4C is applied.

[0022] [Figure 5B] Enlarged view of the RF current waveform shown in Figure 5A.

[0023] [Figure 5C] Figure 5B is an explanatory diagram showing a sinusoidal waveform, which is an enlarged version of the RF current waveform shown.

[0024] [Figure 6] A diagram showing an embodiment of a system comprising a transcoupled plasma (TCP) source having RF pulses within pulses and RF bias by RF pulses within pulses.

[0025] [Figure 7] The figure shows examples of RF current waveforms for TCP sources and RF bias when the ON-OFF pulses between TCP and bias are in different phases or asynchronous, as well as for simultaneous ON-OFF asynchronous TCP bias pulses, multi-level TCP pulses, and arbitrary waveform bias pulses.

[0026] [Figure 8A] A diagram illustrating an embodiment of a graph representing an ON-OFF pulse RF clock signal shaped according to inter-level pulses.

[0027] [Figure 8B] A diagram illustrating an embodiment of a graph representing an ON-OFF pulse RF clock signal shaped according to a multilevel pulse.

[0028] [Figure 8C] A diagram illustrating an embodiment of a graph representing an ON-OFF pulse RF clock signal shaped according to an arbitrary waveform.

[0029] [Figure 9]A flowchart illustrating an embodiment of a method for generating pulses within a pulsed signal using a matchless RF source.

[0030] [Figure 10A] A diagram representing pulses within pulses.

[0031] [Figure 10B] A diagram showing the square wave voltage at the output of a bridge circuit.

[0032] [Figure 10C] A diagram showing the RF current output from a bridge circuit and supplied to an antenna or plasma load. [Modes for carrying out the invention]

[0033] The following embodiments describe radio frequency (RF) pulses within pulses for semiconductor RF plasma processing. It will be apparent that these embodiments may be carried out without some or all of these specific details. In other examples, well-known process behaviors are not described in detail so as not to unnecessarily obscure these embodiments.

[0034] A high-frequency (RF) clock signal generator is provided in addition to a high-speed ON-OFF pulse frequency signal generator. A waveform generator is also provided to generate a shaped waveform. The RF clock signal generated by the RF clock signal generator is filtered using the pulse signal generated by the high-speed ON-OFF pulse frequency signal generator to output a filtered signal. The filtered signal is supplied to a gate driver to output multiple square wave signals. The square wave signals are supplied to an amplification circuit to generate an amplified square wave signal. The amplified waveform signal is then shaped using the filtered waveform. The filtered waveform is generated by filtering a direct current (DC) voltage using the shaped waveform. The shaped waveform may be an arbitrary-shaped waveform, a multilevel waveform, or an interlevel waveform. Shaping the amplified square wave signal generates a shaped waveform. The higher harmonics of the shaped waveform are filtered by a reactance circuit to output the RF power supplied to the electrodes for processing the wafer.

[0035] Figure 1 shows an embodiment of system 100 for performing a process described herein as “pulse within pulse.” In one embodiment, system 100 includes a controller, a radio frequency (RF) clock 104, a fast ON-OFF pulse frequency signal generator 106, a slow pulse frequency signal generator 108, an AND gate 110, a gate driver 112, a half-bridge circuit 114, and a DC power supply V DC The system includes a matchless dielectric-coupled plasma (ICP) source 102, which includes a DC rail 116 for applying a DC voltage from a DC rail 116, a reactance circuit 118, and another AND gate 122. There is no impedance matching circuit and associated RF cable connected between the matchless ICP source 102 and the plasma load 120. The AND gate, as used herein, sometimes means a filter. The AND gate 122 is connected to the drain terminal D of a field-effect transistor (FET) 144A of a half-bridge circuit 114. The source terminal S of FET 144A is connected to the drain terminal D of another FET 144B of the half-bridge circuit 114, and the source terminal of FET 144B is connected to ground potential.

[0036] An example of a reactance circuit 118 is a variable capacitor connected to a plasma load 120 having electrodes 124 (e.g., an RF antenna or RF coil). The RF frequency clock 104 comprises an oscillator circuit that generates an RF clock signal 134 which is a digital signal or a square wave signal having a high frequency. The fast ON-OFF pulse frequency signal generator 106 generates a fast ON-OFF pulse frequency f such as a digital signal or a square wave signal. Fast pulsing It includes an oscillation circuit that generates an ON-OFF pulse signal 136 having a high-speed ON-OFF pulse frequency f. Fast pulsing This is determined based on the dynamics of the plasma characteristics during the transient state from RF power ON to RF power OFF. The ON-OFF pulse is realized using an AND gate 110 that performs an AND operation as input between the RF clock signal 134 and the ON-OFF pulse signal 136. The AND operation is an example of filtering operation. The AND gate 110 outputs the ON-OFF pulse RF clock signal 126.

[0037] The gate driver 112 receives an ON-OFF pulse RF clock signal 126 and outputs multiple square wave signals 128A and 128B. Gate G1 of the gate driver 112 receives the ON-OFF pulse RF clock signal 126 and either amplifies the magnitude of the ON-OFF pulse RF clock signal 126 to output a square wave signal 128A or not. If no amplification is performed, the ON-OFF pulse RF clock signal 126 passes through gate G1. Another gate G2 of the gate driver 112 receives the ON-OFF pulse RF clock signal 126 and inverts it to output an inverted square wave signal 128B. The square wave signals 128A and 128B are each digital signals or pulse signals. For example, the square wave signals 128A and 128B each transition between low and high levels. The square wave signals 128A and 128B are synchronized in opposite directions. For example, the square wave signal 128A transitions from a low power level to a high power level. During the time interval or period in which the square wave signal 128A transitions from a low power level to a high power level, the square wave signal 128B transitions from a high power level to a low power level. Reverse synchronization allows the FETs 144A and 144B of the half-bridge circuit 114 to be turned on and off sequentially. In this specification, the half-bridge circuit 114 sometimes means an amplifier circuit.

[0038] The agile DC rail 116 and the half-bridge circuit 114 generate an amplified square waveform from the square wave signals 128A and 128B. To generate the amplified square waveform, FETs 144A and FET 144B are operated sequentially. For example, FET 144B is off during the period or time when FET 144A is on, and FET 144A is off during the period or time when FET 144B is on. FETs 144A and FET 144B are not turned on simultaneously or for the same period of time.

[0039] When FET144A is ON, the current is supplied by the DC voltage source V DCCurrent flows from the half-bridge circuit 114 to output O1, generating a voltage at output O1 and turning off FET 144B. The voltage at output O1 is generated according to the voltage value received from the pulse frequency signal generator 108, which includes an oscillator circuit and, in this specification, means a waveform generator. When FET 144B is off, no current flows from output O1 to the ground potential connected to FET 144B. Current flows from output O1 to the reactance circuit 118. When FET 144B is on, current flows through the DC voltage source V DC It is pushed out into the capacitor reactance circuit 118. Also, when FET 144B is on and FET 144A is off, the voltage generated at output O1 generates a current that flows from output O1 to the ground potential connected to FET 144B. The current is drawn out from output O1 by the ground potential. During the time interval when FET 144A is off, the DC voltage source V DC There is no current flowing from there to output O1.

[0040] Furthermore, the low-speed pulse frequency signal generator 108 generates a shaped waveform 138 having an envelope with an arbitrary shape, a multi-level pulse shape, or an inter-level pulse shape. The low-speed pulse frequency of the low-speed pulse frequency signal generator 108, or the low-speed pulse frequency of the shaped waveform 138, is f Slow pulsing This is represented as follows: Inter-level pulse shapes transition periodically between low-power levels and high-power levels. Multi-level pulse shapes transition periodically between three or more power levels. Arbitrary shapes have any shape and repeat periodically. Controller 142 controls the slow pulse frequency signal generator 108 to generate a shaped waveform 138. Controller 142 provides the slow pulse frequency signal generator 108 with the shape of the shaped waveform 138. The slow pulse frequency signal generator 108 generates a shaped waveform 138 having the shape received from Controller 142. The shape of the waveform is the shape of the waveform envelope. Examples of envelopes include peak-to-peak magnitude or zero-to-peak magnitude.

[0041] AND gates such as AND gate 122 are connected to a DC voltage source V DCThe DC voltage provided by is filtered by a shaped waveform 138 to generate a filtered waveform 140 having an amplitude shaped according to the shaped waveform 138. The filtered waveform 140 is applied to an amplified square wave at the output O1 of the half-bridge circuit 114 to shape the amplified square wave (increase or decrease its envelope) to generate a shaped waveform 130 at output O1. The shaped waveform 130 is a digital waveform or a square waveform. The envelope of the amplified square waveform is shaped or adjusted by modifying the zero-to-peak amplitude or peak-to-peak amplitude of the amplified square waveform. Examples of shaped waveforms 130 include level-to-level shaped waveforms, multi-level shaped waveforms, or arbitrary shaped waveforms, and the shape of the shaped waveform 130 matches the shape of the filtered waveform 140. The shape of the envelope of the shaped waveform 130 matches the shape of the envelope of the filtered waveform 140.

[0042] The reactance circuit 118 filters out or removes higher harmonics from the shaped waveform 130 to output or extract a shaped sinusoidal waveform 132 having RF power, which is supplied to the electrodes 124 of the plasma load 120 to generate or maintain plasma in a plasma chamber for processing a substrate. The magnitude of the shaped waveform 130 is a combination of the magnitudes of several waveforms, one of which has the fundamental frequency and the rest have higher harmonics. By filtering out the higher harmonics, a shaped sinusoidal waveform 132 having the fundamental frequency is output. The shaped sinusoidal waveform 132 has an envelope shape that matches the shape of the envelope of the shaped waveform 130. The plasma chamber comprises a plasma load 120. Examples of substrate processing include steps of depositing material on the substrate, etching the substrate, cleaning the substrate, and sputtering the substrate. The shape of the shaped sinusoidal waveform 132 is defined by the shape of the filtered waveform 140. For example, the envelope of the shaped sinusoidal waveform 132 has the same shape as the envelope of the filtered waveform 140.

[0043] In some embodiments, "pulse within a pulse" is defined as a high-speed pulse incorporated within a low-speed pulse. The RF clock generator 104 operates continuously at an RF frequency. In some embodiments, "high-speed pulse" is to turn on and off the RF clock signal 134 at the input of the gate driver 112, and turning on and off may be performed by the AND gate 110 before the input of the gate driver 112. The low-speed pulse or modulation is performed by manipulating the rail voltage, which is the DC voltage provided by the DC voltage source V DC The filter formed by the RF plasma antenna or coil together with one or more reactance elements (e.g., reactance element 118) is a band-pass filter for the RF frequency that transitions the square wave at the bridge output to a sine waveform within the tuning range of the RF frequency or the RF clock frequency. The RF clock frequency is adjusted during operation such that the plasma load 120 and one or more reactance elements are completely resistive at the output O1 of the half-bridge circuit 114 regardless of the presence or absence of plasma.

[0044] In one embodiment, instead of the electrode 124, another electrode such as a lower electrode or plate embedded in the substrate support is used, and the RF power of the shaped sine waveform 132 is supplied to the other electrode. Examples of the substrate support include a chuck.

[0045] In one embodiment, p-type FETs are used instead of the n-type FETs 144A and 144B.

[0046] Figure 2A shows an embodiment of the RF clock signal 134. The RF clock signal 134 has a higher frequency than the ON-OFF pulse signal 136 shown in Figure 2B. For example, multiple pulses of the RF clock signal 134 are generated during the period in which one pulse of the ON-OFF pulse signal 136 is generated. The RF clock signal 134 includes multiple instances 212A, 212B, and 212B in the ON state, and multiple instances 214A and 214B in the OFF state. Instance 214A follows instance 212A, instance 212B follows instance 214A, instance 214B follows instance 212B, and instance 212C follows instance 214B.

[0047] Figure 2B shows the frequency f Fast pulsing This represents an embodiment of an ON-OFF pulse signal 136 having a frequency lower than that of the RF clock signal 134. For example, the on-time of the pulses in the ON-OFF pulse signal 136 is longer than the on-time of the pulses in the RF clock signal 134. As another example, the off-time of the pulses in the ON-OFF pulse signal 136 is longer than the off-time of the pulses in the RF clock signal 134. The ON-OFF pulse signal 136 has multiple instances 210A, 210B, and 210C in the ON state, as well as multiple instances 208A and 208B in the OFF state. The instances in the ON state and the instances in the OFF state repeat periodically. As shown in Figure 2B, instance 210A is followed by instance 208A. Instance 208A is followed by instance 210B, and instance 210B is followed by instance 208B. Instance 208B is followed by instance 210C.

[0048] Figure 2C illustrates an embodiment of an ON-OFF pulsed RF clock generated by performing an AND operation. As shown in Figure 2C, pulses of RF clock signal 134 between two adjacent ON pulses of ON-OFF pulsed signal 136 are filtered out by AND gate 110 to generate ON-OFF pulsed RF clock signal 126. ON-OFF pulsed RF clock signal 126 includes pulse trains T1, T2, and T3 of RF clock signal 134. Train T1 occurs during ON state instance 210A, train T2 occurs during ON state instance 210B, and train T2 occurs during ON state instance 210C. Train T1 is separated from train T2 by OFF state instance 208A, and train T2 is separated from train T3 by OFF state instance 208B. Between each of instance 208A and instance 208B, the ON-OFF pulse RF clock signal 126 removes the ON-OFF pulse of the RF clock signal 134. The ON-OFF pulse RF clock signal 126 between each of instance 208A and instance 208B is filtered out by the AND gate 110 in Figure 1.

[0049] Figure 3A is an embodiment of a graph representing the transient state of the electron temperature kTe in the plasma chamber with respect to time t when the shaped waveform 130 in Figure 1 is generated using the ON-OFF pulse RF clock signal 126. The electron temperature transitions from a high state to a low state when RF power is supplied to the plasma load 120.

[0050] Figure 3B is an embodiment of a graph representing the plasma potential Vp in the plasma chamber as a function of time t, when the shaped waveform 130 is generated using the ON-OFF pulse RF clock signal 126. The plasma potential Vp transitions from a high state to a low state when RF power is supplied to the plasma load 120.

[0051] Figure 3C is an embodiment of a graph showing the ion density Ni in the plasma chamber as a function of time t when the shaped waveform 130 is generated using the ON-OFF pulse RF clock signal 126. Time t in each of Figures 3A to 3C is measured in microseconds. As shown in Figures 3A and 3C, it takes approximately 10 microseconds for the electron temperature to transition from a high level to a low level during the OFF time, while the ion density remains at approximately 80%. Therefore, the fast ON-OFF pulse frequency f Fast pulsing The frequency range is approximately 1 kilohertz (kHz) to 1 megahertz (MHz), and may be 25 kHz or higher.

[0052] In some embodiments, the plasma chamber described herein is a conductor etching chamber used to process 300 mm wafers. This is just one example. In various embodiments, the plasma chamber described herein is a chamber used to process wafers of other sizes. For example, the plasma chamber may be used to process 200 mm wafers, or 450 mm wafers, or wafers of other sizes.

[0053] The angular ion energy rapidly reaches a minimum as a function of electron temperature during the OFF time of the ON-OFF pulse signal 136. When the bias RF is pulsed asynchronously with the TCP ON-OFF pulse, the ions accelerated by the bias RF during the TCP OFF time have high directivity to the wafer, resulting in a desirable vertical profile for etching or a desirable bottom-up deposition for gap filling. This is how high aspect ratio etching is performed to achieve an aspect ratio of up to approximately 150 in deep silicon etching (DSE) processes. However, when the bias RF operates as a multilevel pulse asynchronously with the TCP ON-OFF pulse, the frequency of the multilevel pulse is a frequency f from approximately 10 Hz to 1 kHz. Slow pulsingThe etching rate is limited by the speed at which the DC rail 116 moves within the range. The speed at which the DC rail 116 moves is the speed at which FETs 144A and FET 144B in Figure 1 are turned on and off. If the TCP ON-OFF pulses operate at a low pulse frequency, or if the ON-OFF pulse signal 136 has a long OFF time, the etching rate is limited by the low average ion density during the OFF time. To take full advantage of the benefits of ON-OFF pulses, and multi-level pulses, or arbitrary waveform pulses, or inter-level pulses, a fast ON-OFF pulse frequency f Fast pulsing This is a low-speed pulse frequency f Slow pulsing It is incorporated into slow multilevel pulses, arbitrary waveform pulses, or interlevel pulses having the same frequency f. In process applications where bias RF power is used, the fast ON-OFF pulses of the bias RF are incorporated into the same frequency f. Fast pulsing The high-speed ON-OFF pulses of the TCP source are asynchronous or out of phase. While the ON-OFF pulses always operate asynchronously between TCP and the bias, the multi-level pulses or arbitrary waveform pulses of the TCP source and the bias RF flow independently of each other at their slower pulse frequencies.

[0054] Figure 4A shows embodiments of the RF clock signal 134 in both standard and enlarged views. The RF clock signal 134 flows at a high frequency, such as a high frequency, between high and low levels.

[0055] Figure 4B shows embodiments of the ON-OFF pulse signal 136 in both standard and enlarged views. The ON-OFF pulse signal 136 flows between high and low levels at a lower frequency than the RF clock signal 134, and the frequency of the ON-OFF pulse signal 136 is used to filter the RF clock signal 134.

[0056] Figure 4C shows an example of a slow pulse waveform, such as a multilevel pulse waveform 410A, which is executed simultaneously with the RF clock signal 134 in Figure 4A and the ON-OFF pulse signal 136 in Figure 4B. The multilevel pulse waveform 410A has a multilevel shaping envelope 412A, which is an example of a shaping waveform 138 in Figure 1. The multilevel shaping envelope 412A is multilevel pulse shaping, and a DC voltage source V DC The DC voltage has multiple power levels (e.g., PWR1, PWR2, PWR3, and PWR4). The multiple power levels are repeated periodically. The multilevel shaping envelope 412A is connected to the DC voltage source V DC When applied to the DC voltage, the filtered waveform 140 having a multilevel shaping envelope 412A is output from the AND gate 122 in Figure 1.

[0057] In one embodiment, instead of the four power levels PWR1 to PWR4, another multilevel pulse waveform is used which has power levels greater than or less than those four power levels, and these power levels greater than or less than those four power levels are repeated periodically.

[0058] Figure 4D shows an example of another slow pulse waveform, such as arbitrary waveform 410B, which is executed simultaneously with the RF clock signal 134 in Figure 4A and the ON-OFF pulse signal 136 in Figure 4B. Arbitrary waveform 410B has an arbitrary-shaped envelope 412B and is another example of the shaped waveform 138 in Figure 1. The arbitrary-shaped envelope 412B is connected to a DC voltage source V DC The envelope 412B has different sizes for application to the DC voltage. DC When applied to the DC voltage, a filtered waveform 140 having an arbitrary-shaped envelope 412B is generated by the AND gate 122 in Figure 1.

[0059] Figure 5A shows an embodiment of the RF current waveform 501 in the plasma load 120 of Figure 1 when the multilevel pulse waveform 410A of Figure 4C is applied. The section labeled A in Figure 5A has multiple parts 502, 504, 506, 508, 510, 512, 514, 516, 518, and 520 of the RF current waveform 501. The RF current waveform 501 is generated in the plasma load 120 and is typical of the shaped sinusoidal waveform 132 of Figure 1.

[0060] Figure 5B shows a magnified view of the RF current waveform 501 shown in Figure 5A. Section A in Figure 5A is shown in detail in Figure 5B. For example, sections 502, 504, 506, 508, 510, 512, 514, 516, 518, and 520 are all clearly shown in detail in Figure 5B. Sections 502, 504, 506, 508, 510, 512, 514, 516, 518, and 520 are each sinusoidal RF signals represented in Figure 5C.

[0061] Furthermore, Figure 5C shows a sinusoidal waveform, which is an enlargement of the RF current waveform 501 shown in Figure 5B. Figure 5C is an enlargement of the section labeled B in Figure 5B. As shown in Figure 5C, sections 510 and 512 are sinusoidal signals, respectively.

[0062] Figure 6 shows an embodiment of system 600, which includes a composite TCP source and RF bias by RF pulses within the pulse. System 600 includes the matchless ICP source 102 shown in Figure 1. System 600 further includes a NOT gate 623 such as an inverter and a matchless bias source 602. The matchless bias source 602 includes a controller 142, an RF frequency clock 604, a fast ON-OFF pulse frequency signal generator 106, an AND gate 610, a slow pulse frequency signal generator 608, a gate driver 612, a half-bridge circuit 614, and another DC voltage source V DCThe system includes a DC rail 616 to which a DC voltage is applied, a reactance circuit 618, and an AND gate 622. An example of the reactance circuit 618 is an inductor connected to a plasma load 620. Electrode 124 is a coil or antenna of the plasma chamber, and bias electrode 638 is a lower electrode embedded in the substrate support of the plasma chamber.

[0063] The RF clock 604 has the same structure and function as the RF clock 104. Similarly, the gate driver 612 has the same structure and function as the gate driver 112, and the agile DC rail 616 has the same structure and function as the agile DC rail 116. Likewise, the slow pulse frequency signal generator 608 has the same structure and function as the slow pulse frequency signal generator 108. However, the slow pulse frequency signal generator 608 operates independently of the slow pulse frequency signal generator 108. For example, the slow pulse frequency signal generator 608 generates arbitrary-shaped waveforms, while the slow pulse frequency signal generator 108 generates multi-level shaped waveforms.

[0064] The RF clock 604 generates the RF clock signal 622. The NOT gate 623 inverts the ON-OFF pulse signal 136 and outputs an inverted ON-OFF pulse signal 624. For example, during time intervals when the ON-OFF pulse signal 136 is in the ON state, the inverted ON-OFF pulse signal 624 is in the OFF state, and during time intervals when the ON-OFF pulse signal 136 is in the OFF state, the inverted ON-OFF pulse signal 624 is in the ON state.

[0065] The AND gate 610 filters the RF clock signal 622 using the inverted ON-OFF pulse signal 624 to output an ON-OFF pulse RF clock signal 626. During the period when the ON-OFF pulse RF clock signal 126 is ON or at a high power level, the ON-OFF pulse RF clock signal 626 is OFF or at a low power level, and during the period when the ON-OFF pulse RF clock signal 126 is OFF or at a low power level, the ON-OFF pulse RF clock signal 626 is ON or at a high power level. Multiple instances of the ON state of the ON-OFF pulse RF clock signal 626 have an ON-OFF pulse train of RF clock signal 622 that does not have pulses of RF clock signal 622 during multiple instances of the OFF state of the ON-OFF pulse RF clock signal 626.

[0066] Gate G3 of gate driver 612 receives the ON-OFF pulse RF clock signal 626 and either amplifies or does not amplify the ON-OFF pulse RF clock signal 626 to output the square wave signal 628A. When the ON-OFF pulse RF clock signal 626 is not amplified, it passes through gate G3 and is output as the square wave signal 628A. Gate G4 of gate driver 612 also receives the ON-OFF pulse RF clock signal 626 and inverts it to output the square wave signal 628B. The square wave signal 628B is inverted and synchronized with the square wave signal 628A.

[0067] Just as the half-bridge circuit 114 generates an amplified square waveform, the half-bridge circuit 614 receives square wave signals 628A and 628B and generates an amplified square waveform from them. The slow pulse frequency signal generator 608 also generates a shaped waveform 630 having an envelope with an arbitrary shape, or a multi-level pulse shape, or an inter-level pulse shape. The controller 142 controls the slow pulse frequency signal generator 608 to generate the shaped waveform 630. The controller 142 provides the slow pulse frequency signal generator 608 with the shape of the shaped waveform 630. The shape of the shaped waveform 630 may be different from or the same as the shape of the shaped waveform 138. The slow pulse frequency signal generator 608 generates a shaped waveform 630 having the shape received from the controller 142.

[0068] AND gates such as AND gate 622 are connected to the DC voltage source V of matchless bias source 602. DC The DC voltage provided by is filtered by the shaped waveform 630 to generate a filtered waveform 632 having an amplitude shaped according to the shaped waveform 630. The filtered waveform 632 has an envelope with the same shape as the envelope shape of the shaped waveform 630. The filtered waveform 632 is applied to the amplified square waveform at the output O2 of the half-bridge circuit 614 to shape the amplified square waveform of the matchless bias source 602 (by increasing or decreasing its envelope, etc.) to generate a shaped waveform 634 at the output O2. The shaped waveform 634 is a digital waveform or a square waveform. The envelope of the amplified square waveform generated in the matchless bias source 602 is adjusted by modulating the zero-peak amplitude or the peak-to-peak amplitude of the amplified square waveform. Examples of shaped waveform 634 include inter-level shaped waveforms, or multi-level shaped waveforms, or arbitrary shaped waveforms, the shape of the shaped waveform 634 matches the shape of the filtered waveform 632. The shape of the envelope of the shaped waveform 634 matches the shape of the envelope of the filtered waveform 632.

[0069] The reactance circuit 618 filters out or removes higher-order harmonics from the shaped waveform 634 to output or extract a shaped sinusoidal waveform 636 with RF power. The RF power of the shaped sinusoidal waveform 636 is supplied to the bias electrode 638 of the plasma load 620 to generate or maintain plasma in the plasma chamber, so that a substrate supported on the substrate support of the plasma chamber is processed. The magnitude of the shaped waveform 634 is a combination of the magnitudes of multiple waveforms, one of which has the fundamental frequency and the rest have higher-order harmonics. By filtering out the higher-order harmonics, a shaped sinusoidal waveform 636 with the fundamental frequency is output. The shaped sinusoidal waveform 636 has an envelope whose shape matches the shape of the envelope of the shaped waveform 634. The shape of the shaped sinusoidal waveform 636 is defined by the shape of the filtered waveform 632. For example, the envelope of the shaped sinusoidal waveform 636 has the same shape as the envelope of the filtered waveform 632.

[0070] The matchless ICP source 102 supplies a shaped sinusoidal waveform 132 having RF pulses within its pulses to the plasma load 120 of the plasma chamber, and the matchless bias source 602 supplies a shaped sinusoidal waveform 636 having RF pulses within its pulses to the plasma load 620 of the plasma chamber. The shaped sinusoidal waveform 636 is inverted and synchronized with respect to the shaped sinusoidal waveform 132. For example, when or during a period when the shaped sinusoidal waveform 132 has a high power level, the shaped sinusoidal waveform 636 has a low power level, and when or during a period when the shaped sinusoidal waveform 132 has a low power level, the shaped sinusoidal waveform 636 has a high power level.

[0071] In various embodiments, one or more capacitors are used as the reactance circuit instead of an inductor.

[0072] In one embodiment, instead of the NOT gate 623, a phase shifter is used to change the phase of the ON-OFF pulse signal 136 and output an ON-OFF pulse signal that is supplied to the AND gate 610.

[0073] Figure 7 shows examples of RF current waveforms 501 and 704 of a TCP source having simultaneously ON-OFF asynchronous TCP bias pulses, multi-level TCP pulses, and arbitrary-shape bias pulses, where the ON-OFF pulses between TCP and bias are in different phases or asynchronous. For example, a slow pulse frequency signal generator 108 generates a multi-level pulse-shaped waveform to provide the RF current waveform 501 to a plasma load 120, and a slow pulse frequency signal generator 608 generates an arbitrary-shape-shaped waveform to provide the RF current waveform 704 to a plasma load 620.

[0074] In some embodiments, the ON-OFF pulses between TCP and the bias are in phase.

[0075] Figure 8A is an embodiment diagram of a graph representing a shaped waveform 802 applied to a plasma load, such as plasma load 120 or plasma load 620 in Figure 6. The shaped waveform 802 is an example of shaped waveform 130 generated at output O1 of half-bridge circuit 114 in Figure 6, or an example of shaped waveform 634 generated at output O2 of half-bridge circuit 614 in Figure 6. The graph in Figure 8A plots the magnitude or amplitude of the shaped waveform 802 over time t. The shaped waveform 802 is generated based on the RF clock signal 134 and the shaped waveform 804. The shaped waveform 804 is an example of shaped waveform 138 generated by the slow pulse frequency signal generator 108, or an example of shaped waveform generated by the slow pulse frequency signal generator 608 in Figure 6. The shaped waveform 802 is generated when a low-speed pulse frequency signal generator, such as the low-speed pulse frequency signal generator 108 or the low-speed pulse frequency signal generator 608, applies inter-level pulses to the RF clock signal 134. The shaped waveform 802 periodically transitions between low-power levels and high-power levels.

[0076] Figure 8B is an embodiment diagram of a graph representing a shaped waveform 810 applied to the plasma load 120 or plasma load 620 in Figure 6. The shaped waveform 810 is another example of the shaped waveform 130 generated at the output O1 of the half-bridge circuit 114 in Figure 6, or another example of the shaped waveform 634 generated at the output O2 of the half-bridge circuit 614 in Figure 6. The graph in Figure 8B depicts the magnitude of the shaped waveform 810 over time t. The shaped waveform 810 is generated based on the RF clock signal 134 and the shaped waveform 812, and is an example of the shaped waveform 138 generated by the slow pulse frequency signal generator 108, or an example of the shaped waveform generated by the slow pulse frequency signal generator 608 in Figure 6. The shaped waveform 810 is generated when the slow pulse frequency signal generator 108 or the slow pulse frequency signal generator 608 applies multilevel pulses to the RF clock signal 134.

[0077] Figure 8C is a diagram illustrating a graph of a shaped waveform 820 supplied to the plasma load 120 or plasma load 620 in Figure 6. The shaped waveform 820 is yet another example of the shaped waveform 130 generated at the output O1 of the half-bridge circuit 114 in Figure 6, or yet another example of the shaped waveform 634 generated at the output O2 of the half-bridge circuit 614 in Figure 6. The graph in Figure 8C plots the magnitude of the shaped waveform 820 as a function of time t. The shaped waveform 820 is generated based on the RF clock signal 134 and the shaped waveform 822, and is an example of the shaped waveform 138 generated by the slow pulse frequency signal generator 108, or an example of the shaped waveform generated by the slow pulse frequency signal generator 608 in Figure 6. The shaped waveform 820 is generated when the slow pulse frequency signal generator 108 or the slow pulse frequency signal generator 608 applies an arbitrary-shaped pulse to the RF clock signal 134.

[0078] Figure 9 is a flowchart of an embodiment of Method 900 representing the generation of an RF waveform applied to a plasma load, such as plasma load 120 or plasma load 620 in Figure 6. Method 900 includes operation 902 defining an ON-OFF pulse RF clock, such as ON-OFF pulse RF clock 126 or ON-OFF pulse RF clock 626 in Figure 6. The ON-OFF pulse RF clock has an ON-OFF pulse train separated by an OFF state that does not have an ON-OFF pulse. Method 900 further includes operation 902 applying a shaped waveform, such as shaped waveform 138 or shaped waveform 630 (Figure 6), which adjusts the magnitude of the ON-OFF pulse RF clock to generate a shaped sine waveform. The shaped sine waveform may be shaped sine waveform 132 or shaped sine waveform 636 shown in Figure 6. Method 900 includes operation 904 sending the shaped sine waveform to the electrodes of the plasma load, such as plasma load 120 or plasma load 620 in Figure 6.

[0079] Figure 10A is an embodiment diagram of graph 1000, which plots a slow pulse signal 1006 with respect to time t, a fast pulse signal 1008 with respect to time t, and an RF clock signal 134 with respect to time t. The slow pulse signal 1006 is an example of the shaped waveform 138 or shaped waveform 630 in Figure 6, and the fast pulse signal 1008 is an example of the ON-OFF pulse signal 136 in Figure 6. Figure 10A shows the multi-level pulses of the slow pulse signal 1006 along with simultaneous fast ON-OFF pulses.

[0080] Figure 10B is an embodiment diagram of graph 1002 plotting the square wave voltage 1012 at the output O1 of the half-bridge circuit 114 in Figure 1 as time t. The square wave voltage 1012 is an example of a shaped waveform 130 provided at output O1.

[0081] Figure 10C is an embodiment diagram of graph 1004, which plots the sinusoidal RF current 1014 output from the half-bridge circuit 114 in Figure 1. The RF current 1014 is supplied to the electrode 124 in Figure 1, or to the plasma load 120 in Figure 1. The RF current 1014 is an example of the shaped sinusoidal waveform 132 in Figure 1.

[0082] The embodiments described herein may be implemented by a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, and mainframe computers. The embodiments described herein may also be implemented in a distributed computing environment in which tasks are performed by remote processing hardware units connected via a computer network.

[0083] In some embodiments, a controller, such as a host computer, may be part of a system that may be part of the examples described above. The system comprises a semiconductor processing apparatus including processing tools, chambers, processing platforms, and / or specific processing components (such as wafer pedestals and gas flow systems). The system is integrated with electronics for controlling its operation before, during, and after processing of semiconductor wafers or substrates. Electronics means “controllers” that can control various components or sub-components of the system. Depending on the processing conditions and / or the type of system, the controller is programmed to control the processes disclosed herein, including the supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position operation settings, tools and other transport tools connected to or attached to the system, and / or wafer transport to a load lock.

[0084] Generally, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include firmware-type chips that store program instructions, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) and define operating parameters for executing a process on or for a semiconductor wafer. In some embodiments, operating parameters are part of a recipe defined by a process engineer to realize one or more processing steps during the manufacturing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0085] In some embodiments, the controller is part of a computer that is integrated into or connected to the system, or otherwise networked to the system, or a combination thereof, or connected to such a computer. For example, the controller resides in the “cloud” or is all or part of a fab host computer system, enabling remote access to wafer processing. The controller enables remote access to the system to monitor the progress of manufacturing operations, review the history of past manufacturing operations, investigate trends or performance benchmarks from multiple manufacturing operations, modify parameters of the current process, set up subsequent processing steps for the current process, or start a new process.

[0086] In some examples, a remote computer (e.g., a server) provides a process recipe to the system via a computer network, including a local network or the Internet. The remote computer includes a user interface that enables the entry or programming of parameters and / or settings to be transmitted from the remote computer to the system. In some examples, a controller receives instructions in the form of settings for processing a wafer. It should be understood that these settings are specific to the type of process performed on the wafer and the type of tools the controller connects to or controls. Thus, as described above, the controllers may be distributed, for example, by including one or more individual controllers networked together and cooperating toward a common purpose, such as executing the processes described herein. An example of controllers distributed for such a purpose includes one or more integrated circuits on a chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperate to control the process in the chamber.

[0087] Rather than being limiting, in various embodiments the system may include plasma etching chambers, deposition chambers, spin rinse chambers, metal plating chambers, clean chambers, bevel edge etching chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etching (ALE) chambers, ion implantation chambers, and other semiconductor processing chambers associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0088] While the above-described operation is explained with reference to a trans-coupled plasma (TCP) reactor, it should be further noted that in some embodiments, the above-described operation applies to other types of plasma chambers (e.g., conductor tools, dielectric etching chambers, ion implantation chambers, chambers with showerheads, etc.).

[0089] As described above, depending on the process steps performed by the tool, the controller communicates with one or more of the following: other tool circuits or tool modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools installed throughout the factory, the main computer, another controller, or tools used for material handling to load and unload wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing plant.

[0090] Based on the embodiments described above, it should be understood that some embodiments employ various computer operations, including data stored in a computer system. These computer operations manipulate physical quantities.

[0091] Some embodiments also relate to hardware units or devices for performing these operations. These devices are specifically designed for dedicated computers. When defined as a dedicated computer, a computer has the capability to operate for a particular purpose, but also performs other processes, program executions, or routines that are not part of that particular purpose.

[0092] In some embodiments, the operations described herein are performed by a selectively operated computer, or by one or more computer programs stored in computer memory, or are obtained through a computer network. When data is obtained through a computer network, the data may be processed by other computers on the computer network, such as many computing resources.

[0093] One or more embodiments described herein may also be created as computer-readable code for non-temporary computer-readable media. Non-temporary computer-readable media are data storage hardware units such as memory devices that store data to be later read into a computer system. Examples of non-temporary computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), writable CD (CD-R), rewritable CD (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, non-temporary computer-readable media include computer-readable tangible media distributed through a network-attached computer system so that computer-readable code is distributed and stored or executed.

[0094] While some of the method operations described above have been presented in a specific order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, or the method operations may be arranged to occur at slightly different times, or distributed in a system that allows for the occurrence of method operations at various intervals, or to be performed in a different order than described above.

[0095] It should be further noted that in one embodiment, one or more features of the above embodiment may be combined with one or more features of other embodiments without departing from the scope described in the various embodiments described herein.

[0096] While the embodiments described above have been explained in some detail for clear understanding, it will be apparent that certain changes and modifications can be made within the scope of the appended claims. Therefore, these embodiments are considered illustrative rather than restrictive, and the embodiments are not limited to the details described herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. A method for generating a shaped sinusoidal waveform, A step of defining an ON-OFF pulsed high-frequency (RF) clock, wherein the ON-OFF pulsed RF clock has an ON-OFF pulse train separated by an OFF state that does not have an ON-OFF pulse; A step of generating a shaped sine wave by applying a shaped waveform to adjust the magnitude of the ON-OFF pulse RF clock, The process of sending the shaped sinusoidal waveform to the electrode, Methods that include...

2. The method according to claim 1, The method wherein the electrode is a coil or a substrate support.

3. The method according to claim 1, The aforementioned ON-OFF pulse RF clock has an ON state, The above method further, The process of inverting the ON-OFF pulse RF clock to output an inverted square wave signal, The process includes a step of outputting an amplified square waveform from a square wave signal and the inverted square wave signal, The step of applying the shaped waveform is: A step of adjusting the size of the amplified rectangular waveform to generate a shaped waveform, A step of extracting the shaped sinusoidal waveform from the shaped waveform, Methods that include...

4. The method according to claim 3, A method comprising the step of adjusting the magnitude of the amplified rectangular waveform, performed to output an inter-level shaped waveform, a multi-level shaped waveform, or an arbitrary shaped waveform.

5. The method according to claim 1, The aforementioned ON-OFF pulse RF clock has an ON state, A method wherein the ON-OFF pulse train has a frequency greater than the frequencies of the ON state and the OFF state.

6. It is a method, A process for generating a clock signal having a high frequency, The process of providing a pulse signal, A step of filtering the clock signal according to the ON and OFF states of the pulse signal and outputting an ON-OFF pulsed high-frequency (RF) clock signal, A step of generating multiple square wave signals from the ON-OFF pulse RF clock signal, A step of generating an amplified square wave from the plurality of square wave signals, The process of generating a shaped waveform, A step of filtering the DC voltage associated with the agile DC rail according to the shaped waveform to generate a filtered waveform, A step of shaping the amplified square waveform based on the filtered waveform to generate a shaped waveform, A step of extracting a shaped sine wave from the shaped waveform, wherein the shaped sine wave is output based on a shaped envelope defined by the filtered waveform, A step of providing the shaped sinusoidal RF power to generate plasma for processing the substrate, Methods that include...

7. The method according to claim 6, A method wherein the step of providing the pulse signal includes the step of providing the pulse signal at a frequency lower than the high frequency.

8. The method according to claim 6, The step of providing the pulse signal includes the step of providing a plurality of pulses to provide a plurality of instances in the ON state and a plurality of instances in the OFF state, Each of the multiple instances of the pulse signal in the ON state is followed by a corresponding instance of the multiple instances of the pulse signal in the OFF state, and each of the multiple instances of the pulse signal in the OFF state is followed by a corresponding instance of the multiple instances of the pulse signal in the ON state, The step of generating the clock signal includes the step of generating a plurality of pulses to provide a plurality of ON-state instances and a plurality of OFF-state instances, A method wherein each of the plurality of instances of the clock signal in the ON state is followed by a corresponding instance of the plurality of instances of the clock signal in the OFF state, and each of the plurality of instances of the clock signal in the OFF state is followed by a corresponding instance of the plurality of instances of the clock signal in the ON state.

9. The method according to claim 8, A method for filtering the clock signal, comprising the step of filtering out some of the plurality of pulses of the clock signal according to the OFF state of the pulse signal.

10. The method according to claim 6, The step of receiving the ON-OFF pulse RF clock signal and generating the plurality of square wave signals is as follows: A step of passing the ON-OFF pulse RF clock signal through to output the first square wave signal of the plurality of square wave signals, The process of inverting the ON-OFF pulse RF clock signal to output a second square wave signal of the plurality of square wave signals, Methods that include...

11. The method according to claim 6, A method comprising the step of shaping the amplified rectangular waveform based on the filtered waveform to generate the shaped waveform, the step of applying the envelope of the filtered waveform to the amplified rectangular waveform to make the envelope of the amplified rectangular waveform match the envelope of the filtered waveform.

12. The method according to claim 6, A method comprising the step of extracting a shaped sine wave from the shaped waveform, the step of removing higher-order harmonics from the shaped waveform to output a fundamental frequency waveform.

13. The method according to claim 6, The method wherein the shaped envelope is a multilevel pulse-shaped envelope, an interlevel-shaped envelope, or an arbitrary-shaped envelope.

14. A matchless plasma source for supplying radio frequency (RF) power to electrodes of a plasma chamber used for processing a substrate, An RF clock configured to generate a clock signal having a high frequency, A pulse generator configured to provide a pulse signal, A first filter configured to filter the clock signal according to the ON and OFF states of the pulse signal and output an ON-OFF pulse RF clock signal, A gate driver configured to receive the aforementioned ON-OFF pulse RF clock signal and generate multiple square wave signals, An amplification circuit configured to receive the plurality of square wave signals from the gate driver and generate an amplified square wave, A waveform generator configured to generate a shaped waveform, A second filter configured to filter a DC voltage associated with an agile DC rail according to the shaped waveform and generate a filtered waveform, wherein the filtered waveform shapes the amplified square waveform so that a shaped waveform is generated at the output of the amplification circuit. A matchless plasma source comprising a reactance circuit configured to extract a shaped sinusoidal waveform from the shaped waveform, wherein the shaped sinusoidal waveform is output based on a shaped envelope defined by the filtered waveform, and the reactance circuit is configured to provide the RF power of the shaped sinusoidal waveform to generate plasma for the processing of the substrate.

15. A matchless plasma source according to claim 14, The pulse signal has a frequency lower than the high frequency, and is a matchless plasma source.

16. A matchless plasma source according to claim 14, The pulse signal has multiple pulses and provides multiple instances of being ON and multiple instances of being OFF. Each of the multiple instances of the pulse signal in the ON state is followed by a corresponding instance of the multiple instances of the pulse signal in the OFF state, and each of the multiple instances of the pulse signal in the OFF state is followed by a corresponding instance of the multiple instances of the pulse signal in the ON state, The clock signal has multiple pulses and provides multiple instances of being ON and multiple instances of being OFF. A matchless plasma source wherein each of the plurality of instances of the clock signal in the ON state is followed by a corresponding instance of the plurality of instances of the clock signal in the OFF state, and each of the plurality of instances of the clock signal in the OFF state is followed by a corresponding instance of the plurality of instances of the clock signal in the ON state.

17. A matchless plasma source according to claim 16, A matchless plasma source, wherein the first filter is an AND gate configured to filter out some of the plurality of pulses of the clock signal according to the OFF state of the pulse signal.

18. A matchless plasma source according to claim 14, A matchless plasma source comprising a gate driver including a first gate and a second gate, wherein the first gate is configured to pass the ON-OFF pulse RF clock signal and output a first square wave signal of the plurality of square wave signals, and the second gate is configured to invert the ON-OFF pulse RF clock signal and output a second square wave signal of the plurality of square wave signals.

19. A matchless plasma source according to claim 14, A matchless plasma source wherein the filtered waveform shapes the envelope of the amplified rectangular waveform according to the envelope of the filtered waveform.

20. A matchless plasma source according to claim 14, The reactance circuit is configured to extract the shaped sine wave from the shaped waveform by removing higher-order harmonics from the shaped waveform and output the fundamental frequency waveform, thereby providing a matchless plasma source.

21. A matchless plasma source according to claim 14, The amplification circuit includes a plurality of transistors, and the second filter is connected to the plurality of transistors, in a matchless plasma source.

22. A matchless plasma source according to claim 14, The shaping envelope is a multilevel pulse-shaped envelope, an interlevel-shaped envelope, or an arbitrary-shaped envelope, in a matchless plasma source.

23. A matchless plasma source according to claim 14, A matchless plasma source wherein the reactance circuit is configured to remove higher-order harmonics of the shaped waveform to generate a fundamental waveform, and the shaped sinusoidal waveform is the fundamental waveform having the shaped envelope.

24. A matchless plasma source according to claim 14, A matchless plasma source in which the reactance circuit is connected to the electrodes without using an RF match.

25. A matchless plasma source according to claim 14, The DC agile rail comprises a DC voltage source, and the matchless plasma source further comprises a controller configured to control the shape of the shaping waveform.

26. A matchless plasma source according to claim 14, The matchless bias source is a matchless plasma source connected to the substrate support electrode of the plasma chamber.

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