Semiconductor equipment

Abstract

To provide a highly reliable semiconductor device with excellent electrical characteristics and a method for manufacturing the same. [Solution] The transistor 10 has a semiconductor layer 108, a first insulating layer 110 thereon, and a conductive layer 112 thereon. The semiconductor layer includes a first region 108C, a pair of second regions 108L1 flanking the first region, a pair of third regions 108L2 flanking the first and second regions, and a fourth region 108N flanking the first, second, and third regions. The first region has a region that overlaps with the first insulating layer and the conductive layer, the second and third regions each have a region that overlaps with the first insulating layer and does not overlap with the conductive layer, and the fourth region does not overlap with either the first insulating layer or the conductive layer. The thickness of the first insulating layer in the region that overlaps with the second region is approximately equal to the thickness of the first insulating layer in the region that overlaps with the first region. The thickness of the first insulating layer in the region overlapping with the third region is thinner than the thickness of the first insulating layer in the region overlapping with the second region.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. Another aspect of the present invention relates to a display device. One aspect of the invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technology field is semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, Electronic equipment, lighting equipment, input devices, input / output devices, methods for driving them, or methods for manufacturing them. One example is semiconductor devices that function by utilizing semiconductor properties. This refers to all types of devices. [Background technology]

[0003] Oxide semiconductors, which use metal oxides, are attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 describes stacking multiple oxide semiconductor layers, and the multiple oxide semiconductor layers are stacked. In the material semiconductor layer, the oxide semiconductor layer that forms the channel contains indium and gallium, and By making the proportion of indium greater than the proportion of gallium, the field effect mobility (simply move A semiconductor device with increased mobility (sometimes referred to as μFE) is disclosed.

[0004] Metal oxides that can be used in semiconductor layers can be formed using methods such as sputtering. Therefore, it can be used in the semiconductor layer of transistors that make up large display devices. By improving some of the production equipment for transistors using polycrystalline silicon and amorphous silicon, Because it can be used, capital investment can be reduced. Also, a transient using metal oxides Because it has a higher field-effect mobility compared to when amorphous silicon is used, the drive circuit This enables the creation of high-performance display devices.

[0005] In display devices, there is a trend towards larger screen sizes, with diagonal screens exceeding 60 inches. Development is underway with screen sizes of 120 inches or more in diagonal in mind. In addition, the image The screen resolution is also full HD (1920 x 1080 pixels, or sometimes referred to as "2K"). (It is said to be...), Ultra High Definition (3840 x 2160 pixels, or "4K", etc.) It is also said that...), Super Hi-Vision (7680 x 4320 pixels, or "8K") It is also said that there is a trend toward higher resolution.

[0006] Increasing screen size and resolution tends to increase the wiring resistance within the display unit. (Patent) Reference 2 describes increasing wiring resistance in a liquid crystal display device using amorphous silicon transistors. To suppress the large resistance, a technique has been disclosed for forming a low-resistance wiring layer using copper (Cu). ru. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Patent Document 2] Japanese Patent Publication No. 2004-163901 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention provides a method for manufacturing a highly reliable semiconductor device. This is one of the challenges. Alternatively, one aspect of the present invention provides a method for manufacturing a novel semiconductor device. This will be one of the challenges.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title can be extracted from descriptions such as the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention comprises a semiconductor layer, a first insulating layer on the semiconductor layer, and a conductive layer on the first insulating layer. A semiconductor device having a layer. The semiconductor layer has a first region, a pair of second regions, and It has a pair of third regions and a pair of fourth regions. The second region sandwiches the first region, The third region is bordered by the first and second regions, and the fourth region is bordered by the first and second regions. It encloses the first region and the third region. The first region has an area that overlaps with the first insulating layer and the conductive layer. The second and third regions each have a region that overlaps with the first insulating layer and a conductive layer. The fourth region does not overlap with either the first insulating layer or the first conductive layer. The thickness of the first insulating layer in the region that overlaps with the first region is equal to the thickness of the first insulating layer in the region that overlaps with the first region. They are roughly equal. The thickness of the first insulating layer in the region overlapping with the third region is equal to the thickness of the first insulating layer in the region overlapping with the second region. It is thinner than the film thickness of the first insulating layer.

[0011] The semiconductor device described above further has a second insulating layer, the second insulating layer being the first insulating layer It is preferable that it is in contact with the upper and side surfaces of the layer, as well as the upper surface of the fourth region.

[0012] In the aforementioned semiconductor device, the first insulating layer has an oxide or an oxidized nitride, and the second The insulating layer preferably has an oxide or oxidized nitride.

[0013] In the aforementioned semiconductor device, the first insulating layer has an oxide or an oxidized nitride, and the second The insulating layer preferably has a nitride or nitride oxide.

[0014] In the aforementioned semiconductor device, the third region and the fourth region each contain the first element. It is preferable that the concentration of the first element in the third region be greater than the concentration of the first element in the second region. The concentration of the first element in the fourth region is higher than the concentration of the first element in the third region. This is preferable. Furthermore, the first element is one or more of hydrogen, boron, nitrogen, and phosphorus. This is preferable.

[0015] In the semiconductor device described above, the resistance of the second region is lower than the resistance of the first region, and the third region The resistance of the first region is lower than the resistance of the second region, and the resistance of the fourth region is lower than the resistance of the third region. A lower value is preferable.

[0016] In the semiconductor device described above, the resistance of the third region is at least twice the resistance of the second region (1 × 1). 0 3 It is preferable that it be less than or equal to twice the original amount.

[0017] In the semiconductor device described above, the thickness of the first insulating layer in the portion overlapping with the third region is the second It is preferable that the thickness of the first insulating layer in the area overlapping with the region be between 0.2 and 0.9 times the thickness of the first insulating layer. stomach.

[0018] In the aforementioned semiconductor device, the width of the second region and the width of the third region are 50 nm each. Preferably, the particle size is 1 μm or less.

[0019] In the aforementioned semiconductor device, the semiconductor layer comprises indium, element M, and zinc. Element M is preferably one or more of aluminum, gallium, yttrium, and tin. It's nice.

[0020] One aspect of the present invention is a step of forming an island-shaped semiconductor layer and forming an insulating film on the semiconductor layer. The process involves a step of forming a conductive film on an insulating film, and a step of forming a conductive film on the conductive film, with the edges being the edges of the semiconductor layer. A step of forming a first resist mask located on the inside, and using the first resist mask Then, the conductive film is etched, and the conductive film whose edges are located inside the edges of the first resist mask. The process involves forming a layer, etching the insulating film using a first resist mask, and then forming a first insulating film. The process involves forming an edge layer and reducing the size of the first resist mask so that the edges are outside the edges of the conductive layer. A step of forming a second resist mask located at and using the second resist mask, A step of etching a portion of the upper part of the insulating layer 1 to form a second insulating layer, and a step of etching the second resist A step to remove the mask, and a third insulating layer on the conductive layer, the second insulating layer, and the semiconductor layer. The process involves forming a layer and supplying the first element to the semiconductor layer via the second and third insulating layers. This is a method for manufacturing a semiconductor device having the following steps: Here, the first element is hydrogen, boron It is one or more elements: element, nitrogen, or phosphorus.

[0021] In the aforementioned method for manufacturing a semiconductor device, the step of supplying the first element involves the third insulating layer It is preferable that the process be carried out continuously without exposure to the atmosphere after the forming step.

[0022] In the aforementioned method for manufacturing a semiconductor device, the step of forming a conductive layer is wet etching. Using the method, the steps of forming the first insulating layer and forming the second insulating layer are respectively It is preferable to use the Lye etching method. [Effects of the Invention]

[0023] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, reliability We can provide high-performance semiconductor devices. Or, we can provide novel semiconductor devices. Or, electrical This can provide a method for fabricating semiconductor devices with good characteristics, or a method for fabricating highly reliable semiconductor devices. We can provide a manufacturing method, or a method for manufacturing a novel semiconductor device.

[0024] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0025] [Figure 1] Figures 1A, 1B, and 1C show examples of semiconductor device configurations. [Figure 2] Figures 2A, 2B, and 2C show examples of semiconductor device configurations. [Figure 3] Figures 3A and 3B show examples of semiconductor device configurations. [Figure 4] Figures 4A and 4B show examples of semiconductor device configurations. [Figure 5]Figure 5A is a top view of the semiconductor device. Figures 5B and 5C are cross-sectional views of the semiconductor device. [Figure 6] Figures 6A and 6B are cross-sectional views of the semiconductor device. [Figure 7] Figure 7A is a top view of the semiconductor device. Figures 7B and 7C are cross-sectional views of the semiconductor device. [Figure 8] Figures 8A, 8B, and 8C are cross-sectional views of a semiconductor device. [Figure 9] Figure 9A is a top view of the semiconductor device. Figures 9B and 9C are cross-sectional views of the semiconductor device. [Figure 10] Figures 10A and 10B are cross-sectional views of a semiconductor device. [Figure 11] Figures 11A, 11B, and 11C are cross-sectional views of a semiconductor device. [Figure 12] Figure 12 is a cross-sectional view of a semiconductor device. [Figure 13] Figure 13A is a top view of the semiconductor device. Figures 13B and 13C are cross-sectional views of the semiconductor device. [Figure 14] Figure 14 is a cross-sectional view of a semiconductor device. [Figure 15] Figures 15A, 15B, 15C, and 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 16] Figures 16A, 16B, and 16C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 17] Figures 17A, 17B, and 17C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 18] Figures 18A, 18B, and 18C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 19] Figures 19A, 19B, 19C, and 19D are cross-sectional views illustrating a method for fabricating a semiconductor device. [Figure 20] Figures 20A, 20B, and 20C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 21] Figure 21 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 22]Figures 22A, 22B, and 22C are top views of the display device. [Figure 23] Figure 23 is a cross-sectional view of the display device. [Figure 24] Figure 24 is a cross-sectional view of the display device. [Figure 25] Figure 25 is a cross-sectional view of the display device. [Figure 26] Figure 26 is a cross-sectional view of the display device. [Figure 27] Figure 27A is a block diagram of the display device. Figures 27B and 27C are circuit diagrams of the display device. [Figure 28] Figures 28A, 28C, and 28D are circuit diagrams of the display device. Figure 28B is a timing chart of the display device. [Figure 29] Figure 29A shows an example of the display module configuration. Figure 29B is a schematic cross-sectional view of the display module. [Figure 30] Figure 30A shows an example of the configuration of an electronic device. Figure 30B is a schematic cross-sectional view of the electronic device. [Figure 31] Figures 31A, 31B, 31C, 31D, and 31E show examples of electronic device configurations. [Figure 32] Figures 32A, 32B, 32C, 32D, 32E, 32F, and 32G show examples of the configuration of electronic devices. [Figure 33] Figures 33A, 33B, 33C, and 33D show examples of electronic device configurations. [Figure 34] Figures 34A and 34B are cross-sectional STEM images. [Figure 35] Figures 35A and 35B are cross-sectional STEM images. [Figure 36] Figures 36A and 36B are cross-sectional STEM images. [Figure 37] Figures 37A and 37B show the resistance of metal oxide films. [Figure 38] Figures 38A and 38B show the resistance of metal oxide films. [Figure 39] Figures 39A and 39B show the resistance of metal oxide films. [Modes for carrying out the invention]

[0026] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0027] In each figure described herein, the size, layer thickness, or area of ​​each component is clearly indicated. It may be exaggerated for the sake of clarity.

[0028] The ordinal numbers "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This was added to avoid it, and does not limit the number of occurrences.

[0029] In this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the constituent elements. The positional relationships are used for convenience in explaining them with reference to the drawings. Also, the positions of the components are shown. The arrangement changes appropriately depending on the direction in which each component is depicted. Therefore, the specification The vocabulary is not limited to what has been explained above; it can be appropriately rephrased depending on the situation.

[0030] In this specification, the source and drain functions of a transistor are defined as having different polarities. When using transistors, or when the direction of current changes during circuit operation, They can be swapped. Therefore, the terms source and drain can be used interchangeably. It shall be done.

[0031] In this specification and elsewhere, the channel length direction of a transistor refers to the source region and the drain region. It refers to one of the directions parallel to the straight line connecting the two points by the shortest distance. In other words, the channel length direction is This corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. Furthermore, the channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the zista, the channel length and channel width directions may not be uniquely determined. There are cases where this is the case.

[0032] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where they are connected via. Here, "something that has some kind of electrical effect" is There are no particular restrictions as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes, wiring, transistors, etc. Switching elements, resistive elements, inductors, capacitors, and other elements with various functions This includes children, etc.

[0033] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible. For example, the terms "conductive layer" and "insulating layer" are similar to "conductive film" and "insulating layer". In some cases, the term "membrane" can be used interchangeably.

[0034] In this specification, "approximately matching top surface shapes" means that at least one layer is between the stacked layers. This refers to the overlapping of parts of the outlines. For example, the upper layer and the lower layer may have the same mask pattern, This includes cases where parts are processed using the same mask pattern. However, strictly speaking, if the contours overlap They do not align, and the edge of the upper layer is located inside the edge of the lower layer, or the edge of the upper layer is located inside the edge of the lower layer. It may also be located outside the part, in which case it is said that "the top surface shape is roughly the same."

[0035] In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state. This refers to the drain current when the device is in a non-conductive state or interrupted state. The off state is a special state. Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source V gs but Threshold voltage V th Lower than (in p-channel transistors, V th (Higher than) To describe a state or attitude.

[0036] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0037] In this specification, the substrate of the display panel is, for example, FPC (Flexible Printed Circuit). ed Circuit) or TCP (Tape Carrier Package) Connectors such as those mentioned above are attached, or COG (Chip On Glare) is attached to the circuit board. A display panel module, display module, etc., is a device on which an IC is mounted using the ss) method, etc. Alternatively, it may simply be called a display panel.

[0038] In this specification, a touch panel, which is one form of a display device, displays images, etc. on its display surface. The display function detects when a finger, stylus, or other object touches, presses, or comes near the display surface. It has the function of a touch sensor that detects things like touching. Therefore, touch panel This is one form of an input / output device.

[0039] A touch panel is, for example, a display panel (or display device) with a touch sensor. It can also be called a display panel (or display device) with a touch function. It can also be configured to have a panel and a touch sensor panel. Alternatively, the display panel The configuration can also include a touch sensor functioning either internally or on its surface.

[0040] In this specification, a touch panel circuit board with connectors and ICs mounted on it is referred to as a touch panel. It may be called a touch panel module, display module, or simply a touch panel.

[0041] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention and a method for manufacturing the same. The following describes an example of a semiconductor device using an oxide semiconductor in the channel formation region. This section describes examples of sta configurations and their manufacturing methods.

[0042] <Configuration Example 1> [Configuration Example 1-1] Figure 1A shows a schematic cross-sectional view of transistor 10 in the channel length direction.

[0043] The transistor 10 has a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The edge layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 10 has a gate electrode provided on the semiconductor layer 108, a so-called top-mounted transistor. It is a gate-type transistor.

[0044] The semiconductor layer 108 consists of region 108C, a pair of regions 108L1, and a pair of regions 108L2 It has a pair of regions 108N and a region 108C. The region 108C consists of a conductive layer 112 and an insulating layer 110 It has an overlapping region and functions as a channel-forming region. The pair of regions 108L1 are region The pair of regions 108L2 are provided on either side of region 108C. Regions 108L1 and 108L2 are provided on either side of the conductive layer 11. It has a region that does not overlap with region 2 and overlaps with the insulating layer 110. The pair of regions 108N are region 1 08C is provided between a pair of regions 108L1 and a pair of regions 108L2. Region 10 8N does not overlap with either the conductive layer 112 or the insulating layer 110.

[0045] Region 108N has lower resistance than region 108C, and serves as both the source and drain regions. It works. Regions 108L1 and 108L2 each have lower resistance than region 108C. Furthermore, it is preferable that the resistance is higher than that of region 108N. Region 108L1 and region 108 L2 functions as a buffer region to mitigate the drain electric field. Region 108 L1 and region 108L2 are what is known as LDD (Lightly Doped Drain). It functions as a domain.

[0046] Region 108C that functions as a channel-forming region, and a source region or drain region Between region 108N which functions as an LDD region, region 108L1 and region 10 By providing 8L2, the electric field in the drain region can be mitigated, so the drain This can reduce fluctuations in the transistor's threshold voltage caused by the electric field in the region.

[0047] The electrical resistance in region 108N is preferably as low as possible. For example, the sheet resistance value in region 108N is , 1Ω / □ or more 1×10 3 A value less than Ω / □ is preferable, and moreover, 1Ω / □ or greater (8 × 10⁻¹⁰) 2 Ω / □The following is preferable.

[0048] The higher the electrical resistance of region 108C in the state where no channel is formed, the more preferable. . For example, the sheet resistance value of region 108C is preferably 1×10 7 Ω / □ or more, and further 1×10 8 Ω / □ or more, and further 1×10 9 Ω / □ or more is preferable.

[0049] The sheet resistance values of region 108L1 and region 108L2 are, for example, each 1×10 3 Ω / □ or more and 1×10 9 Ω / □ or less is preferable, and further 1×10 3 Ω / □ or more and 1×10 8 Ω / □ or less is preferable, and further 1×10 3 Ω / □ or more and 1×10 7 Ω / □ or less is preferable , and further 1×10 3 Ω / □ or more and 1×10 6 Ω / □ or less is preferable, and further 1×10 3 [[ID=^2]]Ω / □ or more and 1×10 5 Ω / □ or less is preferable. By setting the resistance within the above range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing regions 108L1 and 108L2 having the resistance within the above range between region 108N and region 108C, the source-drain breakdown voltage of transistor 100 can be increased.

[0050] The electrical resistance of region 108C in the state where no channel is formed is 1×10 times or more and 1×10 6 times or less of the electrical resistance of region 108N, and further 1×10 12 times or more 6 is preferable, and further 1 x 10 11 Preferably less than twice the number, and even more preferably 1 × 10 6 more than 1x10 10 Double or less is preferable. stomach.

[0051] The electrical resistance of region 108C in the state where no channel is formed is given by region 108L1 and the electrical resistance of each region 108L2 is 1 × 10 0 more than 1x10 9 A ratio of 2 or less is preferable. Furthermore, 1 x 10 1 more than 1x10 8 Preferably less than twice the number, and even more preferably 1 × 10 2 more than 1 times ×10 7 It is preferable that it be less than double.

[0052] The electrical resistances of regions 108L1 and 108L2 are, respectively, the same as the electrical resistance of region 108N. 1 x 10 0 more than 1x10 9 Preferably less than twice the number, and even more preferably 1 × 10 1 more than 1x10 8 double The following are preferable, and moreover, 1 × 10 1 more than 1x10 7 It is preferable that it be less than double.

[0053] In semiconductor layer 108, the carrier concentration is lowest in region 108C and lowest in region 108N. It is also preferable that the value is high. Between region 108C and region 108N, region 108L1 and region 1 By providing 08L2, for example, impurities such as hydrogen can diffuse from region 108N during the manufacturing process. Even in such cases, the carrier concentration in region 108C can be kept extremely low.

[0054] A lower carrier concentration is preferable in region 108C, which functions as a channel-forming region. , 1 x 10 18 cm -3The following is preferable: 1 × 10 17 cm -3 The following is It is more preferable that 1 × 10 16 cm -3 It is even more preferable that the following conditions apply: 1 × 10 13 cm -3 It is even more preferable that the following conditions apply: 1 × 10 12 cm -3 The following is Even more preferable. Furthermore, there is no particular limitation on the lower limit of the carrier concentration in region 108C. However, for example, 1 × 10 -9 cm -3 It can be done this way.

[0055] On the other hand, the carrier concentration in region 10⁸N is, for example, 5 × 10⁻⁶. 18 cm -3 The above is preferred Or 1 x 10 19 cm -3 The above is more comfortable 5x10 19 cm -3 That's all. This is possible. There are no particular limitations on the upper limit of the carrier concentration in region 10⁸N, For example, 5 x 10 21 cm -3 , or 1 × 10 22 cm -3 It can be done in this way.

[0056] The carrier concentrations in region 108L1 and region 108L2 are, respectively, those in region 108C and The value can be within the range of 10⁸N. For example, 1 × 10⁸ 14 cm -3 The above 1 x 10 20 cm -3 The value should be in the range less than or equal to.

[0057] Note that the carrier concentrations in regions 108L1 and 108L2 are not uniform. Often, a gradient is used where the carrier concentration decreases from region 108N to region 108C. It may have. Also, the hydrogen concentration in region 108L1 and region 108L2 is in region 10 The gradient may be such that it decreases from the 8N side to the 108C side.

[0058] It is even more preferable that region 108L2 has a lower resistance than region 108L1. The resistance of the conductor layer 108 decreases in a stepwise manner from region 108C towards region 108N. This is preferable. In the order of region 108C, region 108L1, region 108L2, and region 108N. By reducing the resistance, the electric field in the drain region can be effectively mitigated, This allows for a further reduction in the threshold voltage fluctuations of the zista.

[0059] In addition to having a higher resistance in region 108L1 than in region 108L2, the sheathing of region 108L1 The value of the resistor is, for example, 1 × 10 4 Ω / □ or more 1×10 9 Preferably Ω / □ or less, and further is 1 x 10 4 Ω / □ or more 1×10 8 Preferably, the ratio is Ω / □ or less, and even more preferably 1 × 10⁻⁶. 4 Ω / □ or less top 1×10 7 Preferably, the ratio is Ω / □ or less, and even more preferably 1 × 10⁻⁶. 4 Ω / □ or more 1×10 6 Ω / □ or less The bottom is preferable, and even better, 1 × 10 4 Ω / □ or more 1×10 5 A value of Ω / □ or less is preferable. Also, The sheet resistance value of region 108L2 is, for example, 1 × 10 3 Ω / □ or more 1×10 8 Ω / □ or less The bottom is preferable, and even better, 1 × 10 3 Ω / □ or more 1×10 7 Preferably Ω / □ or less, and further is 1 x 103 Ω / □ or more 1×10 6 Preferably, the ratio is Ω / □ or less, and even more preferably 1 × 10⁻⁶. 3 Ω / □ or less top 1×10 5 Preferably, the ratio is Ω / □ or less, and even more preferably 1 × 10⁻⁶. 3 Ω / □ or more 1×10 4 Ω / □ or less The bottom is preferable.

[0060] The resistance of region 108L1 is more than twice the resistance of region 108L2, which is 1 × 10⁻⁶. 3 Less than double Preferably, and even more preferably, 3 times or more (1 × 10⁻⁶). 2 Preferably, it should be less than or equal to 2x, and more preferably between 4x and 10x. Preferably, regions 108L1 and 108L2 having the aforementioned range of resistance are defined as region 10 By placing it between 8N and region 108C, the source-drain breakdown voltage of transistor 100 is It can be improved.

[0061] Region 108L1, Region 108L2, and Region 108N each contain the first element. It is a region. The first element is, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, Arsenic, aluminum, magnesium, helium, neon, argon, krypton, and ky One or more cenons can be used. In particular, hydrogen, boron, nitrogen, and ri are used as the first element. One or more of the elements can be suitably used. Note that region 108L1, region 108L2, and Each region 108N may contain multiple instances of the first element.

[0062] The concentration of the first element in semiconductor layer 108 is in region 108C, region 108L1, and region 108 It is preferable that the concentration is higher in the order of L2, then region 108N. The concentration of the first element in semiconductor layer 108 is , for example, secondary ion mass spectrometry (SIMS). Spectrometry and X-ray photoelectron spectroscopy (XPS) Analysis can be performed using analytical methods such as lectron spectroscopy (XPS analysis). When using this method, combine ion sputtering from the front or back side with XPS analysis. By combining these, the concentration distribution in the depth direction can be determined. Note that the concentration of the first element is low. In some cases, the first element may not be detected in the analysis, or may be detected below the detection limit. In region 108C, the concentration of the first element is low, and therefore the first element is not detected in the analysis. or may be below the detection limit. Similarly, in region 108L1, the analysis showed that Element 1 may not be detected, or may be detected below the detection limit.

[0063] The thickness of the insulating layer 110 in the region overlapping with region 108L1 is the thickness of the insulating layer 110 in the region overlapping with region 108C. It is preferable that the thickness of the margin layer 110 is approximately equal to that of the margin layer 110. Also, the insulating layer of the region overlapping with region 108L2 The thickness of the edge layer 110 is thinner than the thickness of the insulating layer 110 in the region that overlaps with region 108L1. This is preferable. In other words, the thickness of the insulating layer 110 is from region 108C to region 108N. It is preferable that the shape becomes progressively thinner in stages, with steps (hereinafter also referred to as a stepped shape). .

[0064] The insulating layer 110 has a stepped shape, which defines region 108C, region 108L1, and region 1 The amount of the first element added to region 108N can be controlled, and the resistance of semiconductor layer 108 can be controlled. The regions can be made lower in the order of region 108C, region 108L1, region 108L2, and region 108N. It can be done. Also, because the insulating layer 110 has a stepped shape, it can be formed on the insulating layer 110. The coverage of the layer (for example, the insulating layer 118) is improved, and defects such as stepped breaks or porosity occur in the layer. This can suppress the action.

[0065] In this specification, etc., when it is stated that the film thickness of A is approximately equal to the film thickness of B, it means that the film thickness of A is approximately equal to the film thickness of B. This refers to a ratio of film thickness B between 0.8 and 1.2.

[0066] As shown in Figure 1A, the edge of the insulating layer 110 is located inward from the edge of the semiconductor layer 108. The insulating layer 110 also has a first side surface 110S1 and a second side surface 110S2. In a cross-sectional view along the channel length, the first side surface 110S1 and the second side surface 110S2 Each of these is located on the semiconductor layer 108. Also, in a cross-sectional view in the channel length direction, The first side surface 110S1 is located outside the edge of the conductive layer 112, and the second side surface 110S2 is located outside the edge of the conductive layer 112. It is located outside of side 110S1 of 1.

[0067] The insulating layer 110 in contact with the semiconductor layer 108 preferably has an oxide or oxiditride. Furthermore, the insulating layer 110 has regions that contain an excess of oxygen compared to the stoichiometric composition. It is more preferable that the insulating layer 110 is an insulating film capable of releasing oxygen. It has, for example, forming an insulating layer 110 in an oxygen atmosphere, and forming a film of the insulating layer 110. Afterward, heat treatment is performed in an oxygen atmosphere, and after the deposition of the insulating layer 110, plasma is applied in an oxygen atmosphere. Performing a treatment such as oxidizing, or applying an oxide film or oxidative nitriding to the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by forming a film. In each of the above oxygen supply processes, an oxidizing gas may be used instead of or in addition to oxygen. For example, nitrous oxide or ozone may be used.

[0068] The insulating layer 110 is formed by, for example, sputtering or chemical vapor deposition (CVD). (Vapor Deposition) method, vacuum deposition method, pulsed laser deposition (PLD) :Pulsed Laser Deposition) method, atomic layer deposition (ALD: Ato It can be formed using methods such as the mic Layer Deposition method. CVD is a method of plasma chemical vapor deposition (PECVD). Examples include CVD (Chemical Vapor Deposition) and thermal CVD (Chemical Vapor Deposition).

[0069] In particular, the insulating layer 110 is preferably formed by the PECVD (plasma CVD) method. stomach.

[0070] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The semiconductor layer 108 preferably contains at least indium and oxygen. The presence of indium oxide in 108 can increase its carrier mobility. For example, A transistor that can carry a larger current than one made of amorphous silicon. This can be achieved.

[0071] The crystallinity of the semiconductor material used in semiconductor layer 108 is not particularly limited; amorphous semiconductors are also acceptable. , single-crystal semiconductors, or semiconductors having crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors) Either a single-crystal semiconductor or a semiconductor having a crystalline region in part may be used. Using a crystalline semiconductor is preferable because it suppresses the degradation of transistor characteristics. .

[0072] The semiconductor layer 108 preferably has a metal oxide. Alternatively, the semiconductor layer 108 may be It may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon. Examples include silicon (low-temperature polysilicon, single-crystal silicon, etc.).

[0073] When using a metal oxide as the semiconductor layer 108, for example, indium and element M(M) These are gallium, aluminum, silicon, boron, yttrium, tin, copper, and vanadium. Beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, rancid Tan, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium Preferably, the element M is aluminum, galvanic It is preferable that the element M is one or more of yttrium and tin. Also, element M is gallium. It is even more preferable to have either one or both of the above, and tin.

[0074] For example, the semiconductor layer 108 may be indium (In), gallium (Ga), and zinc ( An oxide containing Zn (hereinafter also referred to as IGZO) can be suitably used. Semiconductor layer Assuming 10⁸, for example, if the atomic ratio of metal elements is In:Ga:Zn=1:1:1 or Nearby oxides can be suitably used.

[0075] As semiconductor layer 108, in addition to indium, gallium, and zinc, aluminum, Lycon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, HAF Oxides containing one or more of the following: nium, tantalum, tungsten, or magnesium It can also be used. In particular, as a semiconductor layer, indium, gallium, and zinc can be used in addition to When oxides containing tin, aluminum, or silicon are used, high field-effect mobility is obtained. This is preferable because it allows for the creation of a real-world transistor.

[0076] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... The sputtering target used has an atomic ratio of In to element M of 1 or greater. This is preferable. As the atomic ratio of metal elements in such a sputtering target, In :M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1: 3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4: 2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1:3, In:M: Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Examples include M:Zn=6:1:6 and In:M:Zn=5:2:5. And, if element M includes two or more elements, the proportion of element M in the above atomic ratio is, This corresponds to the sum of the number of atoms of the two or more metal elements.

[0077] When using a sputtering target containing a polycrystalline oxide, the crystallinity is This is preferable because it facilitates the formation of the semiconductor layer. This is plus or minus 4 of the atomic ratio of the metal elements contained in the above sputtering target. Includes 0% variation. For example, the composition of the sputtering target used for the semiconductor layer is In: When M:Zn = 4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer is In:M Zn may be in the vicinity of 4:2:3 [atomic ratio].

[0078] Note that when the atomic ratio is stated as In:M:Zn=4:2:3 or close to it, In is used. When set to 4, this includes the case where element M is between 1 and 3, and Zn is between 2 and 4. Furthermore, when stating that the atomic ratio is In:M:Zn = 5:1:6 or close to it, In When we set it to 5, if M is greater than 0.1 and less than or equal to 2, and Zn is between 5 and 7. It includes [specific elements]. Furthermore, it states that the atomic ratio is In:M:Zn = 1:1:1 or close to it. In this case, when In is set to 1, element M is greater than 0.1 and less than or equal to 2, and Zn is less than or equal to 0.1. This includes cases where the value is greater than or equal to 2.

[0079] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 is at least It is preferable that the semiconductor layer 108 contains a metal oxide containing zinc and oxygen. In addition, it may also contain zinc. Furthermore, the semiconductor layer 108 may contain gallium. stomach.

[0080] The composition of the semiconductor layer 108 significantly affects the electrical characteristics and reliability of the transistor 10. For example, by increasing the indium content in semiconductor layer 108, the carrier mobility can be increased. This improves the field-effect mobility, enabling the creation of transistors with high field-effect mobility.

[0081] Here, as one of the indicators for evaluating the reliability of a transistor, an electric field is applied to the gate. Gate bias stress test (GBT) There is an SS Test. Among them, the gate is used with respect to the source potential and drain potential. A test in which a positive potential is applied and maintained at a high temperature is called PBTS (Positive Voltage Test). (Temperature Stress) test, with a negative potential applied to the gate, The test of holding at high temperatures is called NBTS (Negative Bias Temperature Test). This is called the e-stress test. It is also called a PB test, which is performed under the illumination of light such as white LED light. The TS trial and the NBTS trial were conducted using PBTIS (Positive Bias Test). mperature Illumination Stress) test, NBTIS(N egative Bias Temperature Illumination St This is called a (RESS) test.

[0082] In particular, in n-type transistors using oxide semiconductors, the transistor is in the ON state. When the gate is set to a state where current is flowing, a positive potential is applied to it, therefore in PBTS testing... The fluctuation in key voltage is one of the important factors to consider as an indicator of transistor reliability. This is the result.

[0083] Here, the composition of the semiconductor layer 108 is either gallium-free or gallium-free. By using a metal oxide film with low volts, the fluctuation in threshold voltage during PBTS testing can be reduced. It is possible to do so. Also, if gallium is included, the composition of the semiconductor layer 108 is as follows: It is preferable to have a gallium content that is lower than the um content. This ensures reliability This makes it possible to create high-performance transistors.

[0084] One factor causing the threshold voltage fluctuation in PBTS testing is the relationship between the semiconductor layer and the gate insulating layer. Examples include defect levels at or near the interface. The higher the defect level density, the higher the PB Degradation becomes significant in TS tests. Gallium in the portion of the semiconductor layer that is in contact with the gate insulating layer. By reducing the amount of the substance, the formation of the defect level can be suppressed.

[0085] By eliminating gallium or reducing its gallium content, PBTS degradation can be suppressed. One possible reason for this is the following: The gas contained in semiconductor layer 108 Compared to other metallic elements (such as indium and zinc), lium has a tendency to attract oxygen. It possesses quality. Therefore, a metal oxide film containing a large amount of gallium and an insulating layer 110 containing oxides At the interface with the carrier, gallium combines with excess oxygen in the insulating layer 110, thereby forming a carrier ( Here, it is presumed that it will be easier to create electronic trap sites. When a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer. This could cause the threshold voltage to fluctuate.

[0086] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, the atoms of In A metal oxide film with a numerical ratio higher than the atomic ratio of Ga can be applied to the semiconductor layer 108. It is possible to use a metal oxide film in which the atomic ratio of Zn is higher than that of Ga. , more preferable. In other words, the atomic ratio of the metal elements is In > Ga and Zn > Ga. It is preferable to apply the filling metal oxide film to the semiconductor layer 108.

[0087] For example, in semiconductor layer 108, the atomic ratio of metal elements is In:Ga:Zn=2:1: 3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn =4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5 :1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or this A metal oxide film, which is in the vicinity of these, can be used.

[0088] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, gold The ratio of the number of gallium atoms to the number of atoms of other metal elements in the group oxide (atomic ratio) , greater than 0 and less than 50%, preferably 0.05% to 30%, more preferably 0. The concentration can be 1% to 15%, more preferably 0.1% to 5%. By incorporating gallium into the semiconductor layer 108, oxygen vacancies (hereinafter referred to as V) are created. O (Also written as) It has the effect of making it less likely to happen.

[0089] A gallium-free metal oxide film may be applied to the semiconductor layer 108. For example, In -Zn oxide can be applied to the semiconductor layer 108. At this time, the metal oxide film contains By increasing the ratio of the number of In atoms to the number of atoms of the metal element, the field effect of the transistor can be increased. Fruit mobility can be increased. On the other hand, relative to the number of atoms of the metal element contained in the metal oxide By increasing the atomic ratio of Zn, a highly crystalline metal oxide film is formed, which is why transistors are made. The fluctuations in the electrical characteristics are suppressed, and reliability can be improved. In addition, the semiconductor layer 108 has Alternatively, a metal oxide film that does not contain gallium or zinc, such as indium oxide, may be applied. By using a metal oxide film that contains absolutely no gallium, the threshold in PBTS testing can be significantly reduced. The fluctuation in the voltage can be made extremely small.

[0090] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. When the atomic ratio of the metal element is, for example, In:Zn = 2:3, In:Zn = 4:1, or metal oxide films in the vicinity thereof can be used.

[0091] In particular, for the semiconductor layer 108, it is preferable to apply a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of element M. Also, it is preferable to apply a metal oxide film in which the atomic ratio of Zn is higher than the atomic

[0092] For the semiconductor layer 108, it is preferable to use a metal oxide film having crystallinity. For example, a metal oxide film having a CAAC (c-axis aligned crystal) structure, nc (na no crystal) structure, polycrystalline structure, microcrystalline structure, etc., which will be described later, can be used. By using a metal oxide film having crystallinity for the semiconductor layer 108, the

[0093] density of defect energy levels in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized. The higher the crystallinity of the semiconductor layer 108, the more the density of defect energy levels in the

[0094] film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized. "

[0095] When forming a metal oxide film by sputtering, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the formed metal oxide film. Also, the higher the ratio of the flow rate of oxygen gas to the total flow rate of the film-forming gas used during film formation (also A highly crystalline metal oxide film can be formed. Thus, the metal oxide film that is formed... The crystallinity can be controlled by the substrate temperature and the oxygen flow rate ratio in the deposition gas.

[0096] It is preferable to use a low-resistance material for the conductive layer 112. By using this, parasitic resistance can be reduced, resulting in a transistor with high on-current. This allows for the creation of a semiconductor device with a high on-current. For example, the conductive layer 112 can be made of gold. Using a conductive film containing a compound or alloy is preferable because it can suppress electrical resistance. A conductive film containing an oxide may be used in layer 112. Furthermore, large display devices and high-definition display devices may also be used. By reducing wiring resistance during installation, signal delay is suppressed, enabling high-speed operation. Copper, silver, gold, or aluminum can be used as the electrolytic layer 112. In particular, copper In addition to having low resistance, it is preferable because it is easy to mass-produce.

[0097] The conductive layer 112 may have a laminated structure. When the conductive layer 112 has a laminated structure, low resistance A second conductive layer is provided above, below, or both of the first conductive layer. As the electrical layer, a conductive material that is less susceptible to oxidation (has oxidation resistance) than the first conductive layer is used. It is preferable to use a second conductive layer that suppresses the diffusion of the components of the first conductive layer. It is preferable to use a material. As the second conductive layer, for example, indium oxide, indium Zinc oxide, indium tin oxide (ITO), silicon-containing indium tin oxide Materials (ITSO), metal oxides such as zinc oxide, or titanium nitride, tantalum nitride, molybdenum nitride Metal nitrides such as butene and tungsten nitride can be suitably used.

[0098] The transistor 10 preferably further has an insulating layer 118. The insulating layer 118 is It functions as a protective layer to protect transistor 10. The insulating layer 118 is made of, for example, oxide, acid Inorganic insulating materials such as nitrides, nitride oxides, or nitrides can be used. More specifically Specifically, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide nitride, aluminum oxide Aluminum, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminum Inorganic insulating materials such as laminates can be used. In addition, two or more insulating layers 118 can be stacked. A layered structure is also acceptable.

[0099] In this specification, an oxidized nitride is defined as a compound whose composition contains more oxygen than nitrogen. This refers to materials with a high nitrogen content, and nitride oxides are materials whose composition contains more nitrogen than oxygen. This refers to a composition that contains more oxygen than nitrogen. For example, if silicon oxidiznitride is mentioned, it means that the composition contains more oxygen than nitrogen. When referring to a material with a high content, and it is written as silicon nitride oxide, its composition is such that oxygen This indicates a material with a high nitrogen content.

[0100] Furthermore, in this specification, oxidized nitrides and nitride oxides containing the same elements are described respectively. In that case, the oxidized nitride has a higher oxygen content than the nitride oxide, and nitriding It contains ingredients that satisfy one or both of the following conditions: low content of the element. Furthermore, nitride oxides have a lower oxygen content than oxidized nitrides, and the nitrogen content is also lower. Among the many materials, some satisfy one or both of the following conditions. For example, oxidative nitridation. When silicon and silicon nitride are mentioned, silicon oxide nitride is a type of silicon nitride. It contains materials with a higher oxygen content and a lower nitrogen content than Ricon. , silicon oxynitride contains a material with a lower oxygen content and a higher nitrogen content than silicon oxynitride. The content is included.

[0101] The insulating layer 118 may function as a source of the first element for the regions 108L1, 108L2, and 108N. For example, the insulating layer 118 can function as a source of hydrogen for the regions 108L1, region 1 08L2, and 108N. The regions 1 08L1, 108L2, and 108N have different distances from the insulating layer 118 respectively, so that the amount of hydrogen supplied from the insulating layer 118 can be varied. Specifically , the distances from the insulating layer 118 become shorter in the order of the regions 108L1, 108L2, and 108N , and the amount of hydrogen added can be increased in this order. That is, the resistance of the regions 108L1 , 108L2, and 108N can be lowered in this order. Also, the insulating layer 118 is in contact with the region 108N of the semiconductor layer 108. By providing the insulating layer 118 in contact with the region 108N , the resistance of the region 108N can be particularly lowered. Note that since the region 1 08C has the conductive layer 112 and the insulating layer 110 between it and the insulating layer 118, it is difficult for hydrogen to be added, and it is possible to suppress the lowering of the resistance of the region 108C.

[0102] When hydrogen is used as the first element, the insulating layer 118 may be formed using a mixed gas having a gas containing hydrogen . Thereby, hydrogen can be effectively supplied to the region 108 N exposed during the formation of the insulating layer 118, and the resistance of the region 108N can be further lowered. As the gas containing hydrogen , for example, hydrogen (H2), ammonia (NH3), silane (SiH4), etc. can be used.

[0103] In one aspect of the present invention, transistor 10 has region 1 between region 108C and region 108N. By having region 08L1 and region 108L2, it combines high drain breakdown voltage and high on-current. This allows for the creation of highly reliable transistors.

[0104] [Configuration Example 1-2] Figure 1B shows an example configuration different from the transistor 10 described above. Figure 1B shows transistor 1 This is a schematic cross-sectional view of transistor 0A in the channel length direction. Transistor 10A has a conductive layer 106. In this respect, it mainly differs from transistor 10.

[0105] The conductive layer 106 is connected to the semiconductor layer 108, insulating layer 110, and conductive layer 11 via the insulating layer 103. It has a region that overlaps with 2. The conductive layer 106 is the first gate electrode (also known as the back gate electrode). It functions as (this). The insulating layer 103 also functions as the first gate insulating layer. At that time, the conductive layer 112 is the second gate electrode (also called the top gate electrode), and the insulating layer 110 is It functions as a second gate insulating layer.

[0106] For example, transistor 10A applies the same potential to conductive layer 112 and conductive layer 106. This allows for a larger current to flow when the device is in the ON state. The transistor 10A controls the threshold voltage on one of the conductive layers 112 and 106. One potential is applied to control the on and off states of transistor 10A. It can also be provided. Furthermore, one of the conductive layer 112 and conductive layer 106 and the source are electrically connected. By connecting it, the electrical characteristics of transistor 10A can also be stabilized.

[0107] The insulating layer 103, which functions as a second gate insulating layer, is halfway from the side of the insulating layer 103 that is formed. It is preferable that it functions as a barrier layer that suppresses the diffusion of impurities into the conductive layer 108, etc. i. Examples of such impurities include metal components contained in the conductive layer 106. Also, the insulating layer 103 has high pressure resistance, low membrane stress, and is less likely to release hydrogen and water. It is preferable that the material satisfies one or more of the following conditions: it does not easily diffuse water, and it has few defects. It is even more preferable that all of these conditions be met. The insulating layer 103 is used in the insulating layer 110. An insulating film can be used.

[0108] The conductive layer 106 can be made of a conductive film that can be used for the conductive layer 112.

[0109] Note that Figure 1(B) shows an example where the edge of the conductive layer 106 roughly coincides with the edge of the conductive layer 112. The present invention is shown, but is not limited thereto. The end of the conductive layer 106 is the conductive layer 1 It may be located outside the edge of 12. Also, the edge of conductive layer 106 may be located outside the edge of conductive layer 112. It may be located inside the part. In this specification, "ends roughly coincide" means the area This refers to a situation where at least part of the outlines of two layers overlap. For example, the upper layer and the lower layer However, if the same mask pattern, or a portion of the same mask pattern, is used for processing, Includes. However, strictly speaking, the outlines do not overlap, and the edge of the upper layer is located inside the edge of the lower layer. In some cases, the edge of the upper layer may be located further out than the edge of the lower layer, and in this case as well, "the edge is "Generally consistent."

[0110] [Configuration Examples 1-3] Figure 1C shows an example configuration different from the transistor 10A mentioned above. Figure 1C shows a transistor This is a schematic cross-sectional view of transistor 10B in the channel length direction. Transistor 10B has an insulating layer 103 stacked. It differs primarily from transistor 10A in that it has a layered structure.

[0111] In Figure 1C, the insulating layer 103 is divided into insulating layer 103a and insulating layer 103b from the conductive layer 106 side. This shows an example of a configuration having a three-layer structure in which the layers and insulating layer 103c are stacked in this order. Layer 103a is in contact with the conductive layer 106. The insulating layer 103c is in contact with the semiconductor layer 108.

[0112] Of the three insulating films that the insulating layer 103 has, the insulating film located on the side of the insulating layer 103 that is being formed is It is preferable to use an insulating film containing nitrogen for layer 103a. On the other hand, in contact with semiconductor layer 108 It is preferable to use an insulating film containing oxygen for the insulating layer 103c. The three insulating films of 3 are each processed using a plasma CVD apparatus so as not to come into contact with the atmosphere. It is preferable to deposit the film continuously.

[0113] The insulating layer 103a is a dense film that can prevent the diffusion of impurities from below it. Preferably, the insulating layer 103a is made of a material on the side of the insulating layer 103a that is being formed (for example, a substrate). It is preferable that the film is capable of blocking metal elements, hydrogen, water, etc. contained in (the substance). Therefore, the insulating layer 103a is an insulating layer that was deposited under conditions with a lower deposition rate than the insulating layer 103b. A film can be applied.

[0114] The insulating layer 103a may include, for example, a silicon nitride film, a silicon oxide nitride film, or aluminum nitride. In particular, insulating films containing nitrogen, such as hafnium nitride films, can be used. As 3a, a dense silicon nitride film deposited using a plasma CVD apparatus is used. This is preferable. By using such a nitrogen-containing insulating film, even when the thickness is thin, This effectively suppresses the diffusion of impurities from the surface being formed.

[0115] The insulating layer 103c in contact with the semiconductor layer 108 is an insulating film containing an oxide or oxiditride. It is preferable that the insulating layer 103c is formed in such a way. In particular, the insulating layer 103c is an oxide film or an oxidized nitride It is preferable to use a film. Furthermore, impurities such as water are adsorbed on the surface of the insulating layer 103c. It is preferable to use a dense insulating film that is difficult to penetrate. Furthermore, it is preferable to use a film with as few defects as possible, and water and It is preferable to use an insulating film in which impurities such as hydrogen have been reduced.

[0116] The insulating layer 103c may have regions containing an excess of oxygen compared to its stoichiometric composition. It is preferable. In other words, the insulating layer 103c is an insulating layer that can release oxygen when heated. It is preferable to form a border film. For example, forming the insulating layer 103c under an oxygen atmosphere. The insulating layer 103c after film formation is subjected to heat treatment in an oxygen atmosphere, and the insulating layer 103c Plasma treatment or the like is performed in an oxygen atmosphere after film formation, or an oxygen atmosphere is applied to the insulating layer 103c. By forming an oxide film or an oxidized nitride film under ambient air, acid is introduced into the insulating layer 103c. It is also possible to supply the element. Furthermore, in each of the above oxygen supply processes, instead of oxygen, Alternatively, in addition to oxygen, an oxidizing gas (such as nitrous oxide or ozone) may be used. Alternatively, an insulating film capable of releasing oxygen by heating is deposited on the insulating layer 103c. Oxygen may be supplied from the insulating film to the insulating layer 103c by subsequent heat treatment.

[0117] Furthermore, the metal oxide film that will become the semiconductor layer 108 is formed by sputtering in an oxygen-containing atmosphere. During the formation process, oxygen can be supplied into the insulating layer 103c. After forming the metal oxide film layer, heat treatment is performed to remove oxygen from the insulating layer 103c. The solution is supplied to the metal oxide film, and oxygen vacancies (V) in the metal oxide film are supplied. O ) can be reduced ru.

[0118] For example, the insulating layer 103c can be a silicon oxide film, a silicon oxide nitride film, or a silicon oxide nitride film. Cone film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide Calcium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cereal oxide film An insulating layer containing one or more of a lium film and a neodymium oxide film can be used. In particular, insulating It is preferable to use a silicon oxide film or a silicon oxide-nitride film as layer 103c.

[0119] The insulating layer 103b, located between insulating layer 103a and insulating layer 103c, has low stress, It is preferable to use an insulating film deposited under conditions of high deposition rate. For example, insulating layer 103 b is preferably a film with lower stress than insulating layer 103a and insulating layer 103c. Furthermore, the insulating layer 103b was formed under conditions with a higher film deposition rate than insulating layers 103a and 103c. It is preferable that the film is formed using [a specific method / technology].

[0120] It is preferable to use an insulating film that does not release hydrogen or water as much as possible for the insulating layer 103b. By using such an insulating film, the insulating layer 10 is affected by heat treatment and heat applied during the process. This prevents hydrogen and water from diffusing from 3b through the insulating layer 103c to the semiconductor layer 108, and the region The carrier concentration at 10⁸C can be reduced.

[0121] Furthermore, it is preferable to use an insulating film that does not easily attract oxygen for the insulating layer 103b. Alternatively, it is preferable to use an insulating film that does not easily allow oxygen to diffuse. This results in insulating layer 10 Oxygen is supplied from 3c to semiconductor layer 108 (or the metal oxide film that will become semiconductor layer 108). During the heat treatment for this purpose, oxygen diffuses from the insulating layer 103c to the insulating layer 103b. This makes it possible to suppress a reduction in the amount of oxygen supplied to the semiconductor layer 108.

[0122] For example, the insulating layer 103b may be a silicon nitride film, a silicon nitride film, or aluminum oxide An insulating layer containing one or more of the following: a film, a hafnium oxide film, an aluminum nitride film, and a hafnium nitride film. A silicon nitride film or silicon nitride film can be used as the insulating layer 103b. It is preferable to use a recon film.

[0123] Of the insulating layers 103a, 103b, and 103c that constitute the insulating layer 103, It is preferable to make the thickness of the insulating layer 103b the thickest. The thickness is the required dielectric constant value for the insulating layer 103 and the required dielectric breakdown voltage for the insulating layer 103. The performance of each insulating film is taken into consideration and determined based on the relative permittivity of each insulating film and the thickness of each insulating film. This is possible. In other words, the thickness of each insulating film can be adjusted relative to each other within a range that satisfies the above requirements. can.

[0124] In particular, it is preferable that the insulating layer 103b is thicker than the insulating layer 103a. By making the insulating layer 103a thicker than the insulating layer 103a, the insulating layer 103a releases hydrogen when heated. Even when using a simple film, the amount of hydrogen that can reach the insulating layer 103c is reduced. This can be achieved. Also, by making the insulating layer 103a thinner than the insulating layer 103b, the insulating layer 103 Since the volume of a can be made relatively smaller, the amount of hydrogen that the insulating layer 103a can release can be reduced. It is possible.

[0125] Furthermore, it is preferable that the insulating layer 103b is thicker than the insulating layer 103c. If the layer is too thick, when oxygen is supplied into the insulating layer 103c, heating may cause the insulating layer to become too thick. Because the amount of oxygen that remains without being released from the marginal layer 103c increases, as a result the semiconductor layer 1 The amount of oxygen that can be supplied to 08 (or the metal oxide film that becomes semiconductor layer 108) decreases. There is a risk of this happening. Therefore, the insulating layer 103c is made thinner than the insulating layer 103b (reducing its volume). By doing so, the amount of oxygen remaining in the insulating layer 103c after heating can be reduced. As a result, Of the oxygen supplied to the insulating layer 103c, the proportion of oxygen supplied to the semiconductor layer 108 is increased. This allows for an effective increase in the amount of oxygen supplied to the semiconductor layer 108.

[0126] Furthermore, the thickest insulating layer 103b is formed under conditions of a high film deposition rate, and a thinner insulating layer is formed. The 103a and insulating layer 103c are formed to form a dense film under conditions of low film deposition rate. This allows for a reduction in the film deposition time of the insulating layer 103 without compromising reliability, thereby increasing productivity. It is possible.

[0127] Here, the insulating layer 103a contains an insulating film, typically comprising at least silicon and nitrogen. It is preferable to use a silicon nitride film or a silicon nitride oxide film for the insulating layer. For 103b, it is preferable to use an insulating film containing at least silicon, nitrogen, and oxygen, typically a silicon nitride oxide film or a silicon oxynitride film. Also, for the insulating layer 103 c, it is preferable to use an insulating film containing at least silicon and oxygen, typically a silicon oxide film, or a silicon oxynitride film. At this time, the amount of oxygen contained in the insulating layer 103b is preferably more than that in the insulating layer 103a and less than that in the insulating layer 103c. Furthermore, the amount of nitrogen contained in the insulating layer 103b is preferably less than that in the insulating layer 103a and more than that in the insulating layer 103c.

[0128] The contents of oxygen and nitrogen contained in the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c can be analyzed by analytical methods such as secondary ion mass spectrometry (SIMS) and X-ray photoelectron spectroscopy (XPS). When the content rate of the target element in the film is high (for example, 0.5 atoms / cm 3 or more, or 1 atoms / cm 3 or more), XPS is suitable. On the other hand , when the content rate of the target element in the film is low (for example, 0.5 atoms / cm 3 or less, or 1a toms / cm 3 or less), SIMS is suitable. When comparing the element contents in the film, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0129] If the film densities of the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c are different, in the transmission electron microscope (TEM: Transmission Elec tron Microscopy) image of the cross-section of the insulating layer 1,03, it is observed as a difference in contrast In some cases, these can be distinguished. Furthermore, when the composition and membrane density are similar, the boundaries between them can be blurred. The boundary may become unclear in some cases.

[0130] The insulating layer 103 may consist of two or four or more layers. For example, the insulating layer 103 may consist of two or more layers. A two-layer structure consisting of 103a and an insulating layer 103c can be used.

[0131] [Configuration Examples 1-4] Figure 2A shows an example configuration different from the transistor 10 described above. Figure 2A shows transistor 1 This is a schematic cross-sectional view of transistor 0C in the channel length direction. Transistor 10C has an insulating layer 110 stacked on top of it. It differs primarily from transistor 10 in terms of its structure.

[0132] Figure 2A shows that the insulating layer 110 consists of insulating layer 110a, insulating layer 110b, and so on, from the semiconductor layer 108 side. This shows an example of a three-layer structure in which the insulating layer 110c is laminated in this order.

[0133] The insulating layer 110a has regions in contact with region 108C, region 108L1, and region 108L2. The insulating layer 110c has a region that is in contact with the conductive layer 112. The insulating layer 110b is an insulating layer. It is located between the margin layer 110a and the insulating layer 110c.

[0134] The insulating layer 110a, insulating layer 110b, and insulating layer 110c are each made of oxide or oxidation It is preferable that the insulating film contains a nitride. Also, insulating layer 110a, insulating layer 110b and The insulating layer 110c is deposited continuously using the same deposition apparatus without exposure to the atmosphere. It is preferable to do so. By continuously forming the film, insulating layer 110a, insulating layer 110b and This prevents impurities such as water from adhering to the interface between the insulating layer 110c and the insulating layer 110c.

[0135] For example, silicon oxide can be used as the insulating layer 110a, insulating layer 110b, and insulating layer 110c. Films, silicon oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, ma An insulating film containing one or more of the following: magnesium film, lanthanum oxide film, cerium oxide film, and neodymium oxide film. A marginal layer can be used.

[0136] The insulating layer 110a, insulating layer 110b, and insulating layer 110c are formed, for example, by sputtering. It can be formed using methods such as CVD, vacuum deposition, PLD, and ALD. VD methods include plasma CVD and thermal CVD.

[0137] In particular, insulating layers 110a, 110b, and 110c are formed by plasma CVD. It is preferable to form it in this way.

[0138] Since the insulating layer 110a is formed on the semiconductor layer 108, it is important to keep it as close to the semiconductor layer 108 as possible. It is preferable that the film is deposited under conditions that do not cause damage. For example, the deposition rate (film deposition The film can be deposited under conditions where the rate (also called the rate) is sufficiently low. Damage to semiconductor layer 108. By forming the insulating layer 110a under conditions that do not impart [something], the semiconductor layer 108 and the insulating layer 110 The defect level density at the interface is reduced, resulting in a highly reliable transistor 10C. It is possible.

[0139] For example, a silicon oxidizride film is formed as the insulating layer 110a by plasma CVD. In this case, forming it under low power conditions minimizes damage to the semiconductor layer 108. It can be made smaller.

[0140] The deposition gas used for forming silicon oxide nitride films includes, for example, silanes and disilanes. Depositing gases containing condensate, and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. , can be used as a raw material gas. In addition to the raw material gas, argon, helium, Alternatively, it may contain a diluent gas such as nitrogen.

[0141] For example, the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter also simply referred to as the flow rate ratio) By reducing (u), the deposition rate can be lowered, resulting in the deposition of a dense film with fewer defects. can.

[0142] The insulating layer 110b is a film that was deposited under conditions with a higher deposition rate than the insulating layer 110a. This is preferable. This can improve productivity.

[0143] For example, the insulating layer 110b is subjected to conditions where the flow rate ratio of the depositing gas is increased compared to the insulating layer 110a. This allows for film deposition under conditions that increase the deposition rate.

[0144] The insulating layer 110c has reduced surface defects and absorbs impurities contained in the atmosphere, such as water. It is preferable that the film be extremely dense and difficult to adhere to. For example, similar to the insulating layer 110a, The film can be deposited under conditions where the deposition rate is sufficiently low.

[0145] Furthermore, since the insulating layer 110c is formed on the insulating layer 110b, compared to the insulating layer 110a The effect on the semiconductor layer 108 during the deposition of the insulating layer 110c is small. Therefore, the insulating layer 11 0c can be deposited under higher power conditions than the insulating layer 110a. Flow of depositing gas By reducing the quantity ratio and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained. It is possible.

[0146] In other words, the deposition rate is fastest for insulating layer 110b, followed by insulating layer 110a and insulating layer 110c. A laminated film formed under conditions that slow down in that order can be used as the insulating layer 110. Furthermore, the insulating layer 110 is subjected to the same conditions in wet etching or dry etching. The etching rate was fastest in insulating layer 110b, followed by insulating layer 110a and insulating layer 110c. It will get delayed in order.

[0147] Furthermore, the insulating layer 110b is formed to be thicker than the insulating layers 110a and 110c. This is preferable. By forming the insulating layer 110b, which has the fastest film formation rate, thicker, the insulating layer 110 The time required for the film deposition process can be shortened.

[0148] Note that insulating layers 110a, 110b, and 110c use insulating films of the same type. Therefore, the boundary between insulating layer 110a and insulating layer 110b, and insulating layer 110b In some cases, the boundary of the insulating layer 110c cannot be clearly identified. Therefore, in Figure 2A, etc., The boundaries between them are clearly indicated by dashed lines. Note that the film density of insulating layer 110a and insulating layer 110b is Because they are different, the cross-section of the insulating layer 110 is viewed using a transmission electron microscope (TEM). In images such as those from electron microscopy, these boundaries are This can sometimes be observed as a difference in contrast. Similarly, the insulating layer 110b and The boundary of the insulating layer 110c can sometimes be observed as a difference in contrast.

[0149] In Figure 2A, the insulating layer 110 in the region in contact with region 108C, and region 108L1 are shown. The insulating layers 110 in contact areas are, respectively, insulating layer 110a, insulating layer 110b, and insulating layer 11 It has a layered structure of 0c, and the insulating layer 110 in the region overlapping with region 108L2 is the insulating layer 110a Although a configuration having a laminated structure of the insulating layer 110b has been shown, one aspect of the present invention is not limited thereto. It is not possible. As shown in Figure 2B, transistor 10D provides insulation for the region overlapping with region 108L2. Even if layer 110 has a laminated structure of insulating layer 110a, insulating layer 110b, and insulating layer 110c Good. As shown in Figure 2C, the insulating layer of the region overlapping with region 108L2, as in transistor 10E. 110 may have a single-layer structure of insulating layer 110a.

[0150] Furthermore, the insulating layer 110 consists of two parts: insulating layer 110a and insulating layer 110c on top of insulating layer 110a. It may be a layered structure. Alternatively, the insulating layer 110 may be a single layer structure. Depending on the purpose, one of the aforementioned insulating layers 110a, 110b, or 110c may be used. You can select as appropriate.

[0151] [Configuration Examples 1-5] Figure 3A shows an example configuration different from the transistor 10 described above. Figure 3A shows transistor 1 This is a schematic cross-sectional view of transistor 0F in the channel length direction. Transistor 10F is connected to the insulating layer 110 and the conductive layer It differs from transistor 10 mainly in that it has a metal oxide layer 114 between layers 112. .

[0152] The metal oxide layer 114 has the function of supplying oxygen to the insulating layer 110. Also, the conductive layer When a conductive film containing an easily oxidized metal or alloy is used in 112, the metal oxide layer 114 This acts as a barrier layer to prevent the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. To be able to.

[0153] The metal oxide layer 114 allows hydrogen and water contained in the conductive layer 112 to diffuse towards the insulating layer 110. It also functions as a barrier film to prevent this. The metal oxide layer 114 is, for example, at least an insulating layer. Materials that are less permeable to oxygen and hydrogen than those used in 110 can be used.

[0154] The metal oxide layer 114 makes it easier for the conductive layer 112 to attract oxygen such as aluminum and copper. Even when using a metallic material, oxygen will diffuse from the insulating layer 110 to the conductive layer 112. This can prevent the conductive layer 112 from containing hydrogen. This prevents hydrogen from diffusing from the insulating layer 110 to the semiconductor layer 108. As a result, the carrier concentration in region 108C can be kept extremely low.

[0155] The metal oxide layer 114 can be an insulating material or a conductive material. If the material layer 114 is insulating, the metal oxide layer 114 is part of the gate insulating layer. It functions. On the other hand, if the metal oxide layer 114 is conductive, the metal oxide layer 114 It functions as part of the gate electrode.

[0156] As the metal oxide layer 114, an insulating material with a higher dielectric constant than silicon oxide is used. This is preferred. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminum film is preferred. Using a film or similar material is preferable because it allows for a reduction in the driving voltage.

[0157] A metal oxide can be used as the metal oxide layer 114. For example, indioxide Indium zinc oxide, indium tin oxide (ITO), silicon-containing Indium-containing oxides such as tincture tin oxide (ITSO) can be used. Conductive oxides containing cinnabar are preferred due to their high conductivity. Also, ITSO is silicon Because it contains [a specific compound], it is less likely to crystallize and has high flatness, and therefore it forms on ITSO. Adhesion to the film is improved. The metal oxide layer 114 contains zinc oxide and gallium oxide. Metal oxides such as lead can be used. Furthermore, these can be stacked as the metal oxide layer 114. A layered structure may also be used.

[0158] The metal oxide layer 114 uses an oxide material that contains one or more of the same elements as the semiconductor layer 108. It is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. In this case, the metal oxide layer 114 is preferably sputtered, just like the semiconductor layer 108. By applying a metal oxide film formed using a target, the equipment can be standardized. preferable.

[0159] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When using metal oxide materials, the gallium composition (content) is higher than that of semiconductor layer 108. Using a suitable material is preferable because it can further enhance the blocking properties against oxygen. At this time, the semiconductor layer 108 contains a material with a higher indium composition than the metal oxide layer 114. By using this material, the field-effect mobility of transistor 100 can be increased.

[0160] The metal oxide layer 114 is preferably formed using a sputtering apparatus. When forming an oxide film using a sputtering apparatus, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate addition of oxygen to the insulating layer 110 and the semiconductor layer 108.

[0161] Furthermore, if the metal oxide layer 114 is formed for the purpose of supplying oxygen to the insulating layer 110, Alternatively, a metal oxide film that forms the metal oxide layer 114 may be formed and then removed. The oxide layer 114 may be omitted if it is not needed.

[0162] [Configuration Examples 1-6] Figure 3B shows an example configuration different from the transistor 10 described above. Figure 3B shows transistor 1 This is a schematic cross-sectional view of 0G in the channel length direction. Transistor 10G has region 108N and region It differs from transistor 10 mainly in that it has region 108L3 between 108L2. .

[0163] The semiconductor layer 108 consists of region 108C, a pair of regions 108L1, and a pair of regions 108L2 It has a pair of regions 108L3 and a pair of regions 108N. Region 108L3 is a region It is provided flanking region 108C, a pair of regions 108L1, and a pair of regions 108L2. Furthermore, region 108L3 has a region that does not overlap with the conductive layer 112 but overlaps with the insulating layer 110. For regions 108C, 108L1, and 108L2, please refer to the above description. Therefore, a detailed explanation will be omitted.

[0164] Regions 108L1, 108L2, and 108L3 are each larger than region 108C. It is preferable that the resistance is low and higher than that of region 108N. Region 108L1, region Regions 108L2 and 108L3 function as LDD regions.

[0165] Region 108L3 is even more preferably lower in resistance than region 108L2. The resistance decreases in the order of C, region 108L1, region 108L2, region 108L3, and region 108N. This effectively relaxes the electric field in the drain region, thus reducing the transistor's performance. This can further reduce fluctuations in the key voltage.

[0166] The thickness of the insulating layer 110 in the region overlapping with region 108L3 is the same as the thickness of the insulating layer 110 in the region overlapping with region 108L2. It is preferable that the thickness of the insulating layer 110 is less than the thickness of the insulating layer 110. In other words, the thickness of the insulating layer 110 is less than the thickness of the insulating layer 110. The shape is stepped, gradually becoming thinner from the 108C side towards the 108N side. Preferably, the insulating layer 110 has a stepped shape, which controls the resistance of the semiconductor layer 108. The order of decreasing intensity is region 108C, region 108L1, region 108L2, region 108L3, and region 108N. It can be done.

[0167] As shown in Figure 3B, the insulating layer 110 has a first side surface 110S1 and a second side surface 110S It has 2 and a third side surface 110S3. In a cross-sectional view in the channel length direction, the first side surface 110S1, the second side surface 110S2, and the third side surface 110S3 are each semiconductor layer 10 It is located on 8. Also, in a cross-sectional view along the channel length, the first side surface 110S1 is conductive. Located outside the edge of layer 112, the second side surface 110S2 is outside the first side surface 110S1. Located on the side, the third side 110S3 is located outward from the second side 110S2.

[0168] [Configuration Examples 1-7] In Figures 1A to 1C, Figures 2A to 2C, and Figure 3A, region 108C and region 108N Figure 3B shows a configuration with two LDD regions (region 108L1 and region 108L2) in between. The structure has three LDD regions (region 108L1, region 108L2, and region 108L3). Although this has been shown, the present invention is not limited to this. Between region 108C and region 108N The configuration can have p (where p is 2 or more) LDD regions.

[0169] Figure 4A is a schematic cross-sectional view of transistor 10H in the channel length direction. Transistor 1 0H has regions 108L1 to 108Lp between region 108C and region 108N. This shows the configuration.

[0170] As shown in Figure 4A, the insulating layer 110 has a first side surface 110S1 to the p side surface 110S It has p. In a cross-sectional view in the channel length direction, the first side surface 110S1 to the p side surface 1 Each of the 10Sp is located on the semiconductor layer 108. Also, in a cross-sectional view in the channel length direction... Furthermore, the first side surface 110S1 is located outside the edge of the conductive layer 112, and the second side surface 110 S2 is located outside the first side surface 110S1, and the p side surface 110Sp is the p-1 side surface. It is located outside of 110Sp-1.

[0171] Furthermore, the insulating layer 110 is not in a stepped shape, and the thickness of the insulating layer 110 is on the side of region 108C. It may become continuously thinner from the region towards region 108N. Figure 4B shows transistor 10 This is a schematic cross-sectional view of channel I in the direction of its length. As shown in Figure 4B, the side surface 11 of the insulating layer 110 0S may have a sloped shape. Also, the transistor 10I is an insulating layer 110 The film thickness becomes continuously thinner from region 108C towards region 108N, and This configuration shows a continuous decrease in resistance from region 108L1 towards region 108Lp.

[0172] <Configuration Example 2> The following section will explain more specific examples of transistor configurations.

[0173] [Configuration Example 2-1] Figure 5A is a top view of transistor 100, and Figure 5B shows the dashed line A1 shown in Figure 5A. -This corresponds to a cross-sectional view of the cross-section in A2, and Figure 5C corresponds to the dashed line B1-B2 shown in Figure 5A. This corresponds to a cross-sectional view of the cut surface. Note that in Figure 5A, the components of transistor 100 are shown. Some of the elements (protective layer, etc.) are omitted in the diagram. Also, the dashed line A1-A2 direction is channel The length direction and the direction of the dashed line B1-B2 correspond to the channel width direction. Also, the transistor Regarding the top view, in subsequent drawings, as with Figure 5A, some of the components will be omitted. It shall be shown.

[0174] An enlarged view of the region P enclosed by the dashed line in Figure 5B is shown in Figure 6A. The dashed line in Figure 5C Figure 6B shows an enlarged view of the enclosed region R.

[0175] The transistor 100 is provided on the substrate 102 and has a semiconductor layer 108, an insulating layer 110, and a conductive layer. It has an electrical layer 112, an insulating layer 118, etc. The island-shaped semiconductor layer 108 is provided on the substrate 102. The insulating layer 110 is located on a part of the upper surface of the substrate 102, on the side surface of the semiconductor layer 108, and on the semiconductor layer It is provided covering a portion of the upper surface of 108. The conductive layer 112 is provided on the insulating layer 110. It has a portion that overlaps with the semiconductor layer 108.

[0176] The edges of the conductive layer 112 are located inside the edges of the insulating layer 110. In other words, The edge layer 110 extends at least on the semiconductor layer 108, beyond the edge of the conductive layer 112. It has a protruding part.

[0177] A portion of the edge of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 is a conductive layer The portion that overlaps with 112 and functions as a gate insulating layer, and the portion that does not overlap with conductive layer 112 ( That is, it has a portion that overlaps with region 108L1 or region 108L2.

[0178] The semiconductor layer 108 consists of region 108C, a pair of regions 108L1, and a pair of regions 108L2 It has a pair of regions 108N and a region 108C. The region 108C consists of a conductive layer 112 and an insulating layer 110 It has an overlapping region and functions as a channel-forming region. Region 108L1 is region 108 Region 108L2 is provided with C in between. Region 108L2 sandwiches region 108C and the pair of regions 108L1. And so it is provided. Also, regions 108L1 and 108L2 do not overlap with the conductive layer 112. , and also has a region that overlaps with the insulating layer 110. Region 108N is region 108C, a pair of regions Region 108N is provided between 108L1 and a pair of regions 108L2. It does not overlap with either layer 2 or the insulating layer 110.

[0179] Regions 108L1 and 108L2 overlap with the insulating layer 110 of the semiconductor layer 108. Furthermore, it is a region that does not overlap with the conductive layer 112. In Figure 6A, the channel of transistor 100 The width of region 108C in the length direction is width L0, the width of region 108L1 is width L1, and region 10 The width of 8L2 is indicated by width L2. Also, the film of the insulating layer 110 in the region overlapping with region 108C. The thickness is defined as film thickness TN0, and the film thickness of the insulating layer 110 in the region overlapping with region 108L1 is defined as film thickness TN1, and region The thickness of the insulating layer 110 in the region overlapping with 108L2 is indicated by the thickness TN2.

[0180] The film thickness TN1 is preferably approximately equal to the film thickness TN0. N2 is preferably 0.2 times or more and 0.9 times or less, and more preferably 0.3 times or more and 0.8 times or less. Furthermore, a film thickness of 0.4 times or more and 0.7 times or less is preferable. By setting the film thickness within the aforementioned range, The resistance in regions 108L1 and 108L2 can be controlled.

[0181] As will be described later, regions 108L1 and 108L2 can be formed in a self-consistent manner. Therefore, a photomask is required to form regions 108L1 and 108L2. This reduces manufacturing costs. Furthermore, the region 108L1 and region 108L By forming 2, the relative positions of region 108L1, region 108L2 and conductive layer 112 Because no misalignment occurs, region 108L1 and region 108L in the semiconductor layer 108 The width of 2 can be roughly matched.

[0182] Between region 108C, which functions as a channel-forming region, and region 108N, a gate As an offset region where the electric field does not apply (or is less likely to apply than in region 108C), the device The functional regions 108L1 and 108L2 can be formed stably and without variation. This can improve the source-drain breakdown voltage of transistors, resulting in more reliable transistors. This enables the realization of a static state. Furthermore, the current density at the boundary between region 108C and region 108N can be reduced. Heat generation at the channel-source or drain boundary is suppressed, resulting in a highly reliable transient. It can be used as a semiconductor device.

[0183] The width L1 of region 108L1 and the width L2 of region 108L2 are each 50 nm to 1 μm. The following are preferred, more preferably 70 nm to 700 nm, and more preferably 100 nm or less. Preferably, the upper 500 nm or less. By providing regions 108L1 and 108L2, The concentration of the electric field near the drain is mitigated, especially when the drain voltage is high. This can suppress the degradation of the zista. In particular, the sum of widths L1 and L2 is less than the thickness of the insulating layer 110. By increasing the size, it is possible to effectively suppress electric field concentration near the drain. On the other hand, if the sum of widths L1 and L2 is greater than 2 μm, the source-drain resistance increases. The drive speed of the lunger may be slow. The widths L1 and L2 should be within the aforementioned ranges. This allows for the creation of highly reliable and fast-acting transistors and semiconductor devices. Note that widths L1 and L2 are the thickness of the semiconductor layer 108 and the thickness of the insulating layer 110, respectively. Determined according to the magnitude of the voltage applied between the source and drain when driving the inverter 100. It is possible.

[0184] The first side surface 110S1 and the second side surface 110S2 of the insulating layer 110 are, It is preferable that the first side surface 110S1 and the second side surface 110S2 Because it has a tapered shape, the layer formed on the insulating layer 110 (for example, insulating layer 11 8) The coverage is improved, and defects such as stepped breaks and porosity in the layer can be suppressed. In addition, in the top view shown in Figure 5A, the end of the insulating layer 110, the first side surface 110S1, and The second side 110S2 is shown with a dashed line.

[0185] The angles θ1 and θ2 shown in Figures 6A and 6B will be explained. Angle θ1 is the first The upper surface of the insulating layer 110 that the lower end of the side surface 110S1 is in contact with is an extended surface into the interior of the insulating layer 110. This is the angle formed by the first side surface 110S1. The angle θ2 is formed by the bottom surface of the insulating layer 110 and the second side surface 110S1. This is the angle formed by the side surface 110S2. Angles θ1 and θ2 are each between 30 degrees and 90 degrees. Preferably less than 35 degrees, more preferably 35 degrees or more and 85 degrees or less, and more preferably 40 degrees or more and 80 degrees or more. Preferably, it is less than [angle value], more preferably 45° or more and 80° or less, and even more preferably 50° or more and 80° or less. By setting the angle within the above range, the coverage of the insulating layer 118 provided on the insulating layer 110 can be enhanced.

[0186] In this specification etc., the taper angle refers to the inclination angle formed by the side surface and the bottom surface of the target layer when observed from a direction perpendicular to the cross-section (for example, the plane perpendicular to the surface of the substrate).

[0187] The concentration of the first element in the region 108N preferably has a concentration gradient such that the concentration becomes higher as it approaches the insulating layer 118. Thereby, compared with the case where a uniform concentration is set throughout the region 108N, the total amount of the first element in the region 108N can be reduced, so that the amount of the first element that can diffuse into the region 108C due to the influence of heat etc. during the manufacturing process can be kept low. Also, since the upper part of the region 108N has a lower resistance, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced.

[0188] The process of adding the first element to the regions 108L1, 108L2, and 108N can be performed using the conductive layer 112 and the insulating layer 110 as masks. Thereby, the regions 108L1, 108L2, and 108N can be formed self-aligned.

[0189] The concentration of the first element in the region 108N is 1×10 19 atoms / cm 3 or more and 1×1 0 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5× 10 22 ​​​​​​​​​​atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 That's all. , 1 x 10 22 atoms / cm 3 Preferably, the region includes the following:

[0190] The first element is boron, phosphorus, magnesium, aluminum, silicon, etc. When using easily rottable elements, regions 108L1, 108L2, and 108N are each In this case, it is preferable that the first element exists in an oxidized state. Elements that are easily oxidized can exist stably in an oxidized state by bonding with oxygen in semiconductor layer 108. Therefore, in subsequent processes, high temperatures (for example, 400°C or higher, 600°C or higher, or 800°C or higher) are required. Even if ) is applied, detachment is suppressed. Also, the first element is a semiconductor layer By removing oxygen from region 108, acid is released into regions 108L1, 108L2, and 108N. Prime defect (V O This oxygen deficiency (V O ) Defects into which hydrogen from the membrane enters (hereinafter, V O H (also written as H) is a carrier source, and region 108L1, region 108L2, and region The resistance of 108N will decrease.

[0191] Here, regarding the semiconductor layer 108 and the oxygen vacancies that may be formed in the semiconductor layer 108... I will explain.

[0192] Oxygen vacancies formed in the channel formation region of semiconductor layer 108 affect transistor characteristics. This becomes a problem because it gives. For example, if an oxygen vacancy is formed in the semiconductor layer 108, the oxygen Hydrogen can bind to the defect and become a carrier source. Carrier source within the channel formation region When this is generated, the electrical characteristics of transistor 100 change, typically a shift in the threshold voltage. This occurs. Therefore, in the channel formation region, the less oxygen deficiency there is, the better. .

[0193] Therefore, in one embodiment of the present invention, the insulating film near the channel formation region of the semiconductor layer 108 Specifically, the insulating layer 110 located above the channel formation region, and the insulating layer located below it. The edge layer 103 has a structure that includes an oxide film or an oxidoxide-nitride film. Due to heat during the manufacturing process, By moving oxygen from the insulating layer 103 and the insulating layer 110 to the channel-forming region, This makes it possible to reduce oxygen deficiency in the Nell formation region.

[0194] The semiconductor layer 108 has a region where the atomic ratio of In to element M is greater than 1. It is preferable. The higher the In content, the better the field-effect mobility of the transistor. can.

[0195] Here, in the case of metal oxides containing In, Ga, and Zn, the bonding force between In and oxygen is stronger than that between Ga and acid. Because it is weaker than the elemental bonding force, when the In content is high, oxygen vacancies occur in the metal oxide film. It is easily formed. The same tendency is observed when element M is used instead of Ga. If there are many oxygen vacancies in the oxide film, the electrical characteristics of the transistor will deteriorate and its reliability will decrease. The following occurs.

[0196] However, in one aspect of the present invention, the channel formation region of the semiconductor layer 108 containing a metal oxide A metal oxide material with a high In content is used because it can supply an extremely large amount of oxygen to the region. This makes it possible to achieve extremely high field effect mobility, stable electrical characteristics, and high This makes it possible to create transistors that combine high reliability with superior performance.

[0197] For example, if the atomic ratio of In to element M is 1.5 or greater, or 2 or greater, or 3 or greater, Alternatively, metal oxides with a value of 3.5 or higher, or 4 or higher, can be suitably used.

[0198] In particular, the ratio of the number of In, M, and Zn atoms in semiconductor layer 108 is In:M:Zn=4:2 :3 or a similar ratio is preferable. Alternatively, the ratio of the number of atoms of In, M, and Zn is It is preferable that the ratio of In:M:Zn is 5:1:6 or close to it. Also, semiconductor layer 1 As the composition of 08, the ratio of the number of atoms of In, element M, and Zn in semiconductor layer 108 is approximately equal. It is also possible to do so if the ratio of the number of atoms of In, element M, and Zn is In:M:Zn=1: It may contain materials in a 1:1 ratio or a near-1:1 ratio.

[0199] For example, a transistor with high field-effect mobility as described above can be used to generate a gate signal. By using it in the driver, it is possible to provide a display device with a narrow bezel (also called a narrow-bezel display). Furthermore, The transistor with high field-effect mobility mentioned above is used as a source driver (especially if the source driver is By using it in a demultiplexer connected to the output terminal of a shift register, the display This allows us to provide a display device with a small number of wires connected to the device.

[0200] Furthermore, the semiconductor layer 108 has a region where the atomic ratio of In to element M is greater than 1. However, if the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may be low. The crystallinity of the conductive layer 108 can be determined, for example, by X-ray diffraction (XRD). Analyze using (on) or using a transmission electron microscope (TEM). It can be analyzed using this method.

[0201] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect level density. By reducing oxygen deficiency, the carrier concentration in the membrane can be lowered. In transistors that use such metal oxide films in the channel formation region of the semiconductor layer, the threshold It rarely exhibits electrical characteristics where the voltage value is negative (also known as normally-on). Furthermore, transistors using such metal oxide films exhibit the characteristic of having a remarkably low off-current. It is possible.

[0202] When a highly crystalline metal oxide film is used for the semiconductor layer 108, during processing of the semiconductor layer 108, Damage during the deposition of the insulating layer 110 can be suppressed, enabling the creation of highly reliable transistors. This can be achieved. On the other hand, by using a metal oxide film with relatively low crystallinity for the semiconductor layer 108, This improves air conductivity and enables the creation of transistors with high field-effect mobility.

[0203] The semiconductor layer 108 is a CAAC (c-axis aligned crystal) which will be described later. l) Metal oxide film having a structure, metal acid having an nc (nano crystal) structure It is preferable to use an oxide film, or a metal oxide film containing a mixture of CAAC and nc structures. stomach.

[0204] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0205] For example, a semiconductor layer 108 made by stacking two or more metal oxide films with different compositions can be used. Yes, it is possible. For example, when using In-M-Zn oxide, the atoms of In, element M, and Zn The ratios of the numbers are In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn =1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M: Films formed on a sputtering target with a Zn=1:3:2 ratio, or a ratio close to that ratio. It is preferable to use two or more of these stacked together.

[0206] A semiconductor layer 108 can be made by stacking two or more metal oxide films with different crystallinity. In that case, by using the same oxide target but changing the film deposition conditions, exposure to air can be achieved. It is preferable that they be formed continuously without interruption.

[0207] At this time, the semiconductor layer 108 is a metal oxide film having an nc structure and a CAAC structure It can be a layered structure of metal oxide films having an nc structure. A laminated structure of a material film and a metal oxide film having an nc structure may also be used. The functions of metal oxides suitable for use in films, or the composition of materials, will be described later. The description of CAC (Cloud-Aligned Composite) can be used as a reference.

[0208] For example, the oxygen flow rate ratio during the formation of the first metal oxide film, which is formed earlier, is used for the second film, which is formed later. The oxygen flow rate ratio during deposition of the metal oxide film is made smaller than that of the first metal oxide film. During film formation, conditions are set so that no oxygen is flowed. This prevents acid from entering during the formation of the second metal oxide film. It can effectively supply the element. Also, the first metal oxide film is more crystalline than the second metal oxide film. The film has low thermal conductivity and high electrical conductivity. On the other hand, the second metal acid provided on top By making the oxide film a film with higher crystallinity than the first metal oxide film, the semiconductor layer 108 can be processed. This can suppress damage during time and during the deposition of the insulating layer 110.

[0209] More specifically, the oxygen flow rate ratio during the deposition of the first metal oxide film is set to 0% or more and less than 50%. Preferably 0% to 30%, more preferably 0% to 20%, and typically 10%. Furthermore, the oxygen flow rate ratio during the deposition of the second metal oxide film should be between 50% and 100%, which is preferable. More preferably 60% to 100%, more preferably 80% to 100%, and even more preferably More specifically, between 90% and 100%, typically 100%. Also, the first metal oxide film The conditions for deposition, such as pressure, temperature, and power, may be different for the first and second metal oxide films. By keeping all conditions except the oxygen flow rate the same, the time required for the film deposition process can be shortened, which is preferable. It's nice.

[0210] This configuration provides a transistor 100 with excellent electrical characteristics and high reliability. This can be achieved.

[0211] As shown in Figures 5A and 5B, the transistor 100 has a conductive layer 12 on an insulating layer 118. It may have conductive layer 0a and conductive layer 120b. Conductive layer 120a and conductive layer 120b are It functions as a drain electrode or a conductive electrode. Conductive layers 120a and 120b are Through the openings 141a or 141b provided in the insulating layer 118, region 10 It is electrically connected to 8N.

[0212] The above is an explanation of Configuration Example 2-1.

[0213] The following describes a transistor configuration example that differs in some aspects from the above configuration example 2-1. Yes. Note that in the following, explanations may be omitted for parts that overlap with the above configuration example 2-1. Furthermore, in the drawings shown below, hatches are used for parts that have the same function as the above-mentioned example configuration. The same pattern may be used, but without a sign.

[0214] [Configuration Example 2-2] Figure 7A is a top view of transistor 100A, and Figure 7B is a top view of transistor 100A. Figure 7C is a cross-sectional view in the channel length direction, while Figure 7C is a cross-sectional view of transistor 100A in the channel width direction. Figure 8A shows an enlarged view of region P enclosed by the dashed line in Figure 7B, and Figure 8B shows an enlarged view of region Q. As shown. An enlarged view of the region R enclosed by the dashed line in Figure 7C is shown in Figure 8C.

[0215] The transistor 100A has an insulating layer 103 and a conductive layer between the substrate 102 and the semiconductor layer 108. It differs from transistor 100 mainly in that it has layer 106. The conductive layer 106 is region It has a region that overlaps with 10⁸C.

[0216] In transistor 100A, the conductive layer 106 is the first gate electrode (bottom gate electrode) The conductive layer 112 functions as a second gate electrode (also called a top gate electrode), and the conductive layer 112 is a second gate electrode (top gate electrode). It functions as a pole (also called a pole). In addition, a part of the insulating layer 103 is the first gate insulating layer In this manner, a portion of the insulating layer 110 functions as a second gate insulating layer.

[0217] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 , it functions as a channel formation region. For the sake of simplicity, the semiconductor layer 10 The portion that overlaps with the conductive layer 112 of 8 is sometimes called the channel-forming region, but in reality it is not conductive Channels can also be formed in the portion that overlaps with the conductive layer 106, without overlapping with layer 112.

[0218] As shown in Figures 7A and 7C, the conductive layer 106 is connected to the insulating layer 110 and the insulating layer 103. The conductive layer 112 may be electrically connected through the provided opening 142. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential.

[0219] The conductive layer 106 is used in the conductive layer 112, conductive layer 120a, or conductive layer 120b. Materials that can be used can be used. In particular, if a material containing copper is used for the conductive layer 106, wiring It is preferable because it can reduce resistance. Also, the conductive layer 106 contains tungsten or molybdenum. Using materials containing high-melting-point metals allows for processing at higher temperatures in subsequent steps. ru.

[0220] As shown in Figures 7A and 7C, in the channel width direction, conductive layer 112 and conductive layer 1 It is preferable that 06 protrudes outward beyond the edge of the semiconductor layer 108. In this case, Figure As shown in 7C, the entire channel width direction of the semiconductor layer 108 is connected to the insulating layer 110 and the insulating layer 1 The structure is covered by conductive layer 112 and conductive layer 106 via 03.

[0221] With this configuration, the semiconductor layer 108 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 106 and the conductive layer 112 are the same It is preferable to apply an electric potential. This induces a channel in the semiconductor layer 108. Because the electric field can be effectively applied, the on-current of the 100A transistor can be increased. Yes, it is possible. Therefore, it becomes possible to miniaturize the 100A transistor.

[0222] Furthermore, the conductive layer 112 and the conductive layer 106 may not be connected. In this case, one pair A constant potential is applied to one of the gate electrodes, and a signal to drive transistor 100A is applied to the other. This may be applied. In this case, the potential applied to one gate electrode will affect transistor 100. The threshold voltage when driving A with the other gate electrode can also be controlled.

[0223] The insulating layer 103 can have a laminated structure. Figures 7B and 7C show the insulating layer 103. From the conductive layer 106 side, the insulating layer 103a, insulating layer 103b, and insulating layer 103c are in this order. This shows an example with a stacked three-layer structure. The insulating layer 103a is in contact with the conductive layer 106. Furthermore, the insulating layer 103c is in contact with the semiconductor layer 108. Regarding the insulating layer 103, please refer to the previous description. Since it can be referenced, a detailed explanation will be omitted.

[0224] Furthermore, a metal film or alloy film that does not easily diffuse into the insulating layer 103 is used as the conductive layer 106. In some cases, the insulating layers 103a and 103b are omitted, and a single layer structure of insulating layer 103c is used. It can be considered a success.

[0225] Transistor 100A has a region where the insulating layer 103c and the insulating layer 118 are in contact. By having a region where the edge layer 103c and the insulating layer 118 are in contact, the acid contained in the insulating layer 118 The element diffuses into the semiconductor layer 108 via the insulating layer 103c, reducing oxygen vacancies in the semiconductor layer 108. It can be reduced.

[0226] The above is an explanation of Configuration Example 2-2.

[0227] [Configuration Example 2-3] Figures 9A to 9C show configurations different from transistor 100A. Figure 9A shows the transistor Figure 9B is a top view of transistor 100B, and Figure 9B is a cross-sectional view of transistor 100B in the channel length direction. Figure 9C is a cross-sectional view of transistor 100B in the channel width direction. Figure 10A shows an enlarged view of the region Q enclosed by the dashed line. The region R enclosed by the dashed line in Figure 9C An enlarged view is shown in Figure 10B. For an enlarged view of the area P enclosed by the dashed line in Figure 9B, refer to Figure 8A. It can illuminate.

[0228] As shown in Figures 10A and 10B, transistor 100B has an insulating layer 118 and an insulating layer It differs primarily from transistor 100A in that it has a region where 103b is in contact. The insulating layer 118 in the region that does not overlap with layer 108 is provided in contact with insulating layer 103c. The edges of the insulating layer 103c roughly coincide with the edges of the semiconductor layer 108. For example, insulating layer 11 When forming 0, a portion of the insulating film that will become the insulating layer 103c is removed to form the insulating layer 103c. This allows the edges of the insulating layer 103c and the semiconductor layer 108 to roughly coincide. .

[0229] The above is an explanation of configuration example 2-3.

[0230] [Configuration Example 2-4] Figure 11A is a cross-sectional view of transistor 100C. In Figure 11A, to the left of the dashed line... The cross-section along the channel length is shown on the side, and the cross-section along the channel width is shown on the right side for clarity.

[0231] Transistor 100C is characterized by having a layered structure in its insulating layer 118, whereas transistor 100 It differs mainly from B. The insulating layer 118 can have a laminated structure of two or more layers. Insulating layer When 118 is considered a laminated structure, it is not limited to a laminated structure made of the same material, but is not limited to a laminated structure made of different materials. A layered structure is also acceptable.

[0232] Figure 11A shows that the insulating layer 118 consists of insulating layer 118a and insulating layer 118b on top of insulating layer 118a. An example of a two-layer structure is shown. The insulating layer 118a and insulating layer 118b are shown as insulating layer 11 Materials that can be used in 8 can be used. Insulating layer 118a and insulating layer 118b The same material may be used, or different materials may be used. Note that the insulating layer 118a and the insulating Since layer 118b can use an insulating film of the same material, insulating layer 118a and insulating layer In some cases, the individual interfaces of 118b may not be clearly visible. Therefore, in Figure 11A, The interface between insulating layer 118a and insulating layer 118b is shown by a dashed line.

[0233] A configuration different from that of transistor 100C is shown in Figures 11B and 11C. Figure 11B is... Figure 11C is a cross-sectional view of transistor 100D. In Figures 11B and 11C, the cross-section in the channel length direction is shown to the left of the dashed line, The cross-sections in the channel width direction are clearly shown side by side on the right.

[0234] Transistors 100D and 100E have insulating layers 118a and 118b This shows a configuration using different materials.

[0235] Transistor 100D has an oxygen barrier property in insulating layer 118a, and insulating layer 118b It shows a higher level of composition. For example, if the insulating layer 118a is made of nitride or nitride oxide Furthermore, an oxide or oxidized nitride can be used for the insulating layer 118b.

[0236] In transistor 100E, the barrier property of the insulating layer 118b against oxygen is such that the insulating layer 118a It shows a higher level of composition. For example, using an oxide or oxiditride in the insulating layer 118a Nitride or nitride oxide can be used for the insulating layer 118b.

[0237] When performing a high-temperature process after forming the insulating layer 118, the outside of the transistor A large amount of oxygen is supplied to region 108N from the membrane in the vicinity of region 108N, and the resistance of region 108N The oxygen may increase. Therefore, when performing processes that involve high temperatures, oxygen It is preferable to process the semiconductor layer 108 with a highly barrier insulating layer. .

[0238] The above is an explanation of Configuration Example 2-4.

[0239] [Configuration Example 2-5] Figure 12 is a cross-sectional view of transistor 100F. In Figure 12, to the left of the dashed line The cross-section in the channel length direction is clearly shown, with the cross-section in the channel width direction placed next to it on the right.

[0240] The transistor 100F has a metal oxide layer 114 between the insulating layer 110 and the conductive layer 112. In this respect, it mainly differs from transistor 100C. For materials that can be used, please refer to the above description, and therefore, a detailed explanation will be omitted.

[0241] Figure 12 shows an example where the edges of the conductive layer 112 and the metal oxide layer 114 roughly coincide. It is formed when the conductive layer 112 is formed, by also forming the metal oxide layer 114. The end of 2 and the end of the metal oxide layer 114 can be roughly aligned. The edges of 2 and the edges of the metal oxide layer 114 do not necessarily coincide. For example, the conductive layer 112 The end of the part may be located inside the end of the metal oxide layer 114.

[0242] The above is an explanation of Configuration Example 2-5.

[0243] [Configuration Example 2-6] Figures 13A to 13C show configurations different from those of transistor 100B. Figure 13A shows... Figure 13B is a top view of transistor 100G, and the channel length direction of transistor 100G is shown. Figure 13C is a cross-sectional view of transistor 100G in the channel width direction. Figure 14 shows an enlarged view of the region P enclosed by the dashed line in 13B.

[0244] As shown in Figures 13B, 13C, and 14, between region 108N and region 108L2, It differs primarily from transistor 100B in that it has region 108L3.

[0245] In Figure 14, the width of region 108C in the channel length direction of transistor 100G is defined as width L. 0, the width of region 108L1 is widthL1, the width of region 108L2 is widthL2, the width of region 108L3 is The width is indicated as L3. Furthermore, the thickness of the insulating layer 110 in the region overlapping with region 108C is defined as thickness TN. 0, the thickness of the insulating layer 110 in the region overlapping with region 108L1 is thickness TN1, and region 108L2 is The thickness of the insulating layer 110 in the overlapping region is thickness TN2, and the insulating layer 1 in the overlapping region of region 108L3 The film thickness of 10 is indicated by the film thickness TN3.

[0246] It is preferable that the film thickness TN0 is approximately equal to the film thickness TN1. The film thickness TN2 is preferably 0.2 times or more and 0.9 times or less, and more preferably 0.3 times or more and 0.8 times or less. This is preferable, and more preferably 0.4 times or more and 0.7 times or less. Film thickness relative to film thickness TN1 TN3 is preferably 0.1 times or more and 0.6 times or less, and more preferably 0.15 times or more and 0.5 times or less. Preferably, the film thickness is between 0.2 and 0.4 times. This allows us to control the resistance in regions 108L1, 108L2, and 108L3.

[0247] Widths L1, L2, and L3 are preferably 50 nm or more and 1 μm or less, and furthermore A range of 70 nm to 700 nm is preferred, and a range of 100 nm to 500 nm is even more preferred. In particular, the sum of widths L1, L2, and L3 should be greater than the thickness of the insulating layer 110. This effectively suppresses the concentration of the electric field near the drain. On the other hand, width L1, If the sum of widths L2 and L3 is greater than 2 μm, the source-drain resistance increases, and traction increases. The drive speed of the inverter may be slow. Widths L1, L2, and L3 are within the aforementioned ranges. This allows for the creation of highly reliable and fast-acting transistors and semiconductor devices. It can be done. Note that widths L1, L2, and L3 are the thickness of the semiconductor layer 108 and the insulating layer 11, respectively. Thickness 0, magnitude of the voltage applied between the source and drain when driving transistor 100 It can be decided accordingly.

[0248] The first side surface 110S1, the second side surface 110S2, and the third side surface of the insulating layer 110 Each of the 110S3 preferably has a tapered shape. The first side surface 110S1, the The second side 110S2 and the third side 110S3 have a tapered shape, providing insulation. The coverage of the layer formed on layer 110 (for example, the insulating layer 118) is improved, and the layer does not break down or crack. This can suppress the occurrence of defects such as porosity.

[0249] Figure 14 shows the angle between the surface to which the lower end of the first side surface 110S1 abuts and the first side surface 110S1. An angle θ1 between the surface to which the lower end of the second side surface 110S2 touches and the second side surface 110S2. 2, and the angle θ between the surface to which the lower end of the third side surface 110S3 is in contact and the third side surface 110S3 The third example is shown. Angles θ1, θ2, and θ3 are preferably between 30 degrees and 90 degrees. Furthermore, a temperature of 35 degrees or more and 85 degrees or less is preferable, and even more preferably 40 degrees or more and 80 degrees or less. Furthermore, an angle of 45 degrees or more and 75 degrees or less is preferable. By setting the angle within the aforementioned range, the insulating layer The covering properties of the insulating layer 118 provided on 110 can be improved.

[0250] The angles θ1, θ2, and θ3 shown in Figure 14 will be explained. Angle θ1 is the first The upper surface of the insulating layer 110 that the lower end of the side surface 110S1 is in contact with is an extended surface into the interior of the insulating layer 110. This is the angle formed by the first side surface 110S1. The angle θ2 is the lower end of the second side surface 110S2. The upper surface of the insulating layer 110 that is in contact with the second side surface 110S is an extended surface in the interior of the insulating layer 110. This is the angle formed by 2. The angle θ3 is formed by the bottom surface of the insulating layer 110 and the third side surface 110S3. These are angles. Angles θ1, θ2, and θ3 are preferably between 30 degrees and 90 degrees. Furthermore, a temperature of 35 degrees or more and 85 degrees or less is preferable, and a temperature of 40 degrees or more and 80 degrees or less is preferable. Furthermore, an angle of 45 degrees or more and 75 degrees or less is preferable. By setting the angle within the aforementioned range, insulation The covering properties of the insulating layer 118 provided on layer 110 can be improved.

[0251] The above is an explanation of Configuration Example 2-6.

[0252] <Example of manufacturing method 1> The following describes a method for manufacturing a semiconductor device according to one aspect of the present invention, with reference to the drawings. Here, we will explain using transistor 100C, which was exemplified in the above configuration example, as an example.

[0253] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Methods include chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition. It can be formed using deposition (ALD) methods, etc. CVD is a method of plasma chemical vapor deposition (PECV). Method D) and thermal CVD are examples. One of the thermal CVD methods is organometallic vapor deposition. There is also the (MOCVD: Metal Organic CVD) method.

[0254] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are coated using spin coating, DITCH. Printing methods: spray coating, inkjet, dispensing, screen printing, offset printing. Doctor's knife coat, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by law.

[0255] When processing thin films that make up semiconductor devices, photolithography and other methods are used for processing. It can be done. In addition, thinning can be achieved using methods such as nanoimprint lithography, sandblasting, and lift-off lithography. The film may be processed. Alternatively, a film deposition method using a shielding mask such as a metal mask can be used to form the island. A thin film in this form may be formed directly.

[0256] There are two main methods of photolithography. One is to process the thin material to be processed. A resist mask is formed on the film, and the thin film is processed by etching or the like, One method is to remove the blemishes. Another method is to deposit a photosensitive thin film, then expose it to light and develop it. This method involves performing a certain operation to process the thin film into a desired shape.

[0257] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Then, using extreme ultraviolet (EUV) light and X-rays... It is also possible to use an electron beam instead of light for exposure. Extreme ultraviolet Using light, X-rays, or electron beams is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is unnecessary.

[0258] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0259] Figures 15A to 15D, 16A to 16C, 17A to 17C, 18A to Each figure in Figure 18C shows a cross-section at each stage of the manufacturing process of transistor 100C. In each figure, the cross-section is shown in the channel length direction to the left of the central dashed line and in the channel width direction to the right. They are shown side by side.

[0260] [Formation of conductive layer 106] A conductive film is formed on the substrate 102, and this is processed by etching to form the first gate electrode. A conductive layer 106 is formed that functions as follows. At this time, the end of the conductive layer 106 is tapered and It is preferable to process it in such a way. This will result in a stepped coating of the insulating layer 103 to be formed next. It can enhance sexual performance.

[0261] Furthermore, by using a conductive film containing copper as the conductive film that forms the conductive layer 106, the wiring resistance can be reduced. It can be made smaller. For example, a semiconductor device according to one aspect of the present invention can be used in a large display device. When applying this technology, or when creating a high-resolution display device, a conductive film containing copper may be used. Preferred. Also, even if a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 This suppresses the diffusion of copper towards the semiconductor layer 108, thus enabling highly reliable transients. It can be achieved.

[0262] [Formation of insulating layer 103] Next, an insulating layer 103 is formed by covering the substrate 102 and the conductive layer 106 (Figure 15A). The insulating layer 103 can be formed using methods such as PECVD, ALD, or sputtering.

[0263] Here, the insulating layer 103 is defined as insulating layer 103a, insulating layer 103b, and insulating layer 103 c is formed by laminating layers. In particular, each insulating layer constituting the insulating layer 103 is formed by the PECVD method. It is preferable to form it in this way. For the formation of the insulating layer 103, refer to the description in the above-mentioned Configuration Example 1. Therefore, a detailed explanation will be omitted.

[0264] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment can be performed in an oxygen atmosphere. Alternatively, oxygen can be supplied to the insulating layer 103 by plasma ion doping or ion implantation. That's fine.

[0265] [Formation of semiconductor layer 108] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is formed on the insulating layer 103. Figure 15B).

[0266] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0267] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f has impurities such as hydrogen and water reduced as much as possible, resulting in a high-purity film. It is preferable that the metal oxide film 108f is a crystalline metal oxide. It is preferable to use a membrane.

[0268] When forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helium gas) are used. (For example, argon gas, xenon gas, etc.) may be mixed in. The higher the proportion of oxygen gas in the total film-forming gas (hereinafter also called the oxygen flow rate ratio), This allows for improved crystallinity of metal oxide films, enabling the realization of highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the ON current. It can be configured as a lunger.

[0269] When the semiconductor layer 108 is in a stacked structure, the same sputtering target is used to achieve the same result Continuous film deposition in the film chamber is preferable because it allows for a good interface. Furthermore, the conditions for forming each metal oxide film were varied, including pressure, temperature, and power during film formation. While this is also acceptable, keeping all conditions except the oxygen flow rate ratio the same can shorten the time required for the film deposition process. Therefore, it is preferable. Also, when laminating metal oxide films of different compositions, exposure to the atmosphere is preferable. It is preferable to deposit the film continuously without interruption.

[0270] The metal oxide film 108f is a metal oxide film having a CAAC structure, and a metal having an nc structure. The film is deposited to form an oxide film, or a metal oxide film in which CAAC and nc structures are mixed. It is preferable to set conditions. The film conditions and the deposition conditions for the nc structure depend on the sputtering target used. Because it varies depending on the composition, the substrate temperature, oxygen flow rate ratio, pressure, and power must be considered according to the composition. You can set these as appropriate.

[0271] The substrate temperature during the deposition of the metal oxide film 108f is preferably above room temperature and below 450°C, and further The temperature is preferably above room temperature and below 300°C, and more preferably above room temperature and below 200°C, and further A temperature of room temperature or higher and 140°C or lower is preferred. For example, a large glass substrate or a resin substrate on the substrate 102. When using a board, productivity is higher and preferred if the substrate temperature is above room temperature but below 140°C. Furthermore, the metal oxide film is formed with the substrate at room temperature or without heating. This allows for a reduction in crystallinity.

[0272] Before forming the metal oxide film 108f, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a process to detach materials or to supply oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C to 200°C under reduced pressure. Yes, it is possible. Alternatively, plasma treatment may be performed in an oxygen-containing atmosphere. For example, by performing plasma treatment in an atmosphere containing nitrous oxide gas, the insulating layer 103 It can supply oxygen. Also, plasma processing can be performed in an atmosphere containing nitrous oxide gas. This process effectively removes organic matter from the surface of the insulating layer 103. After this treatment, the insulating layer To continuously deposit a metal oxide film 108f on the surface of 103 without exposing it to the atmosphere. It is preferable.

[0273] Next, the metal oxide film 108f is processed to form island-shaped semiconductor layers 108 (Figure 15C). ).

[0274] For processing the metal oxide film 108f, wet etching and dry etching methods are used. Either one or both of the offsets may be used. In this case, the insulating layer 1 that does not overlap with the semiconductor layer 108 A portion of 03c may be etched and removed. Therefore, the semiconductor layer 108 and the insulating layer 103c have roughly the same top surface shape. By removing a portion of 3c, a portion of the insulating layer 103b is exposed, and the insulating layer that is later formed... The configuration can be such that 118 and the insulating layer 103b are in contact.

[0275] After the metal oxide film 108f is formed, or after the metal oxide film 108f is processed into a semiconductor layer 108 Afterward, heat treatment is performed to remove hydrogen or water from the metal oxide film or semiconductor layer 108. This may be done. By heat treatment, the metal oxide film 108f or semiconductor layer 108 contains It can remove hydrogen or water that has been absorbed or adsorbed on the surface. Also, by heat treatment This improves the film quality of the metal oxide film 108f or semiconductor layer 108 (for example, by reducing defects). (This can sometimes lead to improved crystallinity, etc.)

[0276] Heat treatment causes the metal oxide film 108f or the semiconductor layer 108 to be converted from the insulating layer 103 by acid It is also possible to supply oxygen. When oxygen is supplied from the insulating layer 103, it is added to the semiconductor layer 108. It is more preferable to perform a heat treatment before processing.

[0277] The heat treatment temperature is typically 150°C or higher but below the substrate's strain point, or 250°C or higher. The temperature can be 450°C or lower, or 300°C to 450°C. After the film 108f is formed, or after the metal oxide film 108f is processed into a semiconductor layer 108, Heat treatment is not required. Furthermore, heat treatment can be performed at any stage after the formation of the metal oxide film. It may be done. It may also be combined with a subsequent heat treatment or process that involves applying heat.

[0278] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. After heating with gas, it may be heated in an oxygen-containing atmosphere. Or in a nitrogen-containing atmosphere, or an oxygen-containing atmosphere. As the atmosphere, extremely dry air (CDA: Clean Dry Air) may be used. Furthermore, it is preferable that the atmosphere used for the above heat treatment does not contain hydrogen, water, etc. The dew point is -60. By using a gas purified to a temperature of -100°C or lower, preferably -100°C or lower, the semiconductor layer 10 This process prevents hydrogen, water, etc. from being incorporated into the 8th as much as possible. The heating treatment is performed by an electric Steam furnaces, rapid thermal annealing (RTA) equipment, etc. It can be used. By using an RTA device, the heat treatment time can be shortened.

[0279] Furthermore, it is preferable to quickly form the insulating film 110f after the formation of the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed onto the surface of the semiconductor layer 108. Yes. When water is adsorbed on the surface of the semiconductor layer 108, subsequent heat treatment etc. can cause the semiconductor layer 10 Hydrogen diffuses into 8, V O H may be formed. O H can be a carrier source. Therefore, it is preferable that the amount of adsorbed water in the semiconductor layer 108 is small.

[0280] [Formation of insulating film 110f] Next, the insulating layer 103 and the semiconductor layer 108 are covered to form an insulating film 110f (Figure 1). 5D).

[0281] The insulating film 110f is a film that will later become the insulating layer 110. The insulating film 110f is, for example, oxidized. Oxide films or oxiditride films such as silicon films and silicon oxiditride films are subjected to plasma chemical processes. Formed using a phase deposition apparatus (also known as a PECVD apparatus or plasma CVD apparatus). This is preferable. Alternatively, it may be formed using a microwave-based PECVD method.

[0282] After forming the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, the insulating film Impurities in 110f and adsorbed water on the surface of the insulating film 110f can be removed. Heat treatment is performed using nitrogen, The process is carried out in an atmosphere containing oxygen and one or more noble gases, at a temperature between 200°C and 400°C. This is possible. Furthermore, heat treatment is not required after the formation of the insulating film 110f. Also, The heat treatment may be performed at any stage after the formation of the insulating film 110f. This process may be combined with a process involving the application of heat or chemicals.

[0283] Plasma treatment is performed on the surface of the semiconductor layer 108 before the deposition of the insulating film 110f. This is preferable. The plasma treatment adsorbs impurities such as water onto the surface of the semiconductor layer 108. This can reduce the amount of noise at the interface between the semiconductor layer 108 and the insulating film 110f. Because impurities can be reduced, highly reliable transistors can be realized. In particular, semiconductor layer 10 Between the formation of 8 and the deposition of the insulating film 110f, the surface of the semiconductor layer 108 is exposed to the atmosphere. Plasma treatment is preferable in certain cases. For example, oxygen, ozone, nitrogen, nitrous oxide, aluminum It can be carried out in an atmosphere such as GON. Also, plasma treatment and deposition of insulating film 110f It is preferable that this process be carried out continuously without exposure to the atmosphere.

[0284] Here, it is preferable to perform a heat treatment after forming the insulating film 110f. Therefore, to remove hydrogen or water contained in the insulating film 110f or adsorbed on its surface. This can be achieved. Furthermore, defects in the insulating film 110f can be reduced.

[0285] The conditions for heat treatment can be based on the above.

[0286] After forming the insulating film 110f, or after performing a heat treatment to remove the above-mentioned hydrogen or water Afterward, a process of supplying oxygen to the insulating film 110f may be performed. For example, plasma Plasma treatment or heat treatment can be performed in an oxygen-containing atmosphere. Oxygen can be supplied to the insulating film 110f by methods such as ion doping or ion implantation. For plasma treatment, for example, a PECVD apparatus can be suitably used. When forming the insulating film 110f using apparatus D, after forming the insulating film 110f, in a vacuum It is preferable to perform plasma processing continuously. Formation of insulating film 110f and plasma processing Performing the process continuously in a vacuum can increase productivity.

[0287] If a heat treatment is performed after supplying oxygen to the insulating film 110f, then the insulating film 11 It is preferable to perform the heat treatment after a film (for example, a metal oxide film 114f) has been formed on 0f. It is so. When the insulating film 110f is exposed and heat treatment is performed, the insulating film 110f is supplied with In some cases, oxygen may detach from the insulating film 110f. For example, by performing a heat treatment after the metal oxide film 114f) is formed, the insulating film 110f This prevents the supplied oxygen from detaching from the insulating film 110f.

[0288] [Formation of opening 142] Next, the insulating layer 110 and a portion of the insulating layer 103 are removed, creating an opening that reaches the conductive layer 106. A section 142 is formed (Figure 16A). This allows the conductive layer 106 to be connected through the opening 142. It can be electrically connected to the conductive layer 112 that will be formed later.

[0289] [Formation of conductive film 112f] Next, a conductive film 112f, which will become the conductive layer 112, is deposited (Figure 16B). Conductive film 112f This involves forming a thin film using a sputtering method with a metal or alloy sputtering target. It is preferable to do so.

[0290] [Formation of insulating layer 110 and conductive layer 112] Next, a resist mask 115 is formed on the conductive film 112f (Figure 16B). After that, Remove the conductive film 112f in the area not covered by the resist mask 115, and the conductive layer 112 Form (Figure 16C).

[0291] A wet etching method can be suitably used to form the conductive layer 112. For example, an etchant containing hydrogen peroxide can be used in the etching method. For example, using an etchant having one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid. This is possible. In particular, when using a material having copper in the conductive layer 112, phosphoric acid, acetic acid and nitric acid are used. An etchant having the following properties can be suitably used.

[0292] As shown in Figure 16C, the edge of the conductive layer 112 is inside the contour of the resist mask 115. The material is processed to be positioned on the side. A wet etching method is used to form the conductive layer 112. This is preferable. By adjusting the etching time, the width L0 of region 108C can be controlled. ru.

[0293] The conductive layer 112 is formed using different etching conditions or methods, at least twice. It may be etched in separate steps. For example, the conductive film 112f can be etched using an anisotropic etching method. After etching, the sides of the conductive film 112f are etched using an isotropic etching method. The end face may be recessed (also called side etching). This results in a plan view. This allows for the formation of a conductive layer 112 located inside the insulating layer 110.

[0294] Next, the insulating film 110f is removed in the region not covered by the resist mask 115. Then, an insulating layer 110A is formed (Figure 17A). Anisotropic etching is used to form the insulating layer 110A. It is preferable to use etching. In particular, a dry etching method can be suitably used. By using the dry etching method, the edges of the resist mask 115 and the insulating layer 110 The ends of A can be roughly aligned.

[0295] Next, the resist mask 115 is reduced in size to form the resist mask 115a (Figure 1). 7B). Figure 17B shows the resist mask 115a after reduction, along with the mask before reduction. The resist mask 115 is shown by a dashed line. The edges of the resist mask 115a are the conductive layer It is preferable that it be located outside the edge of 112. That is, the edge of the resist mask 115a. The part is preferably located between the end of the conductive layer 112 and the end of the insulating layer 110A.

[0296] For the formation of the resist mask 115a, the ashing method can be suitably used. For example, For example, as an ashing method, gases such as oxygen and ozone are turned into plasma using high-frequency waves, and then... A plasma ashing method may be used, which involves reacting the resist mask with a plasma. Alternatively, light such as ultraviolet light is irradiated onto gases such as oxygen and ozone to observe the reaction between the gas and the resist mask. Photo-excitation ashing may be used to promote this process. As the area of ​​the resist mask 115 in plan view decreases, the resist mask 11 The film thickness of layer 5 may be reduced.

[0297] Next, in the region not covered by the resist mask 115a, one of the insulating layers 110A The part is removed and an insulating layer 110 is formed (Figure 17C). Anisotropic e It is preferable to use etching. In particular, a dry etching method can be suitably used. In this case, the entire exposed area of ​​the insulating layer 110A is not removed, and the insulating layer 1 in that area is removed. By removing a portion of the upper part of 10A (hereinafter also referred to as half-etching), the film thickness is reduced. It is preferable to process it in such a way. In this way, the resist mask used for processing the insulating layer By reducing the size and then processing the insulating layer again using the reduced resist mask, An insulating layer 110 having a stepped shape can be formed. Also, the amount by which the resist mask is reduced can be adjusted. By adjusting it, the width L2 of region 108L2 can be controlled.

[0298] Since half-etching is used to form the insulating layer 110, the insulating layer 110A is formed in advance. Check the etching rate of the film and calculate the etching time required to reach the desired film thickness TN2. It is preferable to leave it as is. By performing half etching with the calculated etching time, the absolute The edge layer 110 can be formed with high precision. Furthermore, a dry etching method is used to form the insulating layer 110. This allows for fine adjustment of the film thickness TN2, resulting in good electrical characteristics and high reliability. It can be made into a transistor.

[0299] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0300] Here, cleaning may be performed to remove impurities. By performing cleaning, the insulating layer 1 To remove impurities adhering to the exposed areas of 10 and semiconductor layer 108, the electrical properties of the transistor This can suppress the deterioration of characteristics and reliability. Impurities, for example, are etched into the insulating film 110f. The etching gas or etchant components that adhere during etching, or the conductive film 112f These include the components of the metal oxide film 114f, etc.

[0301] The cleaning method may involve wet cleaning using a cleaning solution, or plasma treatment. Yes, it is possible. These cleaning methods may also be combined as appropriate. Wet cleaning is done by Shuu A cleaning solution containing acid, phosphoric acid, ammonia water, or hydrofluoric acid can be used. .

[0302] [Formation of insulating layer 118] Next, the insulating layer 103, semiconductor layer 108, insulating layer 110 and conductive layer 112 are covered, An edge layer 118 is formed. Here, the insulating layer 118 consists of insulating layer 118a and insulating layer 118b A configuration having a layered structure will be described.

[0303] The insulating layer 103, semiconductor layer 108, insulating layer 110, and conductive layer 112 are covered by the insulating layer 11 Formation of 8a (Figure 18A).

[0304] The insulating layer 118a is formed by a plasma CVD method using a hydrogen-containing film-forming gas. This is preferable. For example, using a film-forming gas containing silane gas and ammonia gas, silane nitride A film is formed. By using ammonia gas in addition to silane gas, a large amount of water is deposited in the film. It is possible to include elements. Also, even during film formation, the exposed portion of the semiconductor layer 108 It becomes possible to supply hydrogen to the semiconductor layer 108. A low-resistance region of 10⁸N can be formed.

[0305] Next, using the conductive layer 112 as a mask, semiconductors are transmitted through the insulating layer 110 and insulating layer 118a. The first element 140 is supplied (also called added or injected) to body layer 108 (Figure 18B). By supplying the first element 140 to the semiconductor layer 108, the area not covered by the conductive layer 112 The resistance of the semiconductor layer 108 in region 108L1, region 108L2 and region 108N decreases, This can be formed on region 108L1, region 108L2, and region 108N. The total film thickness of the applied insulating layer 118a and insulating layer 110 is in region 108L1, region 108 The regions become thinner in the order of L2 and then 108N. Therefore, the regions are 108L1, 108L2, and In the range of 108N, the amount of the first element 140 supplied increases, and the resistance decreases in this order. This is possible. The film thickness of the insulating layer 110, the film thickness of the insulating layer 118a, and the first element 140 By adjusting the supply conditions, regions 108L1, 108L2, and 108 Each of the N resistors can be controlled.

[0306] The first element 140 is formed in the region 108C of the semiconductor layer 108 that overlaps with the conductive layer 112. To prevent the supply from being incomplete, the material and thickness of the conductive layer 112 are taken into consideration when supplying the first element 140. It is preferable to determine the conditions under which the semiconductor layer 108 overlaps with the conductive layer 112. A region 108C with a sufficiently reduced impurity concentration can be formed within the region.

[0307] For the elements that can be used as the first element 140, please refer to the description above. Therefore, a detailed explanation will be omitted.

[0308] The supply of the first element 140 can be suitably performed using plasma processing. When using this method, a plasma is generated in a gas atmosphere containing the first element 140 to be added. The first element, 140, can be added by performing plasma treatment. Equipment used to generate this includes dry etching equipment, ashing equipment, and plasma CVD equipment. High-density plasma CVD equipment can be used.

[0309] The supply of the first element 140 is continuous without exposure to the atmosphere after forming the insulating layer 118a. This may be done by using a plasma CVD apparatus to form the insulating layer 118a. Subsequently, a continuous supply of the first element 140 can be provided without exposure to the atmosphere. By doing so, the productivity of semiconductor equipment can be increased.

[0310] When performing plasma processing, the gas supplied with the first element 140 contains the first element. A gas can be used. It is particularly preferable to use a gas containing hydrogen, in the region 108L. 1. By adding hydrogen to regions 10⁸L2 and 10⁸N, the resistance of each region is controlled. This is possible. Examples of gases containing the first element 140 include hydrogen (H2) and ammonia. (NH3) and silane (SiH4) can be preferably used.

[0311] The substrate temperature during plasma treatment is preferably above room temperature and below 450°C, and more preferably below 150°C. Preferably, the temperature is 400°C or lower, and more preferably 200°C to 350°C. By setting the substrate temperature to this, the reaction between the material constituting the semiconductor layer 108 and the first element 140 occurs This facilitates and lowers the resistance of the semiconductor layer 108.

[0312] The pressure inside the processing chamber during plasma processing is preferably between 50 Pa and 1500 Pa, and further Preferably, the pressure is between 100 Pa and 1000 Pa, and more preferably between 120 Pa and 500 Pa. The lower limit is preferable, and more preferably 150 Pa to 300 Pa. The pressure within the aforementioned range and This allows for the stable generation of plasma.

[0313] By appropriately selecting the plasma treatment conditions, the first element added to the semiconductor layer 108 The amount of element 140 can be adjusted to control the resistance value. Also, the first element 140 is... Since it is added to the semiconductor layer 108 via the insulating layer 118a and the insulating layer 110, It is preferable to adjust the thickness of the insulating layer 118a and the insulating layer 110 so that they act as resistance. It's nice.

[0314] Alternatively, the supply of the first element 140 may be by heating using a gas containing the first element 140. A process utilizing thermal diffusion may also be used.

[0315] Alternatively, the supply of the first element 140 may be by plasma ion doping or ion implantation. Methods may also be used. These methods determine the concentration profile in the depth direction, and the ion acceleration voltage. It can be controlled with high precision by adjusting the dose amount, etc. Plasma ion doping method By using it, productivity can be increased. Also, by using ion implantation using mass separation By doing so, the purity of the first element being supplied can be increased. Also, the first element 140 As such, one or more of boron, phosphorus, aluminum, magnesium, or silicon are preferred. It can be used appropriately.

[0316] In the supply process of the first element 140, at the interface between the semiconductor layer 108 and the insulating layer 110, This refers to the portion of the semiconductor layer 108 that is close to the interface, or the portion of the insulating layer 110 that is close to the interface. However, it is preferable to control the processing conditions so that the highest concentration is achieved. This process supplies both the semiconductor layer 108 and the insulating layer 110 with the first element 140 at an optimal concentration. It is possible.

[0317] When using plasma ion doping or ion implantation, the first element 140 is A gas containing the aforementioned first element can be used as the supplied gas. Boron is supplied. In such cases, B2H6 gas or BF3 gas can typically be used. Also, phosphorus When supplying, pH3 gas can typically be used. Also, these raw material gases A mixed gas obtained by diluting the first element 140 with a noble gas may also be used. As for the components, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2 HF, H2, (C5H5)2Mg, and noble gases can be used. The source is not limited to gases; solids or liquids that have been heated and vaporized may also be used.

[0318] The addition of the first element 140 affects the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108. By taking these factors into consideration and setting conditions such as acceleration voltage and dose amount, it can be controlled.

[0319] For example, when adding boron using ion implantation or plasma ion doping, The acceleration voltage is, for example, 5kV to 100kV, preferably 7kV to 70kV, Preferably, the voltage can be in the range of 10kV to 50kV. Also, the dose amount is, for example... ba 1 × 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 ×10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More convenient 1 ×10 15 ions / cm 2 The above is 3 x 10 16 ions / cm 2 The following range It is possible.

[0320] Furthermore, when adding phosphorus ions using ion implantation or plasma ion doping: The acceleration voltage is, for example, 10kV or more and 100kV or less, preferably 30kV or more and 90kV or less. The voltage can be more preferably in the range of 40kV to 80kV. For example, 1 × 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following are preferred Or 1 x 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following are more preferred Or 1 x 10 15 ions / cm 2 The above 3 x 10 16 ions / cm 2 The following range It is possible.

[0321] In one aspect of the present invention, the first element 140 is distributed through the insulating layer 110 and the insulating layer 118a. It can be supplied to the conductive layer 108. Therefore, if the semiconductor layer 108 has crystalline properties Even so, the damage to the semiconductor layer 108 during the supply of the first element 140 is reduced. This suppresses the loss of crystallinity. Therefore, the electrical resistance is reduced due to the decrease in crystallinity. This is suitable in cases where the value increases significantly.

[0322] Here, after forming the insulating layer 118a, the first element 140 is supplied to the semiconductor layer 108. Although a manufacturing method has been shown, the present invention is not limited thereto. Forming an insulating layer 118a The first element 140 may be supplied to the semiconductor layer 108 beforehand. Alternatively, an insulating layer 118b may be formed. The first element 140 may then be supplied to the semiconductor layer 108.

[0323] Next, insulating layer 118b is formed by covering insulating layer 118a (Figure 18C).

[0324] Formation of insulating layer 118a, supply of first element 140, and formation of insulating layer 118b By using a CVD apparatus, these processes can be carried out continuously. By processing continuously in a Zuma CVD apparatus, the insulating layer 118a and the insulating layer 118b This can suppress the adhesion of impurities to the interface. Furthermore, it can increase the productivity of semiconductor devices. Cut.

[0325] When forming the insulating layer 118 by plasma CVD, if the deposition temperature is too high, region 1 Depending on the impurities contained in 08N, etc., these impurities may diffuse into the peripheral area including region 108C. There is a risk that the resistance in region 108C may decrease, or the resistance in region 108N may decrease. There is a risk that the temperature may rise. The film deposition temperature of the insulating layer 118 is, for example, 150°C or higher. Preferably below 0°C, more preferably between 180°C and 360°C, and even more preferably 200°C It is preferable to keep the temperature below 250°C. By forming the insulating layer 118 at a low temperature, Even transistors with short channel lengths can be given good electrical characteristics.

[0326] Heat treatment may be performed after the formation of the insulating layer 118.

[0327] [Formation of openings 141a and 141b] Next, by removing a portion of the insulating layer 118, an opening 141a reaches region 108N. And an opening 141b is formed.

[0328] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is applied to the insulating layer 118 so as to cover the openings 141a and 141b. By forming a film and processing the conductive film, conductive layers 120a and 120b are formed. Figure 11A).

[0329] By following the above steps, transistor 100C can be manufactured.

[0330] <Example of manufacturing method 2> In the following example, a metal is placed between the conductive layer 112 and the insulating layer 110, as illustrated by transistor 100F. The explanation will be given using a configuration having an oxide layer 114 as an example.

[0331] The process up to the formation of the insulating film 110f is the same as in the aforementioned <Fabrication Method Example 1> (Figure 1). (See Figures 5A to 15D).

[0332] [Formation of metal oxide film 114f] Next, the insulating film 110f is covered to form a metal oxide film 114f (Figure 19A).

[0333] The metal oxide film 114f is a film that will later become the metal oxide layer 114. 4f is preferably formed by sputtering in an atmosphere containing oxygen, for example. This allows oxygen to be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0334] The metal oxide film 114f is made of an oxide containing the same metal oxide as in the case of the semiconductor layer 108. The above can be applied when forming using a sputtering method with a target.

[0335] The metal oxide film 114f was formed using oxygen as the deposition gas and a reactive spalling process using a metal target. A metal oxide film may be formed by a tarring method. When used, it can form an aluminum oxide film.

[0336] When forming the metal oxide film 114f, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is The higher the ratio of oxygen flow rate (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more insulating layer 1 It is preferable to increase the amount of oxygen supplied to 10. The oxygen flow rate ratio or oxygen partial pressure is For example, higher than 0% and 100% or less, preferably 10% or more and 100% or less, more preferably is 20% or more and 100% or less, more preferably 30% or more and 100% or less, even more preferably The oxygen flow rate ratio should be between 40% and 100%. In particular, the oxygen flow rate ratio should be 100%, and the oxygen partial pressure should be 100%. It is preferable to get as close as possible to it.

[0337] In this way, a metal oxide film 114f is formed by sputtering in an oxygen-containing atmosphere. This allows oxygen to be supplied to the insulating film 110f during the formation of the metal oxide film 114f. At the same time, it is possible to prevent oxygen from detaching from the insulating film 110f. As a result, insulation A very large amount of oxygen can be trapped in the 110f membrane. And, through subsequent heat treatment... As a result, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, This reduces oxygen deficiency and enables the creation of highly reliable transistors.

[0338] The substrate temperature during the deposition of the metal oxide film 114f is preferably above room temperature and below 450°C, and further The temperature is preferably above room temperature and below 300°C, and more preferably above room temperature and below 200°C, and further A temperature of room temperature or higher and 140°C or lower is preferred. For example, a large glass substrate or a resin substrate on the substrate 102. When using a board, productivity is higher and preferred if the substrate temperature is above room temperature but below 140°C. Furthermore, if the substrate temperature is high during the deposition of the metal oxide film 114f, the metal oxide film 114f Increased crystallinity can lead to slower etching rates. Metal oxides may also be present at lower substrate temperatures. The crystallinity of film 114f may decrease, which can lead to a faster etching rate. To achieve the desired etching speed for the etchant used when processing 14f, The deposition temperature for the metal oxide film 114f may be selected as appropriate.

[0339] After the formation of the metal oxide film 114f, a heat treatment is performed to convert the insulating film 110f into a semiconductor. Oxygen may be supplied to layer 108. The heat treatment includes one or more of nitrogen, oxygen, and noble gases. This can be carried out under controlled conditions at a temperature between 200°C and 400°C. Heat treatment is not required after the formation of film 114f. It can be done at any stage after the 14f film deposition. Also, subsequent heat treatment or heat application It can be combined with the process.

[0340] [Formation of opening 142] Next, remove the metal oxide film 114f, the insulating layer 110f, and a portion of the insulating layer 103. An opening 142 is formed that reaches the conductive layer 106. This allows the conductive layer to enter through the opening 142. The layer 106 and the conductive layer 112, which will be formed later, can be electrically connected.

[0341] [Formation of conductive film 112f] Next, a conductive film 112f, which will become the conductive layer 112, is deposited (Figure 19B). Conductive film 112f Since details can be found in the previous section, a detailed explanation will be omitted.

[0342] [Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112] Next, a resist mask (not shown) is formed on the conductive film 112f, and the resist mask Remove the conductive film 112f and metal oxide film 114f in the areas not covered by the conductive layer 1 Forms 12 and a metal oxide layer 114 (Figure 19C).

[0343] A wet etching method is preferably used to form the conductive layer 112 and the metal oxide layer 114. This is possible. For details on the wet etching method, please refer to the description above. I will omit the explanation.

[0344] Different etching conditions or methods are used to form the conductive layer 112 and the metal oxide layer 114. And, etching may be done in at least two separate steps. For example, an anisotropic etching method After etching the conductive film 112f and the metal oxide film 114f using this method, an isotropic etching is performed. The sides of the conductive film 112f and the metal oxide film 114f are etched using the etching method, and the end faces The side may be recessed (also called side etching). This provides insulation in a plan view. A conductive layer 112 and a metal oxide film 114 can be formed located inside layer 110.

[0345] Next, in the area not covered by the resist mask, the insulating film 110f is removed, and the saturates... A marginal layer 110 is formed (Figure 19D). For details on the formation of the insulating layer 110, please refer to the previous description. Therefore, a detailed explanation will be omitted.

[0346] After the insulating layer 110 is formed, the resist mask is removed.

[0347] Washing may be performed here to remove impurities. Refer to the above description for details on washing. Since it can be understood by looking at the image, a detailed explanation will be omitted.

[0348] From this point onward, the steps after the formation of the insulating layer 118 can be described in <Example of Manufacturing Method 1>. Details will be omitted.

[0349] By following the above steps, transistor 100F can be manufactured.

[0350] <Example of manufacturing method 3> In the following example using transistor 100G, between region 108N and region 108C, This will be explained using a configuration having region 108L1, region 108L2, and region 108L3 as an example. .

[0351] The process up to forming the insulating layer 110A is the same as in the aforementioned <Example of Manufacturing Method 1> (Figure 1). (See Figures 5A to 15D, Figures 16A to 16C, and Figure 17A).

[0352] [Formation of insulating layer 110] Next, the resist mask 115 is reduced in size to form the resist mask 115a (Figure 2). 0A). Figure 20A shows the resist mask 115a after reduction, along with the mask before reduction. The resist mask 115 is shown by a dashed line. The edges of the resist mask 115a are the conductive layer It is preferable that it be located outside the edge of 112. That is, the edge of the resist mask 115a. The part is preferably located between the end of the conductive layer 112 and the end of the insulating layer 110A.

[0353] The ashing method can be suitably used to form the resist mask 115a. By using the SING method, the area of ​​the resist mask 115 in plan view becomes smaller. In both cases, the film thickness of the resist mask 115 may be reduced.

[0354] Next, in the region not covered by the resist mask 115a, on the insulating layer 110A A portion of the material is removed to form an insulating layer 110B (Figure 20B). It is preferable to use anisotropic etching. In particular, dry etching is preferably used. It is possible.

[0355] Next, the resist mask 115a is reduced in size to form the resist mask 115b (Figure 20C). Figure 20C shows the reduced resist mask 115b along with the reduced resist mask 115b. The previous resist mask 115a is shown by a dashed line. The edges of resist mask 115b are It is preferable that it be located outside the edge of the electrode layer 112. In other words, the resist mask 115b The end of the component is preferably located between the end of the conductive layer 112 and the end of the insulating layer 110B.

[0356] For forming the resist mask 115b, the ashing method can be suitably used. By using the Sing method, the area of ​​the resist mask 115a in plan view becomes smaller. In addition, the film thickness of the resist mask 115a may be reduced.

[0357] Next, in the region not covered by the resist mask 115b, on the insulating layer 110B A portion of the material is removed to form an insulating layer 110 (Figure 21). In forming the insulating layer 110, anisotropy It is preferable to use chemical etching. In particular, dry etching is preferably used. can.

[0358] Adjust the amount by which resist mask 115 and resist mask 115a are reduced. As a result, the width L1 of region 108L1, and the width L2 of region 108L2 and region 108L3 The width L3 can be controlled.

[0359] After the insulating layer 110 is formed, the resist mask 115b is removed.

[0360] Washing may be performed here to remove impurities. Refer to the above description for details on washing. Since it can be understood by looking at the image, a detailed explanation will be omitted.

[0361] From this point onward, the steps after the formation of the insulating layer 118 can be described in <Example of Manufacturing Method 1>. Details will be omitted.

[0362] By following the above steps, a 100G transistor can be manufactured.

[0363] <Components of a semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0364] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single crystal made of silicon or silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups Plates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 102. It is also acceptable to have semiconductor elements mounted on these substrates as substrate 102. You may use it.

[0365] A flexible substrate is used as the substrate 102, and transistors 100, etc. are directly mounted on the flexible substrate. Alternatively, a release layer may be formed between the substrate 102 and the transistor 100, etc. The delamination layer is separated from the substrate 102 after the semiconductor device has been partially or completely completed on it. It can be separated and used to transfer to another substrate. In this case, transistor 100 etc. It can be transferred to substrates with poor heat resistance or flexible substrates.

[0366] [Insulating layer 103] The insulating layer 103 is deposited by sputtering, CVD, vapor deposition, or pulsed laser deposition (PLD). It can be formed using appropriate methods such as the ) method. In addition, the insulating layer 103 can be, for example, an oxide insulating film, nitrogen oxide A nitride insulating film, an oxide nitride insulating film, or a nitride insulating film can be formed as a single layer or in a multilayer configuration. Oh, in order to improve the interface characteristics with the semiconductor layer 108, at least half of the insulating layer 103 is used. The region in contact with the conductive layer 108 is preferably formed with an oxide insulating film or an oxidoxide nitride film. Furthermore, it is preferable to use a film that releases oxygen when heated for the insulating layer 103.

[0367] For example, the insulating layer 103 can be silicon oxide, silicon oxide nitride, silicon nitride oxide, or silicon dioxide. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide These can be used, and the structure can be provided in a single layer or in multiple layers.

[0368] On the side of the insulating layer 103 that is in contact with the semiconductor layer 108, there is an oxide film such as a silicon nitride film or an oxide film. When a film other than a nitride film is used, the surface in contact with the semiconductor layer 108 is subjected to oxygen plasma treatment. It is preferable to perform pretreatment such as the above and oxidize the surface or the vicinity of the surface.

[0369] [Conductive film] Conductive layer 106, conductive layer 120a which functions as either a source electrode or a drain electrode, The conductive layer 120b, which functions as the other of the source electrode or drain electrode, is composed of chromium, copper Aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese Metal elements selected from nitrite, nickel, iron, and cobalt, or materials containing the above-mentioned metal elements. These can be formed using alloys or alloys combining the aforementioned metallic elements.

[0370] The conductive layer 106, conductive layer 120a, and conductive layer 120b contain In-Sn oxide, In- W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In- Oxide conductors such as Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide or A metal oxide film can also be applied.

[0371] Here, we will explain oxide conductors (OC). For example, an oxygen vacancy is formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancy. Then, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. It becomes conductive. A metal oxide that has been made conductive can be called an oxide conductor.

[0372] The conductive layer 106, etc., is a conductive film containing the above oxide conductor (metal oxide), and a metal or A laminated structure of conductive films containing an alloy may also be used. By using a conductive film containing a metal or alloy, This allows for reduced wiring resistance. At this time, the insulating layer that functions as a gate insulating film and It is preferable to apply a conductive film containing an oxide conductor to the contacting side.

[0373] The conductive layer 106, conductive layer 120a, and conductive layer 120b contain, among the above-mentioned metal elements, particularly One of the following: titanium, tungsten, tantalum, and molybdenum or It is preferable to have multiple of them. In particular, it is preferable to use a tantalum nitride film. The tal film is conductive and has high barrier properties against copper, oxygen, or hydrogen. Furthermore, because it releases little hydrogen from itself, the conductive film in contact with the semiconductor layer 108, or the semiconductor It can be suitably used as a conductive film in the vicinity of layer 108.

[0374] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for transistors such as transistor 100, is manufactured by the PECVD method. It can be formed by sputtering or the like. The insulating layer 110 is a silicon oxide film, silicon oxidnitridation Cone film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, ma An insulating film containing one or more of the following: magnesium film, lanthanum oxide film, cerium oxide film, and neodymium oxide film. An edge layer can be used. The insulating layer 110 can be a two-layer laminated structure or a three-layer or more laminated structure. A layered structure is also acceptable.

[0375] The insulating layer 110 in contact with the semiconductor layer 108 is an oxide insulating film or an oxiditride film. It is preferable that it has a region containing an excess of oxygen compared to the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed under an oxygen atmosphere, and the insulating layer 110 after film formation is exposed to the oxygen atmosphere. Heat treatment is performed under gas, and after the deposition of the insulating layer 110, plasma treatment, etc., is performed under an oxygen atmosphere. Alternatively, one can perform the following: or deposit an oxide film or an oxidoxide-nitride film on the insulating layer 110 under an oxygen atmosphere. By doing so, oxygen can also be supplied into the insulating layer 110. In each of the processes supplied, an oxidizing gas (e.g., monochloride) is used instead of or in addition to oxygen. You may also use nitrogen dioxide or ozone.

[0376] As the insulating layer 110, silicon oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Materials such as humic acid can also be used. This increases the thickness of the insulating layer 110 and tunnel Leakage current due to current can be suppressed. In particular, crystalline hafnium oxide can suppress amorphous hafnium oxide. It is preferable because it has a higher dielectric constant compared to hafnium oxide.

[0377] [Semiconductor layer] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... The sputtering target used has an atomic ratio of In to element M of 1 or greater. This is preferable. As the atomic ratio of metal elements in such a sputtering target, In :M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1: 3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4: 2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Z Examples include n=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. It can be done.

[0378] When a target containing a polycrystalline oxide is used as a sputtering target, the crystallinity is This is preferable because it facilitates the formation of the semiconductor layer 108. The atomic ratio is the plus of the atomic ratio of the metal elements contained in the sputtering target mentioned above. This includes fluctuations of -40%. For example, the sputtering target used for semiconductor layer 108 When the composition of the material is In:Ga:Zn = 4:2:4.1 [atomic ratio], the semiconductor layer that is deposited The composition of 10⁸ can be close to In:Ga:Zn = 4:2:3 [atomic ratio].

[0379] Note that when the atomic ratio is stated as In:Ga:Zn=4:2:3 or close to it, In When we set the ratio to 4, this includes the case where Ga is between 1 and 3, and Zn is between 2 and 4. Furthermore, when stating that the atomic ratio is In:Ga:Zn = 5:1:6 or close to it, When n is set to 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is between 5 and 7. This includes cases where the atomic ratio is In:Ga:Zn = 1:1:1 or close to it. When listing, if In is set to 1, Ga must be greater than 0.1 and less than or equal to 2, and Zn must be 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0380] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using metal oxides with a wider energy gap than silicon, This can reduce the off-current of the transistor.

[0381] It is preferable to use a metal oxide with a low carrier concentration in the semiconductor layer 108. When reducing the carrier concentration of the oxide, the impurity concentration in the metal oxide is reduced, The defect level density should be lowered. In this specification, the impurity concentration is low and the defect level density is A low level is called high-purity intrinsic or substantially high-purity intrinsic. Note that impurities in metal oxides are... For example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. be.

[0382] In particular, the hydrogen contained in metal oxides reacts with the oxygen bonded to the metal atoms to form water. In some cases, oxygen vacancies may form in the metal oxide. If a primary defect is present, the transistor may exhibit normally-on characteristics. A defect where hydrogen fills an oxygen vacancy acts as a donor, generating electrons, which act as carriers. Sometimes, some of the hydrogen combines with oxygen that is bonded to a metal atom, and the hydrogen acts as a carrier. Transients may be produced. Therefore, transients using metal oxides that contain a lot of hydrogen Stamina tends to have the Normalion trait.

[0383] Defects where hydrogen is present in an oxygen vacancy can function as donors for metal oxides. However, Therefore, it is difficult to quantitatively evaluate the defect. In metal oxides, - In some cases, evaluation is based on carrier concentration rather than concentration. Therefore, in this specification, etc., metal The parameter for the oxide is not the donor concentration, but rather the value assuming a state where no electric field is applied. Carrier concentration may be used. In other words, the "carrier concentration" described in this specification, etc., is "d It can sometimes be rephrased as "ener concentration."

[0384] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, In metal oxides, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is... 1 x 10 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 less than , comfortable 5×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It shall be less than. Metal oxides in which impurities such as hydrogen have been sufficiently reduced shall be tra By using it in the channel formation region of an inverter, stable electrical characteristics can be imparted. .

[0385] The carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 The following This is preferable, 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even better if it is less than Mashiku, 1 x 10 12 cm -3 It is even more preferable that it be less than [a certain value]. Note that the channel formation region There are no particular limitations on the lower limit of the carrier concentration of metal oxides in the region, but for example, 1 × 1 0 -9 cm -3 It can be done this way.

[0386] The semiconductor layer 108 is preferably a non-single crystal structure. A non-single crystal structure is, for example, later This includes the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described below. Non-single-crystal structure In this context, the amorphous structure has the highest defect level density, while the CAAC structure has the lowest defect level density. stomach.

[0387] The following explains CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0388] A CAAC structure is a structure that has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, in which each nanocrystal has its c-axis oriented in a specific direction, and its a-axis and The b-axis does not have orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. This crystal structure has the following characteristics. In particular, thin films with a CAAC structure have each nanocrystal The c-axis is oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film. It has the characteristic of being inexpensive.

[0389] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. It is a conductor. On the other hand, CAAC-OS does not allow for the identification of clear grain boundaries, It can be said that a decrease in electron mobility caused by grain boundaries is less likely to occur in oxide semiconductors. Crystallinity may decrease due to the inclusion of impurities or the formation of defects, therefore CAAC-OS It can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, CAAC- Oxide semiconductors containing OS have stable physical properties. Therefore, CAAC-OS is used. Oxide semiconductors are highly heat-resistant and reliable.

[0390] In crystallography, the three axes a, b, and c constitute the unit cell (crystal). Regarding the axis, it is common to take a unit cell with a specific axis as the c-axis. Especially in layered structures In crystals with a structure, the two axes parallel to the plane direction of the layer are defined as the a-axis and the b-axis, and the axis intersecting the layer is defined as the axis intersecting the layer. It is common to use the c-axis. A typical example of a crystal having such a layered structure is... There is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane. The row is oriented, and the c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure. InGaZnO4 crystals can be classified as hexagonal, and their unit cell a-axis and The b-axis is parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0391] Oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films) can be observed using TEM. In some cases, the crystalline portion cannot be clearly identified. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, with microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having a certain nanocrystal (nc) is called nc-OS (Nanocrystalline Oxide Semiconductor) film Furthermore, in nc-OS films, grain boundaries can be clearly observed, for example, in TEM observation images. It may not be possible.

[0392] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this occurs. For example, XRD using X-rays with a diameter larger than that of the crystalline region on an nc-OS film. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The indicated peak is not detected. Also, the probe diameter is larger than that of the crystalline region in the nc-OS film. Electron diffraction (also called limited-field electron diffraction) using electron beams (for example, 50 nm or greater). When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, when applied to an nc-OS film... Furthermore, the probe diameter should be close to or smaller than the size of the crystal (for example, 1 nm to 30 nm). When electron diffraction (also called nanobeam electron diffraction) is performed using the electron beam shown below, a circle is drawn. A ring-shaped area of ​​high brightness was observed, and multiple spots were observed within that area. This may happen.

[0393] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-O The S film shows no regularity in crystal orientation between different crystalline regions. Therefore, the nc-OS film is Compared to CAAC-OS films, nc-OS films have a higher defect level density. Therefore, nc-OS films are CAAC- Compared to OS films, carrier concentration and electron mobility may be higher. Therefore, nc Transistors using OS films may exhibit high field-effect mobility.

[0394] Compared to CAAC-OS films, nc-OS films require a lower oxygen flow rate ratio during deposition. It can be formed in the following way. Furthermore, the nc-OS film has a substrate temperature during film formation that is lower compared to the CAAC-OS film. It can also be formed by lowering the temperature. For example, nc-OS films can be formed by lowering the substrate temperature to a relatively low temperature (for example Since film formation can be performed at temperatures below 130°C, or even without heating the substrate, It is suitable for use with large glass substrates or resin substrates, and can increase productivity. ru.

[0395] An example of a metal oxide crystal structure is described below. Using a chromium target (In:Ga:Zn=4:2:4.1 [atomic ratio]), sputtering We will explain a metal oxide film deposited by the ring method as an example. Using the above target, Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C. This refers to either an nc (nano crystal) structure or a CAAC structure. or a structure in which these are mixed is likely to be adopted. On the other hand, assuming the substrate temperature is room temperature (RT) Metal oxides formed by sputtering tend to adopt an nc crystal structure. The room temperature (RT) referred to here includes the temperature when the substrate is not heated.

[0396] <Composition of metal oxides> Hereinafter, CAC(C) that can be used in the transistor disclosed in one aspect of the present invention will be described. This document describes the configuration of a loud-Aligned Composite (Loud) OS.

[0397] Furthermore, in this specification, etc., CAAC (c-axis aligned crystal l) and when referring to CAC (Cloud-Aligned Composite) There is. Note that CAAC represents one example of a crystal structure, and CAC represents one of the functions or components of the material. This illustrates an example.

[0398] CAC-OS or CAC-metal oxide is a material in which some parts are conductive. It has both electrical and insulating properties in some parts of the material, and the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used to activate the transistor. When used in layers, the conductive function is the function of allowing electrons (or holes) that act as carriers to flow. In other words, the insulating function is the function of preventing the flow of electrons, which act as carriers. Conductive function and insulating function By making the functions of sex and other functions work complementaryly, a switching function (On / O) is created. The function of ff (fastening) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the respective functions are separated. By doing so, the functions of both can be maximized.

[0399] CAC-OS or CAC-metal oxide has conductive and insulating regions. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. It has the ability to conduct electricity. Furthermore, within the material, the conductive region and the insulating region are separated at the nanoparticle level. They may be separated. Also, conductive regions and insulating regions are unevenly distributed within the material. This can sometimes occur. Also, conductive regions may appear as a cloud-like, connected area with a blurred periphery. There is a match.

[0400] In CAC-OS or CAC-metal oxide, conductive region and insulating region Each region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed within the material at a certain size.

[0401] CAC-OS or CAC-metal oxide has different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxide. This consists of a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. It is composed of a component having a gap. In this configuration, when the carrier is flowed, In components with a low gap, the carrier mainly flows. Also, in components with a narrow gap The component acts complementaryly with the component having a wide gap, and the component having a narrow gap Carriers also flow to components with a wide gap in conjunction with the minutes. Therefore, the above CAC - OS or CAC-metal oxide is used in the channel formation region of the transistor. In this case, the transistor has a high current driving force in the ON state, that is, a large ON current, and High field-effect mobility can be obtained.

[0402] In other words, CAC-OS or CAC-metal oxide is a matrix composite Material (matrix composite), or metal matrix composite material (metal It can also be called a matrix composite.

[0403] The above is an explanation of the constituent elements.

[0404] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0405] (Embodiment 2) In this embodiment, an example of a display device having a transistor as illustrated in the previous embodiment is provided. I will explain about that.

[0406] <Example Configuration> Figure 22A shows a top view of the display device 700. The display device 700 is sealed by a sealing material 712. It has a first substrate 701 and a second substrate 705 that are bonded together. In the region sealed by the second substrate 705 and the sealing material 712, on the first substrate 701 The pixel section 702, source driver circuit section 704, and gate driver circuit section 706 are provided. Furthermore, the pixel section 702 is provided with multiple display elements.

[0407] In the portion of the first substrate 701 that does not overlap with the second substrate 705, FPC716 (FPC:F The FPC terminal section 708 to which the lexible printed circuit is connected It is provided. FPC716 is provided via FPC terminal section 708 and signal line 710 , the same as the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 Various signals are supplied to each of them.

[0408] Multiple gate driver circuits 706 may be provided. The path section 706 and the source driver circuit section 704 are each formed separately on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is on the first substrate 70 It can be implemented on 1 or FPC716.

[0409] The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 have A transistor, which is a semiconductor device according to one aspect of the present invention, can be applied to the transistor.

[0410] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. It is possible to use LEDs (Light Emitting Diodes) as light-emitting elements. de), OLED (Organic LED), QLED (Quantum-dot L Examples include self-luminous light-emitting elements such as EDs and semiconductor lasers. Also, shutter-type or optical interferometry MEMS (Micro Electro Mechanical Systems) (Systems) elements, microcapsule method, electrophoresis method, electrowetting Display elements using methods such as the GL method or the electronic powder fluid (registered trademark) method can also be used. Cut.

[0411] The display device 700A shown in Figure 22B uses a flexible resin instead of the first substrate 701. An example of a display device to which layer 743 is applied and which can be used as a flexible display. That is the case.

[0412] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Furthermore, as shown in region P1 in Figure 22B, the pixel portion 702 and a part of the resin layer 743 It has a notched portion. The pair of gate driver circuit sections 706 are located in the pixel section 702 It is provided on both sides of the . The gate driver circuit section 706 is located at the corner of the pixel section 702. It is provided along an arc-shaped contour.

[0413] The resin layer 743 has a shape in which the portion where the FPC terminal portion 708 is provided protrudes. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, is folded to the back side in area P2 in Figure 22B. It can be folded back. By folding back a part of the resin layer 743, the FPC 716 can be folded back into the pixel section 70 With the display device 700A placed on top of the back of 2, it can be mounted on the electronic device. This allows for space-saving in electronic devices.

[0414] The FPC716 connected to the display device 700A has the IC717 mounted on it. 717 has a function, for example, as a source driver circuit. At this time, the display device 700 The source driver circuit section 704 in A includes a protection circuit, a buffer circuit, and a demultiplexer. The configuration may include at least one circuit or the like.

[0415] The display device 700B shown in Figure 22C is suitable for use in electronic devices having a large screen. This is a display device capable of doing so. The display device 700B can be used, for example, in television equipment, monitor equipment, Personal computers (including notebooks and desktops), tablet devices, and It can be suitably used in digital signage and the like.

[0416] The display device 700B consists of multiple source driver ICs 721 and a pair of gate driver circuits. It has part 722.

[0417] Multiple source driver IC721s are each attached to the FPC723. Furthermore, multiple FPC723s have one terminal connected to the first substrate 701 and the other terminal connected to the printed circuit board Each is connected to board 724. By bending FPC723, the printed circuit board 7 By placing 24 on the back side of the pixel unit 702, it can be mounted on electronic devices, reducing the size of the electronic device. This allows for a more controlled pace.

[0418] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to create electronic devices with even narrower bezels.

[0419] This configuration makes it possible to realize a large and high-resolution display device. For example, Surface size is 30 inches or more diagonally, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. The above display device can be realized. Also, the resolution can be extremely high, such as 4K2K or 8K4K. This enables the creation of high-resolution display devices.

[0420] <Example of cross-sectional configuration> The following describes configurations using liquid crystal elements and EL elements as display elements. This will be explained using Figures 23 to 26. Note that Figures 23 to 25 are shown in Figure 22A. Figure 26 is a cross-sectional view along the dashed line QR. Figure 26 also shows the display device 7 shown in Figure 22B. This is a cross-sectional view along the dashed line ST in 00A. Figures 23 and 24 show the display elements. The configuration uses liquid crystal elements, while Figures 25 and 26 show configurations using electroluminescent (EL) elements.

[0421] [Explanation of common parts of display devices] The display device shown in Figures 23 to 26 comprises a wiring section 711, a pixel section 702, and a saw It has a screwdriver circuit section 704 and an FPC terminal section 708. The routing wiring section 711 is , has a signal line 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. In Figure 24, the capacitance This shows the case where element 790 is absent.

[0422] Transistors 750 and 752 are the transistors exemplified in Embodiment 1. It can be applied.

[0423] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can reduce the off-current. Therefore, it can handle electrical signals such as image signals. The holding time for signal signals can be extended, and the writing interval for image signals, etc., can also be set to be longer. This reduces the frequency of fresh cycles, resulting in lower power consumption.

[0424] The transistor used in this embodiment can obtain relatively high field-effect mobility, High-speed driving is possible. For example, if such a high-speed driving transistor is used in a display device... This allows for the switching transistors in the pixel section and the driver transistors used in the drive circuit section. The inverter can be formed on the same substrate. That is, the inverter can be formed on a silicon wafer or the like. A configuration without applying the circuit is also possible, which reduces the number of components in the display device. Furthermore, by using transistors capable of high-speed operation, high-quality images can be provided.

[0425] The capacitive element 790 shown in Figures 23, 25, and 26 is a part of the transistor 750. The lower electrode is formed by processing the same film as the gate electrode of 1, and the same metal oxide as the semiconductor layer. It has an upper electrode formed by processing a material. The upper electrode is the saw of transistor 750 The resistance is reduced, similar to the drain region. Also, between the lower electrode and the upper electrode This provides a portion of the insulating film that functions as the first gate insulating layer of transistor 750. In other words, the capacitive element 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. It has a stacked structure. Furthermore, the upper electrode contains the source electrode and drain of the transistor. Wiring, obtained by processing the same film as the electrodes, is connected to it.

[0426] A planarizing insulating film 7 is applied to transistors 750, 752, and capacitive element 790. 70 is provided.

[0427] The transistor 750 in the pixel section 702 and the source driver circuit section 704 Transistors with different structures than the 752 transistor may be used. For example, any one of them A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. A configuration using the above gate driver circuit section 706 may also be used. This is the same as the IBA circuit section 704.

[0428] Signal line 710 is the same as the source and drain electrodes of transistors 750 and 752. It is formed of a conductive film. In this case, if a low-resistance material such as a material containing copper elements is used, This is preferable because it minimizes signal delays caused by line resistance, allowing for display on a large screen.

[0429] The FPC terminal section 708 includes wiring 760, part of which functions as a connecting electrode, and an anisotropic conductive film 78. It has 0 and FPC716. Wiring 760 is connected to FPC71 via an anisotropic conductive film 780. It is electrically connected to the terminals of 6. Here, wiring 760 is connected to transistor 750. It is formed of the same conductive film as the source electrode and drain electrode of 752.

[0430] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. Flexible substrates such as acrylic substrates can be used. When using a substrate, water or hydrogen is placed between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer that has barrier properties.

[0431] On the second substrate 705 side, there is a light-shielding film 738, a colored film 736, and an insulating film 7 in contact with them. 34 and are provided.

[0432] [Example configuration of a display device using liquid crystal elements] The display device 700 shown in Figure 23 has a liquid crystal element 775 and a spacer 778. The sub-element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The electrode layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planar insulating film 770 and functions as a pixel electrode. ru.

[0433] The conductive layer 772 may be made of a material that is transparent to visible light or a material that is reflective to visible light. Yes, it is possible. Translucent materials can be oxide materials containing, for example, indium, zinc, or tin. For reflective materials, it is advisable to use materials containing, for example, aluminum or silver.

[0434] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, a transmissive liquid crystal display device is obtained. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device... A pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0435] The display device 700 shown in Figure 24 uses a transverse electric field method (for example, FFS mode) liquid crystal element 77 An example using 5 is shown. A common electrode is formed on the conductive layer 772 via an insulating layer 773. A conductive layer 774 is provided. The electric field generated between the conductive layer 772 and the conductive layer 774 causes the liquid The orientation state of crystal layer 776 can be controlled.

[0436] In Figure 24, the laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772 provides retention capacity. It can create a large quantity. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased. Cut.

[0437] Although not shown in Figures 23 and 24, the configuration includes an alignment film in contact with the liquid crystal layer 776. This is also fine. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, and Light sources such as backlights and sidelights can be provided as needed.

[0438] The liquid crystal layer 776 contains thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersion liquid. Crystal (PDLC: Polymer Dispersed Liquid Crystal) Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0439] The modes of the liquid crystal elements are TN (Twisted Nematic) mode and VA (Vertical). (Critical Alignment) mode, IPS (In-Plane-Switching) ng) mode, FFS (Fringe Field Switching) mode, AS M(Axially Symmetric aligned Micro-cell) model OCB (Optically Compensated Birefringen) ce) mode, ECB (Electrically Controlled Bicycle) You can use modes such as ringence mode and guest host mode.

[0440] A scattering type liquid crystal layer 776 using polymer dispersed liquid crystal or polymer network liquid crystal A liquid crystal can also be used. In this case, a configuration that displays in black and white without providing a colored film 736 is also possible. Alternatively, a configuration may be used in which a colored film 736 is used to display color.

[0441] As a method for driving liquid crystal elements, color display is performed based on the time-division table, which uses a sequential additive color mixing method. A display method (also called a field sequential drive method) may be applied. In that case, A configuration without a color film 736 is possible. When a time-division display method is used, for example, There is no need to provide subpixels that exhibit the respective colors R (red), G (green), and B (blue). Therefore, it offers advantages such as improving the aperture ratio of pixels and increasing the resolution.

[0442] [Display devices using light-emitting elements] The display device 700 shown in Figure 25 has a light-emitting element 782. The light-emitting element 782 is a conductive layer It has 772, an EL layer 786, and a conductive film 788. The EL layer 786 is an organic compound, and It contains inorganic compounds such as quantum dots.

[0443] Examples of materials that can be used with organic compounds include fluorescent materials or phosphorescent materials. Furthermore, colloidal quantum dot materials can be used as materials for quantum dots. alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. These are some examples.

[0444] The display device 700 shown in Figure 25 has a conductive layer 772 covering a portion of the planar insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788, This is a top-emission type light-emitting element. The light-emitting element 782 emits light towards the conductive layer 772. The bottom emission structure that is ejected emits light, and light is emitted to both the conductive layer 772 side and the conductive film 788 side. It may also be a dual-emission structure.

[0445] The colored film 736 is provided in a position that overlaps with the light-emitting element 782, and the light-shielding film 738 is an insulating film 730 It is provided in the overlapping position, the routing wiring section 711, and the source driver circuit section 704. Furthermore, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between element 782 and insulating film 734 is filled with sealing film 732. Furthermore, the EL layer 786 When forming island-like structures for each pixel or striped structures for each row of pixels, that is, when forming them by color separation: In this configuration, the colored film 736 may not be provided.

[0446] Figure 26 shows a display device configuration that is suitably applicable to a flexible display. Figure 26 is a cross-sectional view of the display device 700A shown in Figure 22B along the dashed line ST. be.

[0447] The display device 700A shown in Figure 26 replaces the first substrate 701 shown in Figure 25 with a support base The structure has a laminated configuration consisting of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750 and the capacitive element 790 are located on the insulating layer 744 provided on the resin layer 743. It is located at [location].

[0448] The support substrate 745 is a substrate containing organic resin, glass, etc., and is thin enough to be flexible. The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. Insulating layer 744 This includes an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 74 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferable that the substrate is thinner than the support substrate 745.

[0449] The display device 700 shown in Figure 26 has a protective layer 74 instead of the second substrate 705 shown in Figure 25. It has 0. The protective layer 740 is bonded to the sealing film 732. The protective layer 740 is gas Lath substrates and resin films can be used. Also, a polarizing plate can be used as the protective layer 740. Optical components such as scattering plates, input devices such as touch sensor panels, or two or more of these. A stacked configuration may also be applied.

[0450] The EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. It is made that the EL layer 786 is made so that each sub-pixel emits a different color of light. Color display can be achieved without using a color film 736. Furthermore, a protective layer covers the light-emitting element 782. A protective layer 741 is provided. The protective layer 741 prevents impurities such as water from diffusing into the light-emitting element 782. It has the function of preventing the following. The protective layer 741 preferably uses an inorganic insulating film. It is more preferable to have a laminated structure that includes one or more mechanical insulating films and one or more organic insulating films.

[0451] Figure 26 shows the foldable region P2. In region P2, the support substrate 745, In addition to the adhesive layer 742, there are portions where no inorganic insulating film such as an insulating layer 744 is provided. Furthermore, in region P2, a resin layer 746 is provided covering the wiring 760. In the functional region P2, an inorganic insulating film is provided as little as possible, and a conductive layer containing a metal or alloy is provided. By constructing a structure in which only layers containing organic materials are laminated, cracks will not occur when bent. This can be prevented. Also, by not providing the support substrate 745 in region P2, extremely small curves can be prevented. By adjusting the radius, a portion of the 700A display device can be bent.

[0452] [Example of a configuration in which an input device is provided to the display device] An input device may be provided in the display device shown in Figures 23 to 26. An example of such an input device is... Examples include touch sensors.

[0453] For example, sensor types include capacitive, resistive, surface acoustic wave, infrared, and optical. Various methods can be used, such as the standard method and the pressure-sensitive method. Alternatively, two or more of these can be combined. They can be used together.

[0454] The touch panel configuration is a so-called in-cell type, where the input device is formed between a pair of circuit boards. A so-called on-cell type touch panel, which forms a touch panel and input device on a display device, Alternatively, there are so-called out-cell type touch panels that are attached to display devices.

[0455] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0456] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0457] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 27. We will use it to explain.

[0458] The display device shown in Figure 27A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0459] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Furthermore, a transistor according to one aspect of the present invention can also be applied to the protection circuit 506. That's good too.

[0460] The pixel section 502 is arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has multiple pixel circuits 501 that drive a number of display elements.

[0461] The drive circuit section 504 outputs a scanning signal to the gate lines GL_1 to GL_X. Source driver 504a, which supplies data signals to data lines DL_1 to DL_Y. It has a drive circuit such as 04b. The gate driver 504a has at least a shift register The configuration should include, for example, multiple analog switches. It is constructed using switches, etc. Furthermore, it uses shift registers, etc., to configure the source driver 504 You may also construct b.

[0462] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0463] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 27A is, for example, The gate lines GL_1 to G are the wiring between the gate driver 504a and the pixel circuit 501. L_X, or data line DL, is the wiring between source driver 504b and pixel circuit 501. It is connected to various wirings such as _1 to DL_Y.

[0464] The gate driver 504a and the source driver 504b are based on the same base as the pixel unit 502. It may be provided on the board, or the gate driver circuit or source driver circuit may be provided separately. The completed substrate (for example, a drive circuit board formed from a single-crystal semiconductor or polycrystalline semiconductor) Mounted on the circuit board using COG or TAB (Tape Automated Bonding). This configuration is also acceptable.

[0465] The multiple pixel circuits 501 shown in Figure 27A have, for example, the configurations shown in Figures 27B and 27C. It is possible.

[0466] The pixel circuit 501 shown in Figure 27B consists of a liquid crystal element 570, a transistor 550, and a capacitive element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0467] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 in each row One of the electrodes may be given a different potential.

[0468] The pixel circuit 501 shown in Figure 27C consists of transistors 552 and 554, and a capacitor. It has an element 562 and a light-emitting element 572. The pixel circuit 501 also has a data line DL_ n, gate line GL_m, potential supply line VL_a, potential supply line VL_b, etc. are connected.

[0469] Furthermore, one of the potential supply lines VL_a and VL_b has a high power supply potential (VDD). A voltage is given to the other side, and a low power supply potential (VSS) is given to the other side. The gateway of transistor 554 The current flowing through the light-emitting element 572 is controlled according to the potential applied to the terminal, thereby generating The luminescence brightness from the optical element 572 is controlled.

[0470] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0471] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0472] (Embodiment 4) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device will be described below. The transistor exemplified in Embodiment 1 is exemplified below. This can be applied to transistors used in pixel circuits.

[0473] <Circuit Configuration> Figure 28A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0474] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The source and the other drain of the transistor are connected to one electrode of capacitance C1, respectively. M2 has a gate connected to wiring G2, and one of its sources and drains connected to wiring S2, and the source and drain The other end of the input is connected to the other electrode of capacitance C1 and to circuit 401, respectively.

[0475] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While various types can be used, typically light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements are used. Child, or MEMS (Micro Electro Mechanical System) ms) Elements and the like can be applied.

[0476] The node connecting transistor M1 and capacitor C1 is node N1, and the node connecting transistor M2 and... Let node N2 be the node connecting to path 401.

[0477] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the potential of node N2 can be maintained. It can be done. Also, with transistor M2 in the OFF state, via transistor M1, By writing a predetermined potential to node N1, capacitive coupling via capacitor C1 occurs, and the potential of node N1 The potential at node N2 can be changed according to the potential displacement.

[0478] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 1, can be applied. Therefore, extremely low The off-current allows the potentials of nodes N1 and N2 to be maintained for a long period of time. , if the period for which the potential of each node is held is short (specifically, if the frame frequency is 30 Hz or less) In cases such as those mentioned above, transistors using semiconductors such as silicon may be used.

[0479] <Example of driving method> Next, an example of how the pixel circuit 400 operates will be explained using Figure 28B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of the threshold voltage of the staccato are not considered.

[0480] In the operation shown in Figure 28B, one frame period is divided into period T1 and period T2. Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0481] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a fixed potential V ref It supplies the first day to wiring S2. Potential V w To supply.

[0482] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, node N2 receives the first data potential V from wiring S2 via transistor M2. w is given Therefore, a potential difference V can be obtained across capacitance C1. w -V ref This state is maintained.

[0483] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and The wire G2 is given a potential that turns off transistor M2. Also, the wiring S1 is supplied with the second diode DATA potential V data It supplies a predetermined constant potential to the wiring S2, or a floating It may also be in a ling state.

[0484] Node N1 receives a second data potential V from wiring S1 via transistor M1. data but Given. At this time, the second data potential V is generated by capacitive coupling with capacitance C1. data in response Then the potential of node N2 changes by a potential of dV. That is, circuit 401 receives the first data Potential V w The input will be the sum of the potential dV and the potential dV. Note that in Figure 28B, the potential dV Although it is shown to be a positive value, it may also be a negative value. That is, the second data potential. V data The potential is V ref It can be lower.

[0485] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second dV. DATA potential V data The potential will be close to that.

[0486] Thus, the pixel circuit 400 combines two types of data signals to form a display element. Since it is possible to generate the potential supplied to path 401, grayscale correction can be performed within the pixel circuit 400. It becomes possible.

[0487] The pixel circuit 400 generates a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. This also becomes possible. For example, when using light-emitting elements, high dynamic range (HD) is possible. R) can be displayed, etc. Also, when using a liquid crystal element, overdrive can be used. It can achieve dynamic operation, etc.

[0488] <Examples of application> [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 28C has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0489] The liquid crystal element LC has one electrode which is the capacitance C1 and the other electrode which is the source of the transistor M2 and The other electrode of the drain is connected to one electrode of the capacitor C2, and the other electrode is at potential V co m2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Given Connect to the wiring.

[0490] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed.

[0491] The 400LC pixel circuit can supply a high voltage to the liquid crystal element LC, for example, overdrive This involves achieving high-speed display through live driving and applying liquid crystal materials with high driving voltage. This can be done. Also, by supplying a correction signal to wiring S1 or wiring S2, the operating temperature and liquid can be adjusted. The gradation can also be corrected according to the degradation state of the LC crystal elements.

[0492] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 28D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0493] Transistor M3 has its gate connected to one electrode of capacitance C2, and one of its source and drain electrodes is Potential V HOne wire is provided, and the other is connected to one electrode of the light-emitting element (EL). Capacitor C2 is the capacitance of the other electrode when it is at potential V com It connects to the provided wiring. The light-emitting element EL is The other electrode is at potential V L Connect to the provided wiring.

[0494] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 This functions as a holding capacity. Capacity C2 can be omitted if not needed.

[0495] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0496] The pixel circuit 400EL generates light by applying a high potential to the gate of transistor M3. Because it can supply a large current to the sub-EL, it can enable features such as HDR display. By supplying a correction signal to wiring S1 or wiring S2, the transistor M3 and light-emitting element E It is also possible to correct for variations in the electrical characteristics of L.

[0497] Note that the circuits are not limited to those illustrated in Figures 28C and 28D, and may also include transistors, capacitors, etc. A configuration with the addition of this element is also acceptable.

[0498] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0499] (Embodiment 5) This embodiment describes a display module that can be manufactured using one aspect of the present invention. ru.

[0500] The display module 6000 shown in Figure 29A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006 connected to the FPC6005, the frame 6009, and the printed circuit board. It has a board 6010 and a battery 6011.

[0501] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of a display module with extremely low power consumption. ru.

[0502] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0503] The display device 6006 may also have the functionality of a touch panel.

[0504] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0505] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It includes a processing circuit, a battery control circuit, and the like.

[0506] Figure 29B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0507] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0508] The display device 6006 connects to the printed circuit board 6010 and the battery via the frame 6009. - It is installed overlapping with 6011. The display device 6006 and frame 6009 are connected to the light guide section 6 017a is fixed to the light guide section 6017b.

[0509] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or a stand When light 6018 is blocked by an object to be detected, such as an illustration, touch operation can be detected. ru.

[0510] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0511] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0512] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0513] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0514] (Embodiment 6) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0515] The electronic device 6500 shown in Figure 30A can be used as a portable smartphone. It is a news terminal device.

[0516] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0517] A display device according to one embodiment of the present invention can be applied to the display unit 6502.

[0518] Figure 30B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0519] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0520] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0521] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is there. Also, the FPC6515 is connected to the folded portion. FPC651 IC6516 is mounted on board 5. FPC6515 is mounted on printed circuit board 6517. It is connected to a terminal provided there.

[0522] A flexible display panel according to one aspect of the present invention can be applied to the display panel 6511. Therefore, it is possible to realize extremely lightweight electronic devices. Also, the display panel 6511 is extremely Because it is thin, it is possible to keep the thickness of electronic devices down while also incorporating a large-capacity 6518 battery. Also, a part of the display panel 6511 is folded back, and the FPC6515 is attached to the back of the pixel area. By positioning the connection points, it is possible to realize electronic devices with narrow bezels.

[0523] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together.

[0524] (Embodiment 7) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0525] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0526] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0527] Examples of electronic devices include television equipment, notebook personal computers, and more. Features include relatively large screens such as those found on NITA devices, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and mobile phones Examples include telephones, portable game consoles, personal digital assistants, and audio playback devices.

[0528] An electronic device to which one aspect of the present invention is applied includes the interior or exterior walls of houses and buildings, the interior of automobiles, etc. It can be incorporated along the flat or curved surfaces of the fittings or exterior.

[0529] Figure 31A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0530] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0531] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0532] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0533] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can connect to devices such as power supply units.

[0534] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0535] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0536] Button 8103 functions as a power button, etc.

[0537] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Furthermore, a camera 8000 with a built-in viewfinder can be used. That's fine.

[0538] Figure 31B shows the external appearance of the head-mounted display 8200.

[0539] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0540] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can do that. Furthermore, the main unit 8203 is equipped with a camera that inputs information about the user's eyeball and eyelid movements. It can be used as a step.

[0541] The attachment part 8201 is located at a position that touches the user, and current flows in accordance with the user's eye movements. Multiple electrodes capable of detecting gaze may be provided, and the device may have a function to recognize gaze. The device may also have a function to monitor the user's pulse rate based on the current flowing through the electrode. The mounting section 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It may also have a function to display the user's biometric information on the display unit 8204, and to detect the user's head movements. The display unit 8204 may also have a function to change the image displayed on it.

[0542] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0543] Figures 31C, 31D, and 31E show the appearance of the head-mounted display 8300. This is a diagram. The head-mounted display 8300 consists of a housing 8301 and a display unit 8302 It also includes a band-shaped fastener 8304 and a pair of lenses 8305.

[0544] The user can see the display on the display unit 8302 through the lens 8305. Arranging part 8302 in a curved shape is preferred because it allows the user to experience a high level of realism. Furthermore, another image displayed in a different area of ​​the display unit 8302 is passed through the lens 8305. By viewing it in this way, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one 02; two display units 8302 are provided, and one of the user's eyes... A single display unit may be provided.

[0545] Furthermore, a display device according to one aspect of the present invention can be applied to the display unit 8302. Display devices with semiconductor devices have extremely high resolution, so as shown in Figure 31E, lens 83 Even when enlarged using 05, the user cannot see the individual pixels, resulting in a more realistic image. It can display video.

[0546] The electronic equipment shown in Figures 32A to 32G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0547] The electronic devices shown in Figures 32A to 32G have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device can be equipped with a camera, etc., to take still images and videos, and the recording medium (external or It has features such as saving to the camera (built-in), and displaying the captured image on the display unit. That's good too.

[0548] Details of the electronic equipment shown in Figures 32A to 32G will be explained below.

[0549] Figure 32A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0550] Figure 32B is a perspective view showing the personal digital assistant 9101. The personal digital assistant 9101 is, for example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text and image information on its multiple surfaces. Figure 32B shows three icons. An example of displaying 9050 is shown. Also, the information 9051, indicated by the dashed rectangle, is displayed on the display unit 90 It can also be displayed on other sides of 01. Examples of information 9051 include email and social media. Incoming call notifications, email and social media notifications, subject, sender name, date, time, etc. This includes the remaining battery level and antenna signal strength. Alternatively, information 9051 may be displayed. You may display an icon such as 9050 at this location.

[0551] Figure 32C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0552] Figure 32D is a perspective view showing a wristwatch-type personal information terminal 9200. Personal information terminal 92 00 can be used, for example, as a smartwatch (registered trademark). Also, the display unit The 9001 has a curved display surface, allowing it to display information along the curved surface. It can. Furthermore, the portable information terminal 9200 can communicate with, for example, a wireless communication headset. By doing so, hands-free calling is also possible. Furthermore, the 9200 mobile information terminal is The connection terminal 9006 allows for mutual data transmission with other information terminals and charging. It is also possible to perform the charging operation via wireless power supply.

[0553] Figures 32E, 32F, and 32G show a perspective view of the foldable portable information terminal 9201. This is a diagram. Figure 32E shows the mobile information terminal 9201 in its unfolded state, and Figure 32G shows it in its folded state. In this state, Figure 32F is a perspective view of the intermediate state in which one of Figures 32E and 32G changes to the other. Yes. The 9201 personal digital assistant offers excellent portability when folded and is convenient when unfolded. The seamless, wide display area provides excellent readability of the display. The indicator part 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. ru.

[0554] Figure 33A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0555] The television device 7100 shown in Figure 33A is operated by the operation switches provided on the housing 7101. This can be done by using the remote control unit 7111 or by using the display unit 7500. A touch panel can be applied to it, allowing the television device 7100 to be operated by touching it. The remote control unit 7111 may have a display unit in addition to the operation buttons.

[0556] The television equipment 7100 is a television broadcast receiver and for network connectivity. It may have a communication device.

[0557] Figure 33B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0558] Figures 33C and 33D show digital signage. An example of a small sign is shown.

[0559] The digital signage 7300 shown in Figure 33C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0560] Figure 33D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is installed along the curved surface of the column 7401. To possess.

[0561] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0562] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This means that it can be used not only for advertising purposes, but also for route information, traffic information, and commercial facility information, It can also be used to provide users with the information they are looking for.

[0563] As shown in Figures 33C and 33D, the digital signage 7300 or digital signage The Neige 7400 communicates wirelessly with the user's smartphone or other information terminal 7311. It is preferable that the information displayed on the display unit 7500 is linked. To display this on the screen of the information terminal 7311, or by operating the information terminal 7311 The display on the 7500 display unit can be switched.

[0564] Digital signage 7300 or digital signage 7400, information terminal 731 It is also possible to run a game using 1 as the control device (controller). A large number of users can participate in and enjoy the game simultaneously.

[0565] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 33A to 33D. Cut.

[0566] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0567] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. [Examples]

[0568] In this example, a sample (sample) that mimics the shape of transistor 100A shown in Figure 7 is used. A) and a sample (sample B) that mimics the shape of transistor 100G shown in Figure 13. A sample was fabricated, and its cross-sectional shape was evaluated.

[0569] <Sample preparation> First, a 30nm thick titanium film and a 100nm thick copper film are laid on a glass substrate in that order. The first gate electrode (bottom gate) was obtained by forming it using the puttering method and then processing it. .

[0570] Next, as the first gate insulating layer, a silicon nitride layer with a thickness of 300 nm and a layer with a thickness of 100 nm The first silicon oxidizride layer of m was deposited in this order. The first gate insulating layer was PECVD The film was deposited using the apparatus.

[0571] Next, a 25 nm thick metal oxide film was deposited on the first silicon oxidnitride layer. The group oxide film is an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [original The film was deposited by sputtering using a [number of particles ratio]. The pressure during deposition was 0.6 Pa, and the power supply was also used. The power was set to 2.5 kW and the substrate temperature to room temperature. Oxygen gas and argon gas were used as the film deposition gas. Using a mixed gas, the ratio of the oxygen gas flow rate to the total film-forming gas flow rate (oxygen flow rate ratio) is set to 30 It was expressed as a percentage.

[0572] Next, the metal oxide film was processed into an island-like structure to form a metal oxide layer.

[0573] Next, the mixture was heated at 370°C for 1 hour under a nitrogen atmosphere, followed by mixing of nitrogen and oxygen. Heat treatment at 370°C for 1 hour under a gas atmosphere (nitrogen gas flow rate:oxygen gas flow rate = 4:1). The process was carried out using an oven for heat treatment.

[0574] Next, a second silicon oxide-nitride film with a thickness of 130 nm is deposited as the second gate insulating layer. The second gate insulating layer was deposited using a PECVD apparatus.

[0575] Next, the samples were heat-treated at 370°C for 1 hour under a nitrogen atmosphere. The heat treatment was performed using an oven. A device was used.

[0576] Next, a 100 nm thick molybdenum film was deposited on the second silicon oxidizride film. The molybdenum film was deposited by sputtering.

[0577] Next, a first resist mask was formed on the molybdenum film to create a molybdenum layer. Wet etching was used to form the molybdenum layer. The etching was done using a mixed acid aluminum etchant. A chipping solution was used. At this time, the edge of the molybdenum layer was closer to the edge of the first resist mask. The etching time was adjusted so that it would be on the inside.

[0578] Next, the second silicon oxide nitride film was processed using the first resist mask as a mask. .

[0579] Next, the first resist mask was reduced in size to form the second resist mask. The ashing method was used to reduce the resist mask.

[0580] Next, using the second resist mask as a mask, the second silicon oxide nitride film is processed. A second silicon oxidnitride layer was obtained. The samples prepared up to this point were designated as sample A and did.

[0581] Next, sample B reduces the second resist mask and then the third resist mask A screen was formed. The ashing method was used to reduce the size of the second resist mask.

[0582] Next, sample B uses the third resist mask as a mask and performs the second oxidative nitridation. The silicon film was processed to obtain a second silicon oxidizride layer.

[0583] Sample A and Sample B were obtained through the above process.

[0584] <Cross-sectional observation> Next, sample A and sample B are subjected to a focused ion beam (FIB). The tissue was thinned using sed Ion Beam, and the cross-section was observed using STEM.

[0585] Figure 34A shows the STEM image of the cross-section of sample A, and Figure 34A shows the STEM image of the cross-section of sample B. The M image is shown in Figure 34B. Figures 34A and 34B are transmitted electron images at a magnification of 1800x, respectively. This is a TE (Transmission Electron) image.

[0586] Figure shows a magnified STEM image of the area near the edge of the second silicon oxidizide layer of sample A. This is shown in Figures 35A and 35B. The area near the edge of the second silicon oxidizride layer of sample B Enlarged STEM images are shown in Figures 36A and 36B. Figures 36B and 36B are transmission electron (TE) images at a magnification of 100,000x.

[0587] Note that Figure 35B shows the same STEM image as Figure 35A, and Figure 36B shows the same STEM image as Figure 36A. The M image is shown. Figures 35B and 36B show the width L1 of region 108L1 and region The second acid in the region overlapping with region 108L1, with width L2 of region 108L3 and width L3 of region 108L1. The second silicon oxide nitride layer has a thickness of TN1 and overlaps with region 108L2. The thickness of the second silicon oxidizide layer in the region overlapping with region 108L3, TN2, and T This indicates the location where N3 was measured.

[0588] In Figures 34A, 34B, 35A, 35B, 36A, and 36B, the glass substrate The plate is Glass, the copper layer is Cu, the silicon nitride layer is SiN, and the first silicon oxide nitride layer is S iON-1, metal oxide layer is OS, second silicon oxide nitride layer is SiON-2, molybdenum The 'n' layer is abbreviated as 'Mo', and the photoresist as 'PR'.

[0589] As shown in Figures 34A, 34B, 35A, 35B, 36A, and 36B, the second We were able to confirm that the silicon oxidizride layer has a stepped shape.

[0590] Sample A and Sample B: Width L1 of area 108L1, area 108 Second oxidative nitridation of the region overlapping with region 108L1, with width L2 of L2 and width L3 of region 108L3. The second silicon oxidizride layer film in the region overlapping with region 108L2, where the silicon layer film thickness TN1 is located. The thickness TN2 and the thickness TN3 of the second silicon oxidizide layer in the region overlapping with region 108L3 are This is shown in Table 1. Note that in Table 1, sample A does not have region 108L3. Therefore, the values ​​for width L3 and film thickness TN3 are not shown.

[0591] [Table 1]

[0592] As shown in Figures 34A, 34B, 35A, 35B, 36A, 36B, and Table 1 In sample A, the transistor has regions 108L1 and 108L2. In sample B, the shape has regions 108L1, 108L2, and 108L3. The shape of the transistor could be confirmed. Also, in sample A, the film thickness The ratio of film thickness TN1 to TN0 is 0.97, and film thickness TN0 and film thickness TN1 are approximately equal. This was confirmed. In sample B as well, the ratio of film thickness TN1 to film thickness TN0 was The value was 0.99, confirming that film thickness TN0 and film thickness TN1 were approximately equal. [Examples]

[0593] In this embodiment, region 108C, region 108L1, region 108L2, region 108L3, Samples corresponding to the 10⁸N range were prepared, and their resistances were evaluated.

[0594] <Sample preparation> First, a first silicon nitride film with a thickness of 240 nm is placed on the glass substrate, and a second film with a thickness of 60 nm is placed on the glass substrate. A silicon nitride film (layer 2) and a first silicon oxide nitride film (layer 100 nm thick) were deposited in this order. .

[0595] Next, a 25 nm thick metal oxide film was deposited on the first silicon oxidoxide film. The group oxide film is an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [original The film was deposited by sputtering using a [number of particles ratio]. The pressure during deposition was 0.6 Pa, and the power supply was also used. The power was set to 2.5 kW and the substrate temperature to room temperature. Oxygen gas and argon gas were used as the film deposition gas. A mixed gas was used, with an oxygen flow rate ratio of 30%.

[0596] Next, the mixture was heat-treated at 340°C for 1 hour under a CDA atmosphere. A bunning device was used.

[0597] Next, a second silicon oxide-nitride film was deposited on the metal oxide film. Here, between the samples... The thickness of the second silicon oxide nitride film was varied. The thickness of the second silicon oxide nitride film was 20 The wavelengths were set to nm, 40 nm, 60 nm, 80 nm, 100 nm, and 140 nm. Also, the second acid Samples were also prepared without forming a silicon oxide nitride film. The second silicon oxide nitride film was actually... When supplying the first element 140 as shown in the first embodiment of the application, it is provided on the semiconductor layer 108. This corresponds to an insulating layer. The second silicon oxidizride film is, for example, the insulating layer 110 shown in Figure 18B. And it corresponds to the insulating layer 118a.

[0598] Next, the mixture was heat-treated at 340°C for 1 hour under a CDA atmosphere. A Bun device was used. Samples that did not form a second silicon oxide-nitride film were subjected to the same heat treatment. They did not do it.

[0599] Next, plasma treatment was performed using ammonia gas. Here, plasma treatment was performed between the samples. The substrate temperature during processing and the processing time for plasma treatment were varied. The temperatures were set to 240°C and 350°C. The plasma treatment times were 15 seconds and 30 seconds. The plasma treatment time was set to 60 seconds and 90 seconds. Samples without plasma treatment were also prepared.

[0600] Next, a heat treatment was performed under a nitrogen atmosphere for 1 hour. An oven was used for the heat treatment. Here, the heat treatment temperature was varied between the samples. The heat treatment temperatures were 250°C and 3 The temperatures used were 00°C and 350°C. Samples without heat treatment were also prepared.

[0601] Next, an opening is formed in the second silicon oxidizride film that reaches the metal oxide film, and terminals are provided. keta.

[0602] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0603] The sheet resistance values ​​of the metal oxide film for each sample are shown in Figures 37A, 37B, 38A, and 38B. This is shown in Figures 39A and 39B.

[0604] In Figures 37A, 37B, 38A, and 38B, the horizontal axis represents the processing time of the plasma treatment. The graph shows the interval, and the vertical axis shows the sheet resistance Rs of the metal oxide film. Figure 37A shows the plasma treatment Results for samples where the substrate temperature during processing was 350°C and no post-plasma heating treatment was performed. This is an excerpt. Figure 37B shows the results when the substrate temperature during plasma treatment is 240°C, and the plasma... The results for samples that were not subjected to post-treatment heat treatment are shown in excerpts. Figure 38A shows the plasma The substrate temperature during the plasma treatment was set to 350°C, and the temperature during the post-plasma treatment heating was set to 250°C. The results for the sample are shown in excerpts. Figure 38B shows the results when the substrate temperature during plasma treatment was 240°C. Furthermore, the results for samples where the heat treatment temperature after plasma treatment was 250°C are shown as an excerpt. .

[0605] In Figures 39A and 39B, the horizontal axis represents the thickness of the second silicon oxide nitride film (SiON). The vertical axis shows the film thickness, and the vertical axis shows the sheet resistance Rs of the metal oxide film. Note that Figure 39A shows the plasma A sample was prepared with a substrate temperature of 350°C during plasma treatment and a plasma treatment time of 60 seconds. The results are shown in excerpts. Figure 39B shows the results when the substrate temperature during plasma treatment was 240°C, and The results for samples with a rasma treatment time of 60 seconds are shown as an excerpt.

[0606] As shown in Figures 37A, 37B, 38A, and 38B, the processing time for plasma treatment is We were able to confirm that the resistance of the metal oxide film decreases as the length increases. Also, during plasma treatment... Compared to a sample with a substrate temperature of 240°C, the sample with a substrate temperature of 350°C showed a higher resistance of the metal oxide film. It was found that the value decreased. As shown in Figures 39A and 39B, heating after plasma treatment The treatment increases the resistance of the metal oxide film, and if the heat treatment temperature is high, the metal oxidation We were able to confirm a tendency for the resistance of the material film to increase. Also, the thickness of the second silicon oxide nitride film was thin. Indeed, we were able to confirm that the resistance of the metal oxide film was reduced. Furthermore, the second silicon oxide nitride In samples treated with plasma without forming a film, the resistance of the metal oxide film tends to be high. The samples that did not form a second silicon oxidizride film had the metal oxide film exposed. Plasma treatment is performed, and the resistance has increased due to damage to the metal oxide film. It is thought that this was the case.

[0607] Based on the above results, the film thickness of the second silicon oxidnitride film and the plasma treatment conditions were adjusted. It was found that the resistance of the metal oxide film can be controlled by doing so. In this example, Although heat treatment was performed after the lazma treatment, the heat treatment can be replaced with a treatment that applies heat. As shown in this embodiment, the resistance of the metal oxide film differs depending on the temperature of the heat treatment after plasma treatment. Therefore, taking into account the temperature of the process to which heat is applied after plasma treatment, the second oxidative nitriding silica By adjusting the film thickness and plasma treatment conditions, the resistance of the metal oxide film can be controlled. I found out that it is possible. [Explanation of symbols]

[0608] C1: Capacitance, C2: Capacitance, DL_Y: Data line, DL_1: Data line, G1: Wiring, G2 :Wiring, GL_X:Gate wire, GL_1:Gate wire, M1:Transistor, M2:Transistor Zista, M3: Transistor, N1: Node, N2: Node, P1: Region, P2: Region, S1: Wiring, S2: Wiring, T1: Period, T2: Period, TN0: Film Thickness, TN1: Film Thickness, TN 2: film thickness, TN3: film thickness, 10: transistor, 10A: transistor, 10B: transistor Zista, 10C: Transistor, 10D: Transistor, 10E: Transistor, 10F : Transistor, 10G: Transistor, 10H: Transistor, 10I: Transistor , 100: transistor, 100A: transistor, 100B: transistor, 100C :transistor, 100D:transistor, 100E:transistor, 100F:transistor Zista, 100G: Transistor, 102: Substrate, 103: Insulating layer, 103a: Insulating layer, 103b: insulating layer, 103c: insulating layer, 106: conductive layer, 108: semiconductor layer, 108C: area, 108f: metal oxide film, 108L1: area, 108L2: area, 108L3: area Region, 108Lp: region, 108N: region, 110: insulating layer, 110a: insulating layer, 110A : insulating layer, 110b: insulating layer, 110B: insulating layer, 110c: insulating layer, 110f: insulating film , 110S1: First side, 110S2: Second side, 110S3: Third side, 110 Sp: p-th side, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114 f: metal oxide film, 115: resist mask, 115a: resist mask, 115b: resist Dist mask, 118: insulating layer, 118a: insulating layer, 118b: insulating layer, 120a: conductive Layer, 120b: conductive layer, 140: first element, 141a: opening, 141b: opening, 1 42: Aperture, 400: Pixel circuit, 400EL: Pixel circuit, 400LC: Pixel circuit, 40 1: Circuit, 401EL: Circuit, 401LC: Circuit, 501: Pixel circuit, 502: Pixel section, 504: Drive circuit section, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal section, 550: Transistor, 552: Transistor, 554: Rangitar, 560: Capacitive element, 562: Capacitive element, 570: Liquid crystal element, 572: Light-emitting element child, 700: display device, 700A: display device, 700B: display device, 701: board, 70 2: Pixel section, 704: Source driver circuit section, 705: Circuit board, 706: Gate driver circuit 708: FPC terminal section, 710: signal line, 711: wiring section, 712: sealing material, 7 16: FPC, 717: IC, 721: Source driver IC, 722: Gate driver IC Path section, 723: FPC, 724: Printed circuit board, 730: Insulating film, 732: Encapsulation film, 73 4: insulating film, 736: colored film, 738: light-shielding film, 740: protective layer, 741: protective layer, 74 2: Adhesive layer, 743: Resin layer, 744: Insulating layer, 745: Support substrate, 746: Resin layer, 7 50: Transistor, 752: Transistor, 760: Wiring, 770: Planarizing insulating film, 7 72: conductive layer, 773: insulating layer, 774: conductive layer, 775: liquid crystal element, 776: liquid crystal layer, 778: Spacer, 780: Anisotropic conductive film, 782: Light-emitting element, 786: EL layer, 788 : Conductive film, 790: Capacitive element, 6000: Display module, 6001: Top cover, 60 02: Lower cover, 6005: FPC, 6006: Display device, 6009: Frame, 60 10: Printed circuit board, 6011: Battery, 6015: Light-emitting part, 6016: Light-receiving part, 6 017a: Light guiding part, 6017b: Light guiding part, 6018: Light, 6500: Electronic equipment, 6501 : Enclosure, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker -Ka, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6 511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7100: Television equipment, 7101: housing, 7103: stand, 7111: remote control unit, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard 7213: Pointing device, 7214: External connection port, 7300: Digital sensor Inage, 7301: enclosure, 7303: speaker, 7311: information terminal, 7400: Digital signage, 7401: Pillar, 7500: Display unit, 8000: Camera, 8001: Enclosure Body, 8002: Display unit, 8003: Operation buttons, 8004: Shutter button, 8006 :Lens, 8100:Viewfinder, 8101:Body, 8102:Display unit, 8103:Body Tan, 8200: Head-mounted display, 8201: Wearing part, 8202: Lens, 8203: Main unit, 8204: Display unit, 8205: Cable, 8206: Battery, 83 00: Head-mounted display, 8301: Housing, 8302: Display unit, 8304: Fixture Fixture, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9 005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone ,9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television equipment, 9101: Portable information terminal, 91 02: Mobile information terminal, 9200: Mobile information terminal, 9201: Mobile information terminal

Claims

[Claim 1] It comprises a semiconductor layer, a first insulating layer on the semiconductor layer, and a conductive layer on the first insulating layer, The semiconductor layer has a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second region encloses the first region, The third region encloses the first region and the second region, The fourth region encloses the first region, the second region, and the third region, The first region has a region that overlaps with the first insulating layer and the conductive layer, The second region and the third region each have a region that overlaps with the first insulating layer and does not overlap with the conductive layer. The fourth region does not overlap with either the first insulating layer or the conductive layer. The thickness of the first insulating layer in the region overlapping with the second region is approximately equal to the thickness of the first insulating layer in the region overlapping with the first region. A semiconductor device in which the thickness of the first insulating layer in the region overlapping with the third region is thinner than the thickness of the first insulating layer in the region overlapping with the second region.

Images