Indication device

Abstract

The present invention provides a display device that can suppress the increase in line memory even when employing an overlap scan drive method. [Solution] The display device comprises a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns, a plurality of scan signal lines, each associated with one of the plurality of pixel rows, a plurality of display signal lines, each associated with one of the plurality of pixel columns, a scan signal line drive circuit that supplies scan signals to the plurality of scan signal lines, each containing a selection pulse for selecting one of the plurality of pixel rows, and a display signal line drive circuit that supplies display signals to the plurality of display signal lines, wherein the scan signal line drive circuit is configured to make at least one horizontal scanning period near the beginning of a frame shorter than other horizontal scanning periods, including the first horizontal scanning period of a plurality of horizontal scanning periods that exist from the start of the frame at the input of the scan signal line drive circuit until the selection pulse supplied to the first scan signal line falls.

Description

[Technical Field]

[0001] The present invention relates to an active-matrix display device, and more particularly to a display device in which a scanning signal line driving circuit that supplies scanning signals for selecting pixel rows is integrally provided on the active-matrix substrate of the display panel. The present invention relates, for example, to a so-called gate-on-array (GOA) type liquid crystal display device in which a gate driving circuit is integrally provided on the active-matrix substrate of the liquid crystal display panel. [Background technology]

[0002] In recent years, the increasing resolution and high-speed operation of display devices have made it difficult to adequately charge pixels. Therefore, the overlap scan driving method has been proposed as a method for adequately charging pixels. The overlap scan driving method is disclosed, for example, in Patent Documents 1 and 2. In the overlap scan driving method, the selection pulse width of the scan signal is lengthened (i.e., the selection period of each scan signal line is lengthened), so the selection periods of adjacent scan signal lines partially overlap. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2006-106394 [Patent Document 2] International Publication No. 2018 / 025412 [Overview of the project] [Problems that the invention aims to solve]

[0004] When the selection pulse (gate-on pulse) width of the scanning signal (gate scanning signal) is increased, as in the overlap scan drive method, or when dummy stages (for example, stages DSR1, DSR2, and DSR3 in Figure 11) are provided in the gate drive circuit such as the GOA, the period from the start of the frame to the end of writing the first row of pixels becomes longer. Consequently, the amount of line memory required to hold the source signal (display signal) increases, leading to increased costs.

[0005] Here, a frame refers to the period during which a complete image is displayed in the display area, and is sometimes called the vertical scan period. The reciprocal of the vertical scan period is sometimes called the vertical frequency; for example, in the case of 120Hz drive, 120 images are displayed per second, and this is sometimes expressed as 120fps (120 frames / sec). A frame has a beginning and an end, and does not simply represent a length of time. The timing of the end of a frame is the same as the timing of the beginning of the next frame. When expressing the length of time of a frame, it is sometimes called 1 frame period or 1 vertical scan period (1V). 1 frame period (1 vertical scan period) corresponds to the period from when the selection of an arbitrary pixel row (scan line) begins in a given frame until when the selection of that pixel row (scan line) begins in the next frame. 1 frame period includes the effective scan period (E), which is the period from when the selection (writing) of the first pixel row begins (rising edge of the selection pulse) to when the selection (writing) of the last pixel row ends (falling edge of the selection pulse), and the ineffective scan period (NE), also known as the retrace period. Furthermore, within a frame, the period from the start of selection of one pixel row to the start of selection of the next pixel row is called one horizontal scan period (1H).

[0006] Generally, the vertical scanning period (V) = effective scanning period (E) + ineffective scanning period (NE), where the effective scanning period (E) = horizontal scanning period (H) × number of pixel rows (m). Also, the ineffective scanning period (NE) = vertical scanning period (V) - effective scanning period (E) = vertical scanning period (V) - horizontal scanning period (H) × number of pixel rows (m). If the overlap scan drive method is adopted and the precharge period is set to, for example, 2H, then the effective scanning period (E) = horizontal scanning period (H) × number of pixel rows (m) + 2H, and the ineffective scanning period (NE) = vertical scanning period (V) - horizontal scanning period (H) × number of pixel rows (m) - 2H.

[0007] The object of the present invention is to provide a display device that can suppress the increase in line memory even when an overlap scan drive method is employed, or when a dummy stage is provided in a gate drive circuit such as a GOA. [Means for solving the problem]

[0008] According to embodiments of the present invention, the following solutions are provided.

[0009] [Item 1] Multiple pixels arranged in a matrix having multiple pixel rows and multiple pixel columns, Each of the scan signal lines is associated with one of the aforementioned row of pixels, Each of the multiple display signal lines is associated with one of the multiple pixel rows, A scan signal line drive circuit supplies a scan signal to the plurality of scan signal lines, which includes a selection pulse that selects one of the plurality of pixel rows. A display signal line drive circuit that supplies display signals to the plurality of display signal lines, It has, A display device wherein the scanning signal line drive circuit is configured such that at least one near-frame horizontal scanning period, including the first of a plurality of horizontal scanning periods that exist during the period from the start of an input frame in the scanning signal line drive circuit until the falling edge of the selection pulse supplied to the first scanning signal line, is shorter than the other horizontal scanning periods.

[0010] [Item 2] The system further includes a control circuit that supplies control signals to the scanning signal line drive circuit and the display signal line drive circuit. The control circuit includes a timing controller and a level shifter. The level shifter is configured to supply to the scan signal line drive circuit a plurality of gate clock signals (GCK1~m) that shorten the at least one frame-first reference horizontal scanning period to the other horizontal scanning periods, based on a first gate clock signal (A or B) which includes high pulses at a shorter period than other reference horizontal scanning periods of the frame in the timing controller, during at least one frame-first reference horizontal scanning period including the first reference horizontal scanning period of the frame in the timing controller. The display device described in item 1.

[0011] [Item 3] The display device according to item 2, wherein the timing controller is configured to generate and supply the first gate clock signal (A or B) to the level shifter.

[0012] [Item 4] The control circuit further includes an OR circuit, The timing controller is configured to generate a second gate clock signal (A) which includes a high pulse with the same period as the other reference horizontal scanning period, and a third gate clock signal (B) which has at least one high pulse during the period when the second gate clock signal is at a low level in each of the at least one reference horizontal scanning period near the beginning of a frame, and is at a low level during periods other than the at least one reference horizontal scanning period near the beginning of a frame. The OR circuit generates the first gate clock signal (AorB) based on the second gate clock signal (A) and the third gate clock signal (B) generated by the timing controller, and is configured to supply the first gate clock signal (AorB) to the level shifter. The display device according to item 2.

[0013] [Item 5] When the other horizontal scanning period is 1H0, the horizontal scanning period near the start of at least one frame is 0.5H0 or less. The display device according to any one of items 1 to 4.

[0014] [Item 6] The horizontal scanning period near the start of at least one frame includes all of the plurality of horizontal scanning periods. The display device according to any one of items 1 to 5.

[0015] [Item 7] The horizontal scanning period near the start of at least one frame includes the first horizontal scanning period and at least one horizontal scanning period consecutive to the first horizontal scanning period. The display device according to any one of items 1 to 5.

[0016] [Item 8] When the other horizontal scanning period is 1H, the horizontal scanning period near the start of at least one frame is 0.3H or more. The display device according to any one of items 1 to 7.

[0017] [Item 9] The width of the selection pulse is longer than two horizontal scanning periods. The display device according to any one of items 1 to 8.

[0018] [Item 10] The scanning signal line driving circuit has a shift register circuit, and the shift register circuit has at least one dummy stage in a stage before the first stage that supplies a scanning signal to the scanning signal line connected to the pixel row of the first row. The display device according to any one of items 1 to 9.

[0019] [Item 11] The display device according to item 10, wherein the output of at least one dummy stage is connected to the corresponding at least one dummy scan signal line.

[0020] [Item 12] The display device according to any one of items 1 to 11, wherein the scanning signal line driving circuit is formed on the same substrate as the plurality of scanning signal lines. [Effects of the Invention]

[0021] According to embodiments of the present invention, a display device is provided that can suppress the increase in line memory even when employing an overlap scan drive method. [Brief explanation of the drawing]

[0022] [Figure 1] This is a schematic diagram of a liquid crystal display device 100 according to an embodiment of the present invention. [Figure 2] This is a block diagram showing the configuration of the control circuit 150C of the comparative example liquid crystal display device. [Figure 3] This is a timing chart of various signals in a comparative example liquid crystal display device. [Figure 4] This is a block diagram showing the configuration of the control circuit 150A of the liquid crystal display device according to Embodiment 1 of the present invention. [Figure 5] This is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 1 of the present invention. [Figure 6] This is a block diagram showing the configuration of the control circuit 150B of the liquid crystal display device according to Embodiment 2 of the present invention. [Figure 7] This is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 3 of the present invention. [Figure 8] This is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 4 of the present invention. [Figure 9]This is an example of timing charts for various signals in a liquid crystal display device, as in another comparative example. [Figure 10] This is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 5 of the present invention. [Figure 11] This is a block diagram showing the configuration of a shift register circuit 130 that can be used in the gate drive circuit 120 of a liquid crystal display device according to an embodiment of the present invention. [Figure 12] Figure 11 shows the timing chart of each signal when the gate drive circuit 120, which has the shift register circuit 130 shown, is driven using a conventional method. [Figure 13] This is a timing chart of each signal when the shift register circuit 130 shown in Figure 11 is driven using the fast-scanning method of Embodiment 1. [Figure 14] This is a block diagram showing the configuration of another shift register circuit 135 that may be used in the gate drive circuit 120 of the liquid crystal display device according to an embodiment of the present invention. [Figure 15] Figure 14 shows the timing chart of each signal when the gate drive circuit 120, which has a shift register circuit 135, is driven using a conventional method. [Figure 16] This is a timing chart of each signal when the shift register circuit 135 shown in Figure 14 is driven using the rapid scanning method of Embodiment 5. [Modes for carrying out the invention]

[0023] A display device according to an embodiment of the present invention comprises a plurality of pixels arranged in a matrix having a plurality of pixel rows (m rows) and a plurality of pixel columns (n ​​columns), a plurality of scan signal lines (m lines), each associated with one of the plurality of pixel rows, a plurality of display signal lines (n lines), each associated with one of the plurality of pixel columns, a scan signal line drive circuit that supplies scan signals to the plurality of scan signal lines, each including a selection pulse that selects one of the plurality of pixel rows, and a display signal line drive circuit that supplies display signals to the plurality of display signal lines, wherein the scan signal line drive circuit is configured to make at least one horizontal scanning period near the beginning of a frame, including the first horizontal scanning period among a plurality of horizontal scanning periods that exist from the start of a frame at the input of the scan signal line drive circuit until the selection pulse supplied to the first scan signal line falls, shorter than the other horizontal scanning periods.

[0024] Here, let H0 be the other horizontal scanning periods, and H1 be the horizontal scanning period near the beginning of the frame that is shorter than the other horizontal scanning periods H0. If, for example, there are four horizontal scanning periods near the beginning of the frame H1 that include the first horizontal scanning period among the multiple horizontal scanning periods that exist in the period from the start of the frame to the falling edge of the selection pulse supplied to the first scan signal line at the input of the scan signal line drive circuit, and if H1 = H0 / 2, then the two horizontal scanning periods 2H0 in the conventional drive method can be changed to four horizontal scanning periods 4H1. Therefore, in the period during which only two scan lines could be scanned in the conventional drive method, four scan lines can be scanned. This is sometimes called "rapid scanning (high-speed scanning)". Also, at least one horizontal scanning period near the beginning of the frame during which rapid scanning (high-speed scanning) is performed is sometimes called the "rapid scanning period (high-speed scanning period)".

[0025] In a display device according to an embodiment of the present invention, the horizontal scanning period near the beginning of a frame (H1), which is shorter than the other horizontal scanning periods (H0), is sometimes referred to as the "shortened horizontal scanning period (H1)," and the other horizontal scanning periods (H0) are sometimes referred to as the "standard horizontal scanning period (H0)."

[0026] The display device has, for example, a control circuit that supplies control signals to the scan signal line drive circuit and the display signal line drive circuit, and the control circuit has a timing controller and a level shifter. Later, as shown in the timing charts in Figures 3 and 5, the start of the "vertical scanning period (frame) in the display area" is the rising edge of the on-pulse of the first gate signal (GOP of GS(1)) from the output of the scan signal line drive circuit (GOA), excluding the dummy gate signal (i.e., the start of the effective scanning period (E)), and the start of the "vertical scanning period (frame) at the input of the scan signal line drive circuit" is the rising edge of the gate start pulse GSP. The rising edge timing of the gate start pulse GSP is determined by the timing controller. GSP is the signal obtained by level-shifting the output Tcon-GSP of the timing controller by the level shifter, and generally the timing of Tcon-GSP and GSP are substantially the same (in reality, there is a very small delay necessary for level conversion, but this can be considered to be within the margin of error). The timing controller determines each period based on the (input) synchronization signal, which is input along with or included in the input video signal, according to the resolution and drive frequency of the display device. These periods are referred to as each period "in the timing controller" (for example, the vertical scanning period and the horizontal scanning period in the timing controller). Furthermore, each period in the timing controller is referred to as each reference period (for example, the reference vertical scanning period (V B ) and reference horizontal scanning period (H B )) That's also a possibility.

[0027] In the display device according to the embodiment of the present invention, the horizontal scanning period in the display area of ​​a conventional display device that does not perform rapid forwarding (high-speed scanning) is always the reference horizontal scanning period (H B ) is equal to H1 = H B If set to / 2, the two reference horizontal scanning periods H B This corresponds to generating four horizontal scanning periods 4H1.

[0028] In a display device according to an embodiment of the present invention, the scanning signal line drive circuit (GOA) is configured such that at least one frame-beginning horizontal scanning period (H1), which includes the first horizontal scanning period among a plurality of horizontal scanning periods that exist from the start of a frame at the input of the scanning signal line drive circuit until the falling edge of the selection pulse supplied to the first scanning signal line, is shorter than the other horizontal scanning periods (H0). The other horizontal scanning periods (H0) are the reference horizontal scanning period (H B ) may be the same as the reference horizontal scanning period (H0). B By making it the same as ), the advantage is that the configuration of the control circuit can be simplified.

[0029] Fast scanning is performed at least during the non-effective scanning period (NE). For example, as illustrated later, fast scanning may be performed only during the non-effective scanning period (NE) (e.g., Figures 5 and 13), or it may be performed during both the non-effective scanning period (NE) and the subsequent effective scanning period (E) (e.g., Figures 7, 8, 10, and 16). Performing fast scanning during the non-effective scanning period (NE) immediately preceding the effective scanning period (E) can reduce the memory required by the timing controller (Tcon-IC).

[0030] In a display device according to an embodiment of the present invention, for example, the level shifter is configured to supply a plurality of gate clock signals (GCK1~m) to the scan signal line drive circuit, which shorten the horizontal scanning period near the beginning of at least one frame in the frame in the scan signal line drive circuit to a horizontal scanning period near the beginning of a frame, based on a first gate clock signal (A or B) that includes high pulses with a shorter period than other horizontal scanning periods in the timing controller, during at least one reference horizontal scanning period near the beginning of a frame in the timing controller, including the first reference horizontal scanning period in the timing controller.

[0031] In a display device according to an embodiment of the present invention, for example, the control circuit further comprises an OR circuit, and the timing controller is configured to generate a second gate clock signal (A) which includes a high pulse with the same period as other reference horizontal scanning periods, and a third gate clock signal (B) which has at least one high pulse during the period when the second gate clock signal (A) is low level in each of at least one reference horizontal scanning periods near the beginning of a frame, and is low level during periods other than at least one reference horizontal scanning period near the beginning of a frame, and the OR circuit is configured to generate a first gate clock signal (A or B) based on the second gate clock signal (A) and the third gate clock signal (B) generated by the timing controller, and to supply the first gate clock signal (A or B) to a level shifter (see, for example, Embodiment 1, Figure 4 described later). For example, the third gate clock signal (B) may have one high pulse within one reference horizontal scanning period near the beginning of a frame. In this case, the third gate clock signal (B) may have the same waveform as the second gate clock signal (A) and be out of phase with the second gate clock signal (A). Furthermore, the third gate clock signal (B) may have two or more high pulses within a reference horizontal scanning period near the beginning of a single frame.

[0032] Furthermore, in the display device according to an embodiment of the present invention, the timing controller may be configured to generate a first gate clock signal (A or B) and supply it to the level shifter (see, for example, Embodiment 2 described later, Figure 6).

[0033] If the other horizontal scanning periods are H0, then the horizontal scanning period H1 near the beginning of at least one frame is 0.5H0 or less. Preferably, the horizontal scanning period H1 near the beginning of at least one frame is 0.1H0 or more. If the horizontal scanning period H1 near the beginning of at least one frame is less than 0.1H0, insufficient charging of pixels becomes noticeable. Furthermore, it is preferable that the horizontal scanning period near the beginning of at least one frame is 5 horizontal scanning periods or less. If the fast-forward period is extended, the pixels at the top of the screen cannot be sufficiently charged, increasing concerns about a decrease in display quality. In addition, the margin of operational stability of the GOA may decrease.

[0034] The display devices according to embodiments of the present invention will be described below with reference to the drawings. The display devices according to embodiments of the present invention are not limited to those exemplified below.

[0035] The following describes an active-matrix display device in which each pixel has a TFT. In the active-matrix display device of this embodiment, each of a plurality of pixels has a display medium layer, a pair of electrodes arranged opposite each other across the display medium layer, and a TFT with a drain electrode connected to one of the pair of electrodes; a plurality of scan signal lines are a plurality of gate bus lines; a plurality of display signal lines are a plurality of source bus lines; the gate electrode of the TFT is connected to a gate bus line associated with a pixel row containing a pixel having a TFT; the source electrode of the TFT is connected to a source bus line associated with a pixel column containing a pixel having a TFT; the scan signal line drive circuit is a gate drive circuit, and the scan signal is a gate scan signal (GS) which includes a gate-on pulse (GOP) as a selection pulse that turns on the TFT; the display signal line drive circuit is a source drive circuit, and the display signal is a source signal (SS).

[0036] The following describes an active-matrix type liquid crystal display device in which the display medium layer is a liquid crystal layer, with reference to the drawings. Note that the liquid crystal display device according to the embodiments of the present invention is not limited to those exemplified below.

[0037] Figure 1 shows a schematic diagram of a liquid crystal display device 100 according to an embodiment of the present invention.

[0038] The liquid crystal display device 100 has a plurality of pixels P arranged in a matrix having a plurality of pixel rows (m rows) and a plurality of pixel columns (n ​​columns). The liquid crystal display device 100 is an active matrix type liquid crystal display device, and each pixel P has a thin-film transistor (TFT) and a liquid crystal capacitance Clc. The pixel P may further have an auxiliary capacitance Cs (not shown) electrically connected in parallel with the liquid crystal capacitance Clc. For simplicity, the explanation of the auxiliary capacitance Cs is omitted here. The liquid crystal capacitance Clc is composed of, for example, a pixel electrode (not shown) formed on the active matrix substrate 110 and a common electrode (also called a counter electrode; not shown) arranged to face the pixel electrode via a liquid crystal layer (not shown). The common electrode is formed on, for example, a counter substrate 112 arranged facing the active matrix substrate 110.

[0039] The region where multiple pixels P are formed is called the active region AA or display region. The pixel in the k row and l column of a pixel arranged in m rows and n columns is sometimes represented as P(k, l). k, l, m, and n are positive integers that satisfy the relationships 1 ≤ k ≤ m and 1 ≤ l ≤ n. For example, in a liquid crystal display device with a so-called resolution of 2K or 4K, m = 2160 and n = 3840 × 3 (when a color display pixel is composed of R pixels, G pixels, and B pixels, the "pixel" here is sometimes called a "dot," and the "color display pixel" composed of three "dots" is sometimes called a "pixel"). Each of the multiple pixels has a liquid crystal capacitance Clc including a pixel electrode and a TFT with a drain electrode connected to the pixel electrode.

[0040] The liquid crystal display device 100 further includes a plurality of gate bus lines GB (m lines), each associated with one of a plurality of pixel rows, and a plurality of source bus lines SB (n lines), each associated with one of a plurality of pixel columns. The gate electrode of the TFT of each pixel is connected to the gate bus line GB associated with the pixel row in which the pixel is contained, and the source electrode of the TFT is connected to the source bus line SB associated with the pixel column in which the pixel is contained.

[0041] The liquid crystal display device 100 further includes a gate drive circuit 120 that supplies gate scanning signals, including gate-on pulses GOP that turn on the TFTs, to multiple gate bus lines GB, and a source drive circuit 140 that supplies source signals to multiple source bus lines SB. Here, the gate drive circuit 120 is shown as an example in which two gate drive circuits (GOA(L) and (R)) 120 are arranged on both the left and right sides of the active region AA, but of course, a single gate drive circuit 120 located on either the left or right side may supply gate scanning signals to all gate bus lines. The gate drive circuit 120 is sometimes denoted as GOA.

[0042] The liquid crystal display device 100 is of the GOA type, and the gate drive circuit 120 is formed on the active matrix substrate 110, as well as the pixel electrodes, TFTs, multiple source bus lines SB, and multiple gate bus lines GB. The active matrix substrate 110 is manufactured by known methods, for example, on a glass substrate, having a conductive layer (metal layer), a semiconductor layer, and an insulating layer, as is well known. The source drive circuit 140 may be mounted on the active matrix substrate 110 as, for example, source drive ICs (S-DrICs), or a flexible substrate on which source drive ICs are mounted may be connected to the active matrix substrate 110.

[0043] The gate drive circuit 120 and the source drive circuit 140 are controlled by a control circuit 150. The control circuit 150 includes a timing controller (Tcon-IC) and a level shifter. The timing controller determines a reference vertical scanning period (V B ) and a reference horizontal scanning period (H B ) according to the resolution, driving frequency, etc. of the display device based on the (input) synchronization signal input together with or included in the input video signal. The control circuit 150 supplies control signals necessary for the gate drive circuit 120 and the source drive circuit 140 respectively. The liquid crystal display device 100 further has a power supply circuit (not shown) that supplies power supply voltages necessary for the gate drive circuit 120 and the source drive circuit 140 respectively.

[0044] The control circuit 150 outputs a synchronization signal (horizontal synchronization signal), a gate start pulse GSP, and a gate clock signal GCK to the gate drive circuit 120. Here, eight-phase gate clock signals GCK1 to 8 are output. The control circuit 150 also outputs a synchronization signal (vertical synchronization signal) and a display signal to the source drive circuit 140.

[0045] The gate drive circuit 120 supplies a gate scan signal so as to sequentially apply a gate on pulse GOP for turning on the TFTs to a plurality of gate bus lines GB along the scanning direction, and the source drive circuit 140 supplies a display signal to a plurality of source bus lines SB so that a gradation voltage to be displayed at the pixel is applied to the pixel electrode connected to the TFT turned on by the gate on pulse GOP.

[0046] Next, with reference to Figures 2 and 3, the configuration of the control circuit 150C of the comparative example liquid crystal display device and the timing of various signals will be explained. The comparative example liquid crystal display device is driven by a conventional driving method that does not perform fast-forwarding (high-speed scanning). Figure 2 is a block diagram showing the configuration of the control circuit 150C of the comparative example liquid crystal display device, and Figure 3 is a timing chart of various signals in the comparative example liquid crystal display device. For example, a similar timing chart is described in Patent Document 2 for the liquid crystal display device. The timing chart in Figure 3 corresponds to the timing chart in Figure 7 of Patent Document 2, in which the number of GCK phases is changed from 4 phases to 8 phases and the L / H duty cycle of GCK is changed from 2:2 to 3:5.

[0047] Refer to Figure 2. The control circuit 150C receives the video signal and synchronization signal from the Tcon-IC 152C, generates the Tcon-GSP (gate start pulse output by the Tcon-IC 152C) and Tcon-GCK signal (gate clock signal output by the Tcon-IC 152C), outputs them to the level shifter 154C, and also outputs the display signal and synchronization signal to the source drive circuit 140. In the comparative example liquid crystal display device, the horizontal scanning period H in the display area is the reference horizontal scanning period H in the Tcon-IC. B The same standard horizontal scanning period H0. Tcon-GSP and Tcon-GCK are digital signals with voltages of, for example, 0V and 3.3V. The level shifter 154C generates gate start pulse GSP and gate clock signals GCK1~GCK8 based on the input Tcon-GSP and Tcon-GCK, and outputs them to the gate drive circuit 120. These are analog signals with voltages of, for example, -7V and 35V.

[0048] Refer to Figure 3. When the Tcon-IC takes in the input signal, it uses a 1-line memory delay (1H) for purposes such as recognizing the synchronization signal and rearranging it for the internal bus. B) occurs. The Tcon-IC can then begin generating the gate start pulse GSP (high-level portion, pulse width 4H0), which is the leading signal of the frame at the input of the scan signal line drive circuit (GOA). The input signal to the Tcon-IC in Figure 3 is 1H B This is shown in each block. The scanning signal line drive circuit (GOA) starts its internal operation when the gate start pulse GSP rises.

[0049] In this example, GOA requires 8H0 from the rising edge of the gate start pulse GSP to the falling edge of the gate-on pulse GOP (high-level portion) included in the gate scan signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row in the active region AA. Note that, since the overlap scan drive method is applied here, the gate-on pulse GOP has a width of 3H0 including a pre-charge period of 2H0 (the high-level period is 3H0).

[0050] Furthermore, a 1H0 delay occurs in S-Dr (d1 in Figure 3), and S-Dr outputs a voltage for the corresponding pixel for a 1H0 period (s1 in Figure 3), resulting in a line delay of 6H0 (8H0-1H0-1H0) required for the Tcon-IC. In this way, the S-Dr output synchronizes with the gate-on pulse GOP (high-level portion) included in the gate scan signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row.

[0051] The GOA outputs gate scanning signals GS(1), GS(2), ... GS(m) based on GSP and GCK1-8. For example, in the case of a liquid crystal display with a resolution of 2K or 4K, there are up to GS(2160).

[0052] Next, a liquid crystal display device according to Embodiment 1 of the present invention will be described with reference to Figures 4 and 5. Figure 4 is a block diagram showing the configuration of the control circuit 150A of the liquid crystal display device according to Embodiment 1 of the present invention, and Figure 5 is an example of a timing chart of various signals in the liquid crystal display device according to Embodiment 1 of the present invention.

[0053] As shown in Figure 4, the control circuit 150A includes a Tcon-IC 152A, a level shifter 154A, and an OR circuit 156A. The Tcon-IC 152A generates Tcon-GSP and two types of gate clocks, Tcon-GCK-A and Tcon-GCK-B, and outputs a display signal and a synchronization signal to the source drive circuit 140. Tcon-GCK-A and Tcon-GCK-B are input to the OR circuit 156A, which performs an "OR" operation to generate a gate clock signal GCK-A or B and outputs it to the level shifter 154A. The OR circuit 156A can be implemented, for example, with a relatively inexpensive external discrete IC (one unit). Alternatively, a wired-OR circuit may be used instead of a discrete IC. These are digital signals, and their voltages are, for example, 0V and 3.3V. The level shifter 154A generates a gate start pulse GSP and gate clock signals GCK1~GCK8 based on the input Tcon-GSP and gate clock signal GCK-A or B, and outputs them to the gate drive circuit 120. These are analog signals, and their voltages are, for example, -7V and 35V.

[0054] Refer to Figure 5. The waveform of Tcon-GCK-A is the same as Tcon-GCK in the comparative example above. The waveform of Tcon-GCK-B is out of phase with Tcon-GCK-A by 0.5H0 near the beginning of the frame (2H0), and is constant at "L" (low level) everywhere else. By performing an "OR" operation on Tcon-GCK-A and Tcon-GCK-B, a gate clock signal GCK-A or B can be generated, which has a waveform in which the period of the GCK "H" pulse is 0.5H0 (=1H1) only near the beginning of the frame.

[0055] When the level shifter 154A generates a signal to output to GOA based on the gate clock signal GCK-A or B, the horizontal scan period of GOA is shortened to 0.5H0 (=1H1) only during the horizontal scanning period near the beginning of the frame (here, the period corresponding to the pulse width of GSP, the reference horizontal scanning period near the beginning of the frame in the timing controller (1st to 2nd reference horizontal scanning periods, corresponding to 1 and 2 in the second row from the top in Figure 5)) (from the start of the frame until 1H0 before the rising edge of the gate-on pulse GOP (high-level portion) included in the gate scanning signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row), allowing for what could be called fast scanning. Note that the horizontal scanning period of the Tcon-IC output and the S-Dr output is H0 (the H of the signal input to Tcon-IC). B It is constant (same as above).

[0056] In this way, the line delay required for the Tcon-IC can be shortened, and in this example it is 4H0 (6H0-1H0-1H0), which is 2H0 shorter than the 6H0 in the comparative example liquid crystal display shown in Figure 3. The period during which the horizontal scanning period of GOA is shortened to 0.5H0 (=1H1) is until 1H0 before the rising edge of the gate-on pulse GOP (high-level portion) included in the gate scanning signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row. Therefore, the width of the gate scanning signal GS(1) of the GOA output is the same as the width of the GOP from GS(2) onward.

[0057] Next, refer to Figure 6. Figure 6 is a block diagram showing the configuration of the control circuit 150B of the liquid crystal display device according to Embodiment 2 of the present invention. The timing charts for the various signals in the liquid crystal display device according to Embodiment 2 may be the same as the timing charts for the various signals in the liquid crystal display device according to Embodiment 1 shown in Figure 5, so they are omitted here.

[0058] Unlike the control circuit 150A in the liquid crystal display device according to Embodiment 1, the control circuit 150B in the liquid crystal display device according to Embodiment 2 uses the Tcon-IC 152B to generate Tcon-GSP and GCK-A or B, eliminating the need for an OR circuit. Therefore, the control circuit 150B can be implemented at a lower cost than the control circuit 150A.

[0059] Next, refer to Figure 7. Figure 7 is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 3 of the present invention. The control circuit of the liquid crystal display device according to Embodiment 3 may be the same as, for example, the control circuit 150A of the liquid crystal display device according to Embodiment 1 shown in Figure 4.

[0060] In the liquid crystal display device according to Embodiment 3, the period of fast scanning (high-speed scanning) is made longest near the beginning of the frame. In the timing chart of various signals in the liquid crystal display device according to Embodiment 1 shown in Figure 5, the horizontal scanning period of GOA is shortened to 0.5H0 (=1H1) only during the horizontal scanning period near the beginning of the frame (reference horizontal scanning period near the beginning of the frame in the timing controller (here, the first to second reference horizontal scanning periods, corresponding to 1 and 2 in the second row from the top of Figure 5)) (from the start of the frame until 1H0 before the rising edge of the gate on pulse GOP (high-level portion) included in the gate scanning signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row). In contrast, in the liquid crystal display device of Embodiment 3, the horizontal scanning period of GOA is shortened to 0.5H0 (=1H1) only within the frame-preceding horizontal scanning period (reference horizontal scanning period near the frame in the timing controller (here, the 1st to 4th reference horizontal scanning periods, corresponding to 1 to 4 in the second row from the top in Figure 7)) from the start of the frame to the falling edge of the gate on-pulse GOP (high-level portion) included in the gate scanning signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row. As a result, in the liquid crystal display device of Embodiment 3, the line delay required for the Tcon-IC is shortened to 2H0 (4H0-1H0-1H0).

[0061] Thus, extending the period during which the horizontal scan period of the GOA is shortened (sometimes called the fast-forward period) increases the amount of line memory that can be reduced, resulting in the advantages of cost reduction and / or an increase in the selection of Tcon-ICs. On the other hand, extending the fast-forward period may prevent the pixels at the top of the screen (for example, from the first to the third row of pixels) from being sufficiently charged, increasing concerns about a decrease in display quality. It may also reduce the margin of GOA operational stability.

[0062] In Figure 7, the width of the GOP for the gate scan signals GS(1), GS(2), and GS(3) of the GOA output is smaller than the width of the GOP from GS(4) onwards, resulting in a shorter charging time and a reduced effect of the overlap scan drive method. However, the first to third pixel rows are located at the edge of the screen and are therefore less noticeable, and the charging time decreases in the order of the first to third pixel rows, making them less noticeable and thus less likely to cause practical problems. However, since it is difficult to shorten the 1 horizontal scan period (1H0) of the Tcon-IC output (for S-Dr), it is preferable that the fast-forward period be set to the falling edge of the gate-on pulse GOP (high-level portion) included in the gate scan signal GS(1) supplied to the gate bus line GB(1) connected to the first pixel row.

[0063] Next, refer to Figure 8. Figure 8 is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 4 of the present invention. The control circuit of the liquid crystal display device according to Embodiment 4 may be the same as, for example, the control circuit 150A of the liquid crystal display device according to Embodiment 1 shown in Figure 4.

[0064] In the liquid crystal display device according to Embodiment 4, the fast-forward speed is greater than that of the liquid crystal display device according to Embodiment 1 (Embodiment 1: 2 times faster, Embodiment 4: 3 times faster). That is, in the liquid crystal display device according to Embodiment 1, the horizontal scanning period in the display area (i.e., GOA) is shortened to 0.5H0 (=1H1), whereas in the liquid crystal display device according to Embodiment 4, it is shortened to 0.33H0 (=1H1) (see Tcon-GCK-B in Figure 8). The fast-forward period is the same as in the liquid crystal display device according to Embodiment 1, consisting only of the reference horizontal scanning period near the beginning of the frame in the timing controller (1st to 2nd reference horizontal scanning periods).

[0065] In the liquid crystal display device according to Embodiment 4, the line delay required for the Tcon-IC is reduced to 2H0 (4H0-1H0-1H0). In the liquid crystal display device according to Embodiment 3, the line delay required for the Tcon-IC is also reduced to 2H0, but as mentioned above, the width of the GOP for the gate scan signals GS(1), GS(2), and GS(3) of the GOA output is smaller than the width of the GOP from GS(4) onwards, resulting in a shorter charging time. In contrast, in the liquid crystal display device according to Embodiment 4, only the width of the GOP for the gate scan signal GS(1) of the GOA output is smaller than the width of the GOP from GS(2) onwards. Therefore, it can be said that the impact of the deterioration of display quality due to fast rotation is smaller in the liquid crystal display device according to Embodiment 4. However, since the liquid crystal display device according to Embodiment 4 has a faster rotation speed than the liquid crystal display device according to Embodiment 3, the operating margin is smaller.

[0066] Next, refer to Figures 9 and 10. Figure 9 is an example of timing charts for various signals in a liquid crystal display device of another comparative example, and Figure 10 is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 5 of the present invention. The control circuit of the liquid crystal display device according to Embodiment 5 may be the same as, for example, the control circuit 150A of the liquid crystal display device according to Embodiment 1 shown in Figure 4.

[0067] In the timing chart of the comparative example shown in Figure 3, the GOA delay (the period from the rising edge of the GSP pulse to the falling edge of the GOP of the gate scan signal GS(1)) was 8H0, whereas Figure 9 shows an example where the GOA delay is 4H0.

[0068] Furthermore, in the timing chart shown in Figure 3, the S-Dr output of the Tcon-IC is the same display signal supplied to the first pixel row for two lines for precharging the first pixel row (two-line copy). Therefore, the S-Dr output of the Tcon-IC in Figure 3 supplies the signal to the first pixel row during the 5th, 6th, and 7th reference horizontal scanning periods in the timing controller (corresponding to periods 5-7 in the second row from the top in Figure 3). (The "1" indicated for the S-Dr output of the Tcon-IC in Figure 3 during the 5th, 6th, and 7th reference horizontal scanning periods indicates that the same signal as the source signal SS1 supplied during the 7th reference horizontal scanning period is supplied to the two lines during the 5th and 6th reference horizontal scanning periods.) In contrast, line copying is not used in the timing chart shown in Figure 9. Whether or not to use line copying is mainly determined based on the panel's source time constant and the target display quality.

[0069] In the comparative example liquid crystal display device shown in Figure 9, the horizontal scanning period H is the same for all outputs of the Tcon-IC, the S-Dr, and the GOA input / output. B The standard horizontal scanning period H0 is the same and is always constant. The line delay required for the Tcon-IC is 2H0 (4H0-1H0-1H0).

[0070] Next, refer to Figure 10. Figure 10 is an example of timing charts for various signals in a liquid crystal display device according to Embodiment 5 of the present invention. The control circuit of the liquid crystal display device according to Embodiment 5 may be the same as, for example, the control circuit 150A of the liquid crystal display device according to Embodiment 1 shown in Figure 4.

[0071] In the liquid crystal display device according to Embodiment 5, the period of fast forwarding (high-speed scanning) near the beginning of the frame is shortened. In the timing chart of various signals in the liquid crystal display device according to Embodiment 5 shown in Figure 10, the horizontal scanning period of GOA is shortened to 0.5H0 (=1H1) only within the horizontal scanning period near the beginning of the frame (here, the reference horizontal scanning period near the beginning of the frame in the timing controller (first reference horizontal layer period, the period corresponding to 1 in the second row from the top in Figure 10)).

[0072] In the liquid crystal display device according to Embodiment 5, the line delay required for the Tcon-IC is reduced to 1H0 (3H0-1H0-1H0). In the liquid crystal display device according to Embodiment 5, only the width of the GOP of the gate scan signal GS(1) of the GOA output is smaller than the width of the GOPs from GS(2) onward. Therefore, the charging time is shortened only for the first pixel row, and the effect of the overlap scan driving method is reduced. However, since the first pixel row is located at the edge of the screen, it is not very noticeable, so it is unlikely to cause practical problems.

[0073] As the gate drive circuit 120 of the liquid crystal display device according to an embodiment of the present invention, for example, the gate drive circuit described in U.S. Patent Application Publication No. 2022 / 0208137 can be suitably used. All disclosures of U.S. Patent Application Publication No. 2022 / 0208137 are incorporated herein by reference.

[0074] The gate drive circuit 120 of the liquid crystal display device according to an embodiment of the present invention can use the shift register circuit 130 shown in Figure 11. Figure 11 is a block diagram showing the configuration of a shift register circuit 130 that can be used in the gate drive circuit 120 of the liquid crystal display device according to Embodiment 1 of the present invention. Note that CLK1 to CLK8 in Figures 11 to 16 below represent the same signals as GCK1 to CLK8 in Figures 1 to 10.

[0075] The gate drive circuit 120 has, for example, the shift register circuit 130 shown in Figure 11. The shift register circuit 130 has multiple stages (sometimes called unit circuits or shift circuits) SR1, SR2, ... SR3.

[0076] Multiple input signals are supplied to the gate drive circuit 120 from a control circuit (for example, the control circuit 150 in Figure 1) via multiple input signal lines. Here, the input signals are clock signals CLK1 to CLK8 and a reference voltage signal Vss, and the respective input signal lines are sometimes referred to as clock signal lines CLK1 to CLK8 and reference voltage signal line Vss. Each stage of the shift register circuit 130 receives the clock signal CLK, the reference voltage signal Vss, the Set signal S, and the Reset signal R. The Set signal S and Reset signal R are signals generated in other stages. From each stage of the shift register circuit 130, a gate scan signal GS is output to the gate bus line GB corresponding to each pixel row. In Figure 11, the gate signal corresponding to the k-th pixel row is represented as GS(k), and the k-th stage of the shift register circuit 130 is represented as SRk. Note that the terminals that output or receive each signal will be represented by the same reference numeral for the signals output or received from that terminal.

[0077] The shift register circuit 130 shown in Figure 11 has three dummy stages DSR3, DSR2, and DSR1 preceding the first stage SR1, which supplies the gate signal GS(1) to the gate bus line GB(1) connected to the first row of pixels. The dummy gate signals DGS(3), DGS(2), and DGS(1) are output from the output terminal Gout of the dummy stages DSR3, DSR2, and DSR1, respectively. The output Gout of the dummy stages DSR3, DSR2, and DSR1 may be connected to a dummy bus line, for example, or it may not be connected to anything.

[0078] The output terminal Gout of the third dummy stage DSR3 is connected to the dummy gate signal terminal DGS(3) and also to the Set signal terminal S of the first stage SR1. Similarly, the output terminal Gout of the second dummy stage DSR2 is connected to the dummy gate signal terminal DGS(2) and also to the Set signal terminal S of the second stage SR2. The output terminal Gout of the first dummy stage DSR1 is connected to the dummy gate signal terminal DGS(1) and also to the Set signal terminal S of the third stage SR3.

[0079] The shift register circuit 130 operates in the following manner, sequentially outputting gate signals GS(1~m) to the gate bus line GB(1~m), thereby sequentially scanning the gate bus line GB(1~m).

[0080] The gate start pulse GSP is input to the Set signal terminal S of the third dummy stage DSR3, and the gate clock signal CLK6 is input to the gate clock signal terminal CLK. After the gate start pulse GSP (high level) is input, when the gate clock signal CLK6 (high level) is input, the gate open pulse GOP (high level) is output from the output terminal Gout of the third dummy stage DSR3 (third dummy gate signal DGS(3)).

[0081] When a gate open pulse GOP (high level) is output from the output terminal Gout of the third dummy stage DSR3, a high level is input to the Set signal terminal S of the first stage SR1. Subsequently, when a high level of the clock signal CLK1 is input to the first stage SR1, a gate open pulse GOP (high level) is output from the output terminal Gout of the first stage SR1 (first gate signal GS(1)).

[0082] When a gate open pulse GOP (high level) is output from the output terminal Gout of the first stage SR1, a high level is input to the SET signal terminal S of the fourth stage SR4. Subsequently, when a high level of the clock signal CLK4 is input to the fourth stage SR4, a gate open pulse GOP (high level) is output from the output terminal Gout of the fourth stage SR4 (fourth gate signal GS(4)).

[0083] The gate start pulse GSP is input to the Set signal terminal S of the second dummy stage DSR2, and the gate clock signal CLK7 is input to the gate clock signal terminal CLK. After the gate start pulse GSP (high level) is input, when the gate clock signal CLK7 (high level) is input, the gate open pulse GOP (high level) is output from the output terminal Gout of the second dummy stage DSR2 (second dummy gate signal DGS(2)).

[0084] When a gate open pulse GOP (high level) is output from the output terminal Gout of the second dummy stage DSR2, a high level is input to the SET signal terminal S of the second stage SR2. Subsequently, when a high level of the clock signal CLK2 is input to the second stage SR2, a gate open pulse GOP (high level) is output from the output terminal Gout of the second stage SR2 (second gate signal GS(2)).

[0085] When a gate open pulse GOP (high level) is output from the output terminal Gout of the second stage SR2, a high level is input to the SET signal terminal S of the fifth stage SR5. Subsequently, when a high level of the clock signal CLK5 is input to the fifth stage SR5, a gate open pulse GOP (high level) is output from the output terminal Gout of the fifth stage SR5 (fifth gate signal GS(5)).

[0086] When a gate open pulse GOP (high level) is output from the output terminal Gout of the second stage SR2, a high level is input to the Reset signal terminal R of the third dummy stage DSR3. When a high level is input to the Reset signal terminal R of the third dummy stage DSR3, the third dummy gate signal DGS(3) output from the output terminal Gout of the third dummy stage DSR3 becomes low level.

[0087] The shift register circuit 130 operates similarly to the connection relationships between each stage and each signal line shown in Figure 11.

[0088] The shift register circuit 130 has three dummy stages DSR3, DSR2, and DSR1 before the first stage that supplies the gate signal GS(1) to the gate bus line corresponding to the first pixel row of the active area (display area) AA, and therefore may have the following advantages.

[0089] The waveforms of the dummy gate signals DGS(3), (2), and (1) output from the three dummy stages DSR3, DSR2, and DSR1 may differ slightly from the waveforms of the gate signals GS(1), (2), and (3) supplied to the first, second, and third gate bus lines GB of the active region AA. Dummy stages are provided to prevent this waveform difference from affecting the display.

[0090] For example, the signal input to the SET signal terminal S of the three dummy stages DSR3, DSR2, and DSR1 is the gate start pulse GSP output from the control circuit 150, whereas the signal input to the SET signal terminal S of the first, second, and third stages SR1, SR2, and SR3 is the signal output from the output terminal Gout of the dummy stages DSR3, DSR2, and DSR1 (dummy gate signal DGS(1~3)). Therefore, the waveform of the signal output from the output terminal Gout of the dummy stages DSR3, DSR2, and DSR1 (dummy gate signal DGS(1~3)) may be slightly different from the waveform of the signal output from the output terminal Gout of the first, second, and third stages SR1, SR2, and SR3 (gate signal GS(1~3)). Therefore, if the signals output from the Gout output terminals of the dummy stages DSR3, DSR2, and DSR1 (dummy gate signals DGS(1~3)) are output to the active region gate bus line GB, the display quality of those three pixel rows may differ from that of the other pixel rows.

[0091] Figure 12 shows the timing chart of each signal when the shift register circuit 130 shown in Figure 11 is driven using a conventional method without high-speed scanning.

[0092] As mentioned above, using the shift register 130 shown in Figure 11 prevents the GOA delay from negatively affecting the display. However, when driven using the conventional driving method, the GOA delay (from the rising edge of GSP ↑ to the falling edge of the gate open pulse (high level) of the first gate signal GS(1) ↓) is 8H0, which presents a problem of a large GOA delay.

[0093] Figure 13 shows the timing chart of each signal when the shift register circuit 130 shown in Figure 11 is driven by the fast-scanning (high-speed scanning) method of Embodiment 1. In this way, the fast-scanning of Embodiment 1 can be performed using the shift register circuit 130, and the GOA delay (from the rising edge ↑ of GSP to the falling edge ↓ of the gate open pulse (high level) of the first gate signal GS(1)) can be set to 6H0.

[0094] Figure 14 is a block diagram showing the configuration of another shift register circuit 135 that may be used in the gate drive circuit 120 of the liquid crystal display device according to an embodiment of the present invention. The shift register circuit 135 shown in Figure 14 has the same structure as the shift register circuit 130 shown in Figure 11, except that it does not have a dummy stage, and operates similarly. Therefore, the waveforms of the signals (gate signals GS(1~3)) output from the output terminals Gout of the first, second, and third stages SR1, SR2, and SR3 may be slightly different from the waveforms of the signals (gate signals GS(4~6)) output from the output terminals Gout of the fourth, fifth, and sixth stages SR4, SR5, and SR6, and this may lead to a decrease in display quality. However, this effect is limited to three pixel rows and may not be a problem depending on the application.

[0095] Figure 15 shows the timing chart of each signal when the shift register circuit 135 shown in Figure 14 is driven using a conventional method without fast scanning.

[0096] As described above, using the shift register circuit 135 shown in Figure 14, there is no dummy stage, so when driven by the conventional driving method, the GOA delay (from the rising edge of GSP ↑ to the falling edge of the gate open pulse (high level) of the first gate signal GS(1) ↓) can be shortened to 4H0.

[0097] Figure 16 shows the timing chart of each signal when the shift register circuit 135 shown in Figure 14 is driven by the fast-scanning method of Embodiment 5. In this way, the fast-scanning method of Embodiment 5 can be performed using the shift register circuit 135, and the GOA delay (from the rising edge ↑ of GSP to the falling edge ↓ of the gate open pulse (high level) of the first gate signal GS(1)) can be set to 3H0.

[0098] As described above, in the liquid crystal display device according to the embodiment of the present invention, the GOA delay can be shortened, and therefore the delay of the display signal (source signal) can also be shortened. Consequently, the line memory can be reduced. Furthermore, it becomes possible to drive the GOA using a Tcon-IC for GCOF, which has a short delay. Tcon-ICs for GCOF have the advantage of being less expensive and more readily available than Tcon-ICs for GOA. [Industrial applicability]

[0099] The liquid crystal display device according to the embodiment of the present invention can be widely used in large and / or high-resolution liquid crystal display devices. [Explanation of Symbols]

[0100] 100:Liquid crystal display device 110: Active matrix substrate 112: Opposing substrate 120: Gate drive circuit 130, 135: Shift register circuit 140: Source drive circuit 150: Control circuit

Claims

1. Multiple pixels arranged in a matrix having multiple pixel rows and multiple pixel columns, Each of the scan signal lines is associated with one of the aforementioned row of pixels, Each of the multiple display signal lines is associated with one of the multiple pixel rows, A scan signal line drive circuit supplies a scan signal to the plurality of scan signal lines, which includes a selection pulse that selects one of the plurality of pixel rows. A display signal line drive circuit that supplies display signals to the plurality of display signal lines, It has, A display device wherein the scanning signal line drive circuit is configured such that at least one frame-beginning horizontal scanning period, including the first of a plurality of horizontal scanning periods that exist during the period from the start of a frame of input to the scanning signal line drive circuit until the falling of a selection pulse supplied to the first scanning signal line, is shorter than the other horizontal scanning periods.

2. The system further includes a control circuit that supplies control signals to the scanning signal line drive circuit and the display signal line drive circuit. The control circuit includes a timing controller and a level shifter. The level shifter is configured to supply to the scan signal line drive circuit a plurality of gate clock signals that shorten the at least one frame-first reference horizontal scanning period to the other horizontal scanning periods, based on a first gate clock signal that includes high pulses with a shorter period than other reference horizontal scanning periods in the timing controller, during at least one frame-first reference horizontal scanning period including the first reference horizontal scanning period of a frame in the timing controller. The display device according to claim 1.

3. The display device according to claim 2, wherein the timing controller is configured to generate the first gate clock signal and supply it to the level shifter.

4. The control circuit further includes an OR circuit, The timing controller is configured to generate a second gate clock signal that includes a high pulse with the same period as the other reference horizontal scanning period, and a third gate clock signal that has at least one high pulse during the period when the second gate clock signal is at a low level in each of the at least one reference horizontal scanning period near the beginning of a frame, and is at a low level during periods other than the at least one reference horizontal scanning period near the beginning of a frame. The display device according to claim 2, wherein the OR circuit is configured to generate a first gate clock signal based on the second gate clock signal and the third gate clock signal generated by the timing controller, and to supply the first gate clock signal to the level shifter.

5. The aforementioned other horizontal scanning period is 1H ０ Therefore, the horizontal scanning period near the beginning of at least one frame is 0.5H. ０ The display device according to any one of claims 1 to 4, which is as follows:

6. The display device according to any one of claims 1 to 4, wherein the at least one horizontal scanning period near the beginning of a frame includes all of the plurality of horizontal scanning periods.

7. The display device according to any one of claims 1 to 4, wherein the at least one horizontal scanning period near the beginning of a frame includes the first horizontal scanning period and at least one horizontal scanning period that is continuous with the first horizontal scanning period.

8. The aforementioned other horizontal scanning period is 1H ０ Therefore, the horizontal scanning period near the beginning of at least one frame is 0.3H. ０ The display device according to any one of claims 1 to 4.

9. The display device according to any one of claims 1 to 4, wherein the width of the selection pulse is longer than two horizontal scanning periods.

10. The display device according to any one of claims 1 to 4, wherein the scanning signal line driving circuit has a shift register circuit, and the shift register circuit has at least one dummy stage preceding a first stage that supplies a scanning signal to a scanning signal line connected to a pixel row of the first row.

11. The display device according to claim 10, wherein the output of at least one dummy stage is connected to the corresponding at least one dummy scan signal line.

12. The display device according to any one of claims 1 to 4, wherein the scanning signal line driving circuit is formed on the same substrate as the plurality of scanning signal lines.

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