Magnetic storage device, and method for manufacturing a magnetic storage device.

Abstract

The present invention provides a magnetic storage device that can suppress the degradation of the characteristics of a magnetoresistive element, and a method for manufacturing a magnetic storage device. [Solution] A magnetic memory device 1 of one embodiment includes a first wiring 21 extending in a first direction X, a second wiring 28 extending in a second direction Y intersecting the first direction and provided above the first wiring, a first memory cell provided between the first wiring and the second wiring, a third wiring 21 extending in the first direction and provided above the second wiring, and a second memory cell provided between the second wiring and the third wiring. The first memory cell includes a first selector body 24, a first conductor 26, and an MTJ body 27 provided on the upper surface of the first conductor. The second memory cell includes a second selector body 24, a second conductor 26, and a second MTJ body 27 provided on the upper surface of the second conductor. The upper surface of the first conductor is flattened.

Description

Technical Field

[0001] Embodiments of the present invention relate to a magnetic storage device and a method for manufacturing a magnetic storage device.

Background Art

[0002] A magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistive effect element as a memory element is known. The magnetoresistive effect element is connected in series with a switching element and functions as a memory cell.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a magnetic storage device capable of suppressing deterioration of characteristics of a magnetoresistive effect element and a method for manufacturing a magnetic storage device.

Means for Solving the Problems

[0005] The magnetic memory device according to this embodiment includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction and provided above the first wiring, a first memory cell provided between the first and second wirings, a third wiring extending in the first direction and provided above the second wiring, and a second memory cell provided between the second and third wirings. The first memory cell includes a first selector body, a first conductor, and a first MTJ body provided on the upper surface of the first conductor. The second memory cell includes a second selector body, a second conductor, and a second MTJ body provided on the upper surface of the second conductor. The upper surface of the first conductor is flattened. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a magnetic storage device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a magnetic storage device according to the first embodiment. [Figure 3] A perspective view showing an example of the three-dimensional structure of a memory cell array included in a magnetic storage device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a magnetic storage device according to the first embodiment. [Figure 5] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a magnetic storage device according to the first embodiment. [Figure 6] A cross-sectional view showing an example of the cross-sectional structure of a magnetoresistive element included in a magnetic storage device according to the first embodiment. [Figure 7] A flowchart showing an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 8] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 9] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 10]A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 11] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 12] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 13] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 14] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 15] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 16] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 17] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 18] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 19] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 20] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 21] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 22] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 23] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment. [Figure 24] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the first embodiment. [Figure 25] Cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in a magnetic memory device according to the second embodiment. [Figure 26] Cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in a magnetic memory device according to the second embodiment. [Figure 27] Flowchart showing an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 28] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 29] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 30] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 31] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 32] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 33] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 34] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 35] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 36] Cross-sectional view for explaining an example of a method for manufacturing a memory cell array in a magnetic memory device according to the second embodiment. [Figure 37]A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment. [Figure 38] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment. [Figure 39] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment. [Figure 40] A cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. Embodiments illustrate devices and methods for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. Dimensions and proportions in each drawing are not necessarily the same as those in reality. Diagrams of the components are omitted where appropriate. Hatching added to the plan views is not necessarily related to the material or properties of the components. In this specification, components having substantially the same function and configuration are assigned the same reference numeral. Numbers and letters added to reference numerals are used to distinguish similar elements that are referred to by the same reference numeral. In this specification, “laminated film containing A / B” indicates a laminated structure of a film containing element A and a film containing element B.

[0008] 1. First Embodiment A magnetic storage device according to the first embodiment will now be described. The magnetic storage device according to the first embodiment includes a perpendicular magnetization type magnetic storage device that uses, for example, an element having a magnetoresistance effect by a magnetic tunnel junction (MTJ) as a resistive switching element. In the following description, the resistive switching element will also be called a magnetoresistance effect element (MTJ).

[0009] 1.1 Configuration First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0010] 1.1.1 Configuration of Magnetic Storage Devices Figure 1 is a block diagram showing an example of the configuration of a magnetic storage device according to the first embodiment. As shown in Figure 1, the magnetic storage device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0011] The memory cell array 10 includes multiple memory cells MC, each associated with a row and column pair. Memory cells MC in the same row are connected to the same word line WL. Memory cells MC in the same column are connected to the same bit line BL.

[0012] The row selection circuit 11 is connected to the memory cell array 10 via a word line WL. The row selection circuit 11 is supplied with the decoded result (row address) of address ADD from the decode circuit 13. The row selection circuit 11 sets the word line WL corresponding to the row based on the decoded result of address ADD to a selected state.

[0013] The column selection circuit 12 is connected to the memory cell array 10 via a bit line BL. The column selection circuit 12 is supplied with the decoded result (column address) of address ADD from the decode circuit 13. The column selection circuit 12 sets the bit line BL corresponding to the column based on the decoded result of address ADD to a selected state.

[0014] The decoding circuit 13 decodes the address ADD from the input / output circuit 17. The decoding circuit 13 supplies the decoding result of address ADD to the row selection circuit 11 and the column selection circuit 12. Address ADD includes the row address and column address to be selected.

[0015] The writing circuit 14 writes data to the memory cell MC. The writing circuit 14 includes, for example, a writing driver (not shown).

[0016] The readout circuit 15 reads data from the memory cell MC. The readout circuit 15 includes, for example, a sense amplifier (not shown).

[0017] The voltage generation circuit 16 generates voltages for various operations of the memory cell array 10 using a power supply voltage supplied from an external device (not shown) to the magnetic memory device 1. For example, the voltage generation circuit 16 generates various voltages required during a write operation and outputs them to the write circuit 14. Also, for example, the voltage generation circuit 16 generates various voltages required during a read operation and outputs them to the read circuit 15.

[0018] The input / output circuit 17 is responsible for communication between the magnetic storage device 1 and the outside world. The input / output circuit 17 forwards the address ADD from the outside of the magnetic storage device 1 to the decode circuit 13. The input / output circuit 17 forwards the control signal CNT and command CMD from the outside of the magnetic storage device 1 to the control circuit 18. The input / output circuit 17 forwards the data DAT from the outside of the magnetic storage device 1 to the write circuit 14 and outputs the data DAT forwarded from the read circuit 15 to the outside of the magnetic storage device 1.

[0019] The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decode circuit 13, write circuit 14, read circuit 15, voltage generation circuit 16, and input / output circuit 17 in the magnetic storage device 1 based on the control signal CNT and command CMD.

[0020] 1.1.2 Configuration of Memory Cell Array Next, the configuration of the memory cell array 10 of the magnetic storage device 1 according to the first embodiment will be described with reference to Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment. In Figure 2, word lines WL and bit lines BL are classified and shown by subscripts including the index "<>".

[0021] As shown in Figure 2, the memory cells MC are arranged in a matrix within the memory cell array 10, and multiple bit lines BL (BL <0> BL <1> ..., BL <n>) one of them and multiple word lines WL (WL <0> WL <1> ...WL <m>One of the ) is associated with a pair of (M and N are natural numbers). That is, memory cell MC<i,j> (0≦i≦M, 0≦j≦N) represents the word line WL and bit line BL <j>It is connected between the two.

[0022] Memory Cell MC<i,j> These are switching elements SEL connected in series.<i,j> and magnetoresistive element MTJ<i,j> Includes.

[0023] The switching element SEL is a two-terminal switching element. Two-terminal switching elements differ from three-terminal switching elements such as transistors in that they do not have a third terminal. When the voltage applied between the two terminals is less than the threshold voltage Vth (voltage applied between the two terminals < threshold voltage Vth), the switching element SEL is in a high-resistance state. The high-resistance state is, for example, an "off" state in which it is electrically non-conductive. When the voltage applied between the two terminals is greater than or equal to the threshold voltage Vth (voltage applied between the two terminals ≥ threshold voltage Vth), the switching element SEL is in a low-resistance state. The low-resistance state is, for example, an "on" state in which it is electrically conductive. More specifically, for example, when the voltage applied to the corresponding memory cell MC is less than the threshold voltage Vth (voltage applied to the corresponding memory cell MC < threshold voltage Vth), the switching element SEL acts as a high-resistance insulator, blocking the current. That is, it is in an off state. The switching element SEL acts as a low-resistance conductor, allowing current to flow when the voltage applied to the corresponding memory cell MC is equal to or greater than the threshold voltage Vth (voltage applied to the corresponding memory cell MC ≥ threshold voltage Vth). In other words, it is in the ON state. Regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current), the switching element SEL switches between allowing or blocking current depending on the magnitude of the voltage applied to the corresponding memory cell MC.

[0024] The magnetoresistive element (MTJ) enters either a low-resistance state or a high-resistance state depending on the current controlled by the switching element (SEL). That is, the resistance state of the magnetoresistive element (MTJ) can be switched between a low-resistance state and a high-resistance state by the current controlled by the switching element (SEL). The magnetoresistive element (MTJ) functions as a memory element that can write data based on the change in its resistance state, and retains the written data non-volatilely, making it readable.

[0025] 1.1.3 Structure of a memory cell array Next, the structure of the memory cell array 10 of the magnetic memory device 1 according to the first embodiment will be described. In the following description, the xyz orthogonal coordinate system will be used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate used to form the magnetic memory device 1. The term "down" and its derivatives and related terms indicate a smaller coordinate position on the z axis. The term "up" and its derivatives and related terms indicate a larger coordinate position on the z axis. Hatching is added to the perspective view as appropriate. The hatching added to the perspective view is not necessarily related to the material or properties of the component to which the hatching is added. In the perspective view and cross-sectional view, the structure of the interlayer insulating film and other components is omitted.

[0026] 1.1.3.1 Three-dimensional structure of memory cell array An example of the three-dimensional structure of the memory cell array 10 will be explained using Figure 3. Figure 3 is a perspective view showing an example of the three-dimensional structure of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment.

[0027] The memory cell array 10 is provided above a semiconductor substrate (not shown).

[0028] As shown in Figure 3, the memory cell array 10 includes a plurality of conductors (wirings) 21, a plurality of conductors (wirings) 28, and a plurality of memory cells MC.

[0029] Multiple conductors 28 are provided above multiple conductors 21. Multiple conductors 21 are provided above multiple conductors 28.

[0030] Each of the multiple conductors 21 has a portion extending in the X direction. The multiple conductors 21 are arranged side by side in the Y direction and spaced apart from one another. Each conductor 21 is used as a word line WL.

[0031] Each of the multiple conductors 28 has a portion extending in the Y direction. The multiple conductors 28 are arranged side by side in the X direction and spaced apart from one another. Each conductor 28 is used as a bit line BL.

[0032] Conductors 21 and 28 are provided spaced apart from each other in the Z direction. One memory cell MC is provided at each of the intersections of the multiple conductors 21 and the multiple conductors 28. In other words, each memory cell MC is provided columnarly between the associated word line WL and bit line BL. The memory cell MC has a structure in which, for example, a switching element SEL is provided below the magnetoresistive element MTJ. That is, the switching element SEL constitutes a selector body SEL and the magnetoresistive element MTJ constitutes a stacked structure of magnetoresistive element layers (MTJ bodies).

[0033] The memory cell array 10 has multiple structures (hereinafter referred to as "stacked structures"), each including a conductor 21, a conductor 28, and memory cells MCs provided between them. Hereinafter, the multiple stacked structures will be referred to as the "first-stage stacked structure," the "second-stage stacked structure," and so on, from bottom to top. The first-stage stacked structure has a structure in which the conductor 21, memory cells MC, and conductor 28 are stacked in that order. The second-stage stacked structure has a structure in which the conductor 28, memory cells MC, and conductor 21 are stacked in that order.

[0034] The memory cell MC may have a structure in which a selector body SEL, which is a switching element SEL, is provided above a magnetoresistive element layer (MTJ body), which is a magnetoresistive element MTJ. In the following description, the switching element SEL will be referred to as the selector body SEL, and the magnetoresistive element MTJ as the MTJ body. Furthermore, the first-stage stacked structure may have a structure in which a conductor 28, memory cell MC, and conductor 21 are stacked in that order, and the second-stage stacked structure may have a structure in which a conductor 21, memory cell MC, and conductor 28 are stacked in that order.

[0035] 1.1.3.2 Cross-sectional structure of memory cell array An example of the cross-sectional structure of the memory cell array 10 will be explained using Figures 4 and 5. Figure 4 is a cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment. Figure 5 is a cross-sectional view along line VV in Figure 3, showing an example of the cross-sectional structure of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment.

[0036] As shown in Figures 4 and 5, the memory cell array 10 includes a plurality of conductors 21, a plurality of conductors 22, a plurality of electrodes 23, a plurality of selector bodies 24, a plurality of electrodes 25, a plurality of conductors 26, a plurality of MTJ bodies 27, a plurality of conductors 28, a plurality of conductors 29, an insulator 40, an insulator 41, a plurality of insulators 42, an insulator 43, a plurality of insulators 44, and an insulator 45.

[0037] On a semiconductor substrate (not shown), for example, a plurality of conductors 21 are provided. The plurality of conductors 21 are arranged along the Y direction. Each of the plurality of conductors 21 extends along the X direction. Each of the plurality of conductors 21 is conductive and functions as a word line WL.

[0038] An insulator 40 is provided in the region between two adjacent conductors 21 in the Y direction. This insulates each of the multiple conductors 21 from each other in the Y direction. The insulator 40 is made of an insulating material. For example, the insulator 40 includes silicon oxide (SiO2) or silicon nitride (SiN). The insulator 40 may be composed of multiple insulating materials.

[0039] The multiple conductors 21 and insulators 40 may be provided on the upper surface of the semiconductor substrate, or they may be provided separately from the semiconductor substrate without contacting it.

[0040] Multiple conductors 22 are provided on the upper surface of each of the multiple conductors 21. Multiple conductors 22 provided on the upper surface of the same conductor 21 are aligned in the X direction. Each of the multiple conductors 22 is conductive. A single conductor 21 and the multiple conductors 22 provided on the upper surface of said conductor 21 are collectively called a word line WL.

[0041] On the upper surface of each of the multiple conductors 22, one corresponding electrode 23 is provided from among the multiple electrodes 23. Each of the multiple electrodes 23 is conductive and functions as a lower electrode BE.

[0042] On the upper surface of each of the multiple electrodes 23, one corresponding selector body 24 is provided from among the multiple selector bodies 24. Each of the multiple selector bodies 24 functions as a switching element SEL.

[0043] On the upper surface of each of the multiple selector bodies 24, one corresponding electrode 25 is provided from among the multiple electrodes 25. Each of the multiple electrodes 25 functions as an intermediate electrode ME. Details of the configuration of the electrodes 25 will be described later.

[0044] Hereinafter, the structure including the conductor 22, electrode 23, selector body 24, and electrode 25 will be referred to as the "first stack." The memory cell array 10 includes a plurality of first stacks. An insulator 42 (side wall) is provided on each side of the plurality of first stacks so as to cover that side. That is, the insulator 42 covers the side of the conductor 22, the side of the electrode 23, the side of the selector body 24, and the side of the electrode 25. The insulator 42 is provided, for example, from a position equivalent to the top surface of the conductor 21 to a position equivalent to the top surface of the electrode 25. As a result, each of the plurality of conductors 22 is insulated from each other in the Y direction. Each of the plurality of electrodes 23 is insulated from each other. Each of the plurality of selector bodies 24 is insulated from each other. Each of the plurality of electrodes 25 is insulated from each other. The insulator 42 is made of an insulating material. The insulator 42 includes, for example, silicon nitride. The insulator 42 may be made of multiple insulating materials.

[0045] An insulator 41 is provided in the region between two adjacent insulators 42. The insulator 41 is made of an insulating material. The insulator 41 includes, for example, silicon oxide or silicon nitride. Note that the insulator 41 may be made of multiple insulating materials.

[0046] On the upper surface of each of the multiple electrodes 25, one corresponding conductor 26 is provided from among the multiple conductors 26. Each of the multiple conductors 26 is conductive. Hereinafter, the conductor 26 will also be referred to as the "buffer layer BF". The buffer layer BF is a layer provided to cancel the crystallinity of the electrodes 25 provided below the MTJ body 27. In other words, the buffer layer BF is a layer provided so that the crystallinity of the electrodes 25 provided below the MTJ body 27 does not affect the crystallinity of each layer contained in the MTJ body 27. As the conductor 26, a material is used in which the crystallinity of the electrodes 25 does not affect the crystallinity of each layer contained in the MTJ body 27. The conductor 26 includes, for example, hafnium (Hf) and hafnium boride (HfB). The upper surface of the conductor 26 is flattened. The thickness of the conductor 26 is, for example, about 3 nanometers (nm).

[0047] On the upper surface of each of the multiple conductors 26, one corresponding MTJ body 27 is provided from among the multiple MTJ bodies 27. Each of the multiple MTJ bodies 27 functions as a magnetoresistive element MTJ. Details of the configuration of the MTJ bodies 27 will be described later.

[0048] Hereinafter, the structure including the conductor 26 and the MTJ body 27 will be referred to as the "second stack." The memory cell array 10 includes a plurality of second stacks. An insulator 44 (side wall) is provided on each side of the plurality of second stacks so as to cover that side. That is, the insulator 44 covers the side of the conductor 26 and the side of the MTJ body 27. The insulator 44 is provided, for example, from a position equivalent to the upper surface of the electrode 25 to a position equivalent to the upper surface of the MTJ body 27. As a result, each of the plurality of conductors 26 is insulated from each other. Each of the plurality of MTJ bodies 27 is insulated from each other. The insulator 44 is made of an insulating material. The insulator 44 includes, for example, silicon nitride. The insulator 44 may be made of a plurality of insulating materials.

[0049] An insulator 43 is provided in the region between two adjacent insulators 44. The insulator 43 is made of an insulating material. The insulator 43 includes, for example, silicon oxide or silicon nitride. Note that the insulator 43 may be made of multiple insulating materials.

[0050] A single conductor 28 extending in the Y direction is provided so as to be in contact with the upper surface of each of the multiple MTJ bodies 27 arranged in the Y direction. The multiple conductors 28 are arranged in the X direction. Each of the multiple conductors 28 extends along the Y direction. Each of the multiple conductors 28 is conductive and functions as a bit line BL.

[0051] An insulator 45 is provided in the region between two adjacent conductors 28 in the X direction. This insulates each of the multiple conductors 28 from each other in the X direction. The insulator 45 is made of an insulating material, such as silicon oxide or silicon nitride. The insulator 45 may be composed of multiple insulating materials.

[0052] Thus, a structure in which conductor 21, conductor 22, electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, and conductor 28 are stacked in this order corresponds to the first-stage stacked structure. The memory cell MC of the first-stage stacked structure includes conductor 22, electrode 23, selector body 24, electrode 25, conductor 26, and MTJ body 27. Electrode 25 is provided between selector body 24 and conductor 26.

[0053] In the first layer of the laminated structure, the upper surface of the conductor 26 (buffer layer BF) that contacts the lower surface of the MTJ body 27 is flattened. As a result, the upper surfaces of each layer included in the MTJ body 27, which is provided on the upper surface of the conductor 26, are also flattened. Therefore, the MTJ body 27 has relatively good properties (for example, coercivity).

[0054] Furthermore, in the first layered structure, the conductor 26 (buffer layer BF) is provided between the MTJ body 27 and the electrode 25. As a result, the crystallinity of each layer contained in the MTJ body 27 is not affected by the crystallinity of the electrode 25. Therefore, the MTJ body 27 has a relatively good crystal structure.

[0055] Multiple conductors 22 are provided on the upper surface of each of the multiple conductors 28. Multiple conductors 22 provided on the upper surface of the same conductor 28 are aligned in the Y direction. Each of the multiple conductors 22 is conductive. One conductor 28 and the multiple conductors 22 provided on the upper surface of the conductor 28 are collectively called a bit line BL.

[0056] On the upper surface of each of the multiple conductors 22, electrodes 23, a selector body 24, and an electrode 25 are provided, similar to the first-stage laminated structure. The structure of the electrode 25 is the same as the first-stage laminated structure. On the sides of each of the multiple first laminates, each containing a conductor 22, an electrode 23, a selector body 24, and an electrode 25, an insulator 42 is provided, similar to the first-stage laminated structure. That is, the insulator 42 covers the sides of the conductor 22, the sides of the electrode 23, the sides of the selector body 24, and the sides of the electrode 25. In the region between two adjacent insulators 42, an insulator 41 is provided, similar to the first-stage laminated structure.

[0057] On the upper surface of each of the multiple electrodes 25, a conductor 26 (buffer layer BF) and an MTJ body 27 are provided, similar to the first-stage stacked structure. The conductor 26 includes, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductor 26 is, for example, about 1 nanometer (nm). The structure of the MTJ body 27 is the same as that of the first-stage stacked structure.

[0058] Similar to the first-stage laminated structure, an insulator 44 is provided on each side of each of the multiple second laminates, each containing a conductor 26 and an MTJ body 27. That is, the insulator 44 covers the sides of the conductor 26 and the sides of the MTJ body 27. Similar to the first-stage laminated structure, an insulator 43 is provided in the region between two adjacent insulators 44.

[0059] On the upper surface of each of the multiple MTJ bodies 27, one corresponding conductor 29 is provided from among the multiple conductors 29. The multiple conductors 29 are arranged in the X and Y directions. Each of the multiple conductors 29 is conductive. An insulator 45 is provided in the region between two adjacent conductors 29. This insulates each of the multiple conductors 29 from one another.

[0060] A single conductor 21 is provided extending in the X direction so as to be in contact with the upper surface of each of the multiple conductors 29 arranged in the X direction. The multiple conductors 21 are arranged in the Y direction. Each of the multiple conductors 21 extends along the X direction. Each of the multiple conductors 21 is conductive and functions as a word line WL. The single conductor 21 and the multiple conductors 29 provided on the lower surface of the conductor 21 are collectively referred to as the word line WL.

[0061] Similar to the first layered structure, an insulator 40 is provided in the region between two adjacent conductors 21 in the Y direction. As a result, each of the multiple conductors 21 is insulated from the others in the Y direction.

[0062] Thus, a structure in which conductor 28, conductor 22, electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, conductor 29, and conductor 21 are stacked in this order corresponds to the second-stage stacked structure. The memory cell MC of the second-stage stacked structure includes conductor 22, electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, and conductor 29. Electrode 25 is provided between selector body 24 and conductor 26.

[0063] The thickness of the conductor 26 in the first layer of the laminated structure is different from the thickness of the conductor 26 in the second layer of the laminated structure. For example, the thickness of the conductor 26 in the first layer of the laminated structure is greater than the thickness of the conductor 26 in the second layer of the laminated structure. However, the thickness of the conductor 26 in the first layer of the laminated structure may be less than the thickness of the conductor 26 in the second layer of the laminated structure.

[0064] The thickness of the conductor 26 included in the first layer of the laminated structure is set considering the degradation of the properties of the MTJ body 27 due to the two annealing treatments described later. Specifically, the annealing treatment is performed with varying temperatures, times, and number of treatments, and the degradation of the properties of the MTJ body 27 is recorded as data for each temperature, time, and number of treatments. Based on the recorded data, the thickness of the conductor 26 included in the first layer of the laminated structure is set.

[0065] Furthermore, in the second layered structure, the conductor 26 (buffer layer BF) is provided between the MTJ body 27 and the electrode 25. As a result, the crystallinity of each layer contained in the MTJ body 27 is not affected by the crystallinity of the electrode 25. Therefore, the MTJ body 27 has a relatively good crystal structure.

[0066] Furthermore, in the second layered structure, the upper surface of the conductor 26 may be flattened. In this case, the upper surfaces of each layer included in the MTJ body 27 provided on the upper surface of the conductor 26 are also flattened. As a result, the properties of the MTJ body 27 included in the second layered structure are improved.

[0067] 1.1.4 Cross-sectional structure of the intermediate electrode Next, an example of the cross-sectional structure of the intermediate electrode ME of the magnetic storage device 1 according to the first embodiment will be described using Figures 4 and 5.

[0068] Each of the multiple electrodes 25 includes conductors 251 and 252. Hereinafter, conductor 251 will also be referred to as "sub-electrode 251," and conductor 252 will also be referred to as "sub-electrode 252."

[0069] The conductor 251 is provided on the upper surface of the selector body 24. The conductor 251 is composed of at least one element or compound selected from, for example, carbon (C) and carbon nitride (CN). Preferably, the conductor 251 has an amorphous structure. The thickness of the conductor 251 is, for example, 2 nanometers (nm) or more and 20 nanometers (nm) or less. If the thickness of the conductor 251 is within this range, peeling of the conductor 251 from the upper surface of the selector body 24 is suppressed.

[0070] In this specification, a portion "composed" of each element may contain unintended impurities different from those elements. Unintended impurities include, for example, elements contained in the gas used in the manufacturing process of the magnetic memory device 1, and elements that have entered the portion from its surroundings.

[0071] The conductor 252 is provided on the upper surface of the conductor 251. The conductor 252 is composed of at least one element or compound selected from, for example, high-melting-point metal elements and compounds of high-melting-point metal elements. In this embodiment, the high-melting-point metal is, for example, a material with a melting point higher than iron (Fe) and cobalt (Co). Examples of high-melting-point metal elements and compounds of high-melting-point metal elements are titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductor 252 has, for example, a crystalline structure. The thickness of the conductor 252 is preferably, for example, 0.1 nanometers (nm) or more and 3 nanometers (nm) or less.

[0072] Note that the intermediate electrode ME is not limited to the structure shown in Figures 4 and 5. The intermediate electrode ME may include, for example, other layers.

[0073] 1.1.5 Cross-sectional structure of magnetoresistive element Next, an example of the cross-sectional structure of the magnetoresistive element MTJ, or MTJ body, of the magnetic storage device 1 according to the first embodiment will be described with reference to Figure 6. Figure 6 is a cross-sectional view of an example of the cross-sectional structure of the magnetoresistive element MTJ included in the magnetic storage device 1 according to the first embodiment.

[0074] The MTJ body 27 used as a magnetoresistive element MTJ includes a ferromagnetic material 31, a non-magnetic material 32, a ferromagnetic material 33, a non-magnetic material 34, a ferromagnetic material 35, and a non-magnetic material 36.

[0075] The ferromagnetic material 31 is a conductive film having ferromagnetism. The ferromagnetic material 31 has an easy magnetization axis in the direction perpendicular to the film surface (Z direction). The ferromagnetic material 31 contains iron (Fe). The ferromagnetic material 31 may further contain at least one element selected from cobalt (Co) and nickel (Ni). The ferromagnetic material 31 may further contain boron (B). More specifically, for example, the ferromagnetic material 31 includes cobalt iron boron (CoFeB), iron boride (FeB), or cobalt boride (CoB). The ferromagnetic material 31 is used as a memory layer SL.

[0076] A non-magnetic material 32 is provided on the lower surface of the ferromagnetic material 31. The non-magnetic material 32 is a non-magnetic insulating film. The non-magnetic material 32 is used as a tunnel barrier layer TB. The non-magnetic material 32 is provided between the ferromagnetic material 31 and the ferromagnetic material 33, and together with the ferromagnetic material 31 and the ferromagnetic material 33, it forms a magnetic tunnel junction. Furthermore, when an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer between the ferromagnetic material 31 and the ferromagnetic material 33, the non-magnetic material 32 functions as a seed material that acts as a nucleus for growing a crystalline film from the interface with the ferromagnetic material 31 during the crystallization treatment of the ferromagnetic material 31. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic material 33, the non-magnetic material 32 also functions as a seed material for the ferromagnetic material 33. Here, the initial amorphous layer is a layer that is in an amorphous state immediately after film formation and crystallizes after annealing. The non-magnetic material 32 has a tetragonal or cubic structure with its film surface oriented to the (001) plane. An example of an oxide used for the non-magnetic material 32 is magnesium oxide (MgO). Magnesium oxide (MgO) has an NaCl structure. When magnesium oxide (MgO) is used for the non-magnetic material 32, the (001) interface of magnesium oxide (MgO) and the (001) interface of cobalt iron boron (CoFeB) are compatible. Therefore, cobalt iron boron (CoFeB) undergoes crystal growth through annealing treatment to form a body-centered cubic structure oriented to the (001) plane.

[0077] A ferromagnetic material 33 is provided on the lower surface of the non-magnetic material 32. The ferromagnetic material 33 is a conductive film having ferromagnetism. The ferromagnetic material 33 is used as a reference layer RL. The ferromagnetic material 33 has an easy magnetization axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic material 33 is fixed. In the example of Figure 6, the magnetization direction of the ferromagnetic material 33 is from the ferromagnetic material 33 toward the ferromagnetic material 31. Note that "the magnetization direction is fixed" means that the magnetization direction does not change due to a torque of a magnitude that can reverse the magnetization direction of the ferromagnetic material 31. Typically, an interface layer is used for the ferromagnetic material 33. As the interface layer of the ferromagnetic material 33, an initial amorphous layer such as cobalt iron boron (CoFeB) is used. Furthermore, an auxiliary ferromagnetic layer is provided so as to be in contact with the surface of the cobalt iron boron (CoFeB) layer opposite to the surface in contact with the magnesium oxide (MgO) layer. This auxiliary ferromagnetic layer includes, for example, at least one alloy film selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). This auxiliary ferromagnetic layer is a laminated film such as a Co / Pt laminated film or a Co / Pd laminated film. The cobalt iron boron (CoFeB) layer, which is the initial amorphous layer, is used in lamination with the above-mentioned CoPt, CoPd, Co / Pt laminated film, Co / Pd laminated film, etc. In this case, the interface layer of the ferromagnetic material 33, for example the above-mentioned CoFeB layer, has (001)-oriented MgO formed on the non-magnetic material 32 side compared to other layers.

[0078] A non-magnetic material 34 is provided on the lower surface of the ferromagnetic material 33. The non-magnetic material 34 is a non-magnetic conductive film. The non-magnetic material 34 is used as a spacer layer SP. The non-magnetic material 34 includes, for example, elements selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr), or alloys thereof. The thickness of the non-magnetic material 34 is, for example, 2 nanometers (nm) or less.

[0079] A ferromagnetic material 35 is provided on the lower surface of the non-magnetic material 34. In other words, the ferromagnetic material 35 is provided on the side opposite to the ferromagnetic material 31 relative to the ferromagnetic material 33. The ferromagnetic material 35 is a conductive film having ferromagnetism. The ferromagnetic material 35 is used as a shift-cancellation layer SCL. The ferromagnetic material 35 has an easy magnetization axis direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic material 35 is fixed. In the example of Figure 6, the magnetization direction of the ferromagnetic material 35 is from the ferromagnetic material 33 towards the ferromagnetic material 35. The ferromagnetic material 35 includes, for example, at least one alloy layer selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). Alternatively, the ferromagnetic material 35 may be a multilayer film such as a multilayer film containing Co / Pt and a multilayer film containing Co / Pd.

[0080] The ferromagnetic material 33 and the ferromagnetic material 35 are antiferromagnetically coupled by the non-magnetic material 34. That is, the ferromagnetic material 33 and the ferromagnetic material 35 are coupled so that they have magnetization directions that are antiparallel to each other. This coupling structure of the ferromagnetic material 33, the non-magnetic material 34, and the ferromagnetic material 35 is called the SAF (Synthetic Anti-Ferromagnetic) structure. The SAF structure allows the ferromagnetic material 35 to cancel out the effect of the leakage magnetic field of the ferromagnetic material 33 on the change in the magnetization direction of the ferromagnetic material 31. As a result, the ferromagnetic material 35 can effectively reduce the leakage magnetic field of the ferromagnetic material 33.

[0081] A non-magnetic material 36 is provided on the lower surface of the ferromagnetic material 35. The non-magnetic material 36 is a non-magnetic conductive film. The non-magnetic material 36 is used as an underlayer (UL). The non-magnetic material 36 includes, for example, at least one element selected from zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0082] The magnetoresistive element MTJ can be in either a low-resistance state or a high-resistance state depending on whether the relative magnetization directions of the memory layer SL and the reference layer RL are parallel or antiparallel. In this embodiment, the magnetization direction of the memory layer SL with respect to the magnetization direction of the reference layer RL is controlled by passing a writing current through such a magnetoresistive element MTJ. Specifically, a writing method is employed that utilizes spin transfer torque generated by passing a current through the magnetoresistive element MTJ.

[0083] When a write current Ic0 of a certain magnitude is applied to the magnetoresistive element MTJ in the direction from the memory layer SL to the reference layer RL, i.e., in the direction of arrow A1 in Figure 6, the relative relationship of the magnetization directions of the memory layer SL and the reference layer RL becomes parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ becomes the lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (Parallel) state" and is defined, for example, as the data "0" state.

[0084] Furthermore, when a write current Ic1 greater than the write current Ic0 is applied to the magnetoresistive element MTJ in the direction from the reference layer RL to the memory layer SL, i.e., in the direction of arrow A2 in Figure 6, the relative relationship of the magnetization directions of the memory layer SL and the reference layer RL becomes antiparallel. In this antiparallel state, the resistance value of the magnetoresistive element MTJ, i.e., the MTJ body 27, becomes the highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state" and is defined, for example, as the data "1" state.

[0085] Note that the definitions of data "1" and data "0" are not limited to the examples given above. For example, state P may be defined as data "1" and state AP as data "0".

[0086] Furthermore, the MTJ body 27 is not limited to the structure shown in Figure 6. The MTJ body 27 may include other layers, for example, and each magnetic material may be composed of multiple layers.

[0087] 1.2 Method for manufacturing memory cell arrays Next, a method for manufacturing the memory cell array 10 of the magnetic storage device 1 according to the first embodiment will be described. Figure 7 is a flowchart showing an example of a method for manufacturing the memory cell array 10 in the magnetic storage device 1 according to the first embodiment. Figures 8 to 24 are cross-sectional views illustrating an example of a method for manufacturing the memory cell array 10 in the magnetic storage device 1 according to the first embodiment. Figures 8 to 24 are cross-sectional views corresponding to Figure 4.

[0088] First, in S11 of Figure 7, a plurality of conductors 21 and insulators 40 are formed on the upper surface of a semiconductor substrate (not shown) which is a wafer WF.

[0089] Specifically, as shown in Figure 8, after a conductive layer is provided on the upper surface of the semiconductor substrate, a mask is formed by photolithography or the like, with openings in the areas excluding the region corresponding to the word line WL. Then, anisotropic etching using the formed mask divides the conductive layer, forming multiple conductors 21 aligned along the Y direction, and also forming holes that reach the semiconductor substrate. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). Subsequently, an insulator 40 is embedded in the formed holes. This forms the insulator 40.

[0090] Next, in S12 of Figure 7, a conductor 22, an electrode 23, a selector body 24, and an electrode 25 are formed on the upper surface of each of the multiple conductors 21.

[0091] Specifically, as shown in Figure 8, a conductive layer 122, an electrode layer 123, a switching element layer (hereinafter referred to as the selector layer) 124, and an electrode layer 125 are formed in this order on the upper surfaces of the multiple conductors 21 and the insulator 40. The electrode layer 125 is formed in this order as conductive layer 1251 and conductive layer 1252. Conductive layer 1251 is composed of at least one element or compound selected from carbon (C) and carbon nitride (CN). Conductive layer 1252 is composed of at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements.

[0092] Next, as shown in Figure 9, a plurality of masks 61 are formed. The plurality of masks 61 are formed by photolithography or the like, with openings in the areas of the conductive layer 122, electrode layer 123, selector layer 124, and electrode layer 125, excluding the areas corresponding to the conductor 22, electrode 23, selector body 24, and electrode 25 to be manufactured. The plurality of masks 61 include, for example, titanium nitride (TiN) and protect the areas that function as the conductor 22, electrode 23, selector body 24, and electrode 25 in the ion beam etching (IBE) described later. The plurality of masks 61 are provided, for example, as a plurality of cylindrical structures arranged in a matrix on the upper surface of the electrode layer 125, and each of the plurality of cylindrical structures protects the area corresponding to one memory cell MC.

[0093] Next, as shown in Figure 9, the conductive layer 122, electrode layer 123, selector layer 124, and electrode layer 125 are etched by ion beam etching. As a result, portions of the conductive layer 122, electrode layer 123, selector layer 124, and electrode layer 125 that are not protected by the multiple masks 61 are removed, exposing the multiple conductors 21 and insulators 40 located below those portions. Through this ion beam etching, as shown in Figure 10, multiple conductors 22, multiple electrodes 23, multiple selector bodies 24, and multiple electrodes 25 are formed from the conductive layer 122, electrode layer 123, selector layer 124, and electrode layer 125. In other words, a structure in which the conductors 22, electrodes 23, selector bodies 24, and electrodes 25 are stacked is formed. To put it another way, multiple first stacks are formed, each containing a conductor 22, an electrode 23, a selector body 24, and an electrode 25.

[0094] Next, in S13 of Figure 7, an insulator 42 is formed on each side surface of the multiple first laminates.

[0095] Specifically, as shown in Figure 11, insulating layers 142 are formed on the upper surfaces of each of the multiple conductors 21, on the upper surface of the insulator 40, on the upper surface of each of the multiple first laminates, and on the sides of each of the multiple first laminates.

[0096] Next, as shown in Figure 12, the insulating layer 142 is etched by anisotropic etching. This removes the insulating layer 142 on the upper surface of each of the multiple conductors 21, the insulating layer 142 on the upper surface of the insulator 40, and the insulating layer 142 on the upper surface of each of the multiple first laminates, thereby forming multiple insulators 42.

[0097] Next, in S14 of Figure 7, as shown in Figure 13, an insulator 41 is embedded in the region between two adjacent insulators 42.

[0098] Next, in S15 of Figure 7, the conductor 26 and the MTJ body 27 are formed on the upper surface of each of the multiple first laminates.

[0099] Specifically, as shown in Figure 14, a conductive layer 126, a conductive layer 151, and a conductive layer 152 are formed in this order on the upper surfaces of multiple electrodes 25 (multiple first laminates), an insulator 41, and multiple insulators 42. The conductive layer 126 contains, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductive layer 126 is, for example, about 3 nanometers (nm). The thickness of the conductive layer 151 is, for example, about 0.5 nanometers (nm). The conductive layer 152 contains, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductive layer 152 is, for example, about 10 nanometers (nm).

[0100] Next, as shown in Figure 14, conductive layers 151 and 152 are etched by ion beam etching. This removes conductive layers 151 and 152, exposing conductive layer 126. As shown in Figure 15, this ion beam etching planarizes the upper surface of conductive layer 126. The thickness of conductive layer 126 after planarization is, for example, about 3 nanometers (nm). For example, as ion beam etching progresses, the endpoint of ion beam etching is detected by detecting the OES (Optical Emission Spectroscopy) signal of conductive layer 151, and the ion beam etching is controlled accordingly.

[0101] The upper surface of the conductive layer 126 may be flattened by CMP (Chemical Mechanical Polishing), RIE, or the like.

[0102] Next, as shown in Figure 16, a magnetoresistive element layer 127 is formed on the upper surface of the conductive layer 126. The magnetoresistive element layer 127 is a laminate in which each layer included in the magnetoresistive element MTJ described in Figure 6 is deposited in a flat plate shape in this stacking order.

[0103] Next, in order to improve the crystallinity of the magnetoresistive element layer 127, the magnetoresistive element layer 127 is subjected to an annealing treatment. The annealing treatment is carried out, for example, at 300°C to 400°C for an arbitrary amount of time. As a result, each layer of the magnetoresistive element layer 127 is crystallized.

[0104] Next, as shown in Figure 17, a plurality of masks 62 are formed. The plurality of masks 62 are formed by photolithography or the like, with openings in the conductive layer 126 and the magnetoresistive element layer 127, excluding the regions corresponding to the conductor 26 and MTJ body 27 to be manufactured. The plurality of masks 62 contain, for example, titanium nitride and protect the regions that function as the conductor 26 and MTJ body 27 in the ion beam etching described later. The plurality of masks 62 are provided, for example, as a plurality of cylindrical structures arranged in a matrix on the upper surface of the magnetoresistive element layer 127, and each of the plurality of cylindrical structures protects the region corresponding to one memory cell MC.

[0105] Next, as shown in Figure 17, the conductive layer 126 and the magnetoresistive element layer 127 are etched by ion beam etching. This removes portions of the conductive layer 126 and the magnetoresistive element layer 127 that are not protected by the multiple masks 62, exposing the insulator 41 located beneath those portions. Through this ion beam etching, as shown in Figure 18, multiple conductors 26 and multiple MTJ bodies 27 are formed from the conductive layer 126 and the magnetoresistive element layer 127. In other words, multiple second laminates are formed, each containing a conductor 26 and an MTJ body 27.

[0106] Next, in S16 of Figure 7, an insulator 44 is formed on each side surface of the multiple second laminates.

[0107] Specifically, after insulating layers are formed on the upper surface of the insulator 41, on the upper surface of each of the multiple second laminates, and on the side surfaces of each of the multiple second laminates, the insulating layers are etched by anisotropic etching. As a result, as shown in Figure 19, the insulating layer on the upper surface of the insulator 41 and the insulating layer on the upper surface of each of the multiple second laminates are removed, and multiple insulators 44 are formed.

[0108] Next, in S17 of Figure 7, as shown in Figure 20, an insulator 43 is embedded in the region between two adjacent insulators 44.

[0109] Next, in S18 of Figure 7, multiple conductors 28 and multiple insulators 45 are formed on the upper surfaces of multiple second laminates, insulators 43, and multiple insulators 44.

[0110] Specifically, as shown in Figure 20, after a conductive layer is provided on the upper surfaces of multiple second laminates, insulators 43 and multiple insulators 44, a mask is formed by photolithography or the like, with the portion excluding the area corresponding to the bit line BL being open. Then, anisotropic etching using the formed mask divides the conductive layer, forming multiple conductors 28 aligned along the X direction, and also forming holes reaching the insulators 43. The anisotropic etching in this process is, for example, RIE. After that, insulators 45 are embedded in the formed holes.

[0111] As described above, the first layered structure is formed by carrying out steps S11 to S18 in Figure 7.

[0112] Next, in S19 of Figure 7, as shown in Figure 21, a conductor 22, an electrode 23, a selector body 24, and an electrode 25 are formed on the upper surface of each of the multiple conductors 28 in the same manner as in the formation of the first layered structure. That is, a structure is formed in which the conductor 22, electrode 23, selector body 24, and electrode 25 are stacked. In other words, multiple first layered structures are formed, each containing a conductor 22, an electrode 23, a selector body 24, and an electrode 25.

[0113] Next, in S20 of Figure 7, as shown in Figure 21, an insulator 42 is formed on each side surface of the multiple first laminates in the same manner as in the formation of the first layered structure.

[0114] Next, in S21 of Figure 7, as shown in Figure 21, an insulator 41 is embedded in the region between two adjacent insulators 42, in the same manner as in the formation of the first layered structure.

[0115] Next, in S22 of Figure 7, the conductor 26 and the MTJ body 27 are formed on the upper surface of each of the multiple first laminates.

[0116] Specifically, as shown in Figure 21, a conductive layer 126 is formed on the upper surfaces of multiple electrodes 25 (multiple first laminates), an insulator 41, and multiple insulators 42. The conductive layer 126 contains, for example, hafnium (Hf), hafnium boride (HfB), etc. The thickness of the conductive layer 126 is, for example, about 1 nanometer (nm). A magnetoresistive element layer 127 is formed on the upper surface of the conductive layer 126. Alternatively, the upper surface of the conductive layer 126 may be flattened in the same manner as in S15 of Figure 7. In this case, the upper surfaces of each layer included in the magnetoresistive element layer 127 provided on the upper surface of the conductive layer 126 are also flattened. This improves the characteristics of the magnetoresistive element layer 127.

[0117] Next, in the same manner as in the formation of the first layered structure, the magnetoresistive element layer 127 is annealed to improve its crystallinity. The annealing is performed, for example, at 300°C to 400°C for an arbitrary amount of time. This causes each layer of the magnetoresistive element layer 127 to crystallize. Note that the temperature and time of the annealing may differ between the formation of the first layered structure and the formation of the second layered structure.

[0118] Next, as shown in Figure 22, multiple masks 62 are formed in the same manner as the formation of the first layered structure.

[0119] Next, as shown in Figure 22, the conductive layer 126 and the magnetoresistive element layer 127 are etched by ion beam etching in the same manner as in the formation of the first layered structure. As a result, as shown in Figure 23, multiple conductors 26 and multiple MTJ bodies 27 are formed from the conductive layer 126 and the magnetoresistive element layer 127. That is, multiple second layered structures are formed, each containing a conductor 26 and an MTJ body 27.

[0120] Next, in S23 of Figure 7, as shown in Figure 24, an insulator 44 is formed on each side surface of the multiple second laminates in the same manner as in the formation of the first layered structure.

[0121] Next, in S24 of Figure 7, as shown in Figure 24, an insulator 43 is embedded in the region between two adjacent insulators 44, in the same manner as in the formation of the first layered structure.

[0122] Next, in S25 of Figure 7, a plurality of conductors 29 and insulators 45 are formed on the upper surfaces of a plurality of second laminates, an insulator 43, and a plurality of insulators 44.

[0123] Specifically, after a conductive layer is provided on the upper surfaces of multiple second laminates, insulators 43 and multiple insulators 44, a mask is formed by photolithography or the like, with openings in the areas excluding those corresponding to the conductors 29. Then, as shown in Figure 24, anisotropic etching using the formed mask divides the conductive layer to form multiple conductors 29 and creates holes reaching the insulators 43. The anisotropic etching in this process is, for example, RIE. Subsequently, as shown in Figure 24, insulators 45 are embedded in the formed holes.

[0124] Next, in S26 of Figure 7, as shown in Figure 4, multiple conductors 21 and insulators 40 are formed on the upper surfaces of multiple conductors 29 and insulators 45 in the same manner as in the formation of the first layered structure.

[0125] As described above, the second layered structure is formed by carrying out steps S19 to S26 in Figure 7.

[0126] As a result, a configuration corresponding to the memory cell array 10 is formed on the wafer WF. Then, the wafer WF is diced into chip units to form the magnetic storage device 1.

[0127] The magnetic memory device 1 is formed by the manufacturing process described above. However, the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing step, or some steps may be omitted or integrated. Furthermore, each manufacturing step may be rearranged to the extent possible.

[0128] 1.3 Effects according to this embodiment According to the magnetic storage device 1 of the first embodiment, the degradation of the characteristics of the magnetoresistive element can be suppressed. The effects of the magnetic storage device 1 of the first embodiment will be described in detail below.

[0129] In a magnetic memory device having a multilayer structure of memory cells (MCs) including magnetoresistive element (MTJ), i.e., a first-stage stacked structure and a second-stage stacked structure, annealing is performed when the first-stage stacked structure is formed, and annealing is performed when the second-stage stacked structure is formed. In other words, two annealing processes are performed. As a result, the magnetoresistive element (MTJ) included in the first-stage stacked structure is subjected to heat a total of two times through the two annealing processes. The magnetoresistive element (MTJ) included in the second-stage stacked structure is subjected to heat once through the one annealing process. Therefore, the characteristics of the magnetoresistive element (MTJ) included in the first-stage stacked structure may be degraded compared to the magnetoresistive element (MTJ) included in the second-stage stacked structure.

[0130] Therefore, in this embodiment, when the first layer of the laminated structure is formed, a conductive layer 126 is formed on the upper surface of the electrode 25, and the upper surface of the conductive layer 126 is flattened. A magnetoresistive element layer 127 is formed on the flattened upper surface of the conductive layer 126. As a result, the upper surfaces of each layer included in the magnetoresistive element layer 127 provided on the upper surface of the conductive layer 126 are also flattened. This improves the characteristics of the magnetoresistive element layer 127. In other words, the characteristics of the MTJ body 27 included in the formed first layer of the laminated structure are improved. As a result, even if the characteristics of the MTJ body 27 included in the first layer of the laminated structure deteriorate after two annealing processes, it is possible to suppress the deterioration of the characteristics of the MTJ body 27 included in the first layer of the laminated structure compared to the characteristics of the MTJ body 27 included in the second layer of the laminated structure. In other words, according to this embodiment, the deterioration of the characteristics of the magnetoresistive element can be suppressed.

[0131] For example, the thickness of the conductor 26 included in the first layer of the laminated structure is set such that, after two annealing treatments, the properties of the MTJ body 27 included in the first layer of the laminated structure become approximately equivalent to those of the MTJ body 27 included in the second layer of the laminated structure. This makes it possible to make the MTJ body 27 included in the first layer of the laminated structure have properties approximately equivalent to those of the MTJ body 27 included in the second layer of the laminated structure.

[0132] Furthermore, the conductive layer 126 is provided between the magnetoresistive element layer 127 and the electrode 25. As a result, the crystallinity of each layer in the magnetoresistive element layer 127 is not affected by the crystallinity of the electrode 25. Therefore, the crystallinity of the magnetoresistive element layer 127 is improved.

[0133] 2. Second Embodiment A magnetic storage device according to the second embodiment will now be described. In the magnetic storage device 1A according to the second embodiment, the cross-sectional structure of the memory cell array 10A and the method of manufacturing the memory cell array 10A differ from those of the first embodiment. The differences from the first embodiment will be described below.

[0134] 2.1 Cross-sectional structure of memory cell array An example of the cross-sectional structure of the memory cell array 10A will be explained using Figures 25 and 26. Figure 25 is a cross-sectional view along line IV-IV in Figure 3 shown in the first embodiment, showing an example of the cross-sectional structure of the memory cell array 10A included in the magnetic storage device 1A according to the second embodiment. Figure 26 is a cross-sectional view along line VV in Figure 3 shown in the first embodiment, showing an example of the cross-sectional structure of the memory cell array 10A included in the magnetic storage device 1A according to the second embodiment.

[0135] As shown in Figures 25 and 26, the memory cell array 10A includes a plurality of conductors 21, a plurality of electrodes 23, a plurality of selector bodies 24, a plurality of electrodes 25, a plurality of conductors 26, a plurality of MTJ bodies 27, a plurality of conductors 28, a plurality of conductors 29, an insulator 40, an insulator 41, a plurality of insulators 44, and an insulator 45.

[0136] On a semiconductor substrate (not shown), for example, a plurality of conductors 21 are provided. The plurality of conductors 21 are arranged along the Y direction. Each of the plurality of conductors 21 extends along the X direction. Each of the plurality of conductors 21 is conductive and functions as a word line WL.

[0137] An insulator 40 is provided in the region between two adjacent conductors 21 in the Y direction. This insulates each of the multiple conductors 21 from each other in the Y direction. The same material as in the first embodiment is used for the insulator 40.

[0138] The multiple conductors 21 and insulators 40 may be provided on the upper surface of the semiconductor substrate, or they may be provided separately from the semiconductor substrate without contacting it.

[0139] Multiple electrodes 23 are provided on the upper surface of each of the multiple conductors 21. Multiple electrodes 23 provided on the upper surface of the same conductor 21 are aligned in the X direction. Each of the multiple electrodes 23 is conductive and functions as a lower electrode BE.

[0140] On the upper surface of each of the multiple electrodes 23, one corresponding selector body 24 is provided from among the multiple selector bodies 24. Each of the multiple selector bodies 24 functions as a switching element SEL.

[0141] On the upper surface of each of the multiple selector bodies 24, one corresponding electrode 25 is provided from among the multiple electrodes 25. Each of the multiple electrodes 25 has the same structure as in the first embodiment. The same materials as in the first embodiment are used for the conductors 251 and 252 included in the electrodes 25. Each of the multiple electrodes 25 functions as an intermediate electrode ME.

[0142] On the upper surface of each of the multiple electrodes 25, one corresponding conductor 26 is provided from among the multiple conductors 26. Each of the multiple conductors 26 is conductive and functions as a buffer layer BF. The conductors 26 include, for example, hafnium (Hf) and hafnium boride (HfB). The upper surface of the conductors 26 is flattened. The thickness of the conductors 26 is, for example, about 3 nanometers (nm).

[0143] On the upper surface of each of the multiple conductors 26, one corresponding MTJ body 27 is provided from among the multiple MTJ bodies 27. Each of the multiple MTJ bodies 27 has the same structure as shown in Figure 6 in the first embodiment. The ferromagnetic material 31, non-magnetic material 32, ferromagnetic material 33, non-magnetic material 34, ferromagnetic material 35, and non-magnetic material 36 included in the MTJ body 27 are the same materials as in the first embodiment. Each of the multiple MTJ bodies 27 functions as a magnetoresistive element MTJ.

[0144] Hereinafter, the structure including the electrode 25, conductor 26, and MTJ body 27 will be referred to as the "third stack." The memory cell array 10A includes a plurality of third stacks. On the side of each of the plurality of third stacks, an insulator 44 (side wall) is provided so as to cover a portion of the side of the conductor 251, the conductor 252, the conductor 26, and the side of the MTJ body 27. That is, the insulator 44 covers the side of the electrode 25, the side of the conductor 26, and the side of the MTJ body 27. The insulator 44 is provided, for example, from a position higher than the top surface of the selector body 24 to a position equal to the top surface of the MTJ body 27. As a result, each of the plurality of conductors 252 is insulated from each other. Each of the plurality of conductors 26 is insulated from each other. Each of the plurality of MTJ bodies 27 is insulated from each other. The same material as in the first embodiment is used for the insulator 44.

[0145] Insulators 41 are provided in the regions between two adjacent electrodes 23, between two adjacent selector bodies 24, between two adjacent conductors 251, and between two adjacent insulators 44. As a result, each of the multiple electrodes 23 is insulated from each other in the Y direction. Each of the multiple selector bodies 24 is insulated from each other. Each of the multiple conductors 251 is insulated from each other by the insulators 41 and 44. The same material as in the first embodiment is used for the insulator 41.

[0146] A single conductor 28 extending in the Y direction is provided so as to be in contact with the upper surface of each of the multiple MTJ bodies 27 arranged in the Y direction. The multiple conductors 28 are arranged in the X direction. Each of the multiple conductors 28 extends along the Y direction. Each of the multiple conductors 28 is conductive and functions as a bit line BL.

[0147] An insulator 45 is provided in the region between two adjacent conductors 28 in the X direction. This insulates each of the multiple conductors 28 from each other in the X direction. The same material as in the first embodiment is used for the insulator 45.

[0148] Thus, a structure in which the conductor 21, electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, and conductor 28 are stacked in this order corresponds to the first-stage stacked structure. The memory cell MC of the first-stage stacked structure includes electrode 23, selector body 24, electrode 25, conductor 26, and MTJ body 27. Electrode 25 is provided between the selector body 24 and the conductor 26.

[0149] Multiple electrodes 23 are provided on the upper surface of each of the multiple conductors 28. Multiple electrodes 23 provided on the upper surface of the same conductor 28 are aligned in the Y direction.

[0150] On the upper surface of each of the multiple electrodes 23, a selector body 24, an electrode 25, a conductor 26, and an MTJ body 27 are provided, similar to the first-stage laminated structure. The structure of the electrode 25 is the same as that of the first-stage laminated structure. The conductor 26 includes, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductor 26 is, for example, about 1 nanometer (nm). The structure of the MTJ body 27 is the same as that of the first-stage laminated structure. On the sides of each of the multiple third laminates, each containing an electrode 25, a conductor 26, and an MTJ body 27, an insulator 44 is provided, similar to the first-stage laminated structure. That is, the insulator 44 covers the sides of the electrode 25, the sides of the conductor 26, and the sides of the MTJ body 27. Similar to the first layered structure, an insulator 41 is provided in the region between two adjacent electrodes 23, the region between two adjacent selector bodies 24, the region between two adjacent conductors 251, and the region between two adjacent insulators 44.

[0151] On the upper surface of each of the multiple MTJ bodies 27, one corresponding conductor 29 is provided from among the multiple conductors 29. The multiple conductors 29 are arranged in the X and Y directions. An insulator 45 is provided in the region between two adjacent conductors 29. As a result, each of the multiple conductors 29 is insulated from the others.

[0152] A single conductor 21 is provided extending in the X direction so as to be in contact with the upper surface of each of the multiple conductors 29 arranged in the X direction. The multiple conductors 21 are arranged in the Y direction. Each of the multiple conductors 21 extends along the X direction. Each of the multiple conductors 21 is conductive and functions as a word line WL. The single conductor 21 and the multiple conductors 29 provided on the lower surface of the conductor 21 are collectively referred to as the word line WL.

[0153] Similar to the first layered structure, an insulator 40 is provided in the region between two adjacent conductors 21 in the Y direction.

[0154] Thus, a structure in which the conductor 28, electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, conductor 29, and conductor 21 are stacked in this order corresponds to the second-stage stacked structure. The memory cell MC of the second-stage stacked structure includes electrode 23, selector body 24, electrode 25, conductor 26, MTJ body 27, and conductor 29. Electrode 25 is provided between the selector body 24 and the conductor 26.

[0155] 2.2 Method for Manufacturing Memory Cell Arrays A method for manufacturing the memory cell array 10A of the magnetic storage device 1A according to the second embodiment will be described. Figure 27 is a flowchart showing an example of a method for manufacturing the memory cell array 10A in the magnetic storage device 1A according to the second embodiment. Figures 28 to 40 are cross-sectional views illustrating an example of a method for manufacturing the memory cell array 10A in the magnetic storage device 1A according to the second embodiment. Figures 28 to 40 are cross-sectional views corresponding to Figure 25.

[0156] First, in S31 of Figure 27, as shown in Figure 28, a plurality of conductors 21 and insulators 40 are formed on the upper surface of a semiconductor substrate (not shown) as a wafer WF, in the same manner as in the first embodiment.

[0157] Next, in S32 of Figure 27, an electrode 23, a selector body 24, an electrode 25, a conductor 26, an MTJ body 27, and an insulator 44 are formed on the upper surface of each of the multiple conductors 21.

[0158] Specifically, as shown in Figure 28, an electrode layer 123, a selector layer 124, an electrode layer 125, a conductive layer 126, a conductive layer 151, and a conductive layer 152 are formed in this order on the upper surfaces of the multiple conductors 21 and the insulator 40. The electrode layer 125 is formed by creating a conductive layer 1251 and a conductive layer 1252 in that order. The conductive layer 126 contains, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductive layer 126 is, for example, about 3 nanometers (nm). The thickness of the conductive layer 151 is, for example, about 0.5 nanometers (nm). The conductive layer 152 contains, for example, hafnium (Hf) or hafnium boride (HfB). The thickness of the conductive layer 152 is, for example, about 10 nanometers (nm).

[0159] Next, the conductive layers 151 and 152 are etched by ion beam etching in the same manner as in the first embodiment. This removes the conductive layers 151 and 152, exposing the conductive layer 126. As shown in Figure 29, the upper surface of the conductive layer 126 is flattened by this ion beam etching. The thickness of the conductive layer 126 after flattening is, for example, about 3 nanometers (nm).

[0160] The upper surface of the conductive layer 126 may be flattened by CMP, RIE, or the like.

[0161] Next, as shown in Figure 30, a magnetoresistive element layer 127 is formed on the upper surface of the conductive layer 126 in the same manner as in the first embodiment. The magnetoresistive element layer 127 is a laminate in which each layer included in the magnetoresistive element MTJ described in Figure 6 is deposited in a flat plate shape in this stacking order.

[0162] Next, the magnetoresistive element layer 127 is annealed in the same manner as in the first embodiment. The annealing is performed, for example, at 300°C to 400°C for an arbitrary amount of time. This causes each layer of the magnetoresistive element layer 127 to crystallize.

[0163] Next, as shown in Figure 31, a plurality of masks 62 are formed in the same manner as in the first embodiment.

[0164] Next, as shown in Figure 31, the conductive layer 1251, conductive layer 1252, conductive layer 126, and magnetoresistive element layer 127 are etched by ion beam etching. The etching is carried out up to a position between the upper surface of the selector layer 124 and the lower surface of the conductive layer 1252. As a result, the portions of the conductive layer 1251, conductive layer 1252, conductive layer 126, and magnetoresistive element layer 127 that are not protected by the multiple masks 62 are removed, and a portion of the upper end of the conductive layer 1251 is removed, exposing the conductive layer 1251. Through this ion beam etching, as shown in Figure 32, multiple conductors 252, multiple conductors 26, and multiple MTJ bodies 27 are formed from the conductive layer 1252, conductive layer 126, and magnetoresistive element layer 127.

[0165] Next, as shown in Figure 33, an insulating layer 144 is formed on the upper surface of the conductive layer 1251, on the upper surface of each of the multiple MTJ bodies 27, and on each of the sides of the multiple conductors 252, multiple conductors 26, and multiple MTJ bodies 27.

[0166] Next, as shown in Figure 34, the insulating layer 144 is etched by anisotropic etching. This removes the insulating layer 144 on the upper surface of the conductive layer 1251 and the insulating layer 144 on the upper surface of each of the multiple MTJ bodies 27, forming multiple insulators 44.

[0167] Next, anisotropic etching removes the portions of the electrode layer 123, selector layer 124, and conductor layer 1251 that are not protected by the insulator 44, exposing the multiple conductors 21 and insulator 40 located beneath those portions. As a result, multiple electrodes 23, multiple selector bodies 24, and multiple conductors 251 are formed, as shown in Figure 35. That is, multiple third laminates are formed, each containing an electrode 25, a conductor 26, and an MTJ body 27. The anisotropic etching in this process is, for example, RIE.

[0168] Next, in step S33 of Figure 27, as shown in Figure 36, an insulator 41 is embedded in the region between two adjacent electrodes 23, the region between two adjacent selector bodies 24, the region between two adjacent conductors 251, and the region between two adjacent insulators 44.

[0169] Next, in S34 of Figure 27, as shown in Figure 36, a plurality of conductors 28 and insulators 45 are formed on the upper surfaces of a plurality of third laminates, an insulator 41, and a plurality of insulators 44, in the same manner as in the first embodiment.

[0170] As described above, the first layered structure is formed by carrying out steps S31 to S34 in Figure 27.

[0171] Next, in S35 of Figure 27, an electrode 23, a selector body 24, an electrode 25, a conductor 26, an MTJ body 27, and an insulator 44 are formed on the upper surface of each of the multiple conductors 28.

[0172] Specifically, as shown in Figure 37, in the same manner as the formation of the first layered structure, electrode layers 123, selector layer 124, and electrode layer 125 are formed in this order on the upper surfaces of the multiple conductors 28 and insulators 45. The electrode layer 125 consists of a conductive layer 1251 and a conductive layer 1252 formed in this order.

[0173] Next, as shown in Figure 37, a conductive layer 126 is formed on the upper surface of the electrode layer 125. The conductive layer 126 contains, for example, hafnium (Hf), hafnium boride (HfB), etc. The thickness of the conductive layer 126 is, for example, about 1 nanometer (nm). A magnetoresistive element layer 127 is formed on the upper surface of the conductive layer 126. Alternatively, the upper surface of the conductive layer 126 may be flattened in the same manner as in S32 of Figure 27. In this case, the upper surfaces of each layer included in the magnetoresistive element layer 127 provided on the upper surface of the conductive layer 126 are also flattened. As a result, the characteristics of the magnetoresistive element layer 127 are improved.

[0174] Next, the magnetoresistive element layer 127 is annealed in the same manner as the formation of the first layer of the stacked structure. The annealing is performed, for example, at 300°C to 400°C for an arbitrary amount of time. This causes each layer of the magnetoresistive element layer 127 to crystallize. Note that the temperature and time of the annealing may differ between the formation of the first layer of the stacked structure and the formation of the second layer of the stacked structure.

[0175] Next, as shown in Figure 38, multiple masks 62 are formed in the same manner as the first layered structure.

[0176] Next, as shown in Figure 38, the conductive layer 1251, conductive layer 1252, conductive layer 126, and magnetoresistive element layer 127 are etched by ion beam etching in the same manner as the first layered structure. As a result, as shown in Figure 39, multiple conductors 252, multiple conductors 26, and multiple MTJ bodies 27 are formed.

[0177] Next, in the same manner as the first layered structure, an insulating layer 144 is formed on the upper surface of the conductive layer 1251, on the upper surface of each of the multiple MTJ bodies 27, and on each of the sides of the multiple conductors 252, multiple conductors 26, and multiple MTJ bodies 27.

[0178] Next, the insulating layer 144 is etched by anisotropic etching, similar to the first layered structure. This forms multiple insulators 44, as shown in Figure 40.

[0179] Next, in the same manner as the first layered structure, anisotropic etching removes the portions of the electrode layer 123, selector layer 124, and conductor layer 1251 that are not protected by the insulator 44, exposing the multiple conductors 21 and insulator 40 located beneath those portions. As a result, multiple electrodes 23, multiple selector bodies 24, and multiple conductors 251 are formed, as shown in Figure 40. In other words, multiple third layered structures are formed, each containing an electrode 25, a conductor 26, and an MTJ body 27.

[0180] Next, in S36 of Figure 27, as shown in Figure 40, insulators 41 are embedded in the region between two adjacent electrodes 23, the region between two adjacent selector bodies 24, the region between two adjacent conductors 251, and the region between two adjacent insulators 44, in the same manner as in the first layered structure.

[0181] Next, in step S37 of Figure 27, as shown in Figure 40, multiple conductors 29 and multiple insulators 45 are formed on the upper surfaces of multiple third laminates, insulators 41, and multiple insulators 44 in the same manner as in the formation of the first layered structure.

[0182] Next, in S38 of Figure 27, as shown in Figure 25, multiple conductors 21 and insulators 40 are formed on the upper surfaces of multiple conductors 29 and insulators 45 in the same manner as in the formation of the first layered structure.

[0183] As described above, the second layer of the stacked structure is formed by carrying out steps S35 to S38 in Figure 27.

[0184] As a result, a configuration corresponding to the memory cell array 10A is formed on the wafer WF. Then, the wafer WF is diced into chip units to form the magnetic memory device 1A.

[0185] The magnetic memory device 1A is formed by the manufacturing process described above. However, the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing step, or some steps may be omitted or integrated. Furthermore, each manufacturing step may be rearranged to the extent possible.

[0186] 2.3 Effects according to this embodiment According to the second embodiment, the same effects as the first embodiment are achieved.

[0187] Furthermore, according to this embodiment, the thickness of the magnetic storage device 1A can be made relatively thin.

[0188] 3. Variations, etc. As described above, the magnetic memory device (1) according to the embodiment includes a first wiring (21) extending in a first direction (X), a second wiring (28) extending in a second direction (Y) intersecting the first direction (X) and provided above the first wiring (21), a first memory cell (MC) provided between the first wiring (21) and the second wiring (28), a third wiring (21) extending in the first direction (X) and provided above the second wiring (28), and a second memory cell (MC) provided between the second wiring (28) and the third wiring (21). The first memory cell (MC) includes a first selector body (24), a first conductor (26), and a first MTJ body (27) provided on the upper surface of the first conductor (26). The second memory cell (MC) includes a second selector body (24), a second conductor (26), and a second MTJ body (27) provided on the upper surface of the second conductor (26). The upper surface of the first conductor (26) is flattened.

[0189] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0190] Furthermore, the flowchart described in the above embodiment allows for rearranging the order of processing as much as possible.

[0191] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0192] 1, 1A…Magnetic memory device, 10, 10A…Memory cell array, 11…Row selection circuit, 12…Column selection circuit, 13…Decode circuit, 14…Write circuit, 15…Read circuit, 16…Voltage generation circuit, 17…Input / output circuit, 18…Control circuit, 21, 22…Conductor, 23…Electrode, 24…Selector body, 25…Electrode, 26…Conductor, 27…MTJ body, 28…Conductor, 31…Strong Magnetic material, 32... Non-magnetic material, 33... Ferromagnetic material, 34... Non-magnetic material, 35... Ferromagnetic material, 36... Non-magnetic material, 40-45... Insulator, 61, 62... Mask, 251, 252... Conductor, 122... Conductive layer, 123... Electrode layer, 124... Selector layer, 125... Electrode layer, 126... Conductive layer, 127... Magnetoresistive effect element layer, 151, 152... Conductive layer, 1251, 1252... Conductive layer< / j> < / m> < / n>

Claims

1. A first wiring is provided extending in the first direction, Extending in a second direction intersecting the first direction, and provided above the first wiring, It includes a first selector body, a first conductor, and a first MTJ body provided on the upper surface of the first conductor, and a first memory cell provided between the first wiring and the second wiring, A third wiring extending in the first direction and provided above the second wiring, The second selector body includes a second conductor and a second MTJ body provided on the upper surface of the second conductor, and a second memory cell provided between the second wiring and the third wiring. Equipped with, The upper surface of the first conductor is flattened. Magnetic storage device.

2. The thickness of the first conductor is greater than the thickness of the second conductor. The magnetic storage device according to claim 1.

3. The first conductor and the second conductor contain hafnium (Hf) or hafnium boride (HfB). The magnetic storage device according to claim 1.

4. The first selector body is provided below the first MTJ body, The second selector body is provided below the second MTJ body, The magnetic storage device according to claim 1.

5. A first electrode is provided between the first selector body and the first conductor, A second electrode is provided between the second selector body and the second conductor. It also has, The magnetic storage device according to claim 4.

6. A first insulator covering the side surface of the first selector body and the side surface of the first electrode, A second insulator covering the side surface of the first conductor and the side surface of the first MTJ body, A third insulator covering the side surface of the second selector body and the side surface of the second electrode, A fourth insulator covering the side surface of the second conductor and the side surface of the second MTJ body It also has, The magnetic storage device according to claim 5.

7. A first insulator covering the side surface of the first electrode, the side surface of the first conductor, and the side surface of the first MTJ body, A second insulator covering the side surface of the second electrode, the side surface of the second conductor, and the side surface of the second MTJ body It also has, The magnetic storage device according to claim 5.

8. The first electrode includes a first sub-electrode and a second sub-electrode provided on the upper surface of the first sub-electrode. The second electrode includes a third sub-electrode and a fourth sub-electrode provided on the upper surface of the third sub-electrode. The magnetic storage device according to claim 5.

9. The first sub-electrode and the third sub-electrode each contain at least one element or compound selected from carbon (C) and carbon nitride (CN), The second sub-electrode and the fourth sub-electrode each contain at least one element or compound selected from high-melting-point metal elements and compounds of high-melting-point metal elements. The magnetic storage device according to claim 8.

10. The first MTJ body and the second MTJ body are First ferromagnetic material and, Second ferromagnetic material and, A third ferromagnetic material is provided on the opposite side of the second ferromagnetic material from the first ferromagnetic material, A first non-magnetic material is provided between the first ferromagnetic material and the second ferromagnetic material, A second non-magnetic material is provided between the second ferromagnetic material and the third ferromagnetic material, A third non-magnetic material provided on the lower surface of the third ferromagnetic material and including, The magnetic storage device according to claim 1.

11. The second ferromagnetic material and the third ferromagnetic material are antiferromagnetically coupled. The magnetic storage device according to claim 10.

12. The first selector unit and the second selector unit are two-terminal type selector units. The magnetic storage device according to claim 1.

13. The first selector body and the first electrode form a stacked structure, Forming a first conductive layer on the upper surface of the first electrode, The upper surface of the first conductive layer is flattened, Forming a first magnetoresistive element layer on the upper surface of the first conductive layer, The first annealing process will be carried out, By removing a portion of the first magnetoresistive element layer and a portion of the first conductive layer, a first conductor and a first MTJ body are formed. Equipped with, A method for manufacturing a magnetic memory device.

14. A structure is formed in which the second selector body and the second electrode are stacked on top of the first MTJ body, Forming a second conductive layer on the upper surface of the second electrode, A second magnetoresistive effect element layer is formed on the upper surface of the second conductive layer, The second annealing process will be carried out, By removing a portion of the second magnetoresistive element layer and a portion of the second conductive layer, a second conductor and a second MTJ body are formed. It also has, A method for manufacturing a magnetic storage device according to claim 13.

15. Flattening the upper surface of the first conductive layer is Forming a third conductive layer on the upper surface of the first conductive layer, Forming a fourth conductive layer on the upper surface of the third conductive layer, The upper surface of the first conductive layer is flattened by removing the third conductive layer and the fourth conductive layer using ion beam etching. including, A method for manufacturing a magnetic storage device according to claim 13.

16. Forming the first conductive layer is Forming the first conductive layer containing hafnium (Hf) or hafnium boride (HfB). including, A method for manufacturing a magnetic storage device according to claim 13.

17. To form the first selector layer, Forming a first electrode layer on the upper surface of the first selector layer, Forming a first conductive layer on the upper surface of the first electrode layer, The upper surface of the first conductive layer is flattened, Forming a first magnetoresistive element layer on the upper surface of the first conductive layer, The first annealing process will be carried out, By removing a portion of the first magnetoresistive element layer, a portion of the first conductive layer, a portion of the first electrode layer, and a portion of the first selector layer, a first selector body, a first electrode, a first conductor, and a first MTJ body are formed. Equipped with, A method for manufacturing a magnetic memory device.

18. A second selector layer is formed above the first MTJ body, Forming a second electrode layer on the upper surface of the second selector layer, Forming a second conductive layer on the upper surface of the second electrode layer, A second magnetoresistive effect element layer is formed on the upper surface of the second conductive layer, The second annealing process will be carried out, By removing a portion of the second magnetoresistive element layer, a portion of the second conductive layer, a portion of the second electrode layer, and a portion of the second selector layer, a second selector body, a second electrode, a second conductor, and a second MTJ body are formed. It also has, A method for manufacturing a magnetic storage device according to claim 17.

19. Flattening the upper surface of the first conductive layer is Forming a third conductive layer on the upper surface of the first conductive layer, Forming a fourth conductive layer on the upper surface of the third conductive layer, The upper surface of the first conductive layer is flattened by removing the third conductive layer and the fourth conductive layer using ion beam etching. including, A method for manufacturing a magnetic storage device according to claim 17.

20. Forming the first conductive layer is Forming the first conductive layer containing hafnium (Hf) or hafnium boride (HfB). including, A method for manufacturing a magnetic storage device according to claim 17.

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