Semiconductor memory

Abstract

The present invention provides a semiconductor memory device that simplifies wiring and reduces power consumption. [Solution] The semiconductor memory device according to this embodiment comprises a plurality of first data lines and a plurality of first control lines used for writing data, a plurality of second data lines and a plurality of second control lines used for reading data, and a plurality of memory cells. A first drive line is provided in common to the plurality of first control lines and a plurality of second control lines and transmits a selection voltage for writing data. A plurality of fourth transistors are connected between the plurality of first control lines and the first drive lines. A plurality of fifth transistors are connected between the plurality of second control lines and the first drive lines. A plurality of third control lines are connected to the gates of the plurality of fourth transistors, respectively. A plurality of fourth control lines are connected to the gates of the plurality of fifth transistors, respectively.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] A gain cell memory reads data by amplifying the stored charge in a sense node with a transistor. In a gain cell memory, the read port and the write port are separated, and bit lines and word lines are provided separately for reading and writing. Therefore, the number of wirings is large and the wiring structure becomes complicated. Also, as the number of wirings increases, the number of drivers increases and the power consumption increases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of simplifying wirings and reducing power consumption.

Means for Solving the Problems

[0005] The semiconductor memory device according to this embodiment comprises a plurality of first data lines and a plurality of first control lines used for writing data, and a plurality of second data lines and a plurality of second control lines used for reading data. The plurality of memory cells include a first transistor whose gate is connected to one of the plurality of first control lines and one end is connected to one of the plurality of first data lines, a second transistor whose gate is connected to one of the plurality of second control lines and one end is connected to one of the plurality of second data lines, and a third transistor whose gate is connected to the other end of the first transistor and holds data from the first data lines, and whose one end is connected to the other end of the second transistor and is in a conductive state according to the data. A first drive line is provided in common to the plurality of first control lines and the plurality of second control lines and transmits a selection voltage for writing data. A plurality of fourth transistors are connected between the plurality of first control lines and the first drive line. A plurality of fifth transistors are connected between the plurality of second control lines and the first drive line. A plurality of third control lines are connected to the gates of the plurality of fourth transistors, respectively. Multiple fourth control lines are connected to the gates of the multiple fifth transistors, respectively. [Brief explanation of the drawing]

[0006] [Figure 1] A circuit diagram showing an example of a single memory cell configuration according to the first embodiment. [Figure 2] A perspective view showing an example configuration of a gain cell memory according to the first embodiment. [Figure 3] A conceptual diagram showing the read operation of the gain cell memory according to the first embodiment. [Figure 4] A timing diagram showing an example of the operation of the gain cell memory according to the first embodiment. [Figure 5] A perspective view showing an example configuration of a gain cell memory according to the second embodiment. [Figure 6] A conceptual diagram showing the read operation of the gain cell memory according to the second embodiment. [Figure 7] A perspective view showing an example of the configuration of a gain cell memory according to the third embodiment. [Figure 8]A perspective view showing an example of the configuration of a gain cell memory according to the fourth embodiment. [Figure 9] A perspective view showing an example configuration of a gain cell memory according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0008] (First Embodiment) Figure 1 is a circuit diagram showing an example of a single memory cell configuration according to the first embodiment. The memory cell MC of the gain cell memory is composed of three transistors MW1, MR1, and MR2. Transistors MW1, MR1, and MR2 are composed of, for example, n-type OSFETs (Oxide Semiconductor Field Effect Transistors).

[0009] The gate of transistor MW1, which acts as the first transistor, is connected to the write word line WWL, which acts as the first control line. One electrode of transistor MW1 is connected to the write bit line WBL, which acts as the first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. The one and the other electrode of transistor MW1 function as source electrodes or drain electrodes depending on the voltage supplied to transistor MW1. Under the control of the write word line WWL, transistor MW1 connects the write bit line WBL to the gate of transistor MR1, which acts as a sense node SN (hereinafter also referred to as sense node SN). When transistor MW1 is conducting (on), it transmits the voltage of the write bit line WBL to sense node SN. When transistor MW1 is not conducting (off), it holds the voltage of sense node SN. In this way, transistor MW1 can write the voltage (data) from the write bit line WBL to sense node SN, or hold the written voltage (data) in sense node SN.

[0010] The gate of transistor MR1, acting as a third transistor, is connected to the other electrode of transistor MW1 and functions as a sense node SN. One electrode of transistor MR1 (e.g., source) is connected to a low voltage source VSS. The other electrode of transistor MR1 (e.g., drain) is connected to one electrode of transistor MR2. Transistor MR1 conducts depending on the voltage (i.e., data) of the sense node SN. For example, when the sense node SN is held at a high level voltage (e.g., data "1"), transistor MR1 is ON. When the sense node SN is held at a low level voltage (e.g., data "0"), transistor MR1 is OFF.

[0011] The gate of transistor MR2, acting as the second transistor, is connected to the read word line RWL, acting as the second control line. One electrode of transistor MR2 is connected to the drain of transistor MR1. The other electrode of transistor MR2 is connected to the read bit line RBL, acting as the second data line. Both electrodes of transistor MR2 can function as source or drain electrodes depending on the voltage supplied to transistor MR2. Under the control of the read word line RWL, transistor MR2 connects the read bit line RBL to the drain of transistor MR1. Transistor MR1 is in a state (on or off) depending on the voltage (data) held at the sense node SN. When transistor MR2 is in the ON state, connecting the read bit line RBL to transistor MR1 causes charge from the read bit line RBL to flow to the low voltage source VSS depending on the state of transistor MR1. When transistor MR1 is in the ON state, charge from the read bit line RBL flows to the low voltage source VSS, and the voltage of the read bit line RBL becomes low. When transistor MR1 is off, very little charge flows from the read bit line RBL to the low voltage source VSS, and the voltage across the read bit line RBL remains high. This allows the voltage based on the data held in sense node SN to be transmitted to the read bit line RBL.

[0012] The sense amplifier SA, acting as a detection circuit, is connected to the write bit line WBL and the read bit line RBL. The sense amplifier SA latches external write data and applies a voltage corresponding to the write data to the write bit line WBL. The sense amplifier SA also detects read data based on the voltage of the read bit line RBL and latches the read data. The read data latched by the sense amplifier SA is transmitted externally. The sense amplifier SA also precharges the write bit line WBL and the read bit line RBL.

[0013] The controller CTL is connected to the write word line WWL and the read word line RWL, and controls the voltages of the write word line WWL and the read word line RWL.

[0014] The write word line WWL and the write bit line WBL are wirings used for writing data. The read word line RWL and the read bit line RBL are wirings used for reading data. Thus, the gain cell memory uses different word lines and bit lines for writing and reading data. Thereby, the gain cell memory can read data while maintaining the data of the sense node SN (non-destructive readout). Also, one memory cell MC is composed of three transistors MW1, MR1, MR2 and does not have a capacitor that is difficult to miniaturize as in a DRAM (Dynamic Random Access Memory). Therefore, the gain cell memory is excellent in miniaturization.

[0015] FIG. 2 is a perspective view showing a configuration example of a gain cell memory according to the first embodiment. The gain cell memory according to the present embodiment includes a three-dimensional memory cell array in which a plurality of memory cells MC are three-dimensionally arranged. The plurality of memory cells MC are arranged in a matrix consisting of a plurality of rows and a plurality of columns. The rows are the X-direction arrangement of the memory cells MC. The columns are the Z-direction arrangement of the memory cells MC. Further, the memory cells MC are arranged in the Y direction in the matrix of the memory cells MC. Thereby, the memory cell array MCA is a three-dimensional array in which a plurality of memory cells MC are three-dimensionally arranged. Note that the number of rows, columns, and matrices of the memory cells MC is not particularly limited.

[0016] The plurality of write word lines WWL as a plurality of first control lines are provided corresponding to each of the plurality of rows of the memory cells MC. The plurality of read word lines RWL as a plurality of second control lines are also provided corresponding to each of the plurality of rows of the memory cells MC. The write word line WWL is used for writing data and extends in the X direction. The read word line RWL is used for reading data and extends in the X direction.

[0017] A drive line WDRV as a first drive line is commonly provided for a plurality of write word lines WWL and a plurality of read word lines RWL arranged in the Y direction. The drive line WDRV transmits a selection voltage for writing data. The plurality of drive lines WDRV each extend in the Y direction and are arranged in the Z direction.

[0018] A plurality of transistors WT1 as a plurality of fourth transistors are each connected between a plurality of write word lines WWL and the drive line WDRV. One electrode of the plurality of transistors WT1 is connected to the plurality of write word lines WWL respectively. The other electrodes of the plurality of transistors WT1 arranged in the Y direction are commonly connected to one drive line WDRV. Incidentally, one and the other electrodes of each of the transistors WT1, RT1, WT2, WTbl, RTbl can function as a source electrode or a drain electrode according to the voltage supplied to the transistors WT1, RT1, WT2, WTbl, RTbl.

[0019] A plurality of transistors RT1 as a plurality of fifth transistors are each connected between a plurality of read word lines RWL and the drive line WDRV. One electrode of the plurality of transistors RT1 is connected to the plurality of read word lines RWL respectively. The other electrodes of the plurality of transistors RT1 arranged in the Y direction are commonly connected to one drive line WDRV. The plurality of transistors WT1, RT1 arranged in the Y direction are commonly connected to one drive line WDRV.

[0020] The main write word line WMWL, acting as a third control line, is commonly connected to the gates of multiple transistors WT1 arranged in the Z direction. That is, the main write word line WMWL is commonly provided to multiple write word lines WWL arranged in the Z direction. Each of the multiple main write word lines WMWL extends in the Z direction and is arranged in the Y direction. The main write word line WMWL selectively turns on the multiple transistors WT1 connected to it, connecting the drive line WDRV to the corresponding write word line WWL. Each of the multiple main write word lines WMWL arranged in the Y direction is driven independently. Therefore, the transistors WT1 shown in Figure 2 are individually controlled to be on or off for each of the multiple rows arranged in the Z direction.

[0021] The read main word line RMWL, acting as the fourth control line, is commonly connected to the gates of multiple transistors RT1 arranged in the Z direction. That is, the read main word line RMWL is commonly provided to multiple read word lines RWL arranged in the Z direction. Each of the multiple read main word lines RMWL extends in the Z direction and is arranged in the Y direction. The multiple read main word lines RMWL are commonly connected, and the corresponding multiple transistors RT1 are turned ON, connecting the drive line WDRV to the multiple read word lines RWL arranged in the Z and Y directions. The multiple read main word lines RMWL arranged in the Y direction are commonly connected and driven identically. Therefore, the transistors RT1 arranged in the Y and Z directions shown in Figure 2 are controlled to be simultaneously ON or OFF.

[0022] A non-write voltage line VUW, acting as a second drive line, is provided in common to multiple write word lines WWL arranged in the Y direction. The non-write voltage line VUW transmits a non-selective voltage that does not write data. Each of the multiple non-write voltage lines VUW extends in the Y direction and is arranged in the Z direction.

[0023] Multiple transistors WT2, acting as the seventh transistor, are each connected between multiple write word lines WWL and multiple non-write voltage lines VUW. One electrode of each of the multiple transistors WT2 is connected to multiple write word lines WWL. The other electrodes of the multiple transistors WT2 arranged in the Y direction are commonly connected to one non-write voltage line VUW. On the other hand, multiple read word lines RWL are electrically isolated from multiple non-write voltage lines VUW. Note that if the non-selective voltage is constant, the multiple non-write voltage lines VUW may be short-circuited to each other as a single drive line.

[0024] The unselected main word line bWMWL is commonly connected to the gates of multiple transistors WT2 arranged in the Z direction. Each of the multiple unselected main word lines bWMWL extends in the Z direction and is arranged in the Y direction. The unselected main word line bWMWL turns on multiple transistors WT2 that are connected to the write word line WWL corresponding to memory cells MC that do not write data, and connects the unwrite voltage line VUW to the corresponding write word line WWL.

[0025] Multiple write bit lines (WBLs) as multiple first data lines are provided corresponding to each of the multiple rows of the memory cell MC. Multiple read bit lines (RBLs) as multiple second data lines are also provided corresponding to each of the multiple rows of the memory cell MC. Note that in Figure 2, only one write bit line (WBL) and one read bit line (RBL) are shown. The write bit line (WBL) is used for writing data and extends in the Z direction. The read bit line (RBL) is used for reading data and extends in the Z direction. The read bit line (RBL), write bit line (WBL), write main word line (WMWL), read main word line (RMWL), and unselected main word line (bWMWL) all extend in the Z direction.

[0026] The write global bit line WGBL, which acts as the third data line, is provided in common to multiple write bit lines WBL arranged in the Y direction. Each of the multiple write global bit lines WGBL extends in the Y direction and is arranged in the X direction. Note that in Figure 2, only one write global bit line WGBL is shown. The write global bit line WGBL is connected to a write bit line WBL selected from the multiple corresponding write bit lines WBL, and transmits data from the sense amplifier SA to this selected write bit line WBL.

[0027] The read global bit line RGBL, which serves as the fourth data line, is provided in common to multiple read bit lines RBL arranged in the Y direction. Each of the multiple read global bit lines RGBL extends in the Y direction and is arranged in the X direction. Note that in Figure 2, only one read global bit line RGBL is shown. The read global bit line RGBL is connected to a read bit line RBL selected from the multiple read bit lines RBL that correspond to it, and transmits the data from the selected read bit line RBL to the sense amplifier SA.

[0028] Multiple transistors WTbl are connected between multiple write bit lines WBL and write global bit line WGBL. One electrode of each of the multiple transistors WTbl is connected to multiple write bit lines WBL. The other electrodes of multiple transistors WTbl arranged in the Y direction are commonly connected to one write global bit line WGBL. The gates of multiple transistors WTbl arranged in the X direction are commonly connected to a write selection line WSEL. Multiple write selection lines WSEL each extend in the X direction and are arranged in the Y direction.

[0029] During a write operation, one of several write selection lines WSEL is selectively driven. Multiple transistors WTbl connected to the selected write selection line WSEL are turned on, electrically connecting the corresponding write bit line WBL and the write global bit line WGBL. As a result, the multiple transistors WTbl connected to the selected write selection line WSEL transmit data from the sense amplifier SA from the corresponding write global bit line WGBL to the write bit line WBL.

[0030] When considering the capacitance of the write bit line WBL, it is preferable to provide a transistor WTbl for high-speed operation of the write bit line WBL. However, if operating speed is not a consideration, the transistor WTbl may be omitted.

[0031] Multiple transistors RTbl, acting as a sixth transistor, are each connected between multiple read bit lines RBL and read global bit lines RGBL. One electrode of each of the multiple transistors RTbl is connected to multiple read bit lines RBL. The other electrodes of the multiple transistors RTbl arranged in the Y direction are commonly connected to one read global bit line RGBL. The gates of the multiple transistors RTbl arranged in the X direction are commonly connected to the read selection line RSEL. The multiple read selection lines RSEL each extend in the X direction and are arranged in the Y direction.

[0032] During a read operation, one of several read selection lines RSEL is selectively driven. Multiple transistors RTbl connected to the selected read selection line RSEL are turned on, electrically connecting the corresponding read bit line RBL and the read global bit line RGBL. As a result, the multiple transistors RTbl connected to the selected read selection line RSEL transmit data from the memory cell MC from the corresponding read bit line RBL to the read global bit line RGBL.

[0033] Multiple memory cells (MCs) are provided corresponding to the intersections of pairs of write word lines (WWL) and read word lines (RWL) adjacent to each other in the Y direction, and pairs of write bit lines (WBL) and read bit lines (RBL) adjacent to each other in the X direction. Therefore, in this embodiment, data can be written to one memory cell (MC) by selecting one write word line (WWL) and one write bit line (WBL) during writing. Similarly, during reading, data can be read from one memory cell (MC) by selecting one read word line (RWL) and one read bit line (RBL).

[0034] A layer containing multiple write word lines WWL, multiple read word lines RWL, and multiple memory cells MC, each corresponding to a single drive line WDRV, constitutes one set. In this case, one write main word line WMWL is commonly connected to the gates of multiple transistors WT1 corresponding to multiple sets. Similarly, one read main word line RMWL is commonly connected to the gates of multiple transistors RT1 corresponding to multiple sets. Furthermore, one unselected main word line bWMWL is commonly connected to the gates of multiple transistors WT2 corresponding to multiple sets. One write main word line WMWL is commonly provided across multiple write word lines WWL corresponding to multiple sets. One read main word line RMWL is commonly provided across multiple read word lines RWL corresponding to multiple sets.

[0035] One end of the write word line WWL is connected to the drive line WDRV via transistor WT1, and the other end is connected to the non-write voltage line VUW via transistor WT2. On the other hand, one end of the read word line RWL is connected to the drive line WDRV via transistor RT1, but the other end is not connected to a transistor or drive line.

[0036] Figure 3 is a conceptual diagram showing the read operation of the gain cell memory according to the first embodiment. Figure 3 shows an extracted configuration related to one read global bit line RGBL involved in the read operation. In reality, multiple read global bit lines RGBL arranged in the X direction simultaneously transmit data from their respective memory cells MC. The read operation will be described below with reference to Figures 2 and 3.

[0037] During the read operation, the read main word line RMWL is activated, and multiple transistors RT1 that share the read main word line RMWL are turned on. In Figures 2 and 3, all transistors RT1 are turned on, and the drive line WDRV <0> ~WDRV <3> Each is connected to multiple read word lines (RWLs) of the corresponding set (layer).

[0038] The controller CTL selects one drive line WDRV (e.g., WDLV) from multiple drive lines WDRV. <0> ) is selectively driven. This allows the selected drive line WDRV to be driven. <0> A corresponding set (for example, the bottom layer in Figure 2) is selected. That is, the drive line WDRV <0> A high-level voltage for reading is applied to the multiple read word lines RWLsel located at the lowest layer connected to the above. As a result, the data from the multiple memory cells MC connected to the multiple read word lines RWLsel at the lowest layer in Figure 2 is transmitted to the multiple read bit lines RBL corresponding to each of them.

[0039] Furthermore, the controller CTL selects one of the multiple read selection lines RSEL shown in Figure 2 and turns on the multiple transistors RTbl connected to that selected read selection line RSEL. This connects the multiple read bit lines RBL corresponding to the selected read selection line RSEL to the corresponding read global bit lines RGBL. As a result, data from multiple rows of selection memory cells MCsel is transmitted via the multiple read global bit lines RGBL corresponding to each row and detected by multiple sense amplifiers SA.

[0040] Figure 3 shows a selected read bit line RBLsel and its corresponding read global bit line RGBL. Therefore, in Figure 3, one read bit line RBLsel selected from multiple read bit lines RBL is connected to one read global bit line RGBL. As a result, data from the selected memory cell MCsel is transmitted via the read global bit line RGBL and detected by the sense amplifier SA.

[0041] On the other hand, in Figure 3, the unselected read bit lines RBL, other than the read bit line RBLsel, transmit data from the memory cell MC, but the corresponding transistor RTbl is in the off state. Therefore, data transmitted to the unselected read bit lines RBL other than RBLsel is not transmitted to the read global bit line RGBL, and no data collision occurs. Furthermore, the gain cell memory allows for non-destructive data readout. Therefore, it is not a problem even if data from the memory cell MC is transmitted to the unselected read bit lines RBL.

[0042] Figure 4 is a timing diagram showing an example of the operation of the gain cell memory according to the first embodiment. Figure 4 shows the write operation. In the write operation, the controller CTL first reads the data to the sense amplifier SA, updates the data in the sense amplifier SA, and then writes the updated data back to the memory cell MC. Note that the drive line WDRV is used here. <0> Assume that it is selectively driven.

[0043] For example, when the controller CTL receives the active command ACT as the command CMD at t0, it activates the read main word line RMWL. Therefore, the selected drive line (e.g., WDRV) is activated. <0> The selected drive line is connected to the read word line RWL of the corresponding set (e.g., the lowest layer), and the data of the memory cell MC corresponding to this selected drive line is read to the read bit line RBL. At this time, all read bit lines RBL included in the selected set transmit the data of the memory cell MC up to the transistor RTbl.

[0044] Furthermore, at t0, the read selection line RSEL <0> This starts the controller CTL, which then uses the same read selection line RSEL. <0> Multiple transistors RTbl connected to (arranged in the X direction (row direction) in Figure 2) are driven at the same timing. Readout selection line RSEL <0> Multiple read bit lines RBL in each connected column transmit data to the read global bit line RGBL.

[0045] Next, the data is updated in the SenseAmp SA.

[0046] Subsequently, at t1, when the controller CTL receives the write command WRT, the write selection line WSEL <0> This starts up the controller CTL, and the write selection line WSEL. <0> Data is transmitted to multiple write bit lines WBL connected to the selected set, and the data is written to the memory cell MC in the selected set. As a result, the data is read on the read selection line RSEL in the selected set (e.g., the lowest layer). <0> and write selection line WSEL <0> It is written to the same memory cell MC that shares it.

[0047] In t2, when the controller CTL receives the precharge command PRE, it precharges the read bit line RBL, write bit line WBL, etc.

[0048] Similarly, in t3-t5, the controller CTL keeps the read main word line RMWL running while the read selection line RSEL remains open. <1> Start it up, and then write selection line WSEL <1> This starts the controller CTL reads the selection line RSEL in the selected set. <1> and write selection line WSEL <1> Data is read from a shared memory cell (MC), and then written to the same memory cell (MC).

[0049] Similarly, in t6-t8, the controller CTL keeps the read main word line RMWL running while the read selection line RSEL remains open. <2> Start it up, and then write selection line WSEL <2> This starts the controller CTL reads the selection line RSEL in the selected set. <2> and write selection line WSEL <2> Data is read from a shared memory cell (MC), and then written to the same memory cell (MC).

[0050] In general, the controller CTL keeps the read main word line RMWL running while the read selection line RSEL is running. (i is a non-negative integer) is raised, and then the write selection line WSEL is used. This starts the controller CTL read selection line RSEL in the selected set. and write selection line WSEL Data is read from a shared memory cell (MC), and then written to the same memory cell (MC).

[0051] Thus, the controller CTL keeps the read main word line RMWL running while the read selection line RSEL is running. and write selection line WSEL These can be started sequentially. This eliminates the need to start the read main word line RMWL each time the read selection line RSEL and write selection line WSEL are started, potentially reducing the time required to start the read main word line RMWL. Note that the read selection line RSEL and write selection line WSEL The order in which you start them is not limited to the example above; other orders are also acceptable.

[0052] In read operations, the write operations shown in Figure 4 (e.g., t1-t2, t4-t5, t7-t8) are omitted, but the other operations are the same as those shown in Figure 4. Therefore, even in read operations, it is not necessary to raise the read main word line RMWL each time the read selection line RSEL is raised, and the time required to raise the read main word line RMWL can be reduced.

[0053] Thus, in this embodiment, the controller CTL has one drive line (for example, WDRV). <0> By selectively driving the transistors, one set (for example, the bottom layer in Figure 2) is selected. At this time, multiple read bit lines RBL each transmit data from multiple memory cells MC within this selected set. Furthermore, the controller CTL selects one read selection line RSEL and turns on multiple transistors RTbl corresponding to one read word line RWL within the selected set. This transmits data from multiple read bit lines RBL corresponding to one read word line RWL within the selected set to their respective read global bit lines RGBL. Therefore, even if the other end of the read word line RWL is not connected to a transistor or drive line, multiple read global bit lines RGBL can transmit data from the selected memory cells MC.

[0054] Furthermore, according to this embodiment, the drive line WDRV is shared by the write word line WWL and the read word line RWL. In addition, multiple read main word lines RMWL are shared. Moreover, no non-read word lines or transistors are provided at the other end of the read word line RWL. This makes non-destructive reading possible while simplifying the wiring. With the simplification of wiring, the number of drivers that drive the voltage of the wiring is also reduced, and power consumption can be reduced as well.

[0055] In this embodiment, since multiple read main word lines (RMWL) are shared, the selection of a read word line (RWL) is performed by selecting the read bit line (RBL) connected to the read global bit line (RGBL). In this case, when there are many row addresses issued that select multiple adjacent read word lines (RWL), it is sufficient to select only the read bit line (RBL) without driving multiple adjacent read word lines (RWL). This reduces the proximity effect of read word lines (RWL).

[0056] (Second Embodiment) Figure 5 is a perspective view showing an example configuration of a gain cell memory according to the second embodiment. According to the second embodiment, the read global bit line RGBL is commonly connected to a plurality of corresponding read bit lines RBL. No transistor RTbl is provided between the plurality of read bit lines RBL and the read global bit line RGBL.

[0057] On the other hand, multiple transistors RT2, acting as the eighth transistor, are connected between multiple read word lines RWL and non-write voltage lines VUW. That is, the other ends of each of the multiple read word lines RWL are connected to the non-write voltage lines VUW via the multiple transistors RT2. One electrode of each of the multiple transistors RT2 is connected to each of the multiple read word lines RWL. The other electrode of each of the multiple transistors RT2 is connected to the reference voltage line VUW. In the second embodiment, VUW is also used as a reference voltage source for the read operation, and is therefore called the reference voltage line. The gates of the multiple transistors RT2 are connected to the read main word line bRMWL. One and the other electrode of each transistor RT2 can function as a source electrode or a drain electrode depending on the voltage supplied to the transistor RT2.

[0058] The read main word line bRMWL is commonly connected to the gates of multiple transistors RT2 arranged in the Z direction. Each of the multiple read main word lines bRMWL extends in the Z direction and is arranged in the Y direction. The multiple read main word lines bRMWL turn on the corresponding multiple transistors RT2 and connect the reference voltage line VUW to the multiple read word lines RWL arranged in the Z direction. The controller CTL can drive each of the multiple read main word lines bRMWL independently according to their addresses.

[0059] Furthermore, in the second embodiment, the multiple read main word lines RMWL arranged in the Y direction are not short-circuited and are electrically isolated. The controller CTL can drive each of the multiple read main word lines RMWL independently according to their addresses. The controller CTL selectively drives pairs of read main word lines RMWL and bRMWL on either side of the multiple read word lines RWL of the selected row. However, the read main word lines RMWL and bRMWL transmit control signals with opposing logic. Therefore, when one of transistors RT1 and RT2 is ON, the other is OFF. As a result, the read word line RWL selected during reading is connected to the drive line WDRV, and the unselected read word line RWL is connected to the reference voltage line VUW.

[0060] Other configurations of the second embodiment may be the same as those of the first embodiment.

[0061] Figure 6 is a conceptual diagram showing the read operation of the gain cell memory according to the second embodiment. Figure 6 shows an extracted configuration related to one read global bit line RGBL involved in the read operation. In reality, multiple read global bit lines RGBL arranged in the X direction simultaneously transmit data from their respective memory cells MC. The read operation will be described below with reference to Figures 5 and 6.

[0062] During a read operation, the read main word line RMWL is raised, and multiple transistors RT1 that share the read main word line RMWL are turned on. In the second embodiment, although the read main word line RMWL is commonly connected to the gates of multiple transistors RT1 arranged in the Z direction, the multiple read main word lines RMWL arranged in the Y direction are electrically isolated from each other. Similarly, although the read main word line bRMWL is commonly connected to the gates of multiple transistors RT2 arranged in the Z direction, the multiple read main word lines bRMWL arranged in the Y direction are electrically isolated from each other. Therefore, the controller CTL can selectively drive one pair of the multiple read main word line RMWL and bRMWL pairs extending in the Z direction. The read main word line RMWL and bRMWL pairs are provided on both sides of the multiple read word lines RWL arranged in the Z direction and share these multiple read word lines RWL.

[0063] The controller CTL selects one drive line WDRV (e.g., WDLV) from multiple drive lines WDRV. <0> ) is selectively driven. This allows the selected drive line WDRV to be driven. <0> A corresponding set (for example, the bottom layer in Figure 5) is selected. That is, drive line WDRV <0> A high-level voltage for reading is applied to multiple transistors RT1 located at the lowest layer connected to it.

[0064] Furthermore, as shown in Figure 6, the controller CTL reads, for example, the main word line RMWL. <0> bRMWL <0> It selectively drives the pair, namely the read main word line RMWL. <0> This is activated, turning on the corresponding transistor RT1. Read main word line bRMWL <0> This is turned down, turning off the corresponding transistor RT2. This results in the read main word line RMWL. <0> bRMWL <0> Multiple read word lines RWL between pairs are drive lines WDRV <0> ~WDRV <3> Selectively connected to the selected drive line WDRV. <0> It transmits a high-level voltage for reading, and other non-selective drive lines WDRV <1> ~WDRV <3> This transmits a low-level voltage for non-readout. Therefore, the read main word line RMWL <0> bRMWL <0> Of the multiple read word lines RWL between the pair, the drive line WDRV <0> A selective read word line RWLsel connected to the column transmits a high-level voltage for reading. Data from the selective memory cell MCsel connected to this selective read word line RWLsel is transmitted to the read global bit line RGBL via the read bit line RBL. The read operation is performed similarly for the other columns, and the data transmitted to the read global bit line RGBL for each column is detected by the corresponding sense amplifier SA.

[0065] On the other hand, the controller CTL reads the main word line RMWL, for example. <1> ~RMWL <3> Lower the power and read the main word line bRMWL <1> ~bRMWL <3> This starts the read main word line RMWL. <1> ~RMWL <3> bRMWL <1> ~bRMWL <3> The multiple read word lines RWL located between them are connected to the reference voltage line VUW and are in a deselected state.

[0066] Thus, in the second embodiment, the controller CTL controls one drive line WDRV <0> By selectively driving, one set (e.g., the bottom layer in Figure 5) is selected. Furthermore, the controller CTL reads one main word line RMWL. <0> bRMWL <0> Select the pair. This will result in one read main word line RMWL. <0> bRMWL <0> Multiple transistors RT1 and RT2 connected to the drive line WDRV are turned ON. <0> ~WDRV <3> Read the main word line RMWL <0> bRMWL <0> Connects to the corresponding read word line RWL. As a result, the read main word line RMWL <0> bRMWL <0> Of the multiple read word lines RWL corresponding to the pair, the drive line WDRV <0> One (lowest layer) read word line RWL can be selectively driven. Multiple read bit lines RBL corresponding to this selected (lowest layer) read word line RWL transmit data from the memory cell MC to multiple read global bit lines RGBL, each corresponding to the other.

[0067] According to the second embodiment, the controller CTL independently drives a plurality of read main word lines RMWL arranged in the Y direction. Furthermore, by providing a read main word line bRMWL and transistor RT2, a non-read voltage can be applied to the read word line RWL corresponding to the unselected pair of read main word lines RMWL, bRMWL, based on the selection of the read main word line bRMWL. This eliminates the need for transistors between a plurality of read bit lines RBL and a read global bit line RGBL. In addition, a plurality of read bit lines RBL arranged in the Y direction can be connected in common to a single read global bit line RGBL.

[0068] Furthermore, according to the second embodiment, the drive line WDRV is shared with the write word line WWL and the read word line RWL. Therefore, as with the first embodiment, power consumption can be reduced while simplifying the wiring.

[0069] (Third embodiment) Figure 7 is a perspective view showing an example of the configuration of a gain cell memory according to the third embodiment. In the first and second embodiments, the drive line WDRV is common to both the read-related configuration, such as the read word line RWL, and the write-related configuration, such as the write word line WWL.

[0070] In contrast, in the third embodiment, the main word line MWL is shared between configurations related to reading, such as the read word line RWL, and configurations related to writing, such as the write word line WWL. The drive lines are divided into a read drive line RWDRV and a write drive line WWDRV. Accordingly, the reference voltage line VUW may also be divided into configurations related to reading and configurations related to writing. If the reference voltage line VUW is constant, there is no particular need to divide it.

[0071] The main word line MWL extends in the Z direction and is arranged in the Y direction. The main word line MWL is shared by multiple write word lines WWL and multiple read word lines RWL located in multiple sets (layers) arranged in the Z direction. Therefore, the main word line MWL is commonly connected to the gates of multiple transistors WT1 and RT1 located in multiple sets (layers) arranged in the Z direction.

[0072] The main word line bMWL extends in the Z direction and is arranged in the Y direction. The main word line bMWL is shared by multiple write word lines WWL and multiple read word lines RWL, which are arranged in the Z direction. Therefore, the main word line bMWL is commonly connected to the gates of multiple transistors WT2 and RT2, which are arranged in the Z direction.

[0073] Therefore, the main word lines MWL and bMWL selectively turn on the corresponding transistors WT1, RT1, WT2, and RT2 during reading and writing.

[0074] On the other hand, the drive lines are divided into read drive lines RWDRV and write drive lines WWDRV. Therefore, during reading, one of the multiple read drive lines RWDRV is selectively driven, and during writing, one of the multiple write drive lines WWDRV is selectively driven.

[0075] This allows the controller CTL to selectively drive one read word line RWL or one write word line WWL from among the multiple read word lines RWL and multiple write word lines WWL connected to the selected main word line MWL, bMWL. In a read operation, if any of the read drive lines RWDRV are selectively driven, one read word line RWL may be selectively driven. In a write operation, if any of the write drive lines WWDRV are selectively driven, one write word line WWL may be selectively driven.

[0076] The bit line configuration and memory cell MC arrangement are not shown in Figure 7, but they can be the same as those shown in Figure 5. Transistors between multiple read bit lines RBL and read global bit lines RGBL can be omitted. Also, multiple read bit lines RBL arranged in the Y direction can be connected to a single read global bit line RGBL in common. On the other hand, transistors between multiple write bit lines WBL and write global bit line WGBL can be omitted. Also, multiple write bit lines WBL arranged in the Y direction can be connected to a single write global bit line WGBL in common. As a result, data from memory cell MCs of multiple columns connected to the selected read word line RWL is transmitted to the read global bit line RGBL of the corresponding column. Alternatively, data from the write global bit line WGBL is transmitted to the memory cell MC of each column connected to the selected write word line WWL.

[0077] Furthermore, in the third embodiment, while the main word line MWL is common to both the read-related configuration and the write-related configuration, the transistor RT2 connected to the read word line RWL and the reference voltage line VUW can be omitted, similar to the first embodiment. In this case, the bit line configuration can be the same as the bit line configuration shown in Figure 2. That is, transistors are provided between multiple read bit lines RBL and read global bit lines RGBL. Also, transistors are provided between multiple write bit lines WBL and write global bit line WGBL.

[0078] According to the third embodiment, the main word line (MWL) is common to both the read-related configuration and the write-related configuration. This simplifies the wiring while maintaining normal operation.

[0079] (Fourth Embodiment) Figure 8 is a perspective view showing an example configuration of a gain cell memory according to the fourth embodiment. In the fourth embodiment, multiple read main word lines RMWL, bRMWL and multiple write main word lines WMWL, bWMWL extend in the Y direction and are arranged in the Z direction. The read main word line RMWL is commonly connected to the gates of multiple transistors RT1 arranged in the Y direction. The write main word line WMWL is commonly connected to the gates of multiple transistors WT1 arranged in the Y direction. The controller CTL selects one set (layer) by selectively driving the read main word lines RMWL, bRMWL or the write main word lines WMWL, bWMWL.

[0080] On the other hand, multiple drive lines WDRV extend in the Z direction and are arranged in the Y direction. Drive lines WDRV are provided in common with multiple write word lines WWL and multiple read word lines RWL, which are arranged in the Z direction. Accordingly, reference voltage lines VUW also extend in the Z direction and are arranged in the Y direction. Reference voltage lines VUW are provided in common with multiple write word lines WWL or multiple read word lines RWL, which are arranged in the Z direction. Reference voltage lines VUW may be divided into configurations related to reading and configurations related to writing. Reference voltage lines VUW do not need to be divided if they are constant.

[0081] In the fourth embodiment, the relationship between the extension directions of the main word lines RMWL, bRMWL, WMWL, bWMWL and the drive line WDRV and the reference voltage line VUW is the opposite of the relationship between their extension directions in the second embodiment.

[0082] Therefore, in a read operation, the controller CTL selects one read main word line RMWL from multiple read main word lines RMWL (for example, RMWL <0> ) selectively drives the selected read main word line RMWL. <0> A corresponding set (for example, the bottom layer in Figure 8) is selected. That is, the read main word line RMWL <0> Multiple transistors RT1 at the bottom layer connected to the drive line WDRV turn on, <0> ~WDRV <3> It is connected to multiple read word lines RWL at the lowest layer. In this case, for example, the drive line WDRV <0> When transmitting a high-level voltage for reading, among the multiple read word lines RWL at the lowest layer, the drive line WDRV <0> A high-level voltage for reading is selectively applied to one read word line RWL connected to it.

[0083] The bit line configuration and memory cell MC arrangement are omitted in Figure 8, but they can be the same as those shown in Figure 5. Transistors between multiple read bit lines RBL and read global bit lines RGBL can be omitted. Also, multiple read bit lines RBL arranged in the Y direction can be connected in common to a single read global bit line RGBL. As a result, data from memory cell MCs in multiple columns connected to the selected read word line RWL is transmitted to the read global bit line RGBL of the corresponding column.

[0084] In write operations, the write word line WWL, write bit line WBL, and selected memory cell MC are selected in the same way as in read operations. Therefore, transistors between multiple write bit lines WBL and write global bit line WGBL can be omitted. In addition, multiple write bit lines WBL arranged in the Y direction can be connected to a single write global bit line WGBL. As a result, data from the write global bit line WGBL is transmitted to the memory cell MC of each column connected to the selected write word line WWL.

[0085] The other configurations of the fourth embodiment may be the same as those of the second embodiment.

[0086] Furthermore, in the fourth embodiment, while the drive line WDRV is common to multiple write word lines WWL and multiple read word lines RWL, the transistor RT2 connected to the read word line RWL and the reference voltage line VUW can be omitted, similar to the first embodiment. That is, the multiple read word lines RWL may be separated from the reference voltage line VUW. In this case, the bit line configuration can be the same as the bit line configuration shown in Figure 2. That is, a transistor is provided between the multiple read bit lines RBL and the read global bit line RGBL. Also, a transistor is provided between the multiple write bit lines WBL and the write global bit line WGBL.

[0087] According to the fourth embodiment, the main word line is divided into a read main word line RMWL and a write main word line MWL. On the other hand, the drive line WDRV is common to both the configuration related to reading and the configuration related to writing. This makes it possible to simplify wiring while maintaining normal operation.

[0088] (Fifth embodiment) Figure 9 is a perspective view showing an example of the configuration of a gain cell memory according to the fifth embodiment. In the fifth embodiment, the main word line MWL is common to configurations related to reading, such as the read word line RWL, and configurations related to writing, such as the write word line WWL. The drive lines are divided into a read drive line RWDRV and a write drive line WWDRV. Accordingly, the reference voltage line VUW may also be divided into configurations related to reading and configurations related to writing. If the reference voltage line VUW is constant, there is no particular need to divide it.

[0089] The main word line MWL extends in the Y direction and is arranged in the Z direction. The main word line MWL is shared by multiple write word lines WWL and multiple read word lines RWL, which are arranged in the Y direction. Therefore, the main word line MWL is commonly connected to the gates of multiple transistors WT1 and RT1, which are arranged in the Y direction.

[0090] The main word line bMWL extends in the Y direction and is arranged in the Z direction. The main word line bMWL is shared by multiple write word lines WWL and multiple read word lines RWL, which are arranged in the Y direction. Therefore, the main word line bMWL is commonly connected to the gates of multiple transistors WT2 and RT2, which are arranged in the Y direction.

[0091] Therefore, the main word lines MWL and bMWL selectively turn on the corresponding transistors WT1, RT1, WT2, and RT2 during reading and writing.

[0092] On the other hand, the drive lines are divided into read drive lines RWDRV and write drive lines WWDRV. Therefore, during reading, one of the multiple read drive lines RWDRV is selectively driven, and during writing, one of the multiple write drive lines WWDRV is selectively driven. The read drive lines RWDRV are shared by multiple read word lines RWL arranged in the Z direction. The write drive lines WWDRV are shared by multiple write word lines WWL arranged in the Z direction.

[0093] This allows the controller CTL to selectively drive one read word line RWL or one write word line WWL from among the multiple read word lines RWL and multiple write word lines WWL connected to the selected main word line MWL, bMWL. In a read operation, if any of the read drive lines RWDRV are selectively driven, one read word line RWL may be selectively driven. In a write operation, if any of the write drive lines WWDRV are selectively driven, one write word line WWL may be selectively driven.

[0094] The bit line configuration and memory cell MC arrangement are not shown in Figure 9, but they can be the same as those shown in Figure 5. Transistors between multiple read bit lines RBL and read global bit lines RGBL can be omitted. Also, multiple read bit lines RBL arranged in the Y direction can be connected to a single read global bit line RGBL in common. On the other hand, transistors between multiple write bit lines WBL and write global bit line WGBL can be omitted. Also, multiple write bit lines WBL arranged in the Y direction can be connected to a single write global bit line WGBL in common. As a result, data from memory cell MCs of multiple columns connected to the selected read word line RWL is transmitted to the read global bit line RGBL of the corresponding column. Alternatively, data from the write global bit line WGBL is transmitted to the memory cell MC of each column connected to the selected write word line WWL.

[0095] In addition, in the fifth embodiment, the read drive line RWDRV is shared by multiple read word lines RWL, and the write drive line WWDRV is shared by multiple write word lines WWL, while the transistor RT2 and reference voltage line VUW connected to the read word line RWL can be omitted, similar to the first embodiment. That is, the multiple read word lines RWL may be separated from the reference voltage line VUW. In this case, the bit line configuration can be the same as the bit line configuration shown in Figure 2. That is, a transistor is provided between the multiple read bit lines RBL and the read global bit line RGBL. Also, a transistor is provided between the multiple write bit lines WBL and the write global bit line WGBL.

[0096] The other components of the fifth embodiment may be the same as those of the fourth embodiment. Therefore, the fifth embodiment can obtain the same effects as the fourth embodiment.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0098] Memory Cell MC MW1, MR1, MR2 transistors WWL writing word line RWL Read Word Line WDRV drive line VUW Non-Writable Voltage Lines WT1, RT1, WT2, WTbl, RTbl transistors WMWL write main word line RMWL Read Main Word Line bWMWL Unselected Main Word Line WBL write bit line RBL Read Bit Line WGBL Write Global Bit Line RGBL Read Global Bit Line WSEL Write Selection Line RSEL Read Selection Line

Claims

1. Multiple first data lines and multiple first control lines used for writing data, Multiple second data lines and multiple second control lines used for reading data, A plurality of memory cells including a first transistor whose gate is connected to one of the plurality of first control lines and one end is connected to one of the plurality of first data lines, a second transistor whose gate is connected to one of the plurality of second control lines and one end is connected to one of the plurality of second data lines, and a third transistor whose gate is connected to the other end of the first transistor and holds data from the first data lines, and one end is connected to the other end of the second transistor and enters a conductive state according to the data, A first drive line is provided in common to the plurality of first control lines and the plurality of second control lines, and transmits a selection voltage for writing data. A plurality of fourth transistors connected between the plurality of first control lines and the first drive line, A plurality of fifth transistors connected between the plurality of second control lines and the first drive line, Multiple third control lines connected to the gates of the multiple fourth transistors, Multiple fourth control lines connected to the gates of the multiple fifth transistors, A semiconductor memory device equipped with the following features.

2. The plurality of first control lines, the plurality of second control lines, and the plurality of memory cells corresponding to one of the first drive lines are considered as a single set, One of the third control lines is connected in common to the gates of the multiple fourth transistors corresponding to the multiple sets, The semiconductor memory device according to claim 1, wherein one of the fourth control lines is commonly connected to the gates of a plurality of fifth transistors corresponding to a plurality of sets.

3. One of the third control lines is provided in common with a plurality of first control lines corresponding to a plurality of sets. The semiconductor memory device according to claim 2, wherein one of the fourth control lines is provided in common with a plurality of second control lines corresponding to a plurality of sets.

4. The plurality of third control lines and the plurality of fourth control lines extend in the first direction in which the plurality of first and second data lines extend. The semiconductor memory device according to claim 1, wherein the first drive line extends in a second direction in which the plurality of first and second control lines extend and in a third direction intersecting the first direction.

5. A fourth data line is provided in common to correspond to the plurality of second data lines, The semiconductor memory device according to claim 2, further comprising a plurality of sixth transistors connected between the plurality of second data lines and the fourth data line.

6. A second drive line is provided in common to the plurality of first control lines and transmits a non-selective voltage that does not write data, The system further comprises a plurality of seventh transistors connected between the plurality of first control lines and the second drive line, The semiconductor memory device according to claim 5, wherein the plurality of second control lines are separated from the second drive lines.

7. Each of the multiple third control lines is driven independently. The semiconductor memory device according to claim 2, wherein the plurality of the fourth control lines are driven in common.

8. One of the multiple first drive lines selects a set from the multiple sets, The plurality of second data lines each transmit data from the memory cells in the selection set. The semiconductor memory device according to claim 6, wherein a plurality of sixth transistors corresponding to one of the second control lines in the selection set transmit data from the second data line to a plurality of fourth data lines, each corresponding to a plurality of fourth data lines.

9. The system further comprises a fourth data line that is commonly connected to the plurality of second data lines, The semiconductor memory device according to claim 2, wherein no transistors are provided between the plurality of second data lines and the fourth data line.

10. A second drive line is provided in common to the plurality of first control lines and the plurality of second control lines, and transmits a non-selective voltage that does not write data, A plurality of seventh transistors connected between the plurality of first control lines and the second drive line, The semiconductor memory device according to claim 9, further comprising a plurality of eighth transistors connected between the plurality of second control lines and the second drive line.

11. One of the multiple first drive lines selects a set from the multiple sets, The fifth transistor corresponding to one of the second control lines in the selection set connects the first drive line to the second control line, The semiconductor memory device according to claim 10, wherein a plurality of second data lines corresponding to one of the second control lines in the selection set transmit data from the memory cell to a plurality of fourth data lines corresponding to each of them.

12. The plurality of third control lines and the plurality of fourth control lines extend in a third direction that intersects with the first direction in which the plurality of first and second data lines extend and the second direction in which the plurality of first and second control lines extend. The semiconductor memory device according to claim 1, wherein the first drive line extends in the first direction.

13. Multiple first data lines and multiple first control lines used for writing data, Multiple second data lines and multiple second control lines used for reading data, A plurality of memory cells including a first transistor whose gate is connected to one of the plurality of first control lines and one end is connected to one of the plurality of first data lines, a second transistor whose gate is connected to one of the plurality of second control lines and one end is connected to one of the plurality of second data lines, and a third transistor whose gate is connected to the other end of the first transistor and holds data from the first data lines, and one end is connected to the other end of the second transistor and enters a conductive state according to the data, A third control line provided in common to the plurality of first control lines and the plurality of second control lines, A plurality of first drive lines provided corresponding to each of the plurality of first control lines, A plurality of second drive lines provided corresponding to each of the plurality of second control lines, A plurality of fourth transistors are connected between the plurality of first drive lines and the plurality of first control lines, and their gates are commonly connected to the third control line, A plurality of fifth transistors are connected between the plurality of second drive lines and the plurality of second control lines, and their gates are commonly connected to the third control line, A semiconductor memory device equipped with the following features.

14. The plurality of first control lines, the plurality of second control lines, and the plurality of memory cells corresponding to one of the first drive lines are considered as a single set, The semiconductor memory device according to claim 13, wherein one of the third control lines is commonly connected to the gates of a plurality of the fourth transistors and the gates of a plurality of the fifth transistors corresponding to a plurality of the sets.

15. The semiconductor memory device according to claim 14, wherein one of the third control lines is provided in common with a plurality of first control lines and a plurality of second control lines corresponding to a plurality of sets.

16. The third control line extends in a third direction that intersects with the first direction in which the plurality of first and second data lines extend and the second direction in which the plurality of first and second control lines extend. The semiconductor memory device according to claim 13, wherein the plurality of first drive lines and the plurality of second drive lines extend in the first direction.

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