Indication device

Abstract

The objective is to provide a display device that enhances the visual appearance of images by making the display area and the area outside the display area translucent, thereby blurring the boundary between the display area and the area outside the display area. [Solution] The display device includes a display panel having a liquid crystal layer between a pair of substrates, and a light source that causes light to enter the liquid crystal layer from one side of the display panel. The display panel includes a display area in which a plurality of pixels are arranged, a non-display area adjacent to the display area in which a plurality of dummy pixels are arranged, a peripheral area arranged along the periphery other than one side of the display panel and surrounding the non-display area, a drive circuit arranged in the peripheral area, a plurality of first wirings connected to the drive circuit and extending in a first direction, and a plurality of second wirings extending in a second direction intersecting the first direction.

Description

[Technical Field]

[0001] This invention relates to a display device. [Background technology]

[0002] Liquid crystal display devices include transmissive displays that display images by transmitting light from a backlight located behind the liquid crystal panel, reflective displays that display images by reflecting ambient light with pixel electrodes, and semi-transmissive displays that combine the features of both transmissive and reflective displays. These liquid crystal display devices are used as displays in electronic devices such as personal computers and smartphones, and have a configuration that prevents the background from being seen through the screen.

[0003] In response to this, display devices have been developed that allow images to be displayed while the background is visible through them. For example, a display device has been disclosed in which the display area is formed by polymer-dispersed liquid crystals placed between a pair of translucent substrates, allowing the background to be seen through (see Patent Documents 1 and 2). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-092748 [Patent Document 2] Japanese Patent Publication No. 2021-092702 [Overview of the project] [Problems that the invention aims to solve]

[0005] While display devices that allow visibility through the background are typically rectangular to match the shape of the display area, various shapes such as semicircles can be adopted instead of conforming to the shape of the display area, enhancing the design.

[0006] However, if a display device adopts a highly aesthetically pleasing shape rather than conforming to the shape of the display area, the transparency of the display area and the area outside the display area will differ. This results in a problem where the boundary between the display area and the area outside the display area is emphasized, making the display device look bad when displaying images.

[0007] One of the objectives of the present invention is to provide a display device that makes the display area and the area outside the display area transparent, blurring the boundary between the display area and the area outside the display area, and thus providing a visually appealing display device for images. [Means for solving the problem]

[0008] A display device according to one embodiment of the present invention comprises a display panel having a liquid crystal layer between a pair of substrates, and a light source that causes light to be incident on the liquid crystal layer from one side of the display panel. The display panel includes a display area in which a plurality of pixels are arranged, a non-display area adjacent to the display area in which a plurality of dummy pixels are arranged, a peripheral area arranged along the periphery other than one side of the display panel and surrounding the non-display area, a drive circuit arranged in the peripheral area, a plurality of first wirings connected to the drive circuit and extending in a first direction, and a plurality of second wirings extending in a second direction intersecting the first direction. The plurality of pixels and the plurality of dummy pixels are the same size and arranged at the same intervals, the display area and the non-display area are light-transmitting, and the image displayed in the display area is visible from the side of the first surface of the display panel and from the side of the second surface opposite to the first surface. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view illustrating the overview of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing the structure corresponding to the area between A1 and A2 of the display device shown in Figure 1. [Figure 3] This is a plan view of a display device according to one embodiment of the present invention. [Figure 4] This is a block diagram illustrating the configuration of a display device according to one embodiment of the present invention. [Figure 5]It is a plan view of a pixel and a dummy pixel in a display device according to an embodiment of the present invention. [Figure 6] It is a plan view of a pixel in a display device according to an embodiment of the present invention. [Figure 7] It is a cross-sectional view of a pixel in a display device according to an embodiment of the present invention. [Figure 8] It is a plan view of a dummy pixel in a display device according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view of a dummy pixel in a display device according to an embodiment of the present invention. [Figure 10] It is a plan view of a display device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments exemplified below. Also, regarding the drawings, in order to make the explanation clearer, the width, thickness, shape, etc. of each part may be schematically represented compared to the actual mode, but these schematic diagrams are just examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, the same or similar elements as those described with respect to the already shown drawings may be given the same reference numerals, and duplicate explanations may be omitted. Note that in this specification and the like, ordinal numbers are for convenience in distinguishing parts, components, etc., and do not indicate priority order or sequence.

[0011] In the present invention, when a single film is processed to form a plurality of films, these plurality of films may have different functions and roles. However, these plurality of films are derived from the films formed as the same layer in the same process and have the same layer structure and the same material. Therefore, these plurality of films are defined as being present in the same layer. Also, when a single film is processed to form a plurality of films, in this specification and the like, they may be described separately with -1, -2, etc.

[0012] In this specification and the like, expressions such as "up" and "down" represent the relative positional relationship between the structure of interest and other structures. In this specification and the like, in a side view, the direction from the array substrate described later toward the pixel electrode is defined as "up", and the opposite direction is defined as "down". In this specification and the claims, when expressing the mode of arranging another structure on a certain structure, if simply expressed as "on", unless otherwise specified, it includes both the case of arranging another structure directly above so as to contact the certain structure and the case of arranging another structure above the certain structure via yet another structure.

[0013] (First Embodiment) The display device 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10.

[0014] <Overview of Display Device> FIG. 1 shows a perspective view of a display device 10 according to an embodiment of the present invention. The display device 10 includes a display panel 102 including a pair of array substrates 150 and a counter substrate 152, a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, and a drive circuit (not shown), a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B sandwiching the display panel 102. In the following description referring to FIG. 1, one direction in the plane of the display panel 102 is defined as the D1 direction, the direction orthogonal to the D1 direction is defined as the D2 direction, and the direction orthogonal to the D1-D2 plane is defined as the D3 direction.

[0015] The array substrate 150 and the counter substrate 152 have light transmittance. The array substrate 150 and the counter substrate 152 are preferably transparent to visible light. The counter substrate 152 is arranged in the D3 direction so as to face the array substrate 150. The array substrate 150 and the counter substrate 152 are arranged to face each other with a gap therebetween and are bonded together by a sealing material 154. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the counter substrate 152. ​​The display panel 102 has a display area 12, a non-display area 13 adjacent to the display area 12, and a peripheral area 14 that surrounds the non-display area 13 and is located outside the display area 12. Multiple pixels PIX are arranged in the row direction and column direction in the display area 12. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction, and n pixels are arranged in the column direction. The values ​​of m and n are set appropriately according to the vertical display resolution and the horizontal display resolution. Scan signal lines (also called gate wiring) are arranged in the D1 direction in the display area 12, and video signal lines (also called source wiring) are arranged in the D2 direction.

[0017] The display panel 102 may have a shape different from that of the display area 12. As shown in Figure 1, the display panel 102 may have a continuously curved portion at its outer edge 1020, unlike the rectangular shape of the display area 12. Figure 1 shows an example where the outer edge 1020 of the display panel 102 is semicircular, but the shape is not limited to this.

[0018] A drive circuit is provided in the peripheral region 14 of the array substrate 150. The drive circuit includes a scan signal line drive circuit that outputs a scan signal to the pixel PIX and a video signal line drive circuit that outputs a video signal. Details of the drive circuit will be described later, but Figure 1 shows an embodiment in which the drive circuit is formed in the peripheral region 14 by thin film transistors (TFTs) of the array substrate 150. In the peripheral region 14, the scan signal line drive circuit can be placed at the end of the scan signal line extending in the display area and the non-display area, and the video signal line drive circuit can be placed at the end of the video signal line extending. The drive circuit is not limited to the embodiment shown and may be provided as an integrated circuit (IC) and mounted on the array substrate 150 using the COG (Chip on Glass) method or the COF (Chip on Film) method.

[0019] The peripheral region 14 may include a scanning signal line region, a common wiring region, and a video signal line region. The scanning signal line region is a region where a pattern is provided formed by wiring connecting the scanning line drive circuit 28 and the scanning line GL arranged in the display region 12. The common wiring region is a region where a pattern is provided formed by common wiring. Circuit-wise, the common wiring region is used as wiring that applies a common voltage to the common electrode 218 (see Figure 7) provided on the opposing substrate 152. The video signal line region is a region where a pattern is provided formed by wiring connecting the video signal line drive circuit and the video signal line SL arranged in the display region 12.

[0020] The light source 104 has a structure aligned along the D1 direction. The light source 104 is composed of, for example, light-emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited, and in addition to light-emitting diodes arranged in the D1 direction, optical components such as reflectors, diffusers, and lenses may be included. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate components independent of the display panel 102, and the timing of light emission of the light source 104 may be controlled by the light emission control circuit 110 which is synchronized with the scan line drive circuit and the video signal line drive circuit. The light emission control circuit 110 that controls the light source 104 may be provided as a separate component, similar to the light source 104, separate from the display panel 102, or it may be mounted on the array substrate 150 as an individual component, or it may be incorporated into the scan line drive circuit or the video signal line drive circuit. The light source 104 is arranged and controlled as described above, and light can be incident on the liquid crystal layer 210 from one side surface 15C of the display panel 102. One side of the display panel 102 is the side from which light from the light source 104 is incident.

[0021] The first transparent substrate 151A and the second transparent substrate 151B are formed to match the shape of the display panel 102. The outer edges of the first transparent substrate 151A and the second transparent substrate 151B are formed to match or substantially match the outer edges of the display panel 102, and the shape of the display device 10 corresponds to the shape of the first transparent substrate 151A and the second transparent substrate 151B and the shape of the display panel 102. The first transparent substrate 151A and the second transparent substrate 151B are provided so as to sandwich the display area 12, the non-display area 13, and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. Furthermore, as will be explained with reference to Figure 2, the first transparent substrate 151A and the second transparent substrate 151B function as light guide plates that introduce light incident from the light source 104 into the display panel 102.

[0022] Figure 2 shows the cross-sectional structure of the display device 10 corresponding to the area between A1 and A2 shown in Figure 1. As shown in Figure 2, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the opposing substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of glass or plastic. Preferably, the first transparent substrate 151A and the second transparent substrate 151B have the same refractive index as the array substrate 150 and the opposing substrate 152. The array substrate 150 and the first transparent substrate 151A, and the opposing substrate 152 and the second transparent substrate 151B are bonded together with a transparent adhesive (not shown).

[0023] The display panel 102 is arranged with an array substrate 150 and a counter substrate 152 facing each other, with a liquid crystal layer 210 provided between them. The array substrate 150 is larger than the counter substrate 152, and is sized such that a portion of the peripheral region 14 is exposed from the counter substrate 152. A drive circuit (light emission control circuit 110 in Figure 2) is mounted on the array substrate 150. A flexible printed circuit 34 is also attached to the periphery of the array substrate 150.

[0024] The light source 104 is positioned adjacent to one side of either the first transparent substrate 151A or the second transparent substrate 151B. Figure 2 shows a configuration in which the light source 104 is positioned along one side of the second transparent substrate 151B. Figure 2 also shows a configuration in which the light source 104 is mounted on the array substrate 150, but there are no limitations on the configuration in which the light source 104 is positioned, and there are no limitations on the mounting structure as long as the mounting position can be fixed. The light source 104 may be supported, for example, by a housing surrounding the display panel 102.

[0025] As shown in Figure 2, the light source 104 is positioned along the first side surface 15C of the second transparent substrate 151B. As shown in Figure 2, the light source 104 irradiates light L onto the first side surface 15C of the second transparent substrate 151B (one side surface 15C of the display panel 102). The light source 104 is sometimes called a side light source because it emits light L toward the first side surface 15C. The first side surface 15C of the second transparent substrate 151B facing the light source 104 becomes the light incident surface.

[0026] As schematically shown in Figure 2, light L incident on the first side surface 15C of the second transparent substrate 151B propagates in the direction away from the first side surface 15C (direction D2) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When light L moves outward from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B, it moves from a medium with a high refractive index to a medium with a low refractive index. At this time, if the angle of incidence of light L incident on the first plane 15A and the second plane 15B is greater than the critical angle, total internal reflection occurs, and the light is guided in the direction D2 while being reflected by the first plane 15A and the second plane 15B.

[0027] The liquid crystal layer 210 is formed of polymer-dispersed liquid crystal. The liquid crystal layer 210, formed of polymer-dispersed liquid crystal, controls the scattering and non-scattering states of pixels PIX (see Figure 1). Since dummy pixels DPIX do not display an image, the state of the liquid crystal layer 210 in dummy pixels DPIX is not controlled. As shown in Figure 2, when light L propagates while reflecting off the first plane 15A and the second plane 15B, if there is a pixel in the liquid crystal layer 210 that is in a scattering state, at least some of the light is scattered, and the incident angle of the scattered light becomes smaller than the critical angle, causing the scattered light LA ​​and LB to be emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA ​​and LB are observed by the observer. In the display panel 102, areas other than those from which scattered light LA ​​and LB are emitted are substantially transparent because the array substrate 150 and the opposing substrate 152, as well as the first transparent substrate 151A and the second transparent substrate 151B are light-transmitting (transparent to visible light), and the liquid crystal layer 210 is in a non-scattering state. As a result, the observer can view the image displayed in the display area 12 from the front side of the display panel 102 and from the back side opposite the front side of the display panel 102.

[0028] Figure 3 is a plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the array substrate 150 includes a display area 12, a non-display area 13, and a peripheral area 14.

[0029] The display area 12 is located in the center or inside of the array substrate 150. The display area 12 may also be located in the area surrounded by the sealing material 154-1. The sealing material 154-1 is provided between the array substrate 150 and the opposing substrate 152. The display area 12 has a plurality of pixels PIX arranged in a matrix. Each of the plurality of pixels PIX has a plurality of transistors and liquid crystal elements. Each of the plurality of transistors is electrically connected to a scan signal line GL extending in the column direction (D2 direction) and a video signal line SL extending in the column direction (D1 direction) intersecting the row direction.

[0030] The non-display area 13 is provided adjacent to the display area 12. The non-display area 13 is provided between the display area 12 and the surrounding area 14. If the display area 12 and the surrounding area 14 are adjacent, the non-display area 13 does not need to be provided between the display area 12 and the surrounding area 14. The non-display area 13 may be provided so as to surround at least a part of the display area 12. For example, in Figure 3, the non-display area 13 is provided so as to surround all sides of the display area 12 except one side. By providing the non-display area 13 to fill the area between the display area 12 and the surrounding area 14, consistency can be achieved between the shape of the display panel 102 and the shape of the display area 12.

[0031] The non-display area 13 may be provided in the area overlapping with the sealing material 154-1 and the area surrounding the overlapping area. As shown in Figure 3, when the sealing material 154-1 is provided so as to surround the display area 12, the non-display area 13 is provided in the area surrounding the sealing material 154-1. In addition, the area overlapping with the sealing material 154-1 in the array substrate 150 may be the non-display area 13.

[0032] The non-display area 13 may be provided in the area surrounded by the sealing material 154-2. In the array substrate 150, the area overlapping with the sealing material 154-2 may be the area surrounding the peripheral area 14, or it may be the area overlapping with the peripheral area 14. Here, the sealing material 154-2 corresponds to the sealing material 154 shown in Figure 1, and the non-display area 13 and the display area 12 are provided in the area surrounded by the sealing material 154-2.

[0033] The non-display area 13 has a plurality of dummy pixels DPIX arranged in a matrix. The plurality of dummy pixels DPIX can be arranged in a plurality of columns extending from the display area 12 toward the peripheral area 14. When the distance between the display area 12 and the peripheral area 14 is short, a small number of dummy pixels DPIX are provided. When the distance between the display area 12 and the peripheral area 14 is long, a large number of dummy pixels DPIX are provided. For example, as shown in Figure 3, when the shape of the display panel 102 is semicircular, the number of plurality of dummy pixels DPIX arranged in a plurality of columns extending from the display area 12 toward the peripheral area 14 increases toward the light source 104 or the chord of the semicircle.

[0034] Multiple dummy pixels (DPIX) are the same size as multiple pixels (PIX) and are arranged at the same intervals. Being the same size as multiple dummy pixels (DPIX) and multiple pixels (PIX) means that the shape of the pixels and the area they occupy are the same. Furthermore, multiple pixels (PIX) and multiple dummy pixels (DPIX) are arranged at the same intervals. Because multiple pixels (PIX) and multiple dummy pixels (DPIX) are the same size and arranged at the same intervals, the display area 12 and the non-display area 13 can have a similar degree of light transmission. Having a similar degree of light transmission in the display area 12 and the non-display area 13 means that the transmittance of the display area 12 and the transmittance of the non-display area 13 are approximated. Alternatively, having a similar degree of light transmission in the display area 12 and the non-display area 13 means that it is difficult for the observer to perceive the boundary between the display area 12 and the non-display area 13.

[0035] Each of the multiple dummy pixels (DPIX) has a structure that lacks at least one of the transistor configurations of a pixel (PIX). The dummy pixel (DPIX) has a structure that does not display an image, that is, no voltage is applied to the liquid crystal layer (210). As will be explained in more detail later, for example, the dummy pixel (DPIX) has a structure that lacks the semiconductor layer of the transistor configuration of a pixel (PIX). Because the dummy pixel (DPIX) does not have a semiconductor layer, no image signal is output to the pixel electrode, and therefore no image is displayed.

[0036] The peripheral region 14 is arranged along the periphery of the display panel 102, excluding one side. One side of the display panel 102 is, for example, the side facing the light source 104 (the side adjacent to the first side 15C), as shown in Figure 2 or Figure 3. The peripheral region 14 is provided so as to surround the display region 12. The peripheral region 14 is provided so as to surround the non-display region 13. The peripheral region 14 may also be provided so as to surround at least one side of the display region 12 and the non-display region 13, as shown in Figure 3. Note that the peripheral region 14 refers to the area on the array substrate 150 from the display region 12 or non-display region 13 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the area on the array substrate 150 other than where the display region 12 and the non-display region 13 are provided (i.e., the area outside the display region 12 or the non-display region 13).

[0037] The peripheral region 14 is provided with a drive circuit, as well as wiring that electrically connects the drive circuit to multiple dummy pixels (DPIX) and to multiple pixels (PIX).

[0038] Figure 4 is a block diagram illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 4, the array substrate 150 includes a display area 12, a non-display area 13, and a peripheral area 14. The solid lines and arrows shown in Figure 4 indicate direct or electrical connections.

[0039] In addition to the scan line drive circuit 28 and the video line drive circuit 38, the peripheral region 14 is provided with a scan signal line region 32, a video signal line region 42, an ESD protection circuit 46, a gate inspection circuit 48, a source inspection circuit 52, common wiring 16, 18, terminal sections 26, 36, flexible printed circuits 24, 34, and various inspection circuits. The terminal sections 26, 36 can be arranged along one side of the array substrate 150.

[0040] A flexible printed circuit board 24 is connected to the terminal section 26. The flexible printed circuit board 24 supplies various signals to the scan line drive circuit 28, common wiring 16, 18, ESD protection circuit 59, and QD pad 56. The scan line drive circuit 28 is connected to a plurality of scan signal lines GL, each of which is electrically connected to a plurality of dummy pixels DPIX in the non-display area 13 and a plurality of pixels PIX in the display area 12. In Figure 4, the area where the plurality of scan signal lines GL are provided is represented as the scan signal line area 32. The number of scan signal lines GL connected to the two scan line drive circuits 28 corresponds to the number of rows of pixels PIX in the display area 12.

[0041] A flexible printed circuit 34 is connected to the terminal section 36. The flexible printed circuit 34 supplies video signals to the video line drive circuit 38. The video line drive circuit 38 is connected to a plurality of video signal lines SL, each of which is electrically connected to a plurality of dummy pixels DPIX in the non-display area 13 and a plurality of pixels PIX in the display area 12. In Figure 3, the area where the plurality of video signal lines SL are provided is represented as the video signal line area 42. The number of video signal lines SL connected to the video line drive circuit 38 corresponds to at least three times the number of rows of pixels PIX in the display area 12.

[0042] The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is also connected to the ESD protection circuit 59.

[0043] The common wiring 16 can be provided so as to surround the peripheral region 14 on the array substrate 150, and signals are supplied from the flexible printed circuit 24. The common wiring 16 is also electrically connected to the mesh-like common wiring region 22.

[0044] The display device 10 is not limited to high-speed drive panels such as the transparent displays shown in Figures 1 and 2. The display device 10 can be applied to large, high-definition panels used in non-transparent display devices.

[0045] <Pixel configuration> Figure 5 is a diagram illustrating the configuration of pixels (PIX) and dummy pixels (DPIX) in a display device 10 according to one embodiment of the present invention. The pixel configuration in this embodiment will be described in detail below.

[0046] Figure 5 shows pixels PIX-B1 and dummy pixels DPIX-B1 arranged in the column direction (D2 direction) in adjacent display area 12 and non-display area 13. Pixels PIX-B1 and dummy pixels DPIX-B1 are electrically connected to the video signal line SL and the scan signal line GL, respectively.

[0047] Pixel PIX-B1 has a transistor Tr and a retaining capacitor (not shown) on the array substrate 150. The gate of transistor Tr is connected to the scan signal line GL, the source of transistor Tr is connected to the video signal line SL, and the drain of transistor Tr is connected to one electrode of the liquid crystal element and one electrode of the retaining capacitor. The other electrode of the liquid crystal element is connected to the common wiring. The other electrode of the retaining capacitor is connected to the capacitance wiring.

[0048] The transistor Tr has the function of controlling the writing time of the video signal supplied from the video signal line to the pixels by switching between an on state and an off state. By turning the transistor Tr on, the potential corresponding to the video signal supplied from the video signal line can be written to the retaining capacitor electrically connected to the transistor Tr. Conversely, by turning the transistor Tr off, the potential held in the retaining capacitor can be retained.

[0049] Next, the configuration of the transistor Tr will be described with reference to Figures 6 and 7. Figure 6 is a plan view illustrating the configuration of the transistor Tr of a pixel PIX in a display device 10 according to one embodiment of the present invention. Figure 7 is a cross-sectional view illustrating the configuration of the transistor Tr of a pixel PIX in a display device 10 according to one embodiment of the present invention.

[0050] Figure 6 is a plan view of the transistor Tr and its surroundings in the pixel PIX-B1 shown in Figure 5. Figure 6 shows the planar layout of conductive layers 202-1 to 202-9, oxide semiconductor layers 204-1 to 204-5, and conductive layers 206-1 to 206-11. Conductive layers 202-1 to 202-9 are provided on the array substrate 150. Conductive layer 202-1 extends in the D1 direction but has a region that branches in the D2 direction. Conductive layers 202-2 to 202-9 also extend in the D2 direction. Oxide semiconductor layers 204-1 to 204-5 are provided on conductive layer 202-1 via a gate insulating film 203 (see Figure 7). Oxide semiconductor layers 204-1 to 204-5 are arranged in a line in the D2 direction. In this embodiment, an example is shown in which five oxide semiconductor layers 204-1 to 204-5 are used to constitute the transistor Tr. The number of oxide semiconductor layers is not particularly limited. Conductive layers 206-1 to 206-11 are provided on the gate insulating film and oxide semiconductor layers 204-1 to 204-5. Conductive layers 206-1, 206-2, and 206-11 extend in the D1 direction, and conductive layers 206-3 to 206-10 extend in the D2 direction.

[0051] Conductive layer 202-1 is superimposed on conductive layers 206-1, 206-2, and 206-11. Conductive layer 202-1 is connected to conductive layer 206-1 via an opening 213-1 provided in the gate insulating film 203, and is connected to conductive layer 206-2 via an opening 213-2 provided in the gate insulating film 203. The region of conductive layer 202-1 extending in the D1 direction functions as a scan signal line. The region of conductive layer 202-1 extending in the D2 direction functions as a gate electrode.

[0052] Conductive layers 202-2 and 202-3 overlap with conductive layer 206-4. Conductive layer 202-2 is connected to conductive layer 206-4 via an opening 213-3 provided in the gate insulating film 203, and conductive layer 202-3 is connected to conductive layer 206-4 via an opening 213-4 provided in the gate insulating film 203. Conductive layer 206-4 intersects with conductive layer 202-1. Conductive layer 206-4 functions as the first video signal line SL1. In addition, the region of conductive layer 206-4 that does not overlap with conductive layers 202-2 and 202-3 functions as the source electrode of transistor Tr. Conductive layer 206-3 functions as the drain electrode of transistor Tr.

[0053] Conductive layer 202-4 is superimposed on conductive layer 206-5 and connected to conductive layer 206-5 via an opening 213-5 provided in the gate insulating film 203. Conductive layer 202-5 is superimposed on conductive layer 206-6 and connected to conductive layer 206-6 via an opening 213-6 provided in the gate insulating film 203. Conductive layer 206-5 is connected to conductive layer 206-6 via conductive layer 208-2. As a result, conductive layers 206-5, 206-6, and 208-2 function as the third video signal line SL3.

[0054] Conductive layer 202-6 is superimposed on conductive layer 206-7 and connected to conductive layer 206-7 via an opening 213-7 provided in the gate insulating film 203. Conductive layer 202-7 is superimposed on conductive layer 206-8 and connected to conductive layer 206-8 via an opening 213-8 provided in the gate insulating film 203. Conductive layer 206-7 is connected to conductive layer 206-8 via conductive layer 208-3. Conductive layers 206-7, 206-8, and 208-3 function as the second video signal line SL2.

[0055] Conductive layer 202-8 is superimposed on conductive layer 206-9 and connected to conductive layer 206-9 via an opening 213-9 provided in the gate insulating film 203. Conductive layer 202-9 is superimposed on conductive layers 206-9 and conductive layer 206-10. Conductive layer 202-9 is connected to conductive layer 206-9 via an opening 213-10 provided in the gate insulating film 203. Conductive layer 202-9 is connected to conductive layer 206-10 via an opening 213-11 provided in the gate insulating film 203. Conductive layer 206-9 has a region that intersects with conductive layer 202-1. Conductive layers 206-9 and 206-10 function as the fourth video signal line SL4.

[0056] Furthermore, the conductive layer 202-1 is superimposed on the conductive layer 206-11 and is connected to the conductive layer 206-11 through an opening 213-12 provided in the gate insulating film 203.

[0057] Conductive layers 202-9 and 206-8 have bent regions. Conductive layer 202-9 has a region that overlaps with and intersects with conductive layer 206-8. In other words, it has a region where the second video signal line SL2 and the fourth video signal line SL4 intersect.

[0058] Although not shown in the diagram, conductive layers 202-2 and 206-5 have bent regions. Conductive layer 202-2 has a region that overlaps with and intersects conductive layer 206-5. In other words, the first video signal line SL1 has a region that intersects with the third video signal line SL3.

[0059] As shown in Figure 6, the scanning signal line GL is constructed by stacking conductive layer 202-1 and conductive layers 206-1 and 206-2. In the region where the scanning signal line GL intersects with video signal lines SL1 to SL4, only conductive layer 202-1 is provided, and conductive layers 206-1 and 206-2 are spaced apart. The video signal line SL1 is constructed by stacking conductive layers 202-2 and 202-3 and conductive layer 206-4. In the region where the video signal line SL1 intersects with the scanning signal line GL, only conductive layer 206-4 is provided, and conductive layers 202-2 and 202-3 are spaced apart.

[0060] Next, the cross-sectional structure of the transistor Tr will be described. As shown in Figure 7, the transistor Tr has a conductive layer 202-1 provided on the array substrate 150, an oxide semiconductor layer 204-1 provided opposite to the conductive layer 202-1, a gate insulating film 203 provided between the conductive layer 202-1 and the oxide semiconductor layer 204-1, and conductive layers 206-3 and 206-4 provided on the oxide semiconductor layer 204-1.

[0061] An insulating film 205 is provided on the transistor Tr. Furthermore, a conductive layer 208-1 is provided on the insulating film 205 at a position opposite to the oxide semiconductor layer 204-1. The conductive layer 208-1 functions as a back gate electrode. In this embodiment, the transistor Tr is described as a bottom-gate driven transistor, but it is not limited to this; it may also be a top-gate driven transistor or a dual-gate driven transistor.

[0062] A planarization film 207 is provided on the conductive layer 208-1 and the insulating layer 105. The planarization film 207 is provided to alleviate the irregularities of the various wirings that constitute the transistor Tr. In Figures 5 and 7, the area on which the planarization film 207 is provided is shown as the wiring area. When the display device 10 is applied to a transparent display, it is preferable to remove the planarization film 207 in the aperture area OP of the pixel PIX. This makes it possible to suppress the absorption of light by the planarization film 207 in the aperture area OP.

[0063] A transparent conductive layer 212 is provided on the planarization film 207 and the insulating film 205. A conductive layer 214 is provided on the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring. An insulating film 209 is provided on the transparent conductive layer 212 and the conductive layer 214. A pixel electrode 216-1 is provided on the insulating film 209. The pixel electrode 216-1 is connected to the conductive layer 206-3 through openings provided in the insulating films 205 and 209.

[0064] A counter substrate 152 is provided opposite the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219 and a common electrode 218 (also called a counter electrode). The light-shielding layer 219 functions as a black matrix. In the structure shown in Figure 6, the light-shielding layer 219 is provided in the region that overlaps with the conductive layer 206-4 in Figure 7. The light-shielding layer 219 is arranged in a grid pattern so as to cover the scanning signal line GL and the video signal lines SL1 to SL4. The common electrode 218 is large enough to cover the entire surface of the display area 12. The light-shielding layer 219 may be made of a metal film and functions as an auxiliary electrode by being provided in contact with the common electrode 218 which is made of a transparent conductive film. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152 and is sealed with a sealing material 154 (see Figure 1). The liquid crystal element LE is composed of a pixel electrode 216-1, a liquid crystal layer 210, and a common electrode 218.

[0065] <Dummy Pixel Configuration> Referring again to Figure 5, the configuration of the dummy pixel DPIX in the display device 10 according to one embodiment of the present invention will be explained.

[0066] Dummy pixels DPIX have the same occupied area and shape as pixels PIX, but do not have the same structure. Dummy pixels DPIX have a structure ST on the array substrate 150 that does not have the structure of a transistor Tr. Structure ST does not have the oxide semiconductor layer 204 of the transistor Tr configuration, as shown in Figures 8 and 9, for example. Note that structure ST is not limited to not having the oxide semiconductor layer 204. Furthermore, the configuration of the transistor Tr that structure ST does not have is not limited to the oxide semiconductor layer 204, but the oxide semiconductor layer 204 is preferred because it has a smaller occupied area and higher transmittance compared to other configurations, and therefore has less impact on the transmittance of dummy pixels DPIX.

[0067] Next, the configuration of the structure ST will be described with reference to Figures 8 and 9. Figure 8 is a plan view illustrating the configuration of the structure ST of the dummy pixel DPIX in the display device 10 according to one embodiment of the present invention. Figure 9 is a cross-sectional view illustrating the configuration of the structure ST of the dummy pixel DPIX in the display device 10 according to one embodiment of the present invention. Note that the explanation of the structure ST may be omitted if it is the same as or similar to the configuration of the transistor Tr.

[0068] Structure ST lacks at least one of the components included in transistor Tr. Structure ST is sufficient if it is configured so that a voltage corresponding to the video signal is not applied to the pixel electrode 216-1 constituting the liquid crystal element LE. Structure ST is sufficient if it lacks at least one of the oxide semiconductor layers 204-1 to 204-5, conductive layer 206-3, conductive layer 206-4, and conductive layer 202-1. It is preferable that structure ST does not include oxide semiconductor layers 204-1 to 204-5, as shown in Figures 8 and 9. By not including oxide semiconductor layers with low absorbance in structure ST, a voltage corresponding to the video signal is not applied to the pixel electrode 216-1, and furthermore, the light transmittance in dummy pixels DPIX and pixels PIX can be made to be of a similar degree.

[0069] <Materials of each component of the display device 10> As the array substrate 150 and the opposing substrate 152, rigid substrates that are translucent and not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, if the array substrate 150 and the opposing substrate 152 need to be flexible, flexible substrates containing resin and having flexibility, such as polyimide substrates, acrylic substrates, siloxane substrates, or fluororesin substrates, can be used as the array substrate 150 and the opposing substrate 152. Impurities may be introduced into the above resins to improve the heat resistance of the array substrate 150 and the opposing substrate 152. Furthermore, when the display device 10 is applied to a transparent display or a large high-definition display, it is preferable to use glass substrates as the array substrate 150 and the opposing substrate 152. In addition, the first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the opposing substrate 152. For this reason, it is preferable to use, for example, a translucent glass substrate or a plastic substrate.

[0070] Common metallic materials can be used as conductive layers 202, 206, 208, and 214. Examples of these materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof. These materials may be used as single layers or in laminated structures. For example, a laminated Al\Ti structure can be used as conductive layer 202. For example, a laminated TiN\Ti\Al\Ti\TiN structure can be used as conductive layer 206. For example, Mo can be used as conductive layer 208. A laminated Mo\Al structure can be used as the conductive layer.

[0071] Common insulating materials can be used as gate insulating film 203, insulating film 205, and insulating film 209. For example, silicon oxide (SiO2) can be used as gate insulating film 203, insulating film 205, and insulating film 209.y ,

[0073] , x , , ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers can be used. As these insulating layers, an insulating layer with few defects can be used. As the planarization film 207, an organic insulating material such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. In addition, as the gate insulating film 203, the insulating film 205, and the insulating film 209, the above organic insulating materials may be used. As the above members, the above materials may be used singly or in a laminated form. For example, as the gate insulating film 203, a laminated structure of silicon nitride and silicon oxide is used. For example, as the insulating film 205, a laminated structure of silicon oxide and silicon nitride is used. Also, as the insulating film 209, silicon nitride is used.

[0072] The above SiO x N<00000​​​​​​​​​​​​​​​​As the oxide semiconductor layer 204, a metal oxide having semiconductor properties can be used. The oxide semiconductor layer 204 is translucent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor with a different composition can also be used. For example, the ratio of In may be increased to improve mobility. Also, the ratio of Ga may be increased to increase the band gap and reduce the effect of light irradiation.

[0074] In this embodiment, an example using an oxide semiconductor layer as the semiconductor layer has been described, but an amorphous silicon or polysilicon semiconductor layer may also be used.

[0075] A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer 212, the pixel electrode 216, and the common electrode 218. Other materials may be used as the transparent conductive layer. The light-shielding layer 219 used for the black matrix BM can be formed from a black resin or metal material. The black matrix BM is formed in contact with the common electrode 218 (see Figure 6). By forming the black matrix BM from a metal material relative to the common electrode 218, which is formed from a transparent conductive film, it can function as an auxiliary electrode to reduce resistance loss. As the metal material for forming the black matrix BM, it is preferable to use chromium, molybdenum, titanium, etc., which have a relatively low reflectivity compared to aluminum.

[0076] When the display device 10 is applied to a transparent display, it is preferable to use a polymer-dispersed liquid crystal as the liquid crystal layer 210. The polymer-dispersed liquid crystal includes bulk and fine particles. The orientation of the fine particles changes in the bulk according to the potential difference between the pixel electrode 216 and the common electrode 218. By individually controlling the potential of the pixel electrode 216 for each pixel PIX, at least the degree of light transmission and dispersion is controlled for each pixel PIX. The degree of scattering of the liquid crystal layer (fine particles) is controlled according to the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, the liquid crystal layer may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel PIX and the common electrode 218 increases, or it may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel electrode 216 and the common electrode 218 decreases.

[0077] In the liquid crystal layer 210, the ordinary refractive indices of the bulk and fine particles are equal to each other. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk and fine particles is zero in all directions. The liquid crystal layer 210 is in a non-scattering state and does not scatter the light emitted from the light source. The light emitted from the light source propagates away from the light source 104 (light-emitting part) while being reflected by the first main surface of the array substrate 150 and the first main surface of the opposing substrate 152. When the liquid crystal layer 210 is in a non-scattering state and does not scatter the light L emitted from the light source, the background of the opposing substrate 152 is visible from the array substrate 150, and the background of the array substrate 150 is visible from the opposing substrate 152.

[0078] Between the pixel electrode 216 to which a voltage is applied and the common electrode 218, the optical axis of the microparticle is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the bulk optical axis does not change due to the electric field, the orientation of the bulk optical axis and the optical axis of the microparticle are different from each other. In a pixel PIX where the voltage is applied to the pixel electrode 216, light emitted from the light source is scattered. As described above, a portion of the scattered light emitted from the light source is radiated outward from the first main surface of the array substrate 150 or the first main surface of the opposing substrate 152 and is observed by the observer.

[0079] In pixels PIX where no voltage is applied to the pixel electrode 216, the background on the first main surface side of the opposing substrate 152 is visible from the first main surface of the array substrate 150, and the background on the first main surface side of the array substrate 150 is visible from the first main surface of the opposing substrate 152. When a video signal is input to the display device 10 of this embodiment, a voltage is applied to the pixel electrode 216 of the pixel PIX on which the image is displayed, and the image based on the video signal is visible together with the background. In this way, when the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area.

[0080] As explained above, by making the display area 12 and the non-display area 13 of the display device 10 translucent, the boundary between the display area 12 and the non-display area 13 can be blurred, thereby improving the appearance of the image.

[0081] Next, a modified example of the display device 10 according to this embodiment will be described with reference to Figure 10.

[0082] (modified version) Modified examples of the shape of the display panel 102 will be described with reference to Figure 10. Figure 10 is a plan view of a display device according to one embodiment of the present invention.

[0083] The outer edge 1020 of the display panel 102 may have a straight portion 1021. Figure 10 shows an example in which the peripheral area 14 and the display area 12 are adjacent and no non-display area 13 is provided by providing a straight portion 1021 on the outer edge 1020 of the display panel 102. However, a non-display area 13 may be provided between the peripheral area 14 and the display area 12.

[0084] While preferred embodiments have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. [Explanation of Symbols]

[0085] 10: Display device, 12: Display area, 13: Non-display area, 14: Peripheral area, 15A: First plane, 15B: Second plane, 15C: First side, 16: Common wiring, 18: Common wiring, 22: Common wiring area, 24: Flexible printed circuit, 26: Terminal section, 28: Scan line drive circuit, 32: Scan signal line area, 34: Flexible printed circuit, 36: Terminal section, 38: Video line drive circuit, 42: Video signal line area, 54: Inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 10 2: Display panel, 104: Light source, 105: Insulating layer, 110: Light emission control circuit, 150: Array substrate, 151A: First transparent substrate, 151B: Second transparent substrate, 152: Opposing substrate, 154: Encapsulation material, 154-1: Encapsulation material, 154-2: Encapsulation material, 202: Conductive layer, 202-1: Conductive layer, 202-2: Conductive layer, 202-3: Conductive layer, 202-4: Conductive layer, 202-5: Conductive layer, 202-6: Conductive layer, 202-7: Conductive layer, 202-8: Conductive layer, 202-9: Conductive layer, 203: Gate insulating film, 204: Oxide semiconductor Layer, 204-1: Oxide semiconductor layer, 204-2: Oxide semiconductor layer, 204-3: Oxide semiconductor layer, 204-4: Oxide semiconductor layer, 204-5: Oxide semiconductor layer, 205: Insulating film, 206: Conductive layer, 206-1: Conductive layer, 206-10: Conductive layer, 206-11: Conductive layer, 206-2: Conductive layer, 206-3: Conductive layer, 206-4: Conductive layer, 206-5: Conductive layer, 206-6: Conductive layer, 206-7: Conductive layer, 206-8: Conductive layer, 206-9: Conductive layer, 207: Planarization film, 208: Conductive layer, 208-1: Conductive Electrode layer, 208-2: Conductive layer, 208-3: Conductive layer, 209: Insulating film, 210: Liquid crystal layer, 212: Transparent conductive layer, 213-1: Aperture, 213-10: Aperture, 213-11: Aperture, 213-12: Aperture, 213-2: Aperture, 213-3: Aperture, 213-4: Aperture, 213-5: Aperture, 213-6: Aperture, 213-7: Aperture, 213-8: Aperture, 213-9: Aperture, 214: Conductive layer, 216: Pixel electrode, 216-1: Pixel electrode, 218: Common electrode, 219: Light-shielding layer, 1020: Outer edge, 1021: Straight section

Claims

1. A display panel having a liquid crystal layer between a pair of substrates, A light source that causes light to be incident on the liquid crystal layer from one side of the display panel, It has, The aforementioned display panel is A display area in which multiple pixels are arranged, Adjacent to the aforementioned display area is a non-display area in which multiple dummy pixels are arranged, Arranged along the periphery of the display panel other than the one side, and surrounding the non-display area, The drive circuit arranged in the peripheral region, Connected to the aforementioned drive circuit, a plurality of first wires extending in a first direction, and a plurality of second wires extending in a second direction intersecting the first direction, Includes, The aforementioned plurality of pixels and the aforementioned plurality of dummy pixels are of the same size and are arranged at the same intervals. The display area and the non-display area are translucent. The image displayed in the display area is visible from the first side of the display panel and from the second side opposite to the first side. A display device characterized by the following features.

2. The pair of substrates includes an array substrate and a counter substrate facing the array substrate, The plurality of pixels include a plurality of pixel electrodes provided on the array substrate and a counter electrode provided on the opposing substrate, The plurality of dummy pixels include a plurality of dummy pixel electrodes provided on the array substrate and the counter electrodes provided on the opposing substrate. The display device according to claim 1.

3. The drive circuit includes a scan signal line drive circuit that outputs a scan signal and a video signal line drive circuit that outputs a video signal. The scanning signal line drive circuit and the video signal line drive circuit are arranged in the peripheral region. The first wiring extends from the scan signal line drive circuit, and the second wiring extends from the video signal line drive circuit. The display device according to claim 1.

4. The scanning signal line driving circuit is arranged in the peripheral region in the direction in which the first wiring extends from the display region. The video signal line driving circuit is arranged in the peripheral region in the direction in which the second wiring extends from the display region. The display device according to claim 3.

5. The shape of the outer edge of the display panel has a continuously curved portion. The display device according to claim 1.

6. The outer edge of the display panel further has a straight portion. The display device according to claim 5.

7. Each of the plurality of pixels includes a transistor having an oxide semiconductor layer, a first conductive layer on the oxide semiconductor layer, an insulating film between the oxide semiconductor layer and the first conductive layer, a second conductive layer electrically connected to the oxide semiconductor layer, and a third conductive layer electrically connected to the oxide semiconductor layer, and the pixel electrode electrically connected to the third conductive layer. The video signal lines further include the second conductive layer and are electrically connected to it. Each of the plurality of dummy pixels includes a structure lacking at least one of the oxide semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, and the pixel electrode. The display device according to claim 2.

8. The first sealing material further comprises the display area, The first sealing material is arranged so as to overlap with the non-display area. The display device according to claim 1.

9. The second sealing material further includes the display area and the non-display area. The display device according to claim 1.

10. The plurality of dummy pixels are arranged in a plurality of rows extending from the display area toward the peripheral area, The number of dummy pixels in the plurality of columns increases toward the light source. The display device according to claim 1.

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