Neural network device and signal processing method

Abstract

Minimize the loss of information transmitted. [Solution] The neural network device according to the embodiment comprises a plurality of synaptic circuits and a plurality of neuron circuits. The first neuron circuit among the plurality of neuron circuits is supplied with synaptic current to its first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit has a charge storage circuit, a spike output circuit and a cutoff circuit. The charge storage circuit stores charge according to the synaptic current and generates a membrane potential according to the stored charge. The spike output circuit outputs a spike signal when the membrane potential is greater than a preset threshold potential. The cutoff circuit stops the supply of synaptic current from the first terminal to the charge storage circuit during a cutoff period, which is a predetermined time after the spike signal is output.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a neural network device and a signal processing method. [Background technology]

[0002] In recent years, artificial intelligence (AI) technology has been rapidly developing, driven by advancements in computer hardware such as GPUs (Graphical Processing Units). For example, image recognition and classification technologies, such as CNNs (Convolutional Neural Networks), are already being used in various real-world scenarios. Currently, widely used AI technologies are based on mathematical models that simplify the operation of biological neural networks. Therefore, such AI technologies are executed using computers such as GPUs. However, executing AI technologies on a GPU requires a large amount of power. In particular, the learning process, which involves extracting and memorizing features from large amounts of data, requires an enormous amount of computation. For this reason, such learning processes require a great deal of power, and it is considered difficult to execute them on edge devices, for example.

[0003] On the other hand, the human brain, despite consuming relatively little energy (around 20W), constantly learns from a vast amount of data online. Therefore, technologies that relatively faithfully reproduce brain activity using electrical circuits to process information are being researched worldwide.

[0004] Within the brain's neural network, information is transmitted from neuron (nerve cell) to neuron via voltage spikes. Neurons are connected by junctions called synapses. A voltage spike generated by one neuron is input to a subsequent neuron via the synapse. At this time, the intensity of the voltage spike input to the subsequent neuron is regulated by the synaptic weight, which is the strength of the synaptic connection.

[0005] A synapse receives voltage spikes from a preceding neuron, converts them into synaptic currents corresponding to the synaptic weight, and transmits them to a subsequent neuron. When the synaptic weight is large, a large synaptic current is transmitted to the subsequent neuron; when the synaptic weight is small, a small synaptic current is transmitted to the subsequent neuron.

[0006] Neurons maintain an internal potential called membrane potential. When a neuron receives a synaptic current from a synapse, it raises its membrane potential in proportion to the magnitude of the received current. Conversely, if no synaptic current is supplied, the neuron's membrane potential decreases over time. Therefore, if a neuron receives synaptic current at short intervals, its membrane potential will rise, and if no synaptic current is supplied for a long period, its membrane potential will decrease. When the membrane potential rises to a threshold potential, which is the firing threshold, the neuron generates a voltage spike. This generation of a voltage spike by a neuron is called firing.

[0007] Furthermore, when a neuron fires, it returns the membrane potential to its initial potential. After returning the membrane potential to its initial potential, the neuron maintains the membrane potential at the initial potential for a certain period called the refractory period. In other words, during the refractory period, the neuron does not raise the membrane potential even when a synaptic current is applied. Then, after the refractory period ends, the neuron changes the membrane potential.

[0008] Information processing that mimics the information transmission principles of the brain's neural networks is called a spiking neural network. In a spiking neural network, information processing is performed without numerical calculations, by increasing or decreasing membrane potential in response to voltage spikes, generating voltage spikes, and transmitting voltage spikes through synapses. Conventional artificial intelligence required enormous amounts of computation for learning operations. In contrast, spiking neural networks do not perform numerical calculations, so they are thought to be able to process data efficiently. For this reason, research into implementing spiking neural networks as semiconductor chips has been actively conducted in recent years.

[0009] When a spiking neural network is implemented on a semiconductor chip, neurons are realized by an analog circuit using resistors, capacitors, comparators, etc. This circuit accumulates the charge corresponding to the received synaptic current in a capacitor, and uses the voltage generated by the charge accumulated in the capacitor as the membrane potential.

[0010] By the way, when an arithmetic neural network that performs arithmetic operations represented by CNN etc. is realized by a conventional spiking neural network, different results are output than when it is realized by a digital arithmetic circuit such as a CPU (Central Processing Unit).

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0012] The problem to be solved by the present invention is to provide a highly accurate spiking neural network device and signal processing method with less loss of transmitted information.

Means for Solving the Problems

[0013] The neural network device according to the embodiment comprises a plurality of synaptic circuits, each with a set synaptic weight, and a plurality of neuron circuits, each outputting a spike signal which is a voltage pulse. Each of the plurality of synaptic circuits acquires the spike signal output from any one of the plurality of neuron circuits, and when it acquires the spike signal, it outputs a synaptic current of an amount corresponding to the set synaptic weight and the spike signal. The first neuron circuit among the plurality of neuron circuits is supplied with the synaptic current to its first terminal from each of the one or more first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit has a charge storage circuit, a spike output circuit, and a cutoff circuit. The charge storage circuit stores a charge corresponding to the synaptic current and generates a membrane potential corresponding to the stored charge. The spike output circuit outputs the spike signal when the membrane potential is greater than a preset threshold potential. The cutoff circuit stops supplying the synaptic current from the first terminal to the charge storage circuit during a cutoff period, which is a predetermined time after the spike signal is output. [Brief explanation of the drawing]

[0014] [Figure 1] A diagram showing an example of the configuration of a neural network device. [Figure 2] A diagram illustrating the connection relationships of the peripheral circuits of the first neuron circuit. [Figure 3] A diagram showing the configuration of the first neuron circuit according to the first embodiment. [Figure 4] A flowchart illustrating the processing flow of the first neuron circuit. [Figure 5] Waveform diagrams of the spike signal, reset signal, and cutoff signal. [Figure 6] A diagram illustrating the components of synaptic current transferred from parasitic capacitance to the charge storage circuit. [Figure 7] A diagram showing the configuration of the first neuron circuit according to the second embodiment. [Figure 8]A diagram showing the configuration of the first neuron circuit according to the third embodiment. [Modes for carrying out the invention]

[0015] The neural network device 10 according to an embodiment will be described below with reference to the drawings.

[0016] When an arithmetic neural network, such as a CNN, is implemented using a conventional spiking neural network, the output differs from that when implemented using a digital computing circuit such as a CPU (Central Processing Unit). One reason for this is that while an arithmetic neural network implemented with a digital computing circuit outputs unlimited numerical information from each neuron, an arithmetic neural network implemented with a conventional spiking neural network suffers from information loss in the neurons. For example, in a conventional spiking neural network, even if synaptic current is applied to each neuron during the period after firing a voltage spike and returning the membrane potential to its initial potential, the membrane potential does not rise. Therefore, the component of the synaptic current applied during this period is not transmitted to the next neuron, resulting in information loss. For this reason, to accurately implement an arithmetic neural network using a spiking neural network, it is necessary to minimize such information loss. The following describes an embodiment that solves this problem.

[0017] (First Embodiment) The neural network device 10 according to the first embodiment is a spiking-type neural network configured with hardware. For example, the neural network device 10 is mounted on a semiconductor device using a process such as CMOS (Complementary Metal Oxide Semiconductor).

[0018] Figure 1 shows an example of the configuration of the neural network device 10. The neural network device 10, as an example, comprises M layers 12 (where M is an integer of 2 or more) and (M-1) synaptic groups 14.

[0019] Each of the (M-1) synaptic groups 14 contains multiple synaptic circuits 20. Each of the multiple synaptic circuits 20 is assigned a synaptic weight. The synaptic weights assigned to the multiple synaptic circuits 20 are set by a learning process. For example, the synaptic weights assigned to the multiple synaptic circuits 20 may be updated by a predetermined update rule such as STDP (Spike Timing Dependent Plasticity) or SDSP (Spike Driven Synaptic Plasticity).

[0020] Each of the M-stage layers 12 contains multiple neuron circuits 22. Each of the multiple neuron circuits 22 outputs a spike signal. The spike signal is a voltage pulse that changes from a second voltage to a first voltage, and then returns to the second voltage after a certain period of time has elapsed since the change from the second voltage to the first voltage.

[0021] The m-th synaptic group 14 (where m is an integer between 1 and (M-1)) of the (M-1) synaptic groups 14 is located between the m-th layer 12 of the M-level layer 12 and the (m+1)-th layer 12 of the M-level layer 12.

[0022] Each of the multiple synaptic circuits 20 included in the m-th synapse group 14 acquires a spike signal output from one of the multiple neuron circuits 22 included in the m-th layer 12. When each of the multiple synaptic circuits 20 included in the m-th synapse group 14 acquires a spike signal, it outputs a synaptic current corresponding to the set synaptic weight and the acquired spike signal. The synaptic weight may be represented as a binary value or as a discrete value with three or more values. The synaptic weight may also be represented as an analog value by the amount of charge stored in a capacitor or the resistance value of a variable resistor.

[0023] Then, each of the multiple synaptic circuits 20 included in the m-th synaptic group 14 supplies a synaptic current to one of the multiple neuronal circuits 22 included in the (m+1)-th layer 12.

[0024] Each of the multiple neuronal circuits 22 contained in the (m+1)th layer 12 of the M-stage layer 12 acquires multiple synaptic currents output from the m-stage synapse group 14 and performs a process equivalent to a sum-of-accumulate operation on the acquired synaptic currents. The first layer 12 of the M-stage layer 12 acquires multiple signals from an external device or input layer. Each of the multiple neuronal circuits 22 then outputs a spike signal that has been processed with an activation function equivalent to the signal representing the calculation result.

[0025] In such a neural network device 10, the first layer 12 receives one or more signals from an external device or input layer. The neural network device 10 then outputs one or more signals from the Mth layer 12 that represent the result of performing calculations by the neural network on the received one or more signals.

[0026] Such a neural network device 10 performs arithmetic neural network operations such as CNNs. As a result, the neural network device 10 can perform tasks such as image recognition and classification processing without using a CPU and GPU, with low energy consumption and a small circuit.

[0027] The neural network device 10 is not limited to a structure that transmits signals only in the forward direction, as shown in Figure 1. For example, the neural network device 10 may include a configuration in which any of the multiple neuron circuits 22 acquires synaptic currents from a synaptic circuit 20 that has acquired one or more spike signals output by itself, or from a synaptic circuit 20 that has acquired one or more spike signals output by a neuron circuit 22 downstream of itself. Furthermore, the neural network device 10 may be a recurrent neural network. For example, if the neural network device 10 is a recurrent neural network, it can be applied to the reservoir computing device 24.

[0028] Figure 2 is a diagram showing the connection relationships of the peripheral circuits of the first neuron circuit 32 in the first embodiment.

[0029] Each of the multiple neuronal circuits 22 has a membrane potential V mem It maintains an internal potential called the membrane potential V. When the neuron circuit 22 acquires a synaptic current from any of the multiple synaptic circuits 20 connected to the preceding stage, the membrane potential V is maintained according to the magnitude of the acquired synaptic current. mem This increases the value. As a result, each of the multiple neuron circuits 22 can perform a process equivalent to a sum-of-accumulate operation on the multiple synaptic currents it has acquired.

[0030] If each of the multiple neuronal circuits 22 does not acquire synaptic current, the membrane potential V will decrease over time. mem The membrane potential V may be lowered. In this case, if each of the multiple neuronal circuits 22 continues to acquire synaptic currents repeatedly at short time intervals, the membrane potential Vmem If it is not raised and the synaptic current is not acquired for a long time, the membrane potential V mem is decreased. Each of the plurality of neuron circuits 22 decreases the membrane potential V mem by decreasing it, so that when the membrane potential V mem reaches a predetermined initial potential, the decrease in the membrane potential V mem is stopped.

[0031] And each of the plurality of neuron circuits 22 has the membrane potential V mem rising to a predetermined threshold potential V th or more, then fires and outputs a spike signal to the subsequent synaptic circuit 20. Each of the plurality of neuron circuits 22 returns the membrane potential V mem to the initial potential after firing.

[0032] Also, each of the plurality of neuron circuits 22 does not raise the membrane potential V mem even when a synaptic current is applied during a cutoff period which is a predetermined time after firing, and further firing is also stopped. In this case, each of the plurality of neuron circuits 22 starts accumulating charge according to the synaptic current after the cutoff period ends. The initial potential is smaller than the threshold potential V th .

[0033] Each of the plurality of synaptic circuits 20 acquires a spike signal output from any one of the plurality of neuron circuits 22.

[0034] Each of the plurality of synaptic circuits 20 has a circuit that generates a current. When each of the plurality of synaptic circuits 20 acquires a spike signal, using the circuit that generates a current, it outputs a synaptic current with a current amount corresponding to the set synaptic weight and the acquired spike signal to the subsequent neuron circuit 22.

[0035] Here, the first neuron circuit 32, one of the multiple neuron circuits 22, acquires synaptic currents from each of the one or more first synaptic circuits 30. The first neuron circuit 32 adjusts the membrane potential V in accordance with the synaptic currents acquired from each of the one or more first synaptic circuits 30. mem To increase.

[0036] Figure 3 shows the configuration of the first neuron circuit 32 and the first synaptic circuit 30 connected to the preceding stage of the first neuron circuit 32 according to the first embodiment.

[0037] Furthermore, in the neural network device 10, all of the multiple neuron circuits 22 may have the same configuration as the first neuron circuit 32, or some of the multiple neuron circuits 22 may have the same configuration as the first neuron circuit 32.

[0038] The first neuron circuit 32 has a first terminal 52. The first neuron circuit 32 receives synaptic currents from each of the one or more first synaptic circuits 30 connected to the preceding stage of the first neuron circuit 32.

[0039] Furthermore, one or more synaptic circuits 20 are connected to the first neuron circuit 32. The first neuron circuit 32 outputs a spike signal to each of the one or more synaptic circuits 20 connected to it.

[0040] The first synaptic circuit 30 includes a synaptic current source 42 and a synaptic output circuit 44.

[0041] The synaptic current source 42 is a variable current source. The synaptic current source 42 is configured with a synaptic weight (W). The synaptic current source 42 outputs a synaptic current of an amount corresponding to the configured synaptic weight (W).

[0042] The synaptic output circuit 44 receives a spike signal output from the preceding neuron circuit 22. Depending on the spike signal output from the preceding neuron circuit 22, the synaptic output circuit 44 switches whether or not to output the synaptic current output from the synaptic current source 42 to the subsequent first neuron circuit 32 via the output terminal 46. For example, if the spike signal is a first voltage, the synaptic output circuit 44 outputs the synaptic current to the first neuron circuit 32, but if the spike signal is a second voltage, it does not output the synaptic current to the first neuron circuit 32.

[0043] For example, the synapse output circuit 44 is a MOSFET (metal-oxide-semiconductor field-effect transistor). In the example in Figure 3, the synapse output circuit 44 is an N-channel MOSFET. In the N-channel MOSFET synapse output circuit 44, a spike signal is applied to the gate, the drain is connected to the synapse current source 42, and the source is connected to the output terminal 46. The MOSFET synapse output circuit 44 then switches whether or not to allow synapse current to flow between the drain and source in response to the spike signal.

[0044] A first synaptic circuit 30 with this configuration can output a synaptic current of a magnitude corresponding to the synaptic weight (W). Note that the first synaptic circuit 30 is not limited to this configuration; other configurations are also possible.

[0045] Here, the first synaptic circuit 30 forms a parasitic capacitance 48 between the output terminal 46 and the ground terminal. The parasitic capacitance 48 accumulates charge corresponding to the synaptic current output from the synaptic current source 42 during the period when the synaptic output circuit 44 outputs a synaptic current from the output terminal 46, for example, during the period when the spike signal acquired from the preceding neuron circuit 22 is the first voltage.

[0046] The first neuron circuit 32 includes a charge storage circuit 60, a spike output circuit 62, a reset circuit 64, a cutoff circuit 66, and a control circuit 68.

[0047] The charge storage circuit 60 stores charge corresponding to the synaptic current supplied to the second terminal 54. The charge storage circuit 60 sets a membrane potential V corresponding to the stored charge at the second terminal 54. mem Therefore, each time a synaptic current is supplied to the second terminal 54, the charge storage circuit 60 generates a membrane potential V at the second terminal 54. mem This increases the voltage. For example, the charge storage circuit 60 is a capacitor connected between the second terminal 54 and the ground terminal.

[0048] The spike output circuit 62 has a threshold potential V th This is set. The spike output circuit 62 receives the membrane potential V generated from the charge storage circuit 60. mem The threshold potential V th If the value is greater than the specified value, a spike signal is output.

[0049] For example, the spike output circuit 62 includes a comparator 72 mounted on a semiconductor device and a spike generation circuit 74.

[0050] Comparator 72 has a threshold potential V at its inverting input terminal. th The non-inverting input terminal is connected to the second terminal 54. Then, the comparator 72 is given the membrane potential V mem The threshold potential V th It outputs a judgment signal indicating whether it is greater than or less than the membrane potential V. For example, comparator 72 outputs a judgment signal indicating whether it is greater than or less than the membrane potential V. mem The threshold potential V th If it is determined that it is not greater than the first value (e.g., L logic), the membrane potential V will be the first value. mem The threshold potential V th If it is determined to be greater than the specified value, a judgment signal with a secondary value (e.g., H logic) is output.

[0051] The spike generation circuit 74 acquires a determination signal from the comparator 72. The spike generation circuit 74 determines that the acquired determination signal is the membrane potential V mem The threshold potential V th Starting with the first value, which represents not being greater than, the membrane potential V mem The threshold potential V thWhen the value changes to the second value, which represents a greater value, a spike signal is output. More specifically, when the determination signal changes from the first value to the second value, the spike generation circuit 74 generates a spike signal, which is a voltage pulse that changes from the second voltage to the first voltage, and then returns to the second voltage after a certain period of time. The spike generation circuit 74 provides the generated spike signal to each of the one or more synaptic circuits 20 connected downstream of the first neuron circuit 32.

[0052] The reset circuit 64 releases the charge stored in the charge storage circuit 60 in response to a spike signal being output from the spike output circuit 62. For example, the reset circuit 64 releases the charge stored in the charge storage circuit 60 during the period from when the spike signal changes from the second voltage to the first voltage until it returns to the second voltage.

[0053] For example, the reset circuit 64 is a switch connected between the second terminal 54 and the ground terminal. The reset circuit 64 disconnects the connection between the second terminal 54 and the ground terminal when the reset signal output from the control circuit 68 is L logic, and short-circuits the connection between the second terminal 54 and the ground terminal when the reset signal output from the control circuit 68 is H logic. The reset circuit 64 can be implemented, for example, by a MOSFET that is turned on or off by the reset signal.

[0054] This reset circuit 64 releases the charge accumulated in the charge storage circuit 60 to the ground terminal, thereby reducing the membrane potential V generated from the charge storage circuit 60. mem The potential can be returned to its initial potential. The reset circuit 64 then stops the discharge of charge from the charge storage circuit 60 and then allows the charge storage circuit 60 to store charge corresponding to the synaptic current supplied to the second terminal 54.

[0055] The cutoff circuit 66 supplies the synaptic current applied to the first terminal 52 to the charge storage circuit 60 during periods other than the cutoff period, which is a predetermined time after the spike signal is output from the spike output circuit 62. The cutoff circuit 66 also stops supplying the synaptic current applied to the first terminal 52 to the charge storage circuit 60 during the cutoff period. The cutoff circuit 66 is a switch connected between the first terminal 52 and the second terminal 54. For example, if the cutoff signal output from the control circuit 68 is high logic, the cutoff circuit 66 short-circuits the connection between the first terminal 52 and the second terminal 54; if the cutoff signal output from the control circuit 68 is low logic, it disconnects the connection between the first terminal 52 and the second terminal 54. The cutoff circuit 66 can be implemented, for example, by a MOSFET that is switched on or off by the cutoff signal.

[0056] The control circuit 68 controls the reset circuit 64 by supplying a reset signal to it. For example, the control circuit 68 sets the reset signal to high logic during the period when the spike signal is at a first voltage. Also, the control circuit 68 sets the reset signal to low logic during the period when the spike signal is at a second voltage. As a result, the control circuit 68 causes the reset circuit 64 to release the charge stored in the charge storage circuit 60 during the period when the spike signal is at a first voltage, and causes the charge storage circuit 60 to store charge corresponding to the synaptic current during the period when the spike signal is at a second voltage.

[0057] Furthermore, the control circuit 68 controls the cutoff circuit 66 by supplying a cutoff signal to it. For example, the control circuit 68 sets the cutoff signal to L logic from the time the spike signal changes from the second voltage to the first voltage until the cutoff period has elapsed. Also, the control circuit 68 sets the cutoff signal to H logic during periods other than the cutoff period. As a result, the control circuit 68 can supply the synaptic current supplied to the first terminal 52 to the charge storage circuit 60 during periods other than the cutoff period, and stop supplying the synaptic current supplied to the first terminal 52 to the charge storage circuit 60 during the cutoff period.

[0058] The cutoff period may coincide with the period during which the spike signal is at the first voltage, or it may be shorter than the period during which the spike signal is at the first voltage. For example, the cutoff period may end simultaneously with the change in the spike signal from the first voltage to the second voltage, or before the spike signal returns from the first voltage to the second voltage. The cutoff period may also be synchronized with the reset signal. Furthermore, the cutoff period may coincide with the refractory period, which is the period during which the neuron does not respond even when synaptic current is applied.

[0059] Figure 4 is a flowchart showing the processing flow of the first neuron circuit 32. Figure 5 shows the waveforms of the spike signal, reset signal, and cutoff signal.

[0060] The first neuron circuit 32 performs processing according to the flow shown in Figure 4.

[0061] First, in S11, the first neuron circuit 32 receives the membrane potential V generated from the charge storage circuit 60. mem However, the threshold potential V th It determines whether it is greater or less. The first neuron circuit 32 determines the membrane potential V mem The threshold potential V th If it is not greater than (No in S11), the process waits in S11. The first neuron circuit 32 measures the membrane potential V mem The threshold potential V th If it is greater than (Yes in S11), proceed to S12.

[0062] In S12, the first neuron circuit 32 begins outputting a spike signal. That is, as shown in the timing at time t1 in Figure 5, the first neuron circuit 32 changes the spike signal from the second voltage to the first voltage.

[0063] Furthermore, in S12, the first neuron circuit 32 turns on the reset circuit 64. That is, as shown in the timing at time t1 in Figure 5, the first neuron circuit 32 changes the reset signal from L logic to H logic, initiating the release of the charge stored in the charge storage circuit 60 to the ground terminal.

[0064] Furthermore, in S12, the first neuron circuit 32 turns off the cutoff circuit 66. That is, as shown in the timing at time t1 in Figure 5, the first neuron circuit 32 changes the cutoff signal from H logic to L logic, stopping the supply of the synaptic current applied to the first terminal 52 to the charge storage circuit 60.

[0065] Next, in S13, the first neuron circuit 32 starts outputting a spike signal, and then T spike Determine whether time has passed or not. spike Time is the duration of the pulse width of the spike signal, which is a voltage pulse. The first neuron circuit 32 is T spike If time has not elapsed (No in S13), the process waits in S13. The first neuron circuit 32 is T spike If time has elapsed (Yes in S13), proceed to S14.

[0066] In S14, the first neuron circuit 32 begins outputting a spike signal. That is, as shown in the timing at time t2 in Figure 5, the first neuron circuit 32 changes the spike signal from the first voltage to the second voltage.

[0067] Furthermore, in S14, the first neuron circuit 32 turns off the reset circuit 64. That is, as shown in the timing at time t2 in Figure 5, the first neuron circuit 32 changes the reset signal from H logic to L logic, stopping the release of the charge stored in the charge storage circuit 60 to the ground terminal.

[0068] Next, in S15, the first neuron circuit 32 determines whether the cutoff period has elapsed since it began outputting the spike signal. The cutoff period is the period from when the first neuron circuit 32 outputs the spike signal until it does not accept synaptic current input from the preceding first synaptic circuit 30. spike It is longer than the time. If the cutoff period has not elapsed (No in S15), the first neuron circuit 32 waits in S15 before proceeding. If the cutoff period has elapsed (Yes in S15), the first neuron circuit 32 proceeds to S16.

[0069] In S16, the first neuron circuit 32 turns on the cutoff circuit 66. That is, as shown in the timing at time t3 in Figure 5, the first neuron circuit 32 changes the cutoff signal from L logic to H logic, making it possible to supply the synaptic current applied to the first terminal 52 to the charge storage circuit 60.

[0070] Then, after completing the processing in S16, the first neuron circuit 32 returns to processing in S11 and repeats the processing from S11 to S16.

[0071] Figure 6 is a diagram illustrating the components of the synaptic current transferred from the parasitic capacitance 48 to the charge storage circuit 60.

[0072] As shown in Figure 6A, the cutoff circuit 66 disconnects the connection between the first terminal 52 and the second terminal 54 from the start of the spike signal output until the cutoff period has elapsed. Therefore, during the cutoff period, the synaptic current generated from the preceding first synaptic circuit 30 is not supplied to the charge storage circuit 60 of the first neuron circuit 32, but is stored in the parasitic capacitance 48 of the first synaptic circuit 30.

[0073] Then, as shown in Figure 6B, the cutoff circuit 66 short-circuits the first terminal 52 and the second terminal 54 after the cutoff period has ended. When the first terminal 52 and the second terminal 54 are short-circuited, the charge accumulated in the parasitic capacitance 48 of the first synaptic circuit 30 is transferred to the charge storage circuit 60 of the first neuron circuit 32. Therefore, the past synaptic current components that the first neuron circuit 32 did not receive due to the cutoff period are accumulated in the charge storage circuit 60 after the cutoff period has ended.

[0074] In this way, the first neuron circuit 32 receives the components of the synaptic current output from the preceding first synaptic circuit 30 during the cutoff period, after the cutoff period has ended. Therefore, the first neuron circuit 32 can transmit information based on the components of the synaptic current output from the preceding first synaptic circuit 30 during the cutoff period to the subsequent neuron circuit 22.

[0075] As a result, the neural network device 10 according to this embodiment can realize a highly accurate spiking network with reduced information loss. Therefore, the neural network device 10 according to this embodiment can accurately perform neural network calculations that were previously implemented by digital arithmetic circuits such as CPUs, such as arithmetic neural networks.

[0076] (Second Embodiment) Next, the neural network device 10 according to the second embodiment will be described. Since the neural network device 10 according to the second embodiment has substantially the same functions and configuration as the neural network device 10 according to the first embodiment, components having substantially the same functions and configurations will be given the same reference numerals, and detailed descriptions will be omitted except for differences. The same applies to the description of the third embodiment.

[0077] Figure 7 shows the configuration of the first neuron circuit 32 according to the second embodiment.

[0078] The first neuron circuit 32 according to the second embodiment further includes a leak circuit 82.

[0079] The leakage circuit 82 reduces the charge stored in the charge storage circuit 60 over time. The leakage circuit 82 is connected in parallel between the two terminals of the charge storage circuit 60 and causes a leakage current to flow from the second terminal 54 to the ground terminal, leaking the charge stored in the charge storage circuit 60. Therefore, when no synaptic current is supplied, the leakage circuit 82 reduces the membrane potential V generated at the second terminal 54. mem It can be made to descend over time.

[0080] For example, the leakage circuit 82 is a resistive element mounted on the semiconductor device. The resistive element is connected between the second terminal 54 and the ground terminal. The magnitude of the leakage current flowing through the leakage circuit 82 is determined by the resistance value of the resistive element and the film potential V generated from the charge storage circuit 60. mem This is determined by the following: The resistive element has a relatively large resistance value, for example, 100 MΩ or more, and releases the charge stored in the charge storage circuit 60 over a sufficiently long period of time. Alternatively, the resistive element may be composed of a transistor. In this case, the magnitude of the leakage current is determined by the gate voltage of the transistor.

[0081] Thus, the neural network device 10 according to the second embodiment can realize a spiking neural network using a LIF (Leaky integrate-and-fire) type neuron model, since the first neuron circuit 32 further has a leak circuit 82.

[0082] (Third embodiment) Next, we will describe the neural network device 10 according to the third embodiment.

[0083] Figure 8 shows the configuration of the first neuron circuit 32 according to the third embodiment.

[0084] The first neuron circuit 32 according to the third embodiment further includes an auxiliary charge storage circuit 84.

[0085] The auxiliary charge storage circuit 84 is provided before the cutoff circuit 66. The auxiliary charge storage circuit 84 stores charge corresponding to the synaptic current applied to the first terminal 52. For example, the auxiliary charge storage circuit 84 is a capacitor connected between the first terminal 52 and the ground terminal.

[0086] During the cutoff period, the auxiliary charge storage circuit 84 can store charges corresponding to the synaptic current generated from the preceding first synaptic circuit 30, along with the parasitic capacitance 48 of the first synaptic circuit 30. After the cutoff period ends, the charges stored in the auxiliary charge storage circuit 84 are transferred to the charge storage circuit 60 of the first neuron circuit 32.

[0087] The first neuron circuit 32 according to this third embodiment has an auxiliary charge storage circuit 84, which allows it to store more charge during the cutoff period. Therefore, the first neuron circuit 32 according to the third embodiment can store charge without loss even when a large synaptic current is output during the cutoff period. In this way, the neural network device 10 according to the third embodiment can reduce the loss of transmitted information and realize a more accurate spiking network. The auxiliary charge storage circuit 84 may also be applied to the first neuron circuit 32 according to the second embodiment.

[0088] Although embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These novel embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0089] <Note> Furthermore, this technology can also be configured as follows.

[0090] (1) Multiple synaptic circuits, each with its own assigned synaptic weight, Multiple neuronal circuits, each outputting a spike signal which is a voltage pulse, Equipped with, Each of the plurality of synaptic circuits acquires the spike signal output from any one of the plurality of neuronal circuits, and when it acquires the spike signal, it outputs a synaptic current of a current amount corresponding to the set synaptic weight and the spike signal. In the first neuron circuit among the plurality of neuron circuits, the synaptic current is supplied to the first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit is, A charge storage circuit that stores charge corresponding to the synaptic current and generates a membrane potential corresponding to the stored charge, A spike output circuit that outputs the spike signal when the membrane potential is greater than a preset threshold potential, A cutoff circuit that stops supplying the synaptic current from the first terminal to the charge storage circuit during a cutoff period which is a predetermined time after the spike signal is output, has A neural network device.

[0091] (2) The charge storage circuit is a capacitor connected between the second terminal and the ground terminal, and generates the film potential from the second terminal. The cutoff circuit is a switch connected between the first terminal and the second terminal, which short-circuits the connection between the first terminal and the second terminal during the cutoff period and disconnects the connection between the first terminal and the second terminal outside of the cutoff period. The neural network device described in (1) above.

[0092] (3) The first neuron circuit further includes a reset circuit that releases the charge stored in the charge storage circuit in response to the output of the spike signal. The neural network device described in (1) or (2) above.

[0093] (4) The first neuron circuit further includes a leakage circuit that reduces the charge accumulated in the charge storage circuit over time. A neural network device as described in any one of (1) to (3) above.

[0094] (5) The aforementioned leakage circuit is a resistive element connected between the second terminal and the ground terminal. The neural network device described in (4) above.

[0095] (6) The circuit further comprises an auxiliary charge storage circuit provided prior to the cutoff circuit, which stores charge corresponding to the synaptic current. A neural network device as described in any one of (1) to (5) above.

[0096] (7) The auxiliary charge storage circuit is a capacitor connected between the first terminal and the ground terminal. The neural network device described in (6) above.

[0097] (8) A signal processing method in a neural network device, The neural network device is Multiple synaptic circuits, each with its own assigned synaptic weight, Multiple neuronal circuits, each outputting a spike signal which is a voltage pulse, Equipped with, Each of the plurality of synaptic circuits acquires the spike signal output from any one of the plurality of neuronal circuits, and when it acquires the spike signal, it outputs a synaptic current of a current amount corresponding to the set synaptic weight and the spike signal. In the first neuron circuit among the plurality of neuron circuits, the synaptic current is supplied to the first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. For the first neuronal circuit, Charge corresponding to the synaptic current is stored in the charge storage circuit, and a membrane potential corresponding to the charge stored in the charge storage circuit is generated. When the membrane potential is greater than a preset threshold potential, the spike signal is output. During a cutoff period, which is a predetermined time after the output of the spike signal, the supply of the synaptic current from the first terminal to the charge storage circuit is stopped. Signal processing method. [Explanation of symbols]

[0098] 10 Neural Network Devices 20 Synaptic Circuits 22 Neuron Circuits 30. First synaptic circuit 32. First Neuron Circuit 42 Synaptic Current Sources 44 Synaptic Output Circuit 46 output terminals 48 Parasitic capacitance 52 1st terminal 54 2nd terminal 60 Charge storage circuit 62 Spike Output Circuit 64 Reset circuit 66 Cutoff Circuit 68 Control circuits 82 Leakage Circuits 84 Auxiliary charge storage circuit

Claims

1. Multiple synaptic circuits, each with its own assigned synaptic weight, Multiple neuronal circuits, each outputting a spike signal which is a voltage pulse, Equipped with, Each of the plurality of synaptic circuits acquires the spike signal output from any one of the plurality of neuronal circuits, and when it acquires the spike signal, it outputs a synaptic current of a current amount corresponding to the set synaptic weight and the spike signal. In the first neuron circuit among the plurality of neuron circuits, the synaptic current is supplied to the first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. The first neuron circuit is, A charge storage circuit that stores charge corresponding to the synaptic current and generates a membrane potential corresponding to the stored charge, A spike output circuit that outputs the spike signal when the membrane potential is greater than a preset threshold potential, A cutoff circuit that stops supplying the synaptic current from the first terminal to the charge storage circuit during a cutoff period which is a predetermined time after the spike signal is output, has A neural network device.

2. The charge storage circuit is a capacitor connected between the second terminal and the ground terminal, and generates the film potential from the second terminal. The cutoff circuit is a switch connected between the first terminal and the second terminal, which short-circuits the connection between the first terminal and the second terminal during the cutoff period and disconnects the connection between the first terminal and the second terminal outside of the cutoff period. The neural network device according to claim 1.

3. The first neuron circuit further includes a reset circuit that releases the charge stored in the charge storage circuit in response to the output of the spike signal. The neural network device according to claim 1.

4. The first neuron circuit further includes a leakage circuit that reduces the charge accumulated in the charge storage circuit over time. The neural network device according to claim 1.

5. The aforementioned leakage circuit is a resistive element connected between the second terminal and the ground terminal. The neural network device according to claim 4.

6. The circuit further comprises an auxiliary charge storage circuit provided prior to the cutoff circuit, which stores charge corresponding to the synaptic current. The neural network device according to claim 1.

7. The auxiliary charge storage circuit is a capacitor connected between the first terminal and the ground terminal. The neural network device according to claim 6.

8. A signal processing method in a neural network device, The neural network device is Multiple synaptic circuits, each with its own assigned synaptic weight, Multiple neuronal circuits, each outputting a spike signal which is a voltage pulse, Equipped with, Each of the plurality of synaptic circuits acquires the spike signal output from any one of the plurality of neuronal circuits, and when it acquires the spike signal, it outputs a synaptic current of a current amount corresponding to the set synaptic weight and the spike signal. In the first neuron circuit among the plurality of neuron circuits, the synaptic current is supplied to the first terminal from each of the first synaptic circuits among the plurality of synaptic circuits. For the first neuronal circuit, Charge corresponding to the synaptic current is stored in the charge storage circuit, and a membrane potential corresponding to the charge stored in the charge storage circuit is generated. When the membrane potential is greater than a preset threshold potential, the spike signal is output. During a cutoff period, which is a predetermined time after the output of the spike signal, the supply of the synaptic current from the first terminal to the charge storage circuit is stopped. Signal processing method.

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