Transmitting circuit, receiving circuit, transmitting and receiving circuit, and communication device

Abstract

To provide a transmitting circuit that functions correctly using optical signals. [Solution] A transmission circuit according to one embodiment includes an interface, a control circuit, and a photoelectric converter. The interface conforms to a first standard that defines the transmission of serial signals and is configured to receive serial electrical signals. The control circuit is configured to output a first output instruction when it detects that the interface has received a first command instructing a device conforming to the first standard to transition to an idle state. The photoelectric converter converts the received electrical signal into an optical signal, outputs an optical signal, and is configured to output a second command in the form of an optical signal, instructing a transition to an idle state, upon receiving the first output instruction.

Description

Technical Field

[0001] Embodiments generally relate to a transmission circuit, a reception circuit, a transmission / reception circuit, and a communication device.

Background Art

[0002] Devices that communicate with each other via wiring are required to improve communication speed. For improving communication speed, optical signals can be used. Due to the characteristics of optical signals, simply converting an electrical signal into an optical signal may not function properly in some cases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a transmission circuit, a reception circuit, a transmission / reception circuit, and a communication device that function properly using optical signals.

Means for Solving the Problems

[0005] A transmission circuit according to an embodiment includes an interface, a control circuit, and an optoelectronic conversion device. The interface conforms to a first standard that defines the transmission of signals in a serial format and is configured to receive electrical signals in a serial format. The control circuit is configured to output a first issuance instruction when detecting that a first command for instructing a transition to an idle state is received by the interface from a device conforming to the first standard. The optoelectronic conversion device is configured to convert the received electrical signal into an optical signal, output the optical signal, and when receiving the first issuance instruction, instruct the transition to the idle state and output a second command in the form of an optical signal.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a block diagram of a communication system including a transmitting circuit and a receiving circuit according to the first embodiment. [Figure 2] Figure 2 shows the connection configuration of a communication device including a transmitting circuit and a receiving circuit according to the first embodiment. [Figure 3] Figure 3 is a block diagram of a communication device including a transmitting circuit and a receiving circuit according to the first embodiment. [Figure 4] Figure 4 is a block diagram of the transmission circuit of the first embodiment. [Figure 5] Figure 5 is a block diagram of the receiving circuit of the first embodiment. [Figure 6] Figure 6 shows the signals transmitted and received during a certain operation of the transmission circuit of the first embodiment. [Figure 7] Figure 7 shows the signals transmitted and received during a certain operation of the receiving circuit in the first embodiment. [Figure 8] Figure 8 shows the signals transmitted and received during a certain operation of the transmission circuit of the first embodiment. [Figure 9] Figure 9 shows the signals transmitted and received during a certain operation of the receiving circuit in the first embodiment. [Figure 10] Figure 10 shows the state of several components and the information indicated by the signals flowing through the components during the operation of the transmitting and receiving circuits of the first embodiment. [Figure 11] Figure 11 shows an example of the application of the transmitting circuit and receiving circuit of the first embodiment. [Figure 12] Figure 12 shows other application examples of the transmitting and receiving circuits of the first embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may be denoted by additional numbers or letters at the end of their reference numerals to distinguish them from one another.

[0008] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0009] 1. First Embodiment 1.1. Structure Figure 1 is a block diagram of a communication system including a transmitting circuit and a receiving circuit according to the first embodiment. As shown in Figure 1, the communication system 1 includes a plurality of communication devices 3 (3_a and 3_b). Each communication device 3 includes a transmitting circuit and a receiving circuit, as described later. The communication devices 3 are configured to communicate with each other. The communication devices 3 are configured to communicate with each other using optical signals. The communication devices 3 are configured to communicate with each other using optical signals in an optical communication method conforming to any standard.

[0010] Figure 2 shows the configuration of connections for a communication device including a transmitting circuit and a receiving circuit according to the first embodiment. As shown in Figure 2, the communication devices 3 are connected to each other via an optical signal transmission path 4. The optical signal transmission path 4 is configured to transmit optical signals. In one example, the optical signal transmission path 4 transmits differential signals. An example of the optical signal transmission path 4 is an optical fiber. The optical signal transmission path 4 may be included in the communication system 1.

[0011] Figure 3 is a block diagram of a communication device including a transmitting circuit and a receiving circuit according to the first embodiment. As shown in Figure 3, the communication device 3 includes a signal processing circuit 11, a transmitting circuit 13, and a receiving circuit 14. In one example, the signal processing circuit 11, the transmitting circuit 13, and the receiving circuit 14 are contained in one device housed in a single enclosure. In another example, the signal processing circuit 11 and the pair of transmitting circuit 13 and receiving circuit 14 are contained in separate devices.

[0012] The signal processing circuit 11 is a circuit that processes data and signals. The signal processing circuit 11 includes a CPU (Central Processing Unit). The signal processing circuit 11 processes various signals, receives electrical signals, and outputs electrical signals. The signal processing circuit 11 can transmit electrical signals compliant with the serial interface standard. An example of the serial interface is PCIe TM (Peripheral Component Interconnect express TM ). The following description is based on this example. The signal processing circuit 11 can transmit and recognize and interpret electrical signals compliant with the PCIe standard. The electrical signals compliant with the PCIe standard have a serial format. The electrical signals compliant with the PCIe standard transmit information by transitioning between two potentials of different magnitudes (i.e., high potential and low potential). The electrical signals compliant with the PCIe standard transmit (or carry) PCIe data and clocks. The PCIe data is data that the user of the communication device 3 or the device controlling the communication device 3 desires to communicate, and includes physical data such as parameters and commands. The clock indicates the timing of transmission and capture of the PCIe data. The clock is superimposed on the PCIe data.

[0013] The transmission circuit 13 is a circuit that receives an electrical signal and transmits an optical signal based on the received electrical signal. The transmission circuit 13 converts the received electrical signal into an optical signal and outputs the obtained optical signal. The transmission circuit 13 can be connected to the optical signal transmission path 4 and outputs an optical signal toward the optical signal transmission path 4. The transmission circuit 13 can recognize and interpret electrical signals compliant with the PCIe standard. The transmission circuit 13 converts the electrical signals compliant with the PCIe standard into optical signals of an optical communication method compliant with the communication device 3 and outputs the obtained optical signals. The transmission circuit 13 is connected to the signal processing circuit 11 by the wiring LN1 and receives the electrical signal flowing through the wiring LN.In1. The wiring LN1 complies with the PCIe standard and transmits differential signals.

[0014] The receiving circuit 14 is a circuit that receives an optical signal and transmits an electrical signal based on the received optical signal. The receiving circuit 14 converts the received optical signal into an electrical signal and outputs the obtained electrical signal. The receiving circuit 14 can be connected to the optical signal transmission line 4 and receives an optical signal from the optical signal transmission line 4. The receiving circuit 14 can generate an electrical signal compliant with the PCIe standard. The receiving circuit 14 converts an optical signal of an optical communication system compliant with the communication device 3 into an electrical signal compliant with the PCIe standard and outputs the obtained electrical signal. The receiving circuit 14 is connected to the signal processing circuit 11 by the wiring LN2 and outputs an electrical signal to the wiring LN2. The wiring LN2 complies with the PCIe standard and transmits a differential signal.

[0015] Hereinafter, an electrical signal compliant with the PCIe standard may be referred to as a PCIe signal.

[0016] FIG. 4 is a block diagram of the transmission circuit of the first embodiment. As shown in FIG. 4, the transmission circuit 13 includes a PCIe interface 21, a scelch circuit 22, a data sampler 23, a clock / data recovery circuit 24, a buffer 25, a pattern detection circuit 26, a control circuit 27, a command issue circuit 28, a multiplexer 29, and an optoelectronic conversion unit 30.

[0017] The PCIe interface 21 is a component including a circuit, terminals, and firmware for receiving a PCIe signal. The PCIe interface 21 includes terminals compliant with the PCIe standard. The PCIe interface 21 can be connected to a wiring (or connector) compliant with the PCIe standard by the terminals. The PCIe interface 21 can be physically and electrically connected to another device compliant with the PCIe standard by the wiring. The PCIe interface 21 is connected to the signal processing circuit 11 by the wiring LN1. The PCIe interface 21 receives a PCIe signal from the signal processing circuit 11. The PCIe signal may be superimposed with unintentional noise. The PCIe interface 21 can continue to receive noise while no PCIe signal is received.

[0018] The squelch circuit 22 is a circuit that performs squelching and removes noise if it receives noise instead of a signal. The squelch circuit 22 receives PCIe signals from the PCIe interface 21. While the PCIe interface 21 is not receiving PCIe signals, the squelch circuit 22 may receive noise. By performing squelching, the squelch circuit 22 removes noise and does not output a signal if the PCIe interface 21 and the squelch circuit 22 receive noise. If the squelch circuit 22 receives a PCIe signal while the PCIe interface 21 and the squelch circuit 22 are not receiving PCIe signals, it outputs a notification signal NS. On the other hand, the squelch circuit 22 does not output a notification signal NS while the PCIe interface 21 and the squelch circuit 22 are not receiving PCIe signals.

[0019] The data sampler 23 receives a PCIe signal from the PCIe interface 21 and a clock from the clock / data recovery circuit 24. The data sampler 23 uses the received clock to sample the received PCIe signal. Through sampling, the data sampler 23 extracts PCIe data from the received PCIe signal. The PCIe data is extracted from the PCIe signal based on the clock and has a sequence of bits that can be recognized as data by the pattern detection circuit 26. The data sampler 23 outputs the PCIe signal in the form of a sequence of bits that can be recognized as PCIe data.

[0020] The clock / data recovery circuit 24 is a circuit that extracts the clock from data that has a clock superimposed on it. The clock / data recovery circuit 24 receives a PCIe signal from the data sampler 23 and extracts the clock superimposed on the received PCIe signal. The clock / data recovery circuit 24 supplies the extracted clock to the data sampler 23.

[0021] Buffer 25 is a circuit that temporarily stores received data. Buffer 25 receives PCIe signals from the data sampler 23 in the form of a sequence of bits that can be recognized as PCIe data. Buffer 25 stores the received sequence of bits in the order they were received. Buffer 25 also outputs the received sequence of bits in the order they were received. In other words, buffer 25 stores and outputs data in a FIFO (First In First Out) format. Buffer 25 includes registers that store the value of each bit.

[0022] The pattern detection circuit 26 is a circuit that monitors data and detects specific patterns within the data. The pattern detection circuit 26 is connected to the output of each register in the buffer 25. The pattern detection circuit 26 sequentially acquires parallel PCIe data by repeatedly acquiring data that is supplied serially to the buffer 25 and stored across multiple registers. The pattern detection circuit 26 constantly monitors the PCIe data stored in the buffer 25 and detects if the PCIe data contains an EIOS (Electrical Idle Ordered Set) command (or packet). When the pattern detection circuit 26 detects an EIOS command, it outputs a detection signal DS. The EIOS command is defined by the PCIe standard and is used by devices that comply with the PCIe standard. Hereinafter, devices that comply with the PCIe standard, including the communication device 3, may be referred to as PCIe devices. When a PCIe device is ready to enter the L1 state, it sends an EIOS command to the PCIe device with which it communicates and enters the L1 state. A PCIe device that receives an EIOS command also enters the L1 state. When a PCIe device is in the L1 state, it is electrically idle and consumes less power than it does in the L0 state, when it can send and receive data.

[0023] The control circuit 27 is a circuit that controls the switching between the L1 state and a state other than the L1 state of another communication device 3 that communicates with the communication device 3 which includes the transmission circuit 13. When the control circuit 27 receives a detection signal DS from the pattern detection circuit 26, it performs control to instruct the other communication device 3 that communicates with the communication device 3 which includes the transmission circuit 13 to enter the L1 state. When the control circuit 27 receives the detection signal DS, it outputs an idle stay command issuance instruction EI.

[0024] The control circuit 27 receives a notification signal NS from the squelch circuit 22. Once the control circuit 27 receives a detection signal DS, it continuously or repeatedly outputs an idle stay command issuance instruction EI at regular intervals until it receives a notification signal NS. Once the control circuit 27 receives a notification signal NS after having received a detection signal DS, it stops outputting the idle stay command issuance instruction EI and outputs an idle exit command issuance instruction LI.

[0025] The control circuit 27 outputs a selection control signal CS1. The selection control signal CS1 may have at least two values, in one example, two values ​​that differ by one bit. The selection control signal CS1 has a first value while the communication device 3, including the transmitting circuit 13, is in normal mode, in other words, until the control circuit 27 receives the detection signal DS. Normal mode is the mode while the communication device 3 is in a state other than the L1 state. The first value indicates normal mode. The selection control signal CS1 has a second value while the communication device 3, including the transmitting circuit 13, is in L1 mode, in other words, until the control circuit 27 receives the notification signal NS after receiving the detection signal DS. L1 mode is the mode while the communication device 3 is in the L1 state. The second value indicates the L1 state.

[0026] The command issuing circuit 28 is a circuit that generates and outputs an idle stay command (or packet) EC and an idle exit command (or packet) LC. The idle stay command EC and the idle exit command LC are electrical signals and have a serial format. The idle stay command EC has a sequence of multiple bits, and the value of the sequence of bits has a pattern specific to the idle stay command EC. The idle exit command LC has a sequence of multiple bits, and the value of the sequence of bits has a pattern specific to the idle exit command LC.

[0027] The command issuing circuit 28 continuously outputs the idle stay command EC, either continuously or repeatedly at regular intervals, while it continues to receive the idle stay command issuance instruction EI. Alternatively, the command issuing circuit 28 outputs the idle stay command EC each time it receives the idle stay command issuance instruction EI. When the command issuing circuit 28 receives the idle exit command issuance instruction LI, it outputs the idle exit command LC.

[0028] Multiplexer 29 is connected to the output of command issuing circuit 28 at input IN1. Multiplexer 29 is connected to the output of buffer 25 at input IN2. Multiplexer 29 receives a selection control signal CS from control circuit 27. While receiving a selection control signal CS with a value indicating normal mode, multiplexer 29 connects input IN2 to its output. As a result, during normal mode, i.e., until control circuit 27 receives a detection signal DS, multiplexer 29 outputs the PCIe signal received from buffer 25. On the other hand, while receiving a selection control signal CS with a value indicating L1 mode, multiplexer 29 connects input IN1 to its output. As a result, during L1 mode, i.e., from the time control circuit 27 receives the detection signal DS until it receives the broadcast signal NS, multiplexer 29 outputs an idle command or idle exit command. Hereinafter, the signal output from multiplexer 29 may be referred to as transmitted data.

[0029] The photoelectric conversion unit 30 is a unit that includes a circuit for converting an electrical signal received by the photoelectric conversion unit 30 into an optical signal. The photoelectric conversion unit 30 includes a connector that can be connected to the optical signal transmission path 4. The photoelectric conversion unit 30 receives transmission data from the multiplexer 29. The photoelectric conversion unit 30 converts the received transmission data into an optical signal and outputs the resulting optical signal. The photoelectric conversion unit 30 is also referred to as a photoelectric conversion device. The photoelectric conversion unit 30 is also referred to as an electro-optical conversion unit or electro-optical conversion device.

[0030] Figure 5 is a block diagram of the receiving circuit of the first embodiment. As shown in Figure 5, the receiving circuit 14 includes a photoelectric conversion unit 31, a data sampler 32, a clock / data recovery circuit 33, a buffer 34, a pattern detection circuit 35, a control circuit 36, a multiplexer 37, and a PCIe interface 38.

[0031] The photoelectric conversion unit 31 is a unit that includes a circuit to convert the optical signal received by the photoelectric conversion unit 31 into an electrical signal. The photoelectric conversion unit 31 includes a connector that can be connected to the optical signal transmission path 4. The photoelectric conversion unit 31 receives an optical signal from a communication device 3 other than the communication device 3 that includes the receiving circuit 14. The photoelectric conversion unit 31 converts the received optical signal into an electrical signal and outputs the resulting electrical signal. The output electrical signal is sometimes referred to as the received electrical signal. The received electrical signal includes received data superimposed with a clock. The received data is the same as the transmitted data generated in the other communication device 3 that transmitted the optical signal to the communication device 3 that includes the receiving circuit 14, and includes PCIe signals, idle stay command EC, or idle exit command LC. The photoelectric conversion unit 31 is also referred to as a photoelectric converter.

[0032] The data sampler 32 receives an electrical signal from the photoelectric conversion unit 31 and a clock from the clock / data recovery circuit 33. The data sampler 32 uses the received clock to sample the received electrical signal. Through sampling, the data sampler 32 extracts received data from the received electrical signal. The data sampler 32 outputs the extracted received data as a received electrical signal. The extracted received data includes a sequence of bits that can be recognized as PCIe data, an idle stay command EC, or an idle exit command LC.

[0033] The clock / data recovery circuit 33 is a circuit that extracts the clock from data that has a clock superimposed on it. The clock / data recovery circuit 33 receives an electrical signal from the data sampler 32 and extracts the clock superimposed on the received electrical signal. The clock / data recovery circuit 33 supplies the extracted clock to the data sampler 32.

[0034] Buffer 34 is a circuit that temporarily stores received data. Buffer 34 receives an electrical signal from the data sampler 32 in the form of a sequence of bits that can be recognized as received data. Buffer 34 stores the received sequence of bits in the order they were received. Buffer 34 outputs the received sequence of bits in the order they were received. In other words, buffer 34 stores and outputs data in a FIFO (First-In, First-Out) format. Buffer 34 includes registers that store the value of each bit.

[0035] The pattern detection circuit 35 is a circuit that monitors data and detects specific patterns within the data. The pattern detection circuit 35 is connected to the output of each register in the buffer 34. The pattern detection circuit 35 sequentially acquires received data in parallel format by repeatedly acquiring data that is supplied serially to the buffer 34 and stored across multiple registers. The pattern detection circuit 35 constantly monitors the received data stored in the buffer 34 and detects when the received data includes an idle stay command EC and an idle exit command LC. When the pattern detection circuit 35 detects an idle stay command EC, it outputs an idle stay command detection signal XDS. When the pattern detection circuit 35 detects an idle exit command LC, it outputs an idle exit command detection signal LDS.

[0036] The control circuit 36 ​​is a circuit that controls the switching between the L1 state and states other than the L1 state of the communication device 3, which includes the receiving circuit 14. When the control circuit 36 ​​receives the idle stay command detection signal XDS from the pattern detection circuit 35, it outputs an idle stay instruction SI.

[0037] The control circuit 36 ​​outputs a selection control signal CS2. The selection control signal CS2 may have at least two values, in one example, two values ​​that differ by one bit. The selection control signal CS2 has a first value while the communication device 3, including the receiving circuit 14, is in normal mode, in other words, until the control circuit 36 ​​receives the idle stay command detection signal XDS. The first value indicates normal mode. Once the control circuit 36 ​​receives the idle stay command detection signal XDS, it continues to output a second value of the selection control signal CS2 until it receives the idle exit command detection signal LDS. The second value indicates L1 mode. When the control circuit 36, which is outputting the second value of the selection control signal CS2, receives the idle exit command detection signal LDS, it starts outputting the first value of the selection control signal CS2 a certain time after reception.

[0038] Multiplexer 37 is connected to the output of control circuit 36 ​​at input IN1. Multiplexer 37 is connected to the output of buffer 34 at input IN2. Multiplexer 37 receives a selection control signal CS2 from control circuit 36. While receiving a selection control signal CS2 with a value indicating normal mode, multiplexer 37 connects input IN2 to its output. As a result, during normal mode, multiplexer 37 outputs the received electrical signal received from buffer 34. While receiving a selection control signal CS2 with a value indicating L1 mode, multiplexer 37 connects input IN1 to its output. As a result, during L1 mode, multiplexer 37 outputs an idle stay instruction SI.

[0039] The PCIe interface 38 is a component that includes circuitry, terminals, and firmware for transmitting PCIe signals. The PCIe interface 38 includes terminals that comply with the PCIe standard. The PCIe interface 38 can be connected by terminals to wiring (or connectors) that comply with the PCIe standard. The PCIe interface 38 can be physically and electrically connected by wiring to another device that complies with the PCIe standard. The PCIe interface 38 is connected to the signal processing circuit 11 by wiring LN2. The PCIe interface 38 transmits PCIe signals to the signal processing circuit 11.

[0040] 1.2.Operation Figure 6 shows the signals transmitted and received during a certain operation of the transmitting circuit in the first embodiment. The operation shown in Figure 6 begins when the signal processing circuit 11, which is connected to the transmitting circuit 13, outputs EIOS. At the start of the operation shown in Figure 6, the multiplexer 29 has selected input IN2.

[0041] As shown in Figure 6, the transmitting circuit 13 receives EIOS (ST1).

[0042] The received EIOS is output from multiplexer 29 (ST2).

[0043] When the photoelectric conversion unit 30 receives EIOS, it outputs EIOS in the form of an optical signal (ST3).

[0044] When the EIOS output by the signal processing circuit 11 is received by the transmission circuit 13, the pattern detection circuit 26 detects the reception of the EIOS. Upon detection, the pattern detection circuit 26 outputs a detection signal DS (ST4).

[0045] When the control circuit 27 receives the detection signal DS, it outputs a selection control signal CS1 indicating the selection of input IN1 (ST5).

[0046] When the control circuit 27 receives the detection signal DS, it outputs an idle stay command issuance instruction EI (ST6). ST6 may be performed in parallel with ST5.

[0047] When the command issuing circuit 28 receives the idle stay command issuance instruction EI, it issues an idle stay command EC (ST7). The idle stay command EC is received by the photoelectric conversion unit 30 via the multiplexer 29 (ST8).

[0048] When the photoelectric conversion unit 30 receives an idle stay command EC, it outputs the idle stay command EC in the form of an optical signal (ST9). The idle stay command EC is a command in the form of an optical signal that can be recognized by the receiving circuit 14, and is different from EIOS.

[0049] Once EIOS is received by ST1, the control circuit 27 continues to output a selection control signal CS1 indicating the selection of input IN1, and repeatedly outputs an idle stay command issuance instruction EI, until EIEOS is received. As a result, idle stay command EC in the form of an optical signal continues to be transmitted from the time EIOS is received until EIEOS is received again.

[0050] Figure 7 shows the signals transmitted and received during a certain operation of the receiving circuit in the first embodiment. The operation shown in Figure 7 begins when the communication device 3, which is communicating with the communication device 3 including the receiving circuit 14, transmits EIOS, and in one example follows the operation shown in Figure 6. At the start of the operation shown in Figure 7, the multiplexer 37 has selected input IN2.

[0051] As shown in Figure 7, the photoelectric conversion unit 31 receives EIOS in the form of an optical signal (ST11). The EIOS in the form of an optical signal is converted into the form of a PCIe signal.

[0052] The converted EIOS is output from multiplexer 37 (ST12).

[0053] When the PCIe interface 38 receives an EIOS, it outputs an EIOS (ST13). The EIOS is received by the signal processing circuit 11, which is connected to the receiving circuit 14. This causes the signal processing circuit 11 to switch to L1 mode if it is ready to enter L1 mode. In one example, the signal processing circuit 11 is ready to enter L1 mode if it does not have any data to send to another circuit that communicates with it.

[0054] The photoelectric conversion unit 31 receives EIOS and idle stay command EC (ST14).

[0055] When the EIOS and idle command EC are received by the photoelectric conversion unit 31, the pattern detection circuit 35 detects the reception of the EIOS and idle command EC. Upon detection, the pattern detection circuit 35 outputs the EIOS detection signal EIDS and the idle command detection signal XDS (ST15). When the control circuit 36 ​​receives the EIOS detection signal EIDS and the idle stay command detection signal XDS, it outputs a selection control signal CS2 indicating the selection of input IN1 immediately after the EIOS passes through the input IN2 of the multiplexer 37 (equivalently, immediately after receiving the EIOS detection signal EIDS) (ST16).

[0056] When the control circuit 36 ​​receives the idle stay command detection signal XDS, it outputs an idle stay instruction SI (ST17).

[0057] The idle stay instruction SI is output from the multiplexer 37 (ST18).

[0058] When the PCIe interface 38 receives an idle stay instruction SI, the PCIe interface 38 remains in an idle state (ST19). That is, the PCIe interface 38 does not output PCIe signals and maintains wiring L2 in common mode. While in common mode, the pair of wires that transmit differential signals on wiring L2 are both maintained at an intermediate potential. The intermediate potential is the potential between two potentials that the wire can take (i.e., a high potential and a low potential). Wires that transmit electrical signals, including wiring L2, do not transmit information while at an intermediate potential. Due to the maintenance of wiring L2 in common mode, the signal processing circuit 11 connected to the receiving circuit 14 remains in L1 mode.

[0059] Figure 8 shows the signals transmitted and received during a certain operation of the transmitting circuit in the first embodiment. The operation shown in Figure 8 begins when the signal processing circuit 11 connected to the transmitting circuit 13 outputs EIEOS. At the start of the operation shown in Figure 8, the multiplexer 29 has selected input IN1. Immediately before the start of the operation shown in Figure 8, the signal processing circuit 11 connected to the transmitting circuit 13 is in L1 mode and therefore does not output a signal. Therefore, the PCIe interface 21 does not receive a signal.

[0060] As shown in Figure 8, PCIe interface 21 receives EIEOS (ST21).

[0061] When EIEOS is received by the PCIe interface 21, the squelch circuit 22 detects the presence of the signal and outputs a notification signal NS (ST22).

[0062] When the control circuit 27 receives the notification signal NS, it outputs an idle exit command instruction LI (ST23).

[0063] When the command issuing circuit 28 receives the idle exit command issuance instruction LI, it issues the idle exit command LC (ST24).

[0064] The idle exit command LC is received by the photoelectric conversion unit 30 via the multiplexer 29 (ST25).

[0065] When the photoelectric conversion unit 30 receives the idle exit command LC, it outputs an idle exit frame in the form of an optical signal (ST26). The idle exit command LC is a command in the form of an optical signal that can be recognized by the receiving circuit 14, and is different from EIEOS.

[0066] Subsequently, the control circuit 27 continues to output a selection control signal CS1 indicating the selection of input IN2 (ST27). In one example, the control circuit 27 may perform ST27 after a predetermined period of time has elapsed that exceeds the time required from the reception of the notification signal NS (ST22) to the output of the idle exit command LC from the multiplexer 29 (ST25).

[0067] Figure 9 shows the signals transmitted and received during a certain operation of the receiving circuit in the first embodiment. The operation shown in Figure 9 begins when the communication device 3, which is communicating with the communication device 3 including the receiving circuit 14, transmits an idle exit command LC, and follows the operation shown in Figure 8. At the start of the operation shown in Figure 9, the multiplexer 37 has selected input IN1.

[0068] As shown in Figure 9, the photoelectric conversion unit 31 receives an idle exit command LC (ST31). The idle exit command LC, in the form of an optical signal, is converted into an electrical signal.

[0069] The converted idle exit command LC is detected by the pattern detection circuit 35. Upon detection, the pattern detection circuit 35 outputs an idle exit command detection signal LDS (ST32).

[0070] When the control circuit 36 ​​receives the idle exit command detection signal LDS, it continues to output a selection control signal CS2 indicating the selection of input IN2 (ST33).

[0071] According to the PCIe standard, EIEOS is to be transmitted multiple times, and the photoelectric conversion unit 31 receives EIEOS in the form of an optical signal (ST34).

[0072] The received EIEOS is converted into an electrical signal and output from the multiplexer 37 (ST35).

[0073] When the PCIe interface 38 receives an EIEOS, it outputs the received EIEOS (ST36). The EIEOS is received by the signal processing circuit 11, which is connected to the receiving circuit 14. As a result, the signal processing circuit 11 switches to normal mode.

[0074] Figure 10 shows the state of several components and the information indicated by the signals flowing through the components during the operation of the transmitting and receiving circuits of the first embodiment. Figure 10 shows the boundary period between transitioning to L1 mode and exiting L1 mode. Hereinafter, it is assumed that communication device 3_a transmits a signal and communication device 3_b receives a signal from communication device 3_a. The signal processing circuit 11 of communication device 3_a may be referred to as signal processing circuit 11_a, and the signal processing circuit 11 of communication device 3_b may be referred to as signal processing circuit 11_b. The transmitting circuit 13 of communication device 3_a may be referred to as transmitting circuit 13_a, and the receiving circuit 14 of communication device 3_b may be referred to as receiving circuit 14_b.

[0075] Part (a) of Figure 10 shows the modes of the signal processing circuit 11_a. As shown in part (a), the signal processing circuit 11_a transitions from normal mode to L1 mode at time t1, and from L1 mode to normal mode at time t2.

[0076] Part (b) shows the state of the wiring LN1 connecting the signal processing circuit 11_a and the transmission circuit 13_a, and the information indicated by the signals flowing through wiring LN1. As shown in Part (b), the signal processing circuit 11_a transmits EIOS to the transmission circuit 13_a from time t11. Time t11 occurs before time t1. Up until time t1, for the transmission of data and EIOS, wiring LN1 transitions between high and low potentials at timings based on the data and EIOS patterns. The figure simplifies this switching by depicting the periodic switching between high and low potentials.

[0077] From time t1 to time t2, the transmitting circuit 13_a remains in an idle state. Therefore, the wiring LN1 remains in common mode.

[0078] The signal processing circuit 11_a transmits EIEOS, TS1, and EIEOS in sequence from time t2. TS1 is the training sequence. As described above, EIEOS is transmitted multiple times repeatedly. The training sequence defines the operation for returning to normal mode. With the transmission of EIEOS, TS1, and EIEOS, the potential of wiring LN1 switches between high and low potential from time t2.

[0079] Section (c) shows the state of the optical signal transmission path 4 connecting the transmitting circuit 13_a and the receiving circuit 14_b, and the information indicated by the optical signal. As shown in section (c), the optical signal transmission path 4 is in the same state as in section (b) until time t1. On the other hand, as described above, when the transmitting circuit 13_a transmits EIOS, it repeatedly transmits the idle stay command EC until it receives EIEOS. The transmission of the idle stay command EC continues until time t2. Therefore, unlike section (b), the optical signal continues to be output between time t1 and time t2. Then, based on receiving EIEOS at time t2, the transmitting circuit 13_a outputs the idle exit command LC from time t2. Since the multiplexer 37 of the transmitting circuit 13_a selects input IN1 until this output is complete, the EIEOS received by the transmitting circuit 13_a from time t2 is output only partially from the transmitting circuit 13_a and does not function as EIEOS. However, since EIEOS is transmitted repeatedly, subsequent EIEOS can notify the return to normal mode. The training sequence TS1 following the first EIEOS is the same as part (b), except that it is either a PCIe signal or an optical signal.

[0080] Section (d) shows the state of the wiring LN2 connecting the receiving circuit 14_b and the signal processing circuit 11_b, and the information indicated by the signals flowing through wiring LN2. As shown in section (d), the receiving circuit 14_b maintains wiring LN2 in common mode from time t1 by continuously receiving idle stay commands EC from time t1. As a result, no signals flow through wiring LN2, and it remains in an electrically idle state.

[0081] The receiving circuit 14_b receives an idle exit command at time t2, and exits the idle state at time t12, after time t2. Therefore, at time t12, wiring LN2 exits common mode. As described above with reference to section (c), the first EIEOS flowing through wiring LN1 flows only partially through the optical signal transmission path 4 in the form of an optical signal, so the receiving circuit 14_b does not output the first EIEOS to wiring LN2 in its complete form. The training sequence TS1 following the first EIEOS is the same as in section (c), except that it is either a PCIe signal or an optical signal.

[0082] 1.3. Advantages (Effects) According to the first embodiment, PCIe L1 mode can be realized using optical signals, as described below.

[0083] The PCIe standard defines L1 mode. The transmitting PCIe device notifies the receiving PCIe device of the continuation of the idle state during L1 mode by maintaining the signal transmission wiring in common mode. Optical signals may be used to improve the communication speed between PCIe devices. In this case, the electrical signal from the transmitting PCIe device is converted to an optical signal by a photoelectric converter module, and the optical signal is received by the photoelectric converter module of the receiving PCIe device and converted back to an electrical signal. That is, the electrical signal from the transmitting PCIe device is transmitted to the receiving PCIe device via an optical signal. The idle state is also notified using an optical signal. However, there is a lower limit to the frequency of optical signals. Therefore, even if the wiring transmitting the electrical signal is set to common mode for the purpose of notifying the continuation of the idle state of the PCIe device, the optical signal obtained by the conversion of that state operates at the lower limit frequency. As a result, the photoelectric converter module connected to the receiving PCIe device cannot correctly recognize the idle state that the optical signal should notify from the optical signal. Therefore, it is not possible to maintain an idle state using optical signals.

[0084] According to the first embodiment, when the transmitting circuit 13 receives EIOS, it does not convert the common-mode state of the subsequent wiring LN1 that occurs after receiving EIOS into an optical signal, but instead outputs an idle stay command EC to the receiving circuit 14 which communicates with the transmitting circuit 13. The idle stay command EC can be recognized by the receiving circuit 14 which communicates with the transmitting circuit 13, and notifies that it should remain in an idle state. Since the optical signal generated based on the common-mode state is not received by the receiving circuit 14, and instead the idle stay command EC is received by the receiving circuit 14, the receiving circuit 14 can correctly recognize the notification that it should remain in an idle state.

[0085] According to the first embodiment, the transmitting circuit 13 includes a squelch circuit 22. The squelch circuit 22 detects when EIEOS is transmitted from a state where wiring LN1 was in common mode. Upon detection of EIEOS, the transmitting circuit 13 outputs an idle exit command LC to a receiving circuit 14 that communicates with the transmitting circuit 13. The idle exit command LC can be recognized by the receiving circuit 14 that communicates with the transmitting circuit 13 and notifies that the circuit should exit the idle state. In addition, upon detection of EIEOS, the receiving circuit 14 switches to a mode in which it outputs PCIe signals in the form of optical signals. As a result, the transmitting circuit 13 can switch to a mode in which it can output PCIe signals in the form of optical signals in accordance with the switching of wiring LN1 from the idle state to the normal state.

[0086] According to the first embodiment, the receiving circuit 14 recognizes the idle stay command EC, and upon receiving the idle stay command EC, sets the wiring LN2 to an idle state. This notifies the signal processing circuit 11, which is connected to the receiving circuit 14, that it should remain in an idle state.

[0087] According to the first embodiment, the receiving circuit 14 recognizes the idle exit command LC, and upon receiving the idle exit command LC, transmits EIEOS to the signal processing circuit 11 connected to the receiving circuit 14, and switches to a mode that outputs PCIe signals in the form of electrical signals. As a result, the receiving circuit 14 causes the signal processing circuit 11 connected to the receiving circuit 14 to return to normal mode. In other words, according to the first embodiment, the information represented by the electrical signal from the signal processing circuit 11 connected to the transmitting circuit 13 can be correctly transmitted to the signal processing circuit 11 connected to the receiving circuit 14 via an optical signal.

[0088] 1.4. Application Examples Figure 11 shows an example of the application of the transmitting circuit and receiving circuit of the first embodiment. Figure 11 shows the application of the communication device 3 of the first embodiment to a host device, and is a block diagram of the host device.

[0089] As shown in Figure 11, communication device 3_a is a host device, and communication device 3_b is a memory system. Hereinafter, communication device 3_a will be referred to as the host device 100, and communication device 3_b will be referred to as the memory system 200. Communication device 3_a is configured to be connectable to communication device 3_b via an optical signal transmission path 4.

[0090] The host device 100 is a device that processes data using the memory system 200. Examples of the host device 100 include a personal computer and a server in a data center. The signal processing circuit 11 of the host device 100 includes a CPU 101, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, and a PCIe interface 104. The CPU 101, ROM (Read Only Memory) 102, RAM (Random Access Memory) 103, and PCIe interface 104 are connected to each other so that they can communicate with one another.

[0091] The CPU 101 is a circuit that controls the overall operation of the host device 100. The firmware, which is stored in the ROM 102 and loaded onto the RAM 103, is executed by the CPU 101, allowing the host device 100 to perform various operations.

[0092] ROM102 is a non-volatile memory. ROM102 stores programs, including firmware.

[0093] RAM103 is volatile memory. RAM103 temporarily stores data and stores programs stored in ROM102 while the host device 100 is powered. RAM103 also functions as buffer memory.

[0094] The PCIe interface 104 is a component comprising circuits, terminals, and firmware for transmitting and receiving PCIe signals. The PCIe interface 104 includes terminals compliant with the PCIe standard. The PCIe interface 104 can be connected by terminals to PCIe-compliant wiring (or connectors). The PCIe interface 104 can be physically and electrically connected by wiring to another PCIe-compliant device. The PCIe interface 104 is connected to the transmitting circuit 13 by wiring LN1. The PCIe interface 104 is connected to the receiving circuit 14 by wiring LN2.

[0095] Figure 12 shows other application examples of the transmitting and receiving circuits of the first embodiment. Figure 12 shows the application of the communication device 3 of the first embodiment to a memory system 200, and is a block diagram of the memory system 200.

[0096] The memory system 200 is a device for storing data. An example of the memory system 200 is an SD TMThis includes memory cards such as card-type memory cards, UFS (Universal Flash Storage) devices, and SSDs (Solid State Drives). The memory system 200 stores, reads, and erases data in response to requests from the host device 100. The memory system 200 can store, read, and erase data without a request from the host device 100.

[0097] The memory system 200 includes a memory controller 201, a non-volatile memory 202, and a volatile memory 203.

[0098] An example of non-volatile memory 202 includes NAND flash memory. Non-volatile memory 202 includes multiple blocks BLK (BLK0 to BLK3). Each block BLK contains multiple memory cells. Each memory cell stores data non-volatilely. In one example, a block BLK is a data erasure unit.

[0099] An example of volatile memory 203 is DRAM (Dynamic Random Access Memory). Volatile memory 203 stores information such as information about the read voltage used when reading data from non-volatile memory 202.

[0100] The memory controller 201 is a controller that controls the non-volatile memory 202. An example of the form of the memory controller 201 is an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 201 controls the non-volatile memory 202 to perform processing requested by the host device 100. Specifically, the memory controller 201 writes data to the non-volatile memory 202 based on a write request from the host device 100. The memory controller 201 reads data from the non-volatile memory 202 based on a read request from the host device 100 and sends data based on the read data to the host device 100.

[0101] The memory controller 201 includes a CPU 211, ROM 212, RAM 213, non-volatile memory interface (NVMI / F) 214, volatile memory interface (VMI / F) 215, error correction circuit 216, and PCIe interface 217. The CPU 211, ROM 212, RAM 213, non-volatile memory interface 214, volatile memory interface 215, error correction circuit 216, and PCIe interface 217 are connected to each other so that they can communicate with one another.

[0102] The CPU 211 is a circuit that controls the overall operation of the memory controller 201. The memory controller 201 performs various operations by executing firmware stored in the ROM 212 and loaded onto the RAM 213, which is executed by the CPU 211. The firmware is configured to enable the CPU 211 to perform the operations described in each embodiment and to realize the functional blocks described in each embodiment.

[0103] ROM212 is a non-volatile memory. An example of ROM212 is EEPROM. TM It includes (Electrically Erasable Programmable Read Only Memory). ROM212 stores programs, including firmware.

[0104] RAM213 is volatile memory. RAM213 temporarily stores data and retains programs stored in ROM212 while the memory system 200 is powered. Examples of RAM213 include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). RAM213 also functions as buffer memory.

[0105] The non-volatile memory interface 214 is an interface for the memory controller 201 to communicate with the non-volatile memory 202. The non-volatile memory interface 214 includes hardware, or a combination of hardware and software. The non-volatile memory interface 214 is connected to the non-volatile memory 202 by wiring that enables communication in a manner based on the type of non-volatile memory 202. The non-volatile memory interface 214 transmits commands, address information, and write data to the non-volatile memory 202 and receives read data from the non-volatile memory 202. The non-volatile memory interface 214 transmits various control signals to the non-volatile memory 202 for controlling the non-volatile memory 202.

[0106] The volatile memory interface 215 is an interface for the memory controller 201 to communicate with the volatile memory 203. The volatile memory interface 215 includes hardware, or a combination of hardware and software. The volatile memory interface 215 is connected to the volatile memory 203 by wiring that enables communication in a manner based on the type of volatile memory 203. In one example, the volatile memory interface 215 conforms to the DRAM interface standard.

[0107] The error correction circuit 216 is a circuit that performs error detection and correction processing for data written to the non-volatile memory 202 and error detection and correction for data read from the non-volatile memory 202. The error correction circuit 216 may be implemented as an independent, dedicated semiconductor chip, as a circuit formed on a semiconductor substrate, or by the CPU 211 executing firmware. The error correction circuit 216 generates an error correction code from the data written to the non-volatile memory 202 (actual write data). Based on the error correction code generation method, the error correction code generated from this actual write data is added to the actual write data. The actual write data and the error correction code generated from this actual write data are written to the non-volatile memory 202. The error correction circuit 216 decodes the read data using the error correction code.

[0108] The PCIe interface 217 is a component comprising circuits, terminals, and firmware for transmitting and receiving PCIe signals. The PCIe interface 217 includes terminals compliant with the PCIe standard. The PCIe interface 217 can be connected by terminals to PCIe-compliant wiring (or connectors). The PCIe interface 217 can be physically and electrically connected by wiring to another PCIe-compliant device. The PCIe interface 217 is connected to the transmitting circuit 13 by wiring LN1. The PCIe interface 217 is connected to the receiving circuit 14 by wiring LN2.

[0109] The interface described so far, using PCIe as an example, could also be UCIe (Universal Chiplet Interconnect Express).

[0110] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0111] 1... Communication systems, 3...Communication equipment, 4…Optical signal transmission path, 11... Signal processing circuit, 13…Transmitter circuit, 14…Receiving circuit, 21…PCIe interface, 22... Squelch circuit, 23...Data sampler, 24... Clock / data recovery circuit, 25...buffer, 26...Pattern detection circuit, 27...Control circuits, 28... Command issuing circuit, 29... Multiplexer, 30... Photoelectric conversion unit, 31... Photoelectric conversion unit, 32...Data sampler, 33…Clock / data recovery circuit, 34...buffer, 35...Pattern detection circuit, 36...control circuit, 37... Multiplexer, 38…PCIe interface, DS...Detection signal, EI... Instruction to issue an idle stay command, LI...Issue command to exit the idle state. CS1, CS2... Selection control signals, EC... Idle stay command, LC... Idle exit command, XDS... Idle status command detection signal, LDS... Idle Exit Command Detection Signal, EIDS…EIOS detection signal, SI... Idol stay instructions

Claims

1. An interface configured to receive serial electrical signals, conforming to the first standard that defines the transmission of serial signals, A control circuit is configured to output a first issuance instruction when it detects that a first command instructing a device conforming to the first standard to transition to an idle state has been received by the interface, A photoelectric converter is configured to convert an received electrical signal into an optical signal, output the optical signal, and, upon receiving the first issuance instruction, instruct the transition to the idle state and output a second command in the form of an optical signal. A transmitting circuit equipped with the following features.

2. The system further includes a detection circuit connected to the interface, which is configured to output a first signal when it detects that the interface, which has not received the serial electrical signal, has received the serial electrical signal. The control circuit is further configured to output a second issuance instruction upon receiving the first signal. The photoelectric converter is further configured to, upon receiving the second issuance instruction, instruct the device to exit the idle state and output a third command in the form of an optical signal. The transmitting circuit according to claim 1.

3. The control circuit is further configured to transition to a state in which, upon receiving the first signal, it transfers the electrical signal received by the interface to the photoelectric converter. The transmitting circuit according to claim 2.

4. A transmitting circuit according to any one of claims 1 to 3, A signal processing circuit that transmits a signal to the interface, A communication device equipped with the following features.

5. A photoelectric converter configured to convert a received optical signal into an electrical signal and output the electrical signal, A control circuit is configured to output a first issuance instruction when the photoelectric converter detects that it has received a first command and a second command instructing a device conforming to a first standard that defines the transmission of serial signals to transition to an idle state, An interface that conforms to the first standard, outputs a serial electrical signal, and is configured to maintain the output of a common-mode electrical signal upon receiving the first issue instruction, A receiving circuit equipped with the following features.

6. The control circuit is further configured such that, when the photoelectric converter receives a second command after receiving the first command, it transitions to a state in which it transfers an electrical signal based on the optical signal received by the photoelectric converter after the second command to the interface. The receiving circuit according to claim 5.

7. The receiving circuit according to claim 5 or claim 6, A signal processing circuit that receives a signal from the aforementioned interface and processes the received signal, A communication device equipped with the following features.

8. The transmitting circuit according to claim 1, A second photoelectric converter is configured to convert a received optical signal into an electrical signal and output the electrical signal, A second control circuit is configured to output a second issuance instruction when it detects that the second photoelectric converter has received a third command and a fourth command instructing a device conforming to the first standard to transition to an idle state. A second interface, which conforms to the first standard, outputs a serial electrical signal, and is configured to maintain the output of a common-mode electrical signal upon receiving the second issue instruction, A transmitting and receiving circuit equipped with this.

9. The transmitting and receiving circuit according to claim 8, A signal processing circuit that transmits a signal to the interface and receives a signal from the second interface, A communication device equipped with the following features.

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