Memory device

Abstract

To provide a storage device with suppressed malfunctions. [Solution] The first and second inverters are connected between the first and second nodes. The first inverter includes a third transistor connected to the third node. The second inverter includes a fifth transistor connected to the fourth node. The sixth transistor is connected to the gate of the fifth transistor and the third node. The seventh transistor is connected to the gate of the third transistor and the fourth node. The eighth transistor is connected to the gate of the third transistor and the third node. The ninth transistor is connected to the gate of the fifth transistor and the fourth node. At the first time step, the voltages at the gates of the sixth and seventh transistors are lowered; at the second time step, the voltages at the gates of the eighth and ninth transistors are lowered; at the third time step, a state is formed in which the first and second voltages are applied to the first and second nodes; and after the first time step and before the third time step, the voltages at the gates of the sixth and seventh transistors are raised.

Description

Technical Field

[0001] Embodiments generally relate to a memory device.

Background Art

[0002] As a memory device, DRAM (Dynamic Random Access Memory) is known. A memory cell of DRAM includes a capacitor and a transistor. The memory cell holds data based on the electric charge stored in the capacitor. A voltage based on the data of the memory cell targeted for data reading is amplified by a sense amplifier, whereby the stored data is discriminated.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device with suppressed malfunction.

Means for Solving the Problems

[0005] A memory device according to one embodiment includes a capacitor, a first transistor, a first inverter circuit, a second inverter circuit, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The first transistor is connected to the capacitor at its first end. The first inverter circuit is connected between a first node and a second node and includes a p-type second transistor and an n-type third transistor connected in series at the third node. The second inverter circuit is connected between a first node and a second node and includes a p-type fourth transistor and an n-type fifth transistor connected in series at the fourth node. The sixth transistor is connected between the gate of the fifth transistor and the third node and between the second end of the first transistor and the third node. The seventh transistor is connected between the gate of the third transistor and the fourth node. The eighth transistor is connected between the gate of the third transistor and the third node. The ninth transistor is connected between the gate of the fifth transistor and the fourth node. At the first time step, the voltage applied to the gates of the sixth transistor and the seventh transistor is reduced. At the second time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced. At the third time step, a state is formed in which the first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node. At the fourth time step, after the first time step and before the third time step, the voltage applied to the gates of the sixth transistor and the seventh transistor is increased. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows the functional block and related components of the storage device according to the first embodiment. [Figure 2] Figure 2 shows the components of the memory cell of the first embodiment and the connections between the components. [Figure 3]Figure 3 shows some of the components of the sense amplifier of the storage device in the first embodiment and the connections between the components. [Figure 4] Figure 4 schematically shows the potentials over time between data readouts of several wires, nodes, and signals in the storage device of the first embodiment. [Figure 5] Figure 5 schematically shows the potentials over time between some nodes and data readout portions of a first embodiment and reference storage device. [Figure 6] Figure 6 schematically shows, over time, the potentials of several wires, nodes, and signals in a modified memory device of the first embodiment during data readout. [Figure 7] Figure 7 shows some of the components and connections of the sense amplifier of the storage device in the second embodiment. [Figure 8] Figure 8 schematically shows the potentials over time between data readouts of several wirings, nodes, and signals in the storage device of the second embodiment. [Figure 9] Figure 9 schematically shows the potentials over time between some nodes and data readout portions of the storage device in the second embodiment. [Figure 10] Figure 10 schematically shows the potentials over time between data readout of several wirings, nodes, and signals in a modified storage device of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may have additional numbers or letters appended to the end of their reference numerals to distinguish them from one another. Embodiments following a previously described embodiment primarily describe the differences from the previously described embodiment. All descriptions of an embodiment also apply to descriptions of other embodiments unless explicitly or obviously excluded.

[0008] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0009] 1. First Embodiment 1.1.Structure (composition) Figure 1 shows the functional block of a storage device according to the first embodiment. The storage device 1 is a device for storing data. The storage device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a read circuit 18, and a sense amplifier 19.

[0010] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL. Each memory cell MC can store 1 bit of data. Each memory cell MC is connected to one bit line BL and one word line WL. The memory cell MC is connected between the bit line BL and a plate line PL (not shown). The word line WL is associated with a row. The bit line BL is associated with a column. By selecting one row and one column, one memory cell MC is identified.

[0011] The input / output circuit 12 is a circuit that performs input and output of data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, an address signal ADD, and data DAT from outside the storage device 1, for example from the memory controller. The input / output circuit 12 outputs data DAT. When data is written to the storage device 1, data DAT is the written data. When data is read from the storage device 1, data DAT is the read data.

[0012] The control circuit 13 is a circuit that controls the operation of the storage device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. The control circuit 13 controls the write circuit 17 and the read circuit 18 based on the control instructed by the command CMD and the control signal CNT.

[0013] The voltage generation circuit 14 is a circuit that generates various voltages used in the storage device 1. The voltage generation circuit 14 generates a plurality of voltages of different magnitudes based on the control of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0014] The row selection circuit 15 is a circuit that selects a row of the memory cell MC. The row selection circuit 15 receives an address signal ADD from the input / output circuit 12. The row selection circuit 15 uses the voltage received from the voltage generation circuit 14 to put one word line WL associated with the row specified by the received address signal ADD in a selected state.

[0015] The column selection circuit 16 is a circuit that selects a column of the memory cell MC. The column selection circuit 16 receives an address signal ADD from the input / output circuit 12. The column selection circuit 16 uses the voltage received from the voltage generation circuit 14 to put the bit line BL associated with the column specified by the received address signal ADD in a selected state.

[0016] The write circuit 17 is a circuit that controls the writing of data to the memory cell MC. The write circuit 17 receives the data to be written from the input / output circuit 12. The write circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16 based on the control and data of the control circuit 13.

[0017] The read circuit 18 is a circuit that controls the reading of data from the memory cell MC. The read circuit 18 determines the data stored in the memory cell MC based on the control of the control circuit 13. The determined data is supplied to the input / output circuit 12. The read circuit 18 also supplies a plurality of control signals to the sense amplifier 19.

[0018] The sense amplifier 19 is a circuit that determines the data stored in the memory cell MC. The sense amplifier 19 includes a plurality of sense amplifier circuits SAC (not shown). The sense amplifier 19 receives a plurality of voltages from the voltage generation circuit 14 and operates using the received voltages. The sense amplifier 19 amplifies the potential on the bit line BL for determining the data stored in the memory cell MC targeted for data reading during data reading. The determined data is supplied to the input / output circuit 12.

[0019] FIG. 2 shows the components of the memory cell and the connections of the components in the first embodiment. Hereinafter, one of the source and drain of the transistor may be referred to as one end of the transistor, and the other may be referred to as the other end of the transistor.

[0020] As shown in FIG. 2, each memory cell MC includes a cell capacitor CC and an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) CT. The cell capacitor CC is connected to the plate line PL at one end and to one end of the transistor CT at the other end. The cell capacitor CC stores data using the charge accumulated at the node connected to the transistor CT. The node of the cell capacitor CC connected to the transistor CT may hereinafter be referred to as the storage node SN.

[0021] The state of whether a storage node SN is accumulating charge corresponds to the state in which a memory cell MC is storing "1" data or "0" data. For example, a state in which the storage node SN is relatively charged to a positive potential is treated as a state in which the memory cell MC is storing "1" data, and a state in which the storage node SN is not relatively charged to a positive potential is treated as a state in which the memory cell MC is storing "0" data.

[0022] The transistor CT is connected to one bit line BL at its other end and to one word line WL at its gate.

[0023] Figure 3 shows some of the components of the sense amplifier in the first embodiment and the connections of the components. As described above, the sense amplifier 19 includes a plurality of sense amplifier circuits SAC. Figure 3 shows one sense amplifier circuit SAC.

[0024] As shown in Figure 3, each sense amplifier circuit SAC is connected to one bit line BL and node ￣BL. Node ￣BL may hereafter be referred to as the complementary bit line ￣BL. The complementary bit line ￣BL functions as a node with a reference potential (or reference potential). The reference potential is used to determine the data stored in the memory cell MC from which data is to be read.

[0025] The sense amplifier circuit SAC includes p-type MOSFETs TP1 and TP2, and n-type MOSFETs TN1 to TN6. The sense amplifier 19 further includes transistors TN11 and TN12.

[0026] Transistor TP1 is connected between node SAP and node SAt. Node SAP receives a voltage, and in one example, receives a voltage from voltage generation circuit 14. Node SAP receives one of several voltages, including the power supply voltage Vddsa and voltage Vddsa / 2, which is dynamically switched. The power supply voltage Vddsa may have the same magnitude as the power supply voltage Vdd used in the memory device 1, or it may have a different magnitude than the power supply voltage Vdd. Transistor TP1 is connected to node SAc at its gate. Transistor TP1 has an on-resistance of a certain magnitude while it is on. The on-resistance of a transistor is the resistance while the transistor is on.

[0027] Transistor TN1 is connected between node SAt and node SAN. Node SAN receives a voltage, and in one example, receives a voltage from voltage generation circuit 14. Node SAN receives one of several voltages, dynamically switched, including the power supply voltage Vddsa / 2 and the ground voltage (common voltage) Vss. In one example, the ground voltage Vss is 0V, and the following description is based on this example. Transistor TN1 is connected at its gate to one complementary bit line BL. Transistor TN1 has an on-resistance of a certain magnitude.

[0028] Transistor TP2 is connected between node SAP and node SAc. Transistor TP2 is connected to node SAt at its gate. Transistor TP2 has an on-resistance substantially the same as that of transistor TP1. In this specification, "substantially identical" characteristics of two elements mean that although two elements are formed with the aim of being identical, they may not be exactly the same due to unavoidable reasons such as limitations of the techniques for fabricating and / or measuring these elements.

[0029] Transistor TN2 is connected between node SAc and node SAN. Transistor TN2 is connected to the bit line BL at its gate. Transistor TN2 has substantially the same on-resistance as transistor TN1.

[0030] Transistor TN3 is connected between node SAt and the gate of transistor TN1. Transistor TN3 receives the signal OC at its gate. In one example, the signal OC is supplied from the readout circuit 18.

[0031] Transistor TN4 is connected between node SAc and the gate of transistor TN2. Transistor TN4 receives the signal OC at its gate.

[0032] Transistor TN5 is connected between node SAt and bit line BL. Transistor TN5 receives the signal ISO at its gate. In one example, the signal ISO is supplied from readout circuit 18.

[0033] Transistor TN6 is connected between node SAc and the complementary bit line BL. Transistor TN6 receives the signal ISO at its gate.

[0034] Transistor TN11 is connected between at least one bit line BL and node NBP. Node NBP receives a precharge voltage Vpc from voltage generation circuit 14. The precharge voltage Vpc is (Vddsa - Vss) / 2, and based on the example where Vss is 0V, it is Vddsa / 2, and also functions as a reference voltage. Transistor TN11 receives the signal EQ at its gate. In one example, the signal EQ is supplied from readout circuit 18.

[0035] Transistor TN12 is connected between at least one complementary bit line BL and node NBP. Transistor TN12 receives the signal EQ at its gate.

[0036] Transistors TP1 and TN1 constitute inverter circuit IV1, and transistors TP2 and TN2 constitute inverter circuit IV2. While transistors TN5 and TN6 are ON, inverter circuits IV1 and IV2 are cross-connected. That is, the input and output nodes of inverter circuit IV1 are connected to the output and input nodes of inverter circuit IV2, respectively.

[0037] 1.2.Operation Figure 4 schematically shows the potentials of some wiring, nodes, and signals of the memory device of the first embodiment over time. Hereinafter, the memory cell MC from which data is read may be referred to as the selective memory cell MC. The word line WL, whose potential is shown in Figure 4, is the word line WL connected to the selective memory cell MC, and may hereafter be referred to as the selective word line WL. The bit line BL, whose potential is shown in Figure 4, is the bit line BL connected to the selective memory cell MC during data reading, and may hereafter be referred to as the selective bit line BL. The complementary bit line BL connected to the sense amplifier circuit SAC, which is connected to the selective bit line BL, may hereafter be referred to as the selective complementary bit line BL. When a voltage is applied to the wiring or wiring that transmits signals shown in the figure, the wiring has a potential substantially equal to the magnitude of the applied voltage. For example, a power supply voltage Vdd is applied because a certain wiring has a power supply potential Vdd.

[0038] At the start of the period shown in Figure 4, the potentials of each wire and node are as follows: The selection word line WL has the power supply potential Vpp. The power supply potential Vpp is the internal power supply potential and, in one example, has a different magnitude from the power supply voltage Vdd (power supply potential) Vdd. Because the selection word line WL has the power supply potential Vpp, the transistor CT of the selection memory cell MC is turned on, and the cell capacitor CC of the selection memory cell MC is connected to the selection bit line BL.

[0039] The signal EQ has a potential (ground potential) Vss that is substantially the same magnitude as the ground voltage Vss. Therefore, transistors TN11 and TN12 are turned off, and neither the selected bit line BL nor the selected complementary bit line BL is connected to node NBP at the precharge potential Vpc.

[0040] The signal ISO has a power supply potential Vddiso. The power supply potential Vddiso is the internal power supply potential and, in one example, has a different magnitude from the power supply potential Vdd. With the power supply potential Vddiso at the gate, transistor TN5 is turned on, and the selection bit line BL is connected to node SAt via the turned-on transistor TN5. Therefore, the selection bit line BL and node SAt have substantially the same potential. With the power supply potential Vddiso at the gate, transistor TN6 is turned on, and the selection complementary bit line BL is connected to node SAc via the turned-on transistor TN6. Therefore, the selection complementary bit line BL and node SAc have substantially the same potential.

[0041] The signal OC has a ground potential Vss. Because the gate has a ground potential Vss, transistor TN3 is turned off, and therefore the gate of transistor TN1 is disconnected from node SAt. Because the gate has a ground potential Vss, transistor TN4 is turned off, and therefore the gate of transistor TN2 is disconnected from node SAc.

[0042] Node SAP has the power supply potential Vddsa, and node SAN has the ground potential Vss. Therefore, the sense amplifier circuit SAC is powered on, meaning it is operational.

[0043] Based on the potential states described above, one of the selected bit line BL and the selected complementary bit line ￣BL has the power supply potential Vddsa, and the other has the ground potential Vss. Whether the selected bit line BL or the selected complementary bit line ￣BL has the power supply potential Vddsa depends on whether the selected memory cell MC is storing "0" data or "1" data.

[0044] When the selected memory cell MC stores "0" data, the selected bit line BL has a ground potential Vss, and the storage node SN also has a ground potential Vss. On the other hand, when the selected memory cell MC stores "1" data, the selected bit line BL has a power supply potential Vddsa, and the storage node SN also has a power supply potential Vddsa. Hereinafter, when the selected memory cell MC stores "0" data, it may be referred to as the "0" data storage case, and when the selected memory cell MC stores "1" data, it may be referred to as the "1" data storage case. Figure 4 shows the "0" data storage case.

[0045] At time t0, the potential of the selected word line WL is set to the ground potential Vss. Therefore, the transistor CT of the selected memory cell MC is turned off, and the cell capacitor CC of the selected memory cell MC is disconnected from the selected bit line BL. The potential of the selected word line WL may also be set to a negative potential.

[0046] During data retrieval, the period from time t1 to time t2 is the equalization period. At time t1, the potential of node SAP is set to potential Vddsa / 2, and the potential of node SAN is also set to potential Vddsa / 2. Therefore, the sense amplifier circuit SAC does not receive power and does not have the function of amplifying potential. The voltage applied to node SAP and node SAN is (Vddsa + Vss) / 2. Based on the example where the ground voltage Vss is 0V, the applied voltage is voltage Vddsa / 2.

[0047] At time t1, the potential of signal EQ is set to the power supply potential Vddeq. The power supply potential Vddeq is the internal power supply potential and, in one example, has a different magnitude from the power supply potential Vdd. By having the power supply potential Vddeq at the gate, transistors TN11 and TN12 are turned on, and the selected bit line BL and the selected complementary bit line ￣BL are connected to node NBP. As a result, the selected bit line BL and the selected complementary bit line ￣BL are equalized to the same potential. Specifically, the selected bit line BL and the selected complementary bit line ￣BL are precharged to the potential of the precharge voltage Vpc, i.e., potential Vddsa / 2.

[0048] At time t1, the potential of signal OC is set to the power supply potential Vddoc. The power supply potential Vddoc is the internal power supply potential and, in one example, has a different magnitude from the power supply potential Vdd. The presence of the power supply potential Vddoc at the gate turns on transistors TN3 and TN4. Thus, node SAt is connected to the selected complementary bit line BL by the turned-on transistor TN3, and node SAc is connected to the selected bit line BL by the turned-on transistor TN4.

[0049] The period from time t2 to time t3 is the offset cancellation period. At time t2, the potential of signal EQ is set to the ground potential Vss. This terminates the precharging of the selected bit line BL and the selected complementary bit line BL.

[0050] At time t2, the potential of signal ISO is given as potential Vng. Potential Vng is lower than the ground potential Vss. Based on the example where the ground potential Vss is 0V, potential Vng is a negative potential. Having potential Vng at the gate causes transistors TN5 and TN6 to turn off.

[0051] During offset cancellation, the selected bit line BL is disconnected from node SAt, i.e., isolated, because transistor TN5 is off. Similarly, the selected complementary bit line BL is disconnected from node SAc, i.e., isolated, because transistor TN6 is off. Therefore, inverter circuit IV1 (transistors TP1 and TN1) and inverter circuit IV2 (transistors TP2 and TN2) are not cross-connected.

[0052] On the other hand, as described above, node SAt is connected to the selected complementary bit line ￣BL by the ON transistor TN3. Therefore, the potential of node SAt is transferred to the selected complementary bit line ￣BL, and node SAt has substantially the same potential as the selected complementary bit line ￣BL. Also, node SAc is connected to the selected bit line BL by the ON transistor TN4. Therefore, the potential of node SAc is transferred to the selected bit line BL, and node SAc has substantially the same potential as the selected bit line BL.

[0053] At time t2, the potential of node SAP is set to the power supply potential Vddsa, and the potential of node SAN is set to the ground potential Vss.

[0054] At time t2, the end of precharging and the start of isolation cause the potentials of the selected bit line BL and the selected complementary bit line ￣BL to change from the precharging potential (Vddsa / 2). During this change, offset cancellation occurs due to the action of the ON transistors TN3 and TN4. That is, transistor TN1 is turned ON by transistor TN3, and therefore an ON resistance of transistor TN1 is formed between node SAt and node SAN. As a result, a potential is generated at node SAt based on the ratio of the ON resistance of transistor TP1 and the ON resistance of transistor TN1. In general, p-type MOSFETs and n-type MOSFETs have different ON resistances, and the ON resistance of an n-type MOSFET is smaller than that of a p-type MOSFET. Therefore, the potential at node SAt is not an intermediate value between the potential of node SAP and the potential of node SAN, but a potential lower than the intermediate value.

[0055] Furthermore, transistor TN2 is turned on by transistor TN4, and thus an on-resistance of transistor TN2 is formed between node SAc and node SAN. As a result, a potential is generated at node SAc based on the ratio of the on-resistance of transistor TP2 to the on-resistance of transistor TN2. Therefore, for the same reasons described for node SAt, the potential of node SAc is not an intermediate value between the potential of node SAP and the potential of node SAN, but rather a potential lower than the intermediate value.

[0056] The change in the potential of node SAt due to offset cancellation also changes the potential of the selected complementary bit line ￣BL connected to node SAt via transistor TN3. In other words, the potential of node SAt is reflected in the potential of the selected complementary bit line ￣BL. The change in the potential of node SAc due to offset cancellation also changes the potential of the selected bit line BL connected to node SAc via transistor TN4. In other words, the potential of node SAc is reflected in the potential of the selected bit line BL. One of the potentials of the selected bit line BL and the selected complementary bit line ￣BL decreases by a certain positive magnitude ΔV1 from the potential Vddsa / 2, and the other decreases by a certain positive magnitude ΔV2 from the potential Vddsa / 2.

[0057] The difference between ΔV1 and ΔV2 leads to an imbalance between the potential of the selected bit line BL and the reference potential when the selected bit line BL has a higher potential (margin), and the difference between the potential of the selected bit line BL and the reference potential when the selected bit line BL has a lower potential. The difference between ΔV1 and ΔV2 is based on the difference in on-resistance between transistors TP1 and TN1, and the difference in on-resistance between transistors TP2 and TN2. Therefore, at the start of subsequent charge sharing, nodes SAt and SAc have potentials based on the difference in on-resistance between transistors TP1 and TN1, and the difference in on-resistance between transistors TP2 and TN2, respectively. The selected complementary bit line BL and the selected bit line BL are then charged by nodes SAt and SAc, respectively, which have such potentials. Sense is performed based on the potentials of the selected bit line BL and the selected complementary bit line BL charged to such potentials. Therefore, the difference in on-resistance between transistors TP1 and TN1, and the difference in on-resistance between transistors TP2 and TN2 can be equivalently canceled (compensated).

[0058] The period from time t3 to time t4 is the charge-sharing period. At time t3, the potential of node SAP is set to potential Vddsa / 2, and the potential of node SAN is also set to potential Vddsa / 2. As a result, the sense amplifier circuit SAC is unable to amplify the potential.

[0059] At time t3, the potential of signal OC is equal to the ground potential Vss. Having the ground potential Vss at the gate causes transistors TN3 and TN4 to turn off. Also at time t3, the potential of signal ISO is equal to the ground potential Vss. Having the ground potential Vss at the gate also causes transistors TN5 and TN6 to remain off, not turn on.

[0060] During charge sharing, transistors TN4 and TN5 are off, so the selected bit line BL is disconnected from both node SAt and node SAc. Also, because transistors TN3 and TN6 are off, the selected complementary bit line BL is disconnected from both node SAt and node SAc.

[0061] Transistor TN5 has parasitic capacitance between its gate and drain. Due to this capacitance, when the gate potential of transistor TN5 rises and falls, the drain potential (i.e., the potential at node SAt) rises and falls, respectively. Similarly, transistor TN6 has parasitic capacitance between its gate and drain. Due to this capacitance, when the gate potential of transistor TN6 rises and falls, the drain potential (i.e., the potential at node SAc) rises and falls, respectively.

[0062] Transistor TN3 has parasitic capacitance between its gate and drain. Due to this capacitance, when the potential of the gate decreases as the potential of signal OC becomes ground potential Vss at time t3, the potential of the drain (i.e., the potential of node SAt) decreases. On the other hand, as the potential of signal ISO increases at time t3, the potential of node SAt increases through the parasitic capacitance between the gate and drain of transistor TN5. Therefore, the decrease in the potential of node SAt due to the decrease in the potential of signal OC at time t3 is suppressed by the increase in the potential of signal ISO. The amount of increase in the potential of node SAt depends on the parasitic capacitance between the gate and drain of transistor TN5 and the amount of increase in the potential of signal ISO. The amount of increase in the potential of signal ISO depends on the potential Vng. Therefore, the potential Vng is predetermined so that the decrease in the potential of node SAt due to the decrease in the potential of signal OC is suppressed to the desired extent by the increase in the potential of signal ISO.

[0063] Similarly, transistor TN4 has parasitic capacitance between its gate and drain. Due to this capacitance, when the gate potential decreases as the potential of signal OC becomes ground potential Vss at time t3, the drain potential (i.e., the potential of node SAc) decreases. On the other hand, as the potential of signal ISO increases at time t3, the potential of node SAc increases through the parasitic capacitance between the gate and drain of transistor TN6. Therefore, the decrease in the potential of node SAc due to the decrease in the potential of signal OC at time t3 is suppressed by the increase in the potential of signal ISO. The amount of increase in the potential of node SAc depends on the amount of parasitic capacitance between the gate and drain of transistor TN6 and the amount of increase in the potential of signal ISO.

[0064] Furthermore, at time t3, the potential of the selected word line WL is set to potential Vpp. This initiates charge sharing. Through charge sharing, the charge stored on the selected bit line BL is shared with the charge stored on the storage node SN of the selected memory cell MC. As a result, the potential of the selected bit line BL rises or falls based on the data stored in the selected memory cell MC. The potential of the selected bit line BL (and the storage node SN) reaches a state where its magnitude is equal to that of the potential of the selected bit line BL and the potential of the storage node SN.

[0065] In the "0" data storage case (shown in Figure 4), the potential of the selected bit line BL decreases toward the potential of the storage node SN, while the potential of the storage node SN increases toward the potential of the selected bit line BL. The selected bit line BL and the storage node SN reach a state where their potentials are equal in magnitude when the decreasing potential of the selected bit line BL and the rising potential of the storage node SN are equal. The potential of the selected complementary bit line BL is maintained.

[0066] On the other hand, in the "1" data storage case, the potential of the selected bit line BL rises toward the potential of the storage node SN, while the potential of the storage node SN falls toward the potential of the selected bit line BL. The selected bit line BL and the storage node SN reach a state where their potentials are equal in magnitude when the rising potential of the selected bit line BL and the falling potential of the storage node SN are equal. The potential of the selected complementary bit line BL is maintained.

[0067] The period from time t4 to time t5 is the presence period. At time t4, the potential of node SAP is set to the power supply potential Vddsa, and the potential of node SAN is set to the ground potential Vss. This puts the sense amplifier circuit SAC in a state where it can amplify the potential. The sense amplifier circuit SAC raises one of the potentials of node SAt and node SAc to the power supply potential Vddsa, while lowering the other to the ground potential Vss. In the "0" data storage case shown in Figure 4, the potential of node SAt is lowered to the ground potential Vss, and the potential of node SAc is raised to the power supply potential Vddsa. In the "1" data storage case, the potential of node SAt is raised to the power supply potential Vddsa, and the potential of node SAc is lowered to the ground potential Vss.

[0068] From time t5 onward, it is the sense (or main sense) period. At time t5, the potential of signal ISO is set to the power supply potential Vddiso. This turns on transistors TN5 and TN6. As a result, node SAt is connected to the selected bit line BL via transistor TN5, and node SAc is connected to the selected complementary bit line ￣BL via transistor TN6. Therefore, in the "0" data storage case shown in Figure 4, the potential of the selected bit line BL is lowered to the ground potential Vss, and the potential of the selected complementary bit line ￣BL is raised to the power supply potential Vddsa. In the "1" data storage case, the potential of the selected bit line BL is raised to the power supply potential Vddsa, and the potential of the selected complementary bit line ￣BL is lowered to the ground potential Vss.

[0069] 1.3. Advantages (Effects) According to the first embodiment, a storage device is provided that can determine the data stored in a memory cell with high reliability, as described below.

[0070] For comparison, a reference memory device is described. The reference memory device includes the sense amplifier circuit SAC of memory device 1. On the other hand, the reference memory device differs from memory device 1 in terms of the change in the potential of the signal ISO.

[0071] Figure 5 schematically shows the potentials of several elements of the first embodiment and a reference storage device over time during data retrieval, showing the potentials of signals and nodes. In part (a), Figure 5 shows the potentials of signals and nodes of the reference storage device, and in part (b), it shows the potentials of signals and nodes of storage device 1.

[0072] Due to offset cancellation, at the end of the offset cancellation, node SAt holds a potential that eliminates the difference between the driving force of transistor TP1 and the driving force of transistor TN1, and node SAc holds a potential that eliminates the difference between the driving force of transistor TP2 and the driving force of transistor TN1.

[0073] In the reference memory device, the potential of signal ISO is maintained at ground potential Vss from time t2 until time t3. As shown above with reference to Figure 4, when the potential of signal OC is set to ground potential Vss at time t3, the potentials of nodes SAt and SAc rapidly decrease from time t3. As a result, the state formed by offset cancellation is disrupted, and the driving force of transistor TP1 becomes greater than that of transistor TN1, and the driving force of transistor TP2 becomes greater than that of transistor TN2. Consequently, the potential of node SAt rises, creating a state where it is easy to determine that the memory cell MC is storing "1" data. Therefore, it may be incorrectly determined that "1" data is stored in the case of "0" data storage.

[0074] According to the first embodiment, the potential of signal ISO is lowered below the ground potential Vss at the start of offset cancellation, and is raised to the ground potential Vss at substantially the same time that the potential of signal OC is lowered to the ground potential Vss. Therefore, the decrease in the potential of node SAt due to the decrease in the potential of signal OC at time t3 is suppressed by the increase in the potential of signal ISO. Thus, as shown in part (b) of Figure 5, at time t3, the potential of node SAt is close to the potential immediately before time t3. Therefore, the condition that is formed when "1" data is stored in a "0" data storage case is unlikely to occur. Thus, the storage device 1 can read data from the selected memory cell MC with high reliability.

[0075] 1.4. Variations The potential changes of some of the wiring, nodes, and signals shown in Figure 4 are examples, and it is not necessary for the changes described as occurring at the same time to occur at the same time. For example, for equalization to be performed, the potential changes of signals EQ and OC, and nodes SAP and SAN do not have to be the same; it is sufficient that the state described as occurring from time t1 to time t2 occurs during the equalization period.

[0076] The potential of the word line WL may be Vpp after time t3.

[0077] The potential of signal ISO may be potential Vng before or after the decrease in the potential of signal EQ to potential Vss, and / or the change in the potentials of nodes SAP and SAN.

[0078] The potential of signal ISO may be set to potential Vss either before or after the decrease in the potential of signal OC to potential Vss. As shown in Figure 6, the potential of signal ISO only needs to be raised at least before the start of the presence (time t4). This also provides the advantages described above.

[0079] 2. Second Embodiment Figure 7 shows some of the components and connections of the sense amplifier of the storage device in the second embodiment. As shown in Figure 7, the sense amplifier circuit SAC of the storage device 1 in the second embodiment further includes p-type MOSFETs TP3 and TP4.

[0080] Transistor TP3 is connected between node SAt and the gate of transistor TN1. Transistor TP3 receives the signal ￣OC at its gate. The signal ￣OC has a logic level that is the inverted logic level of the signal OC. In one example, the signal ￣OC is supplied from the readout circuit 18. Transistor TP3 has a parasitic capacitance between its gate and drain, which is of a similar magnitude to the parasitic capacitance between the gate and drain of transistor TN3. In one example, transistor TP3 has a parasitic capacitance between its gate and drain that is substantially the same magnitude as the parasitic capacitance between the gate and drain of transistor TN3.

[0081] Transistor TP4 is connected between node SAc and the gate of transistor TN2. Transistor TP4 receives the signal ∫OC at its gate. Transistor TP4 has a parasitic capacitance between its gate and drain, which is of a similar magnitude to the parasitic capacitance between the gate and drain of transistor TN4. In one example, transistor TP4 has a parasitic capacitance between its gate and drain that is substantially the same magnitude as the parasitic capacitance between the gate and drain of transistor TN4.

[0082] Figure 8 schematically shows the potentials of several elements of the storage device in the second embodiment over time during data retrieval. As shown in Figure 8, signal ∫OC has a change opposite to the change in potential of signal OC. That is, signal ∫OC has a ground potential Vss while signal OC has a power supply potential Vddoc, and has a power supply potential Vddoc while signal OC has a ground potential Vss.

[0083] The potential of signal ISO is changed to the ground potential Vss at time t2, replacing the potential Vng in the first embodiment, and is maintained at Vss until time t5.

[0084] Figure 9 schematically shows the potentials of several nodes and signals in the storage device of the second embodiment over time. As described above with reference to Figure 8 and as shown in Figure 9, at time t3, the potential of signal OC is raised from the ground potential Vss to the power supply potential Vddoc.

[0085] Due to the parasitic capacitance between the gate and drain of transistor TP3, when the potential of the signal OC becomes equal to the power supply potential Vddoc at time t3, the gate potential rises, and the drain potential (i.e., the potential of node SAt) rises. On the other hand, as described above with reference to Figure 4 of the first embodiment, due to the parasitic capacitance of transistor TN3, when the potential of the signal OC becomes equal to the ground potential Vss at time t3, the gate potential falls, and the drain potential (i.e., the potential of node SAt) falls. However, the rise in the potential of node SAt due to the parasitic capacitance of transistor TP3 suppresses the fall in the potential of node SAt due to the parasitic capacitance of transistor TN3. Therefore, even after time t3, the potential of node SAt remains almost unchanged from the potential before time t3.

[0086] Similarly, due to the parasitic capacitance between the gate and drain of transistor TP4, when the potential of the signal OC becomes equal to the power supply potential Vddoc at time t3, the gate potential rises, and the drain potential (i.e., the potential of node SAc) rises. On the other hand, as described above with reference to Figure 4 of the first embodiment, when the potential of the gate decreases due to the parasitic capacitance of transistor TN4, when the potential of the signal OC becomes equal to the ground potential Vss at time t3, the drain potential (i.e., the potential of node SAc) decreases. However, the rise in the potential of node SAc due to the parasitic capacitance of transistor TP4 suppresses the decrease in the potential of node SAc due to the parasitic capacitance of transistor TN4. Therefore, even after time t3, the potential of node SAc remains almost unchanged from the potential before time t3.

[0087] According to the second embodiment, a transistor TP3 is provided between node SAt and the gate of transistor TN1, and a transistor TP4 is provided between node SAc and the gate of transistor TN2. Transistors TP3 and TP4 receive the signal ∫OC at their gates. Therefore, the decrease in the potential of nodes SAt and SAc due to the decrease in the potential of the signal ∫OC transmitted through transistors TN3 and TN4 is suppressed by the increase in the potential of nodes SAt and SAc due to the increase in the signal ∫OC transmitted through transistors TP3 and TP4. For this reason, the memory device 1 can read data from the selected memory cell MC with high reliability, based on the same principle as in the first embodiment.

[0088] The signal-OS potential may be Vddoc before or after the decrease in the signal OC potential to the potential Vss. As shown in Figure 10, the signal-OS potential only needs to be raised at least before the start of presence (time t4). This also yields the advantages described above.

[0089] The second embodiment may be combined with the first embodiment.

[0090] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0091] 1...Storage device, 11…Memory cell array, 12…Input / Output Circuits, 13…Control circuits, 14…Voltage generation circuit, 15... Row selection circuit, 16…Column selection circuit, 17…Writing circuit, 18...Read circuit, 19...Sense Amp, MC…Memory cell WL... Word line, BL... bit line, CC... Cell Capacitor, PL...plate wire, CT...transistor, SN... Storage node, BL…Complementary bit line, SAC...Sense amplifier circuit, SAP... Node, SAN…node, SAt...node, SAc... node, OC...Signal, ISO…signal,

Claims

1. Capacitor and, A first transistor connected to the capacitor at its first end, A first inverter circuit is connected between the first node and the second node, and includes a p-type second transistor and an n-type third transistor connected in series at the third node. A second inverter circuit is connected between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor connected in series at the fourth node, A sixth transistor connected between the gate of the fifth transistor and the third node and between the second end of the first transistor and the third node, A seventh transistor connected between the gate of the third transistor and the fourth node, An eighth transistor connected between the gate and the third node of the third transistor, A ninth transistor connected between the gate of the fifth transistor and the fourth node, Equipped with, At the first time step, the voltage applied to the gates of the sixth transistor and the seventh transistor is reduced. At the second time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced. At the third time step, a state is formed in which a first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node. At a fourth time point, after the first time point but before the third time point, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor is increased. storage device.

2. At the first time step, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor is reduced from a voltage that turns on the sixth transistor and the seventh transistor to a voltage that turns off the sixth transistor and the seventh transistor. The storage device according to claim 1.

3. The voltage applied to the gates of the sixth transistor and the seventh transistor at the fourth time is a voltage that turns off the sixth transistor and the seventh transistor. The storage device according to claim 2.

4. From the first time step to the fourth time step, the voltage that turns off the sixth transistor and the seventh transistor is continuously applied to the gate of the sixth transistor and the gate of the seventh transistor. The storage device according to claim 3.

5. At the second time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced from a voltage that turns on the eighth and ninth transistors to a voltage that turns off the eighth and ninth transistors. The storage device according to claim 4.

6. At a fifth time point, after the third time point, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor is increased from a voltage that turns off the sixth and seventh transistors to a voltage that turns on the sixth and seventh transistors. The storage device according to claim 3.

7. The voltage applied to the gates of the sixth transistor and the seventh transistor at the fourth time is a voltage that turns off the sixth transistor and the seventh transistor. The storage device according to claim 1.

8. At the second time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced from a voltage that turns on the eighth and ninth transistors to a voltage that turns off the eighth and ninth transistors. The storage device according to claim 1.

9. Capacitor and, A first transistor connected to the capacitor at its first end, A first inverter circuit is connected between the first node and the second node, and includes a p-type second transistor and an n-type third transistor connected in series at the third node. A second inverter circuit is connected between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor connected in series at the fourth node, A sixth transistor connected between the gate of the fifth transistor and the third node and between the second end of the first transistor and the third node, A seventh transistor connected between the gate of the third transistor and the fourth node, An n-type eighth transistor is connected between the gate and the third node of the third transistor, An n-type ninth transistor is connected between the gate and the fourth node of the fifth transistor, A p-type tenth transistor is connected between the gate and the third node of the third transistor, A p-type 11th transistor is connected between the gate and the 4th node of the 5th transistor, A storage device equipped with the following features.

10. The gates of the 10th transistor and the 11th transistor receive a third voltage while the gates of the 8th transistor and the 9th transistor receive a second voltage that is higher than the first voltage. The gates of the 10th transistor and the 11th transistor receive a fourth voltage higher than the third voltage while the gates of the 8th transistor and the 9th transistor receive the first voltage. The storage device according to claim 9.

11. At the first time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced. At the second time step, a state is formed in which a fifth voltage is applied to the first node and a sixth voltage lower than the fifth voltage is applied to the second node. Between the first time point and the third time point, which is before the second time point, the voltage applied to the gates of the tenth transistor and the eleventh transistor is increased. The storage device according to claim 9.

12. The third time is the same time as the first time, or it is later than the first time and earlier than the second time. The storage device according to claim 11.

13. At the first time step, the voltage applied to the gates of the eighth transistor and the ninth transistor is reduced from a voltage that turns on the eighth and ninth transistors to a voltage that turns off the eighth and ninth transistors. The storage device according to claim 11 or claim 12.

14. At the third time step, the voltage applied to the gates of the 10th transistor and the 11th transistor is increased from a voltage that turns on the 10th and 11th transistors to a voltage that turns off the 10th and 11th transistors. The storage device according to claim 13.

Images