Data decompression device, memory system, and method

Abstract

To provide a data decompression device that improves throughput. [Solution] The data decompression device according to the embodiment comprises a dictionary having at least one first dictionary and at least one second dictionary that store uncompressed data corresponding to compressed data having an offset indicating the storage location of the dictionary; an allocation circuit that assigns compressed data to at least one of the first or second dictionaries; and a reference circuit that reads uncompressed data from the dictionary. The storage size of the first dictionary is larger than the storage size of the second dictionary. The allocation circuit assigns the first and second compressed data to separate dictionaries in the first or second dictionary based on the first and second offsets. The reference circuit performs dictionary reading of the first uncompressed data using the first offset and reading of the second uncompressed data using the second offset in parallel.

Description

Technical Field

[0001] Embodiments of the present invention relate to a data expansion device, a memory system, and a method.

Background Art

[0002] In recent years, the amount of data handled by information processing systems has been increasing. In order to reduce the amount of data to be stored, dictionary compression type data compression devices have been developed. An example of a data compression device includes a dictionary compression circuit and an entropy encoding circuit.

[0003] The dictionary compression circuit includes a dictionary (also referred to as a history buffer) that stores a history of past input data, that is, a history of uncompressed data, for a certain size. The dictionary compression circuit generates information (referred to as match length) indicating which storage position (referred to as offset) of the dictionary the input data matches with the uncompressed data and the length of the match. The pair of offset and match length is referred to as match information. When it is expected that the data size of the match information is smaller than the data size of the input data, the dictionary compression circuit replaces the input data with the match information. By this replacement, the dictionary compression circuit compresses the input data.

[0004] The entropy encoding circuit compresses the data as a whole by assigning codewords with different code lengths to individual match information using the difference in the appearance frequency of the match information.

[0005] A data expansion device that expands compressed data generated by such a data compression device includes an entropy decoding circuit and a dictionary expansion circuit.

[0006] The entropy decoding circuit decodes the compressed data to restore the match information. The dictionary expansion circuit includes a dictionary that stores uncompressed data generated in the past. The dictionary expansion circuit refers to the dictionary based on the match information and generates uncompressed data corresponding to the expansion result of the compressed data.

[0007] Data compression devices are required to compress data with high throughput. Data decompression devices are required to decompress data with high throughput. In order to increase the throughput of a dictionary-style decompression circuit, the dictionary-style decompression circuit needs to restore multiple match information in one clock cycle, that is, it needs to refer to the dictionary multiple times in one cycle.

[0008] In dictionary-based compression, the minimum match length is determined by the compression algorithm. For example, gzip has a minimum match length of 3 bytes. If the throughput required for the data decompressor is 4 bytes / cycle or more, the dictionary-based decompression circuit needs to recover multiple match information in one cycle, resulting in multiple dictionary lookups occurring simultaneously in a single cycle. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] U.S. Patent No. 9973205 [Patent Document 2] U.S. Patent Application Publication No. 2023 / 289293 [Patent Document 3] U.S. Patent Application Publication No. 2021 / 89501 [Patent Document 4] U.S. Patent Application Publication No. 2017 / 192708 [Overview of the project] [Problems that the invention aims to solve]

[0010] The object of the present invention is to provide a data decompression device, memory system, and method that improve throughput. [Means for solving the problem]

[0011] The data decompression device according to the embodiment decompresses a compressed data sequence including first compressed data having a first offset obtained by dictionary-style compression. The data decompression device comprises a dictionary having at least one first dictionary and at least one second dictionary that store first uncompressed data corresponding to the first compressed data; an assignment circuit that assigns the first compressed data to at least one of the at least one first dictionary or at least one second dictionary; a reference circuit that reads the first uncompressed data from the at least one dictionary to which the first compressed data is assigned using a first offset; and a generation circuit that generates an uncompressed data sequence including the first uncompressed data read by the reference circuit. The storage size of each of the at least one first dictionary is greater than the storage size of each of the at least one second dictionary. The first offset indicates a storage location in at least one of the at least one first dictionary or at least one second dictionary. The allocation circuit allocates the first compressed data to at least one of at least one first dictionary or at least one second dictionary based on a first offset. If the compressed data sequence includes second compressed data having a second offset indicating the storage location of at least one of the at least one first dictionary or at least one second dictionary, the allocation circuit further allocates the second compressed data to at least one of the at least one first dictionary or at least one second dictionary, which is different from the dictionary to which the first compressed data was allocated, based on a second offset. The reference circuit then performs in parallel the reading of the first uncompressed data from the dictionary to which the first compressed data was allocated using the first offset, and the reading of the second uncompressed data corresponding to the second compressed data from the dictionary to which the second compressed data was allocated using the second offset. The generation circuit generates an uncompressed data sequence containing the first uncompressed data and the second uncompressed data. [Brief explanation of the drawing]

[0012] [Figure 1] A block diagram illustrating an example of an information processing system including a data decompression device according to an embodiment. [Figure 2]A diagram for explaining an example of a compressed stream according to an embodiment. [Figure 3] A diagram for explaining an example of data generated in dictionary compression according to an embodiment and data generated in entropy encoding. [Figure 4] A diagram for explaining an example of data generated in entropy decoding according to an embodiment and data generated in dictionary expansion. [Figure 5] A block diagram for explaining an example of a data compression device according to an embodiment. [Figure 6] A block diagram for explaining an example of a data expansion device according to an embodiment. [Figure 7] A block diagram for explaining an example of a dictionary expansion circuit according to an embodiment. [Figure 8] A flowchart for explaining an example of the processing of a dictionary expansion circuit according to an embodiment. [Figure 9] A flowchart for explaining an example of the processing of a dictionary expansion circuit according to an embodiment. [Figure 10] A flowchart for explaining an example of the processing of a dictionary expansion circuit according to an embodiment. [Figure 11] A block diagram for explaining an example of a dictionary expansion circuit according to a comparative example. [Figure 12] A diagram for explaining and comparing the throughput of a dictionary expansion circuit according to an embodiment with the throughput of a comparative example. [Figure 13] A diagram for explaining an example of a dictionary according to an embodiment. [Figure 14] A diagram for explaining an example of reading from a dictionary composed of SRAM with one write / read port according to an embodiment. [Figure 15] A diagram for explaining another example of a dictionary according to an embodiment. [Figure 16] A diagram for explaining yet another example of a dictionary according to an embodiment. [Figure 17] A diagram for explaining yet another example of a dictionary according to an embodiment. [Figure 18]A diagram illustrating another example of a multiport SRAM according to the embodiment. [Figure 19] A diagram illustrating yet another example of a dictionary according to the embodiment. [Figure 20] A diagram illustrating yet another example of a dictionary according to the embodiment. [Figure 21] A diagram illustrating yet another example of a dictionary according to the embodiment. [Figure 22] A diagram illustrating yet another example of a dictionary according to the embodiment. [Figure 23] Figure 22 is a diagram illustrating an example of writing to the dictionary circuit shown. [Figure 24] Figure 22 is a diagram illustrating an example of a dictionary circuit readout. [Figure 25] Figure 22 illustrates another example of writing to the dictionary circuit shown. [Figure 26] A flowchart illustrating an example of the processing of a dictionary-style expansion circuit in a modified form. [Modes for carrying out the invention]

[0013] The embodiments will be described below with reference to the drawings. The following description illustrates devices and methods for realizing the technical concept of the embodiments, and the technical concept of the embodiments is not limited to the structure, shape, arrangement, material, etc. of the components described below. Modifications that a person skilled in the art can easily conceive of are naturally included in the scope of disclosure. In order to make the explanation clearer, the size, thickness, planar dimensions, or shape of each element may be schematically represented in the drawings with changes from the actual elements. Multiple drawings may include elements with different dimensional relationships or ratios. In multiple drawings, the same reference numeral may be used for corresponding elements to omit redundant explanations. Some elements may be given multiple names, but these examples of names are merely illustrative and do not preclude the use of other names for these elements. Elements that do not have multiple names may also be given other names. "Connection" may include not only direct connections but also connections via other elements. If the number of elements is not explicitly stated as multiple, the element may be singular or plural.

[0014] [Embodiment] Figure 1 is a block diagram illustrating an example of an information processing system 1 including a data decompression device according to an embodiment. The information processing system 1 includes a host device (referred to as the host) 2 and a memory system 3.

[0015] Host 2 is an information processing device that writes data to and reads data from memory system 3. An example of Host 2 is a storage server or personal computer that handles large amounts of diverse data.

[0016] Memory system 3 is a semiconductor storage device configured to write data to non-volatile memory and read data from non-volatile memory. An example of non-volatile memory is NAND flash memory 4. Memory system 3 may be implemented as a solid-state drive (SSD). The following example illustrates the case where memory system 3 is implemented as an SSD. However, memory system 3 may also be implemented as a hard disk drive (HDD).

[0017] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2 or it may be connected to the host 2 via a cable or network.

[0018] The interfaces for connecting host 2 and memory system 3 are SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), and PCI Express. TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM It complies with standards such as ).

[0019] The memory system 3 may include NAND flash memory 4, dynamic random access memory (DRAM) 5, and a controller 6.

[0020] The NAND flash memory 4 includes one or more memory chips. Each memory chip includes multiple blocks. A single block functions as the smallest unit of data erasure operation. A block may also be referred to as an erase block or physical block. Each of the multiple blocks includes multiple pages. Each of the multiple pages includes multiple memory cells connected to a single word line. A single page functions as the unit of write and read operations. The word line may also function as the unit of write and read operations.

[0021] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, referred to as the maximum P / E cycles. One P / E cycle for a block includes an erase operation to erase all memory cells in that block and a write operation to write data to each page of that block.

[0022] DRAM5 is volatile memory. The memory area of ​​DRAM5 is allocated as various regions. Examples of these regions include the firmware memory area, the logical-physical address translation table cache area, and the user data buffer area.

[0023] Controller 6 is a memory controller that controls the NAND flash memory 4 and DRAM 5. An example of controller 6 may be implemented by a circuit such as a System-on-a-chip (SoC). Controller 6 may have built-in static random access memory (SRAM) or DRAM. In this case, an external DRAM 5 is not required to be provided outside of controller 6.

[0024] The controller 6 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 4. Examples of data management performed by this FTL include (1) managing mapping information representing the correspondence between logical addresses and physical addresses of the NAND flash memory 4, and (2) processing to conceal the difference between page-level read / write operations and block-level data erase operations. Examples of block management include bad block management, wear leveling, and garbage collection.

[0025] Logical addresses are used by host 2 to address memory areas in memory system 3. An example of a logical address is a logical block address (LBA).

[0026] The management of the mapping between logical addresses and physical addresses may be performed using a logical-physical address translation table. The controller 6 uses the logical-physical address translation table to manage the mapping between logical addresses and physical addresses in specific management size units. The physical address corresponding to a given logical address represents the physical storage location in the NAND flash memory 4 where the user data for that logical address is written. The logical-physical address translation table may be loaded from the NAND flash memory 4 into the DRAM 5 when the memory system 3 is started.

[0027] Data can only be written to a single page once per P / E cycle. Therefore, the controller 6 writes updated user data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where previous user data corresponding to that logical address is stored. The controller 6 invalidates the previous user data by updating the logical-physical address translation table to associate the logical address with this different physical memory location.

[0028] The controller 6 may include a CPU 11, a NAND interface (NAND I / F) circuit 12, a DRAM interface (DRAM I / F) circuit 13, a host interface (Host I / F) circuit 14, a data compression device 15, and a data decompression device 16. The CPU 11, NAND I / F circuit 12, DRAM I / F circuit 13, Host I / F circuit 14, data compression device 15, and data decompression device 16 may be connected via a bus 10.

[0029] The CPU 11 is a processor configured to control the NAND I / F circuit 12, the DRAM I / F circuit 13, the host I / F circuit 14, the data compression device 15, and the data decompression device 16. The CPU 11 performs various processes by executing firmware loaded from the NAND flash memory 4 into the DRAM 5. The firmware is a control program that includes a set of instructions for the CPU 11 to perform various processes. In addition to the FTL processing described above, the CPU 11 performs command processing to handle various commands from the host 2. The operation of the CPU 11 is controlled by the firmware executed by the CPU 11. Some or all of the FTL processing and command processing may be performed by dedicated hardware in the controller 6.

[0030] The NAND I / F circuit 12 electrically connects the controller 6 and the NAND flash memory 4. The NAND I / F circuit 12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0031] The NAND I / F circuit 12 functions as a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F circuit 12 may be connected to multiple memory chips within the NAND flash memory 4 via multiple channels. By driving multiple memory chips in parallel, the access to the entire NAND flash memory 4 can be widened.

[0032] The DRAM I / F circuit 13 functions as a DRAM control circuit configured to control access to the DRAM 5.

[0033] The host interface circuit 14 is a circuit that functions as an interface for communication between the memory system 3 and the host 2. The host interface circuit 14 includes a circuit that receives various commands from the host 2, such as input / output (I / O) commands and control commands. Examples of I / O commands are write commands or read commands. Examples of control commands are unmap commands (also called trim commands) or format commands. The host interface circuit 14 includes a circuit that outputs responses and data corresponding to the commands to the host 2.

[0034] The data compression device 15 compresses data by encoding it. An example of data to be compressed is data to be written to the NAND flash memory 4. The CPU 11 may, upon receiving a write command from the host 2, input the received write data to the data compression device 15 as uncompressed data (also called plaintext data). The data compression device 15 encodes the uncompressed data input from the CPU 11 to generate a compressed stream (also called compressed data).

[0035] The data compression device 15 may obtain multiple compressed symbols by performing lexicographical compression on each of the multiple symbols contained in the uncompressed data. Hereinafter, symbols obtained by lexicographical compression will be referred to as lexicographically compressed symbols. The data compression device 15 generates a compressed stream containing multiple variable-length codewords by performing entropy coding on the multiple lexicographically compressed symbols.

[0036] Dictionary-based compression is an encoding method that uses a dictionary to store previously input uncompressed data to convert the uncompressed data to be compressed into match information. Dictionary-based compression is also called dictionary coding. Examples of dictionary-based compression algorithms are LZ77 and LZSS. The dictionary is searched, and past data that matches at least part of the uncompressed data to be compressed is retrieved. Match information is generated, consisting of an offset and a match length for the retrieved past data. The offset represents the distance from the location in the dictionary where the uncompressed data is stored to the location where the retrieved past data is stored. The match length represents the length of the portion of the past data that matches the uncompressed data. The data is compressed by converting the uncompressed data into match information. Match information is also called a match symbol or dictionary match symbol.

[0037] If a dictionary search fails to find past data that matches the uncompressed data, at least partially, the uncompressed data (symbols) are output as is. Uncompressed data that is not converted to match symbols and is output as is is called a literal symbol or dictionary mismatch symbol.

[0038] Therefore, the multiple dictionary-compressed symbols obtained by dictionary compression of multiple symbols contained in uncompressed data include at least one of a match symbol and a literal symbol.

[0039] Entropy coding is a variable-length coding method that generates a coding table using the frequency of occurrence of symbols to be coded, such as dictionary-compressed symbols. The compression algorithm used by entropy coding may be one of the algorithms specified in DEFLATE. The coding table contains information representing multiple types of symbols and information representing multiple codewords associated with each of the multiple types of symbols. In entropy coding, symbols with high frequency are assigned short codewords, and symbols with low frequency are assigned long codewords. Entropy coding converts input symbols into codewords according to this assignment. In other words, the codewords obtained by the conversion are variable-length codewords. Therefore, entropy coding can reduce the amount of data by taking advantage of the bias in the frequency of occurrence of dictionary-compressed symbols. The compressed stream generated by entropy coding contains multiple codewords, each of which is a conversion of multiple dictionary-compressed symbols. The compressed stream may further include data representing the coding table used for entropy coding as a header. The data representing the coding table is used to reconstruct the coding table when the compressed stream is decompressed.

[0040] The data decompression device 16 decompresses the compressed stream by decoding it. The compressed stream may be data read from the NAND flash memory 4. The CPU 11 may input the compressed stream read from the NAND flash memory 4 to the data decompression device 16 in response to receiving a read command from the host 2. The data decompression device 16 can also decode the compressed stream input from the CPU 11 to generate uncompressed data.

[0041] The data decompressor 16 obtains multiple dictionary-compressed symbols by performing entropy decoding on each of the multiple codewords contained in the compressed stream. The data decompressor 16 generates uncompressed data containing multiple symbols, i.e., literal symbols, by performing lexicographical decompression on each of the multiple dictionary-compressed symbols.

[0042] Entropy decoding reconstructs the coding table using data contained in the header of the compressed stream, and based on this coding table, converts multiple codewords contained in the compressed stream into multiple dictionary-compressed symbols.

[0043] Dictionary-style decompression is a decoding method that uses a dictionary that stores previously decoded and outputted uncompressed data to convert match symbols in the dictionary-compressed symbol sequence to be decoded into uncompressed data, i.e., literal symbols. Since the literal symbols in the dictionary-compressed symbol sequence are not dictionary-compressed symbols, they are output as is. Dictionary-style decompression is also called dictionary-style decoding.

[0044] Although the memory system 3 was described as including DRAM 5, the memory system 3 may also include SRAM (Static Random Access Memory) as volatile memory.

[0045] Although the controller 6 has been described as including a data compression device 15 and a data decompression device 16, the data compression device 15 and the data decompression device 16 may be located outside the controller 6 or outside the memory system 3.

[0046] Figure 2 is a diagram illustrating an example of a compressed stream 33 output from a data compression device 15 according to the embodiment, or a compressed stream 33 input to a data decompression device 16 according to the embodiment. The compressed stream 33 may include a codeword Mc corresponding to a match symbol and a codeword Lc corresponding to a literal symbol.

[0047] If at least some of the symbols in the uncompressed data being compressed are replaced with match symbols, the compressed stream will have fewer symbols than the uncompressed data being compressed, i.e., a sequence of symbols that consists entirely of literal symbols.

[0048] The data compression device 15 may compress uncompressed data into specific units. These specific units of uncompressed data are also called Huffman blocks. A Huffman block has a specific data size; that is, a Huffman block contains a specific number of symbols. The specific data size can be arbitrarily set in the information processing system 1, more specifically in the data compression device 15 and the data decompression device 16. The data compression device 15 may switch the coding table used for entropy coding for each Huffman block.

[0049] The data compression device 15 may add an End of Block (EOB) symbol to the end of each Huffman block so that the boundaries of the Huffman blocks can be detected. The EOB symbol is a symbol that represents the end of a Huffman block. An example of an EOB symbol may be a bit sequence defined in DEFLATE. The data decompression device 16 may switch the coding table used for entropy decoding depending on whether an EOB symbol has been detected.

[0050] Figure 3 illustrates an example of data generated in dictionary-style compression and data generated in entropy coding by the data compression device 15 according to this embodiment. Here, the uncompressed data sequence 31 is assumed to be an uncompressed data sequence corresponding to one Huffman block.

[0051] Figure 4 illustrates an example of data generated in entropy decoding and lexicographical decompression by the data decompression device 16 according to this embodiment. Here, the data decompression device 16 decompresses the compressed stream 33 into Huffman blocks, which are specific units.

[0052] As shown in Figure 3, an uncompressed data sequence 31, i.e., a Huffman block, input to the data compression device 15 is converted into a dictionary-compressed symbol sequence 32 by dictionary compression. The uncompressed data sequence 31 may contain multiple literal symbols L as uncompressed data. The dictionary-compressed symbol sequence 32 may contain multiple dictionary-compressed symbols. Of the uncompressed data sequence 31, byte sequences that match at least a portion of the byte sequences in the dictionary, which are past byte sequences, are replaced with match symbols M and output as dictionary-compressed symbols. Of the uncompressed data sequence 31, byte sequences for which no matching past byte sequences are found are output as dictionary-compressed symbols as uncompressed byte sequences, i.e., literal symbols L. The dictionary-compressed symbol sequence 32 may consist only of literal symbols L and not contain match symbols M. The dictionary-compressed symbol sequence 32 may consist only of match symbols M and not contain literal symbols L.

[0053] In the example shown in Figure 3, the eight literal symbols L contained in the uncompressed data sequence 31 are converted into a dictionary-compressed symbol sequence 32 containing five dictionary-compressed symbols through dictionary compression. The dictionary-compressed symbol sequence 32 contains two match symbols M and three literal symbols L. In this way, the uncompressed data sequence 31 can be compressed into a dictionary-compressed symbol sequence 32 with a reduced number of symbols through dictionary compression.

[0054] Next, an EOB symbol is added to the end of the dictionary-compressed symbol sequence 32. The dictionary-compressed symbol sequence 32 and the EOB symbol are converted into a compressed stream 33 by entropy coding. Specifically, the dictionary-compressed symbol sequence 32 and the EOB symbol are converted into variable-length codewords symbol by symbol by entropy coding.

[0055] In the example shown in Figure 3, the compressed stream 33 includes three variable-length codewords Lc obtained by entropy coding each of three literal symbols L, two variable-length codewords Mc obtained by entropy coding each of two match symbols M, and a variable-length codeword EOBc obtained by entropy coding the EOB symbol. Entropy coding encodes dictionary-compressed symbols with a coding amount corresponding to their frequency of occurrence. The dictionary-compressed symbol sequence 32 is compressed into the compressed stream 33, whose data size has been reduced by entropy coding. In other words, the compressed stream 33 is data obtained by compressing the uncompressed data sequence 31, in this case a single Huffman block, using dictionary-based compression and entropy coding. Even when the dictionary-compressed symbol sequence 32 consists only of literal symbols L, entropy coding can reduce the data size.

[0056] As mentioned above, the EOB symbol can be used to detect Huffman block boundaries during decoding by the data decompressor 16. The data decompressor 16 switches the coding table used for decoding in response to the detection of a Huffman block boundary.

[0057] As shown in Figure 4, the compressed stream 33 input to the data decompressor 16 is converted into a dictionary-compressed symbol sequence 32 by entropy decoding. Specifically, multiple variable-length codewords contained in the compressed stream 33 are converted into a dictionary-compressed symbol sequence 32 and EOB symbols by entropy decoding. Depending on the acquisition of EOB symbols, the boundaries of Huffman blocks in the compressed stream 33 are detected. EOB symbols are excluded from the dictionary-compressed symbol sequence 32.

[0058] In the example shown in Figure 4, the EOB symbol is obtained by entropy decoding the variable-length codeword EOBc contained in the compressed stream 33, two match symbols M are obtained by entropy decoding the two variable-length codewords Mc contained in the compressed stream 33, and three literal symbols L are obtained by entropy decoding the three variable-length codewords Lc contained in the compressed stream 33. The three literal symbols L and the two match symbols M are output as a dictionary-compressed symbol sequence 32 in the order of decoding.

[0059] Next, the dictionary-compressed symbol sequence 32 is converted into an uncompressed data sequence 31 by dictionary-style decompression. Specifically, the match symbols M in the dictionary-compressed symbol sequence 32 are replaced with past byte sequences indicated by the match information, for example, byte sequences in the dictionary, and output as the uncompressed data sequence 31. On the other hand, the literal symbols L in the dictionary-compressed symbol sequence 32 are uncompressed byte sequences, so they are output as is as the uncompressed data sequence 31. In other words, the uncompressed data sequence 31 is data obtained by decompressing the compressed stream 33, which in this case corresponds to compressed data equivalent to one Huffman block, through entropy decoding and dictionary-style decompression.

[0060] In the example shown in Figure 4, the five dictionary-compressed symbols M and L contained in the dictionary-compressed symbol sequence 32 are converted by dictionary decompression into an uncompressed data sequence 31 containing eight symbols, i.e., eight literal symbols L. Thus, the dictionary-compressed symbol sequence 32 can be decompressed by dictionary decompression into an uncompressed data sequence 31 with an increased number of symbols. In other words, the uncompressed data sequence 31 is a data sequence obtained by decompressing the compressed stream 33 through entropy decoding and dictionary decompression.

[0061] Figure 5 is a block diagram illustrating an example of a data compression device 15 according to this embodiment.

[0062] The data compression device 15 compresses the uncompressed data sequence 31 into a compressed stream 33 by dictionary compression and entropy coding. An example of the uncompressed data sequence 31 is data to be compressed that contains one or more Huffman blocks. The data compression device 15 includes a dictionary compression circuit 21 and an entropy coding circuit 22.

[0063] The dictionary-style compression circuit 21 converts the uncompressed data sequence 31 into a dictionary-compressed symbol sequence 32 by dictionary compression. The dictionary-compressed symbol sequence 32 may include literal symbols L and match symbols M. The dictionary-style compression circuit 21 sends the dictionary-compressed symbol sequence 32 to the entropy coding circuit 22.

[0064] The entropy coding circuit 22 converts the dictionary-compressed symbol sequence 32 into a variable-length codeword by entropy coding to generate a compressed stream 33. The entropy coding circuit 22 may also include a full-literal determination circuit 224, an EOB addition circuit 221, a coding table generation circuit 222, and a variable-length coding circuit 223.

[0065] Each of the dictionary-style compression circuit 21, EOB addition circuit 221, coding table generation circuit 222, variable-length coding circuit 223, and all-literal determination circuit 224 is implemented by at least one of the following: registers, adders, multipliers, selectors, and other arithmetic units. Registers are implemented by logic circuits, such as flip-flops. Adders, multipliers, selectors, and other arithmetic units are implemented by logic circuits.

[0066] The all-literal determination circuit 224 determines whether all of the one or more dictionary-compressed symbols contained in the dictionary-compressed symbol sequence 32 received consecutively from the dictionary-style compression circuit 21 after the first timing are literal symbols L. The first timing is the timing when data compression processing in the data compression device 15 starts or the timing when the end of the Huffman block is notified by the EOB addition circuit 221. The timing when the end of the Huffman block is notified is the timing when the block end flag, described later, is received. The dictionary-compressed symbol sequence 32 contains one or more dictionary-compressed symbols contained in a data block (referred to as the second data block) obtained by dictionary-style compression of one Huffman block (referred to as the first data block). The all-literal determination circuit 224 may determine whether all of the one or more dictionary-compressed symbol sequences 32 are literal symbols L based on whether the byte value of each symbol contained in the dictionary-compressed symbol sequence 32 matches the byte value of any of the predefined literal symbols L. An example of a predefined byte value may be a byte value defined in DEFLATE.

[0067] The all-literal determination circuit 224 sends information (referred to as all-literal determination information) to the EOB addition circuit 221 indicating whether the dictionary-compressed symbol sequence 32 contains only literal symbols L, that is, whether it does not contain match symbols M. An example of all-literal determination information is information that represents either true or false. The value "1" may be used to represent true. The value "0" may be used to represent false. Specifically, the all-literal determination circuit 224 sends a signal containing all-literal determination information to the EOB addition circuit 221 at all times or at regular intervals.

[0068] The EOB addition circuit 221 sends a block end flag to the full literal determination circuit 224. The block end flag is information that indicates the end of a Huffman block. This information indicates that the end of the dictionary-compressed symbol sequence 32 being determined corresponds to the end of a Huffman block. In response to the EOB addition circuit 221 sending the block end flag, the full literal determination circuit 224 may output the current full literal determination information as a header section 331. The full literal determination information may be used in the data decompression device 16 to determine whether the Huffman block corresponding to the dictionary-compressed symbols obtained by entropy decoding of the compressed stream 33 is a Huffman block that contains only literal symbols L and does not contain match symbols M.

[0069] The EOB addition circuit 221 adds an EOB symbol to the end, i.e., the tail, of one or more dictionary compression symbols corresponding to a Huffman block if all literal determination information represents false.

[0070] Specifically, the EOB addition circuit 221 may, each time it receives a dictionary-compressed symbol 32 from the dictionary-compressed circuit 21, obtain the data size of that dictionary-compressed symbol 32 before dictionary-compression and calculate the cumulative value of the obtained data sizes, i.e., the size of the uncompressed data. If the dictionary-compressed symbol is a literal symbol L, an example of the data size before dictionary-compression is 1 byte. If the dictionary-compressed symbol is a match symbol M, the data size before dictionary-compression may be the match length in bytes represented by that match symbol M. The EOB addition circuit 221 sends the dictionary-compressed symbol whose data size has been obtained to the coding table generation circuit 222 and the variable-length coding circuit 223.

[0071] The EOB add-on circuit 221 determines, based on the calculated uncompressed data size and block size information 41, whether the end of one or more dictionary-compressed symbols used to calculate the uncompressed data size corresponds to the end of a Huffman block. The block size information 41 represents the block size of one Huffman block. The block size information 41 may be generated based on a block size defined in the information processing system 1. The block size information 41 may be stored in any area within the data compression device 15 or memory system 3, or it may be received from an external device, such as the host 2. The EOB add-on circuit 221 determines, based on whether the calculated uncompressed data size has reached the block size, whether the end of one or more dictionary-compressed symbols corresponds to the end of a Huffman block. The end of one or more dictionary-compressed symbols, i.e., the last symbol, is the symbol from which the data size was immediately, i.e., last obtained.

[0072] If the calculated uncompressed data size reaches the block size, that is, if the end of one or more dictionary-compressed symbols corresponds to the end of a Huffman block, the EOB addition circuit 221 determines whether the all-literal determination information received from the all-literal determination circuit 224 indicates true or false.

[0073] If all literal determination information represents false, the EOB addition circuit 221 adds an EOB symbol to the end of the current Huffman block. In other words, the EOB addition circuit 221 sends the EOB symbol to the coding table generation circuit 222 and the variable-length coding circuit 223. The sent EOB symbol is placed after the dictionary compression symbol 32 whose data size was obtained immediately beforehand.

[0074] On the other hand, if all literal determination information indicates true, the EOB addition circuit 221 does not add an EOB symbol to the end of the current Huffman block. In other words, the EOB addition circuit 221 does not send an EOB symbol to the coding table generation circuit 222 and the variable-length coding circuit 223. Therefore, an EOB symbol is not placed after the dictionary compression symbol whose data size was obtained immediately beforehand.

[0075] The EOB addition circuit 221 sends information (referred to as a block end flag) to the all-literal determination circuit 224 indicating that the end of one or more dictionary-compressed symbols used to calculate the uncompressed data size corresponds to the end of a Huffman block. The EOB addition circuit 221 may also send the block end flag to the coding table generation circuit 222.

[0076] The coding table generation circuit 222 generates a coding table 42 based on the frequency of occurrence of each symbol of multiple symbols corresponding to one Huffman block. The multiple symbols corresponding to one Huffman block may include symbols received from the EOB addition circuit 221 from the first timing until the end of the block flag is received. Specifically, the coding table generation circuit 222 assigns short codewords to symbols with high occurrence frequency and long codewords to symbols with low occurrence frequency. The coding table generation circuit 222 sends the generated coding table 42 to the variable-length coding circuit 223. The coding table generation circuit 222 outputs data representing the coding table 42 as the header portion 331 of the compressed stream 33.

[0077] The variable-length coding circuit 223 generates multiple variable-length codewords corresponding to multiple symbols corresponding to a single Huffman block through variable-length coding. Specifically, the variable-length coding circuit 223 converts multiple symbols corresponding to a single Huffman block into multiple variable-length codewords based on the coding table 42. The variable-length coding circuit 223 sequentially outputs the variable-length codewords converted from each symbol as the payload section 332 of the compressed stream 33. If EOB symbols are added by the EOB addition circuit 221, the payload section 332 includes one or more variable-length codewords corresponding to one or more dictionary-compressed symbols and a trailing variable-length codeword corresponding to the EOB block. If EOB symbols are not added by the EOB addition circuit 221, the payload section 332 includes multiple variable-length codewords corresponding to multiple dictionary-compressed symbols, all of which are literal symbols L.

[0078] When the coding table generation circuit 222 receives multiple symbols corresponding to the next Huffman block from the EOB addition circuit 221, it generates a new coding table 42 and sends it to the variable-length coding circuit 223. The variable-length coding circuit 223 uses the new coding table 42 to convert the multiple symbols corresponding to that Huffman block into multiple variable-length codewords.

[0079] Therefore, the compressed stream 33 consists of a header section 331 containing an encoding table 42 and a payload section 332 for each Huffman block. The payload section 332 includes either (A) a variable-length codeword sequence obtained by variable-length encoding of the dictionary-compressed symbol sequence 32 and EOB symbols, or (B) a variable-length codeword sequence obtained by variable-length encoding of the dictionary-compressed symbol sequence 32, all of which are literal symbols L.

[0080] If the payload section 332 includes (B) a variable-length codeword sequence obtained by variable-length encoding a dictionary-compressed symbol sequence 32 in which all are literal symbols L, the header section 331 may further include information representing the size of the variable-length codeword sequence (referred to as compression size information). The size of the variable-length codeword sequence included in the payload section 332 is the size of the variable-length codeword sequence obtained by dictionary-style compression and entropy coding of the corresponding Huffman block, i.e., the size of the compressed Huffman block. The compression size information may be used in the data decompressor 16 to determine whether the end of one or more variable-length codewords corresponds to the end of a Huffman block when one or more symbols are obtained by entropy decoding of one or more variable-length codewords in the compressed stream 33. In other words, the compression size information is used to determine the boundaries between Huffman blocks.

[0081] With the above configuration, the data compression device 15 can compress the uncompressed data sequence 31 into a compressed stream 33 by dictionary compression and entropy coding. The data compression device 15 can improve compression efficiency and coding throughput by not adding an EOB symbol if all of the one or more dictionary-compressed symbols obtained by dictionary compression on the Huffman block are literal symbols L. Also, the data compression device 15 can avoid a decrease in throughput during decoding by adding an EOB symbol if at least one of the one or more dictionary-compressed symbols obtained by dictionary compression on the Huffman block is not a literal symbol L.

[0082] Figure 6 is a block diagram illustrating an example of the configuration of a data decompression device 16 according to an embodiment. The data decompression device 16 decompresses a compressed stream 33 into an uncompressed data sequence 31 by entropy decoding and lexicographical decompression. The compressed stream 33 is the data to be decompressed, corresponding to one or more Huffman blocks. The data decompression device 16 includes an entropy decoding circuit 51 and a lexicographical decompression circuit 52.

[0083] The entropy decoding circuit 51 generates a dictionary-compressed symbol sequence 32 from the compressed stream 33 by entropy decoding. An example of the entropy decoding circuit 51 includes a header / payload separation circuit 511, an encoded table restoration circuit 512, a variable-length decoding circuit 513, an EOB detection circuit 514, a block boundary determination circuit 515, a full literal determination circuit 516, and a multiplexer (MUX) 517.

[0084] The dictionary-style expansion circuit 52, the header / payload separation circuit 511, the coded table restoration circuit 512, the variable-length decoding circuit 513, the EOB detection circuit 514, the block boundary determination circuit 515, the all-literal determination circuit 516, and the multiplexer 517 may be implemented by at least one of the following: registers, adders, multipliers, selectors, and other arithmetic units. Registers may be implemented by logic circuits, such as flip-flops. Adders, multipliers, selectors, and other arithmetic units may be implemented by logic circuits.

[0085] The header / payload separation circuit 511 separates the header section 331 and the payload section 332 contained in the compressed stream 33. The header / payload separation circuit 511 sends the header section 331 to the coding table reconstruction circuit 512. The header / payload separation circuit 511 sends the payload section 332, which follows the header section 331, to the variable-length decoding circuit 513. If the header section 331 contains all literal determination information, the header / payload separation circuit 511 may also send all literal determination information to the all literal determination circuit 516.

[0086] The coding table reconstruction circuit 512 reconstructs the coding table 42 using the data contained in the header section 331. The coding table reconstruction circuit 512 then sends the reconstructed coding table 42 to the variable-length decoding circuit 513.

[0087] The variable-length decoding circuit 513 generates multiple symbols corresponding to multiple variable-length codewords contained in the payload section 332 through variable-length decoding. Specifically, the variable-length decoding circuit 513 converts multiple variable-length codewords contained in the payload section 332 into multiple symbols based on the coding table 42. The symbols obtained through the conversion are either dictionary-compressed symbols or EOB symbols. The variable-length decoding circuit 513 sequentially sends the generated symbols to the EOB detection circuit 514, the block boundary determination circuit 515, the full literal determination circuit 516, and the dictionary-style decompression circuit 52, respectively.

[0088] The EOB detection circuit 514 detects an EOB symbol from the symbols received from the variable-length decoding circuit 513 and sends information indicating that an EOB symbol has been detected to the multiplexer 517 and the block boundary determination circuit 515. This information indicating that an EOB symbol has been detected is called the EOB detection flag.

[0089] Specifically, the EOB detection circuit 514 determines whether a symbol it receives from the variable-length decoding circuit 513 matches an EOB symbol. If it receives one or more symbols from the variable-length decoding circuit 513, the EOB detection circuit 514 may determine whether each of those symbols matches an EOB symbol (more specifically, the value assigned to the EOB symbol) in order from the beginning. If no EOB symbol is detected from the first symbol up to the symbol immediately preceding the last symbol, the EOB detection circuit 514 determines whether the last symbol matches an EOB symbol. If the last symbol matches an EOB symbol, the EOB detection circuit 514 detects that last symbol as an EOB symbol. As a result, the EOB detection circuit 514 detects that the end of those one or more symbols corresponds to the end of a Huffman block. The EOB detection circuit 514 sends an EOB detection flag, that is, information indicating that the end of one or more symbols corresponds to the end of a Huffman block, to the multiplexer 517 and the block boundary determination circuit 515.

[0090] The block boundary determination circuit 515 sends information to the multiplexer 517 indicating that the end of one or more symbols received consecutively from the variable-length decoding circuit 513 after the second timing corresponds to the end of a Huffman block, i.e., a block boundary flag. The second timing is the timing when the data decompression process in the data decompression device 16 starts or when the EOB detection flag is received from the EOB detection circuit 514.

[0091] Specifically, each time the block boundary determination circuit 515 receives a symbol from the variable-length decoding circuit 513, it obtains the data size of that symbol if it were lexicographically decompressed, and calculates the cumulative value of the obtained data sizes, i.e., the uncompressed data size. The block boundary determination circuit 515 assumes that the received symbol is a literal symbol L and obtains the data size of that symbol if it were lexicographically decompressed. Since a literal symbol L is a symbol that is not lexicographically compressed, an example of the data size of a literal symbol L if it were lexicographically decompressed is 1 byte. Therefore, by assuming that the symbols received from the variable-length decoding circuit 513 are literal symbols L, the block boundary determination circuit 515 can easily calculate the uncompressed data size by counting the number of symbols received.

[0092] The block boundary determination circuit 515 determines, based on the calculated uncompressed data size and block size information 41, whether the end of one or more symbols used to calculate the uncompressed data size corresponds to the end of a Huffman block. The block size information 41 may be stored in any area of ​​the data decompression device 16 or memory system 3, or it may be received from an external device, such as the host 2. Specifically, the block boundary determination circuit 515 determines that the end of one or more symbols corresponds to the end of a Huffman block when the calculated uncompressed data size reaches the block size. The symbols whose data size was calculated immediately before correspond to the end of one Huffman block. This allows the block boundary determination circuit 515 to detect boundaries between Huffman blocks. When the block boundary determination circuit 515 detects a boundary between Huffman blocks, it sends a block boundary flag to the multiplexer 517. An example of a block boundary flag is a signal that indicates that a boundary between Huffman blocks has been detected, that is, that the end of one or more symbols corresponds to the end of a Huffman block.

[0093] The all-literal determination circuit 516 sends all-literal determination information to the multiplexer 517 and the block boundary determination circuit 515, indicating whether or not one or more symbols (also called target symbols) received consecutively from the variable-length decoding circuit 513 after the third timing are all literal symbols L. The third timing is the timing when data decompression processing in the data decompression device 16 starts or the timing when the end of a Huffman block is notified by the multiplexer 517. The all-literal determination circuit 516 may also determine whether or not the symbol sequence to be determined contains only literal symbols L, that is, whether or not it contains match symbols M, based on whether or not the byte value of each symbol included in the symbol sequence to be determined matches the byte value of any literal symbol L defined in advance, for example, DEFLATE.

[0094] The all-literal determination circuit 516 may use the all-literal determination information received from the header / payload separation circuit 511, that is, the all-literal determination information in the header section 331, to determine whether the symbol sequence to be determined contains only literal symbols L. In this case, the circuit size of the all-literal determination circuit 516, i.e., the computational load, can be reduced.

[0095] The full literal determination circuit 516 continuously or at regular intervals sends full literal determination information to the multiplexer 517 and the block boundary determination circuit 515. The full literal determination process by the full literal determination circuit 516 is almost the same as the full literal determination process by the full literal determination circuit 224 of the data compression device 15. More specifically, the full literal determination process by the full literal determination circuit 516 is equivalent to replacing the dictionary-style compression circuit 21 and the EOB addition circuit 221 in the aforementioned full literal determination process with a variable-length decoding circuit 513 that sends symbols to the full literal determination circuit 516 and a multiplexer 517 that notifies the end of a Huffman block, respectively.

[0096] The multiplexer 517 is a selector that outputs either the EOB detection flag output by the EOB detection circuit 514 or the block boundary flag output by the block boundary determination circuit 515, depending on whether the total literal determination information is true or false. In the example shown in Figure 6, within the multiplexer 517, the total literal determination information that is true is represented as "1", and the total literal determination information that is false is represented as "0". Specifically, if the multiplexer 517 receives the EOB detection flag from the EOB detection circuit 514 while receiving the total literal determination information representing false ("0" in Figure 6) from the total literal determination circuit 516, the multiplexer 517 notifies the coding table restoration circuit 512 to switch the coding table 42 and notifies the total literal determination circuit 516 of the end of the current Huffman block based on the EOB detection flag. In contrast, if the multiplexer 517 receives a block boundary flag from the block boundary determination circuit 515 while receiving full literal determination information representing true ("1" in Figure 6) from the full literal determination circuit 516, the multiplexer 517 notifies the coding table restoration circuit 512 of the switching of coding table 42 and notifies the full literal determination circuit 516 of the end of the current Huffman block based on the block boundary flag. Specifically, the multiplexer 517 may send a signal representing the switching of coding table 42 to the coding table restoration circuit 512 in order to notify the switching of coding table 42. The multiplexer 517 may also send a signal representing the end of the current Huffman block to the full literal determination circuit 516 in order to notify the end of the current Huffman block.

[0097] The coding table restoration circuit 512, in response to notification of the coding table 42 switch from the multiplexer 517, restores a new coding table 42 using the data contained in the next header section received from the header / payload separation circuit 511. The variable-length decoding circuit 513 uses the new coding table 42 to convert the multiple variable-length codewords contained in the subsequent payload section into a dictionary-compressed symbol sequence 32.

[0098] The dictionary-style decompression circuit 52 generates an uncompressed data sequence 31 from the dictionary-compressed symbol sequence 32 received from the variable-length decoding circuit 513 by dictionary-style decompression. Specifically, if the dictionary-compressed symbol is a match symbol M, the dictionary-style decompression circuit 52 outputs the past byte sequence in the dictionary indicated by the match information as uncompressed data. If the dictionary-compressed symbol is a literal symbol L, the dictionary-style decompression circuit 52 outputs the literal symbol L as is as uncompressed data. The dictionary-style decompression circuit 52 does not output the EOB symbol received from the variable-length decoding circuit 513 as uncompressed data.

[0099] With the above configuration, the data decompressor 16 can detect the end of a Huffman block based on the number of dictionary-compressed symbols obtained from the variable-length decoding circuit 513, if all of the variable-length decoded dictionary-compressed symbols corresponding to the Huffman block are literal symbols L. In this case, the data decompressor 16 does not need to decode EOB symbols or calculate the uncompressed data size according to the type of symbols obtained by variable-length decoding. Therefore, the data decompressor 16 can improve the decoding throughput. Also, since no EOB symbols are added to Huffman blocks where all of the corresponding dictionary-compressed symbols are literal symbols L, the input compressed stream 33 is data with high compression efficiency.

[0100] The block boundary determination circuit 515 may use the compressed size information to determine whether the end of one or more dictionary-compressed symbols received consecutively from the variable-length decoding circuit 513 after the second timing corresponds to the end of a Huffman block. The compressed size information represents the size of the data block, or more specifically, the variable-length codeword sequence, obtained by dictionary compression and entropy coding for the corresponding Huffman block. The compressed size information is obtained from the header section 331. Note that compressed size information representing a specific size may be pre-stored in the data decompression device 16.

[0101] Specifically, the block boundary determination circuit 515 calculates the data size (referred to as the compressed data size) of one or more variable-length codes corresponding to one or more symbols received from the variable-length decoding circuit 513. The block boundary determination circuit 515 may use the coding table 42 to obtain the data size of a symbol before it is variable-length decoded, for example, the code length of the corresponding variable-length codeword, each time it receives a symbol from the variable-length decoding circuit 513, and calculate the compressed data size as the cumulative value of the obtained data sizes. If all of the one or more symbols received are literal symbols L, the block boundary determination circuit 515 may send information (block boundary flag) to the multiplexer 517 indicating that the end of one or more symbols used to calculate the compressed data size corresponds to the end of a Huffman block, based on the calculated compressed data size and the compressed size information. More specifically, the block boundary determination circuit 515 sends a block boundary flag to the multiplexer 517 if all literal determination information received from the all literal determination circuit 516 indicates true and the calculated compressed data size is equal to the size indicated in the compressed size information. The same effect as the block boundary determination process described above can be obtained when determining the boundary between Huffman blocks using the compressed size information.

[0102] Figure 7 is a block diagram illustrating an example of a dictionary-style expansion circuit 52 according to an embodiment. The dictionary-style expansion circuit 52 includes a literal / match separation circuit 102, a dictionary assignment circuit 104, a dictionary lookup circuit 106, a decode circuit 108, and a dictionary 110.

[0103] Dictionary 110 contains multiple dictionaries (first dictionary 110-1, second dictionary 110-2, ... nth dictionary 110-N), where N is a positive integer greater than or equal to 2. Each of the first dictionary 110-1 through the nth dictionary 110-N is composed of memory. An example of memory is SRAM (Static Random Access Memory). The first dictionary 110-1 through the nth dictionary 110-N are connected in parallel to the dictionary lookup circuit 106 and can be referenced simultaneously from the dictionary lookup circuit 106. "Simultaneous reference" here means that the reading of data from the first dictionary 110-1 and the reading of data from the second dictionary 110-2 through the nth dictionary 110-N can be performed in parallel.

[0104] The first dictionary 110-1 to the Nth dictionary 110-N are classified into two types of dictionaries based on their memory size. Each of the first dictionary 110-1 to the Nth dictionary 110-N has one of two different memory sizes. The memory size of at least one dictionary is the first size, determined by the maximum offset value determined by the compression / decompression algorithm. The first size is also called the full size. The memory sizes of the remaining dictionaries are any second size, smaller than the first size. Here, the memory size of the first dictionary 110-1 is the first size, and it is classified as a first type of dictionary. The first dictionary 110-1 is also called the full-size dictionary. The memory sizes of the second dictionary 110-2 to the Nth dictionary 110-N are the second size, and they are classified as second type of dictionaries. If the distribution trend of the offsets is known in advance as a trend of the input data, the second size may be designed to match that trend.

[0105] Each of the uncompressed data, i.e., each literal symbol, contained in the uncompressed data sequence 31 output from the decoding circuit 108 is written to the first dictionary 110-1 to the Nth dictionary 110-N. In each of the first dictionary 110-1 to the Nth dictionary 110-N, literal symbols are written starting from the beginning of the free space, with the address increasing. The maximum address of the first dictionary 110-1 is greater than the maximum address of each of the second dictionary 110-2 to the Nth dictionary 110-N. In each of the first dictionary 110-1 to the Nth dictionary 110-N, after literal symbols have been written up to the maximum address, the address pointer is reset to 0, and new literal symbols are written starting from the beginning address. That is, the literal symbols stored in dictionaries 110-1 to 110-N are overwritten with new literal symbols.

[0106] Thus, at least one literal symbol output in the first period in the past, starting from the present, is stored in all of the first dictionaries 110-1 to the Nth dictionary 110-N. Since the storage size of the second dictionaries 110-2 to the Nth dictionary 110-N, i.e., the maximum address, is smaller than the storage size of the first dictionary 110-1, at least one literal symbol output in the second period prior to the first period is not stored in the second dictionaries 110-2 to the Nth dictionary 110-N, but is stored only in the first dictionary 110-1. Each of the second dictionaries 110-2 to the Nth dictionary 110-N stores only at least one literal symbol output in the first period, and is therefore also called a neighbor dictionary. The full-size dictionary (first dictionary) 110-1 stores at least one literal symbol output in the first and second periods.

[0107] The dictionary-compressed symbol sequence 32 output from the entropy decoding circuit 51 is input to the literal / match separation circuit 102. The dictionary-compressed symbol sequence 32 input to the dictionary-style decompression circuit 52 in one cycle contains multiple dictionary-compressed symbols. Here, one cycle refers to one cycle of the clock that serves as the reference for the operation of the dictionary-style decompression circuit 52. Each dictionary-compressed symbol included in one cycle of the dictionary-compressed symbol sequence 32 is either a match symbol M or a literal symbol L. If the number of match symbols M included in one cycle of the dictionary-compressed symbol sequence 32 is 0, then the number of literal symbols L included in one cycle of the dictionary-compressed symbol sequence 32 is 1 or more. Similarly, if the number of literal symbols L included in one cycle of the dictionary-compressed symbol sequence 32 is 0, then the number of match symbols M included in one cycle of the dictionary-compressed symbol sequence 32 is 1 or more. The literal / match separation circuit 102 determines whether each dictionary-compressed symbol in the dictionary-compressed symbol sequence 32 is a literal symbol or a match symbol. The literal / match separation circuit 102 outputs dictionary-compressed symbols determined to be literal symbols to the decode circuit 108. The literal / match separation circuit 102 outputs dictionary-compressed symbols determined to be match symbols to the dictionary assignment circuit 104. In other words, the literal / match separation circuit 102 separates dictionary-compressed symbols into literal symbols and match symbols, outputs the literal symbols to the decode circuit 108, and outputs the match symbols to the dictionary assignment circuit 104.

[0108] The dictionary assignment circuit 104 determines which dictionary to refer to when expanding a match symbol, that is, which dictionary to assign the reference for the match symbol to, and based on the result, rearranges the positions of the match symbols in the one-cycle match symbol sequence output from the literal / match separation circuit 102. The dictionary assignment circuit 104 outputs the rearranged match symbol sequence to the dictionary reference circuit 106. Since the size of the neighbor dictionaries (second dictionary 110-2 to the nth dictionary 110-N) is smaller than the size of the full-size dictionary (first dictionary 110-1), literal symbols corresponding to match symbols with large offsets may not be stored in the neighbor dictionaries 110-2 to 110-N. In other words, match symbols with large offsets cannot be expanded even when referring to the neighbor dictionaries 110-2 to 110-N.

[0109] The dictionary lookup circuit 106 recognizes which dictionary is assigned to a match symbol according to the order in which the match symbols are arranged in the input match symbol sequence. The dictionary lookup circuit 106 recognizes that the full-size dictionary 110-1 is assigned to the first match symbol in a one-cycle match symbol sequence, and that the neighbor dictionaries 110-2 to 110-N are assigned to the second and subsequent match symbols. Therefore, the dictionary assignment circuit 104 outputs a sequence of match symbols with the order of the match symbols M rearranged so that match symbols that cannot be expanded without referring to the full-size dictionary 110-1 are placed earlier than match symbols that can be expanded by referring to the neighbor dictionaries 110-2 to 110-N. In other words, the dictionary assignment circuit 104 compares the offset of the match symbol M with the second size, which is the size of the neighbor dictionaries 110-2 to 110-N. If the offset is greater than or equal to the second size, the match symbol is placed at the beginning of the output symbol sequence so that it can be expanded by referring to the full-size dictionary 110-1. As a result, match symbols M with large offsets are rearranged so that they are output to the dictionary lookup circuit 106 before match symbols M with small offsets. This rearrangement allows the dictionary lookup circuit 106 to refer to the full-size dictionary 110-1 for match symbols with offsets of the second size or larger, and to refer to neighbor dictionaries 110-2 to 110-N for all other match symbols.

[0110] It is assumed that only one match symbol can be referenced in a single dictionary. Therefore, in order to achieve a 100% throughput satisfaction rate for data decompression, for example, the number of dictionaries 110-1 to 110-N, N, must be equal to the number of dictionary references that can occur simultaneously in the dictionary-style decompression circuit 52. The number of dictionary references that can occur simultaneously is determined by the throughput required for the data decompression device 16 and the minimum match length determined by the data compression / decompression algorithm. Each of dictionaries 110-1 to 110-N can be referenced once per unit time. An example of a unit time is one cycle. That is, if the dictionary-style decompression circuit 52 according to this embodiment can simultaneously perform a dictionary reference for each of the match symbols in a match symbol sequence of one cycle using any of dictionaries 110-1 to 110-N, then N dictionary-compressed symbols can be decompressed in one cycle.

[0111] The dictionary lookup circuit 106 includes an interface for writing data to multiple dictionaries 110-1 to 110-N and reading data from multiple dictionaries 110-1 to 110-N. Therefore, the dictionary lookup circuit 106 writes each of the multiple uncompressed data contained in the uncompressed data sequence 31 output from the decoding circuit 108 to multiple first dictionaries 110-1 to the nth dictionary 110-N. The dictionary lookup circuit 106 takes a match symbol sequence as input from the dictionary assignment circuit 104 and simultaneously looks up to N match symbols in the first dictionaries 110-1 to the nth dictionary 110-N. The dictionary lookup circuit 106 outputs to each dictionary 110-1 to 110-N an address obtained by subtracting the address corresponding to the offset of the match symbol from the current write address of each dictionary 110-1 to 110-N as the reference address. If the offset is defined as a negative value, the reference address will be the current write address plus the address corresponding to the offset. The dictionary lookup circuit 106 also outputs the match length of the match symbol to each dictionary 110-1 to 110-N.

[0112] The dictionary lookup circuit 106 reads multiple literal symbols stored in memory locations corresponding to the match length, starting with the reference address, from multiple dictionaries 110-1 to 110-N. The dictionary lookup circuit 106 outputs the multiple literal data read simultaneously from multiple dictionaries 110-1 to 110-N to the decoding circuit 108 simultaneously and in parallel as multiple dictionary lookup data. The dictionary lookup circuit 106 adds the match length of the match symbol to the dictionary lookup data (literal symbol) corresponding to the match symbol and outputs it to the decoding circuit 108.

[0113] The decoding circuit 108 receives literal symbols input from the literal / match separation circuit 102 and dictionary reference data (literal symbols) and match length input from the dictionary reference circuit 106. It rearranges the literal symbols and dictionary reference data (literal symbols) in the same order as the literal symbols and match symbols in the dictionary-compressed symbol sequence 32 for one cycle to generate an uncompressed data sequence 31, which is the decompressed result, and outputs the uncompressed data sequence 31. For this to work, the decoding circuit 108 needs information representing the order of the literal symbols and match symbols in the dictionary-compressed symbol sequence 32. When the literal / match separation circuit 102 separates the dictionary-compressed symbol sequence 32 into literal symbols and match symbols, it generates information representing the byte position of the literal symbol and the starting byte position of the match symbol in one cycle, and outputs this information along with the literal symbols and match symbols. The dictionary lookup circuit 106 outputs this information along with the dictionary lookup data (literal symbol) referenced by the match symbol to the decoding circuit 108.

[0114] As described above, the uncompressed data sequence 31 is written to dictionaries 110-1 to 110-N for reference during dictionary decompression. Since the interface included in the dictionary reference circuit 106 is capable of writing to and reading from multiple dictionaries 110-1 to 110-N, the uncompressed data sequence 31 is output to the dictionary reference circuit 106. The dictionary reference circuit 106 writes the uncompressed data sequence 31 to dictionaries 110-1 to 110-N. If the dictionary reference circuit 106 does not include an interface for writing to multiple dictionaries 110-1 to 110-N, a writing circuit is connected to the decoding circuit 108 and dictionaries 110-1 to 110-N. In this case, this writing circuit, rather than the dictionary reference circuit 106, writes the uncompressed data sequence 31 to dictionaries 110-1 to 110-N.

[0115] Although not shown in the diagram, the dictionary-style expansion circuit 52 includes a buffer memory.

[0116] Figures 8 to 10 are flowcharts illustrating an example of the processing of the dictionary-type expansion circuit 52 according to this embodiment.

[0117] First, the literal / match separation circuit 102 operates. The literal / match separation circuit 102 includes a symbol counter cs and a match counter cm.

[0118] The literal / match separation circuit 102 acquires a dictionary-compressed symbol sequence 32 for one cycle (step S502). The literal / match separation circuit 102 stores the acquired dictionary-compressed symbol sequence 32 in buffer memory.

[0119] The literal / match separation circuit 102 obtains the number of dictionary-compressed symbols SN included in the acquired dictionary-compressed symbol sequence 32 (step S504). The literal / match separation circuit 102 also stores the number of dictionary-compressed symbols SN in the buffer memory.

[0120] The literal / match separation circuit 102 initializes the symbol counter cs (cs=0) (step S506).

[0121] The literal / match separation circuit 102 initializes the match counter cm (cm=0) (step S508).

[0122] The literal / match separation circuit 102 reads one (in this case, the first) dictionary-compressed symbol from the one-cycle dictionary-compressed symbol sequence 32 from the buffer memory and determines whether the dictionary-compressed symbol is a literal symbol or a match symbol. The literal / match separation circuit 102 outputs the dictionary-compressed symbol determined to be a literal symbol to the decode circuit 108 and outputs the dictionary-compressed symbol determined to be a match symbol to the dictionary assignment circuit 104 (step S512). The literal / match separation circuit 102 also outputs the byte position of the literal symbol in the one-cycle dictionary-compressed symbol sequence 32 along with the literal symbol. The literal / match separation circuit 102 also outputs information representing the starting byte position of the match symbol in the one-cycle dictionary-compressed symbol sequence along with the match symbol. The decode circuit 108 writes the literal symbol and byte position information to the buffer memory. The dictionary assignment circuit 104 writes the match symbol and starting byte position information to the buffer memory.

[0123] The literal / match separation circuit 102 increments the symbol counter cs by 1 (cs = cs + 1) (step S514).

[0124] The literal / match separation circuit 102 determines whether the result of the dictionary compression symbol determination in step S512 was a match symbol (step S516).

[0125] If the result of the determination in step S512 is a match symbol (Yes in step S516), the literal / match separation circuit 102 increases the match counter cm by 1 (cm = cm + 1) (step S518).

[0126] If the result of the determination in step S512 is not a match symbol, that is, if it is determined to be a literal symbol (No. in step S516), or if the match counter cm is incremented by 1 in step S518, the literal / match separation circuit 102 determines whether the symbol counter cs is equal to the number of dictionary-compressed symbols SN in one cycle (step S522).

[0127] If the symbol counter cs is not equal to the number of dictionary-compressed symbols SN (No. in step S522), the literal / match separation circuit 102 reads the next dictionary-compressed symbol in the sequence of dictionary-compressed symbols for one cycle from the buffer memory and determines whether the next dictionary-compressed symbol is a literal symbol or a match symbol. The literal / match separation circuit 102 outputs the dictionary-compressed symbol determined to be a literal symbol to the decode circuit 108 and outputs the dictionary-compressed symbol determined to be a match symbol to the dictionary allocation circuit 104 (step S512). The dictionary allocation circuit 104 stores the sequence of match symbols output from the literal / match separation circuit 102 and the starting byte position information of the match symbols in the buffer memory.

[0128] If the symbol counter cs is equal to the number of dictionary-compressed symbols SN (Yes in step S522), the literal / match separation circuit 102 sets the match counter cm to the number of matches MN and outputs the number of matches MN to the dictionary assignment circuit 104 (step S524). The dictionary assignment circuit 104 writes the number of matches MN to the buffer memory.

[0129] The dictionary assignment circuit 104 includes a far-field match counter Fcm. The far-field match counter Fcm represents the number of unprocessed far-field match symbols. A far-field match symbol is a match symbol whose offset is greater than the second size. Literal symbols, which are the expanded results of far-field match symbols, are not stored in the neighbor dictionaries 110-2 to 110-N, but are stored only in the full-size dictionary 110-1. An unprocessed far-field match symbol is a match symbol that has not been used for dictionary lookup. The dictionary assignment circuit 104 initializes the far-field match counter Fcm (Fcm=0) (step S526).

[0130] The dictionary assignment circuit 104 initializes the match counter cm (cm=0) (step S528).

[0131] The dictionary allocation circuit 104 reads one match symbol (in this case, the first one) from the match symbol sequence output from the literal / match separation circuit 102 from the buffer memory and determines whether the offset contained in the match symbol is greater than the second size, which is the size of the neighbor dictionaries 110-2 to 110-N (step S532). This determination determines whether the uncompressed data corresponding to the match symbol is stored in the neighbor dictionaries 110-2 to 110-N.

[0132] If the offset is greater than the second size (step S532, Yes), the dictionary assignment circuit 104 changes the position of the match symbol in the match symbol sequence output from the dictionary assignment circuit 104 to the beginning position (step S534). Due to this change in the position of the match symbol in the match symbol sequence, match symbols with an offset of the second size or greater are assigned to the full-size dictionary 110-1.

[0133] The dictionary assignment circuit 104 increments the far-range match counter Fcm by 1 (Fcm = Fcm + 1) (step S536).

[0134] If the offset is not greater than the second size (step S532, No) or after increasing the far match counter Fcm by 1 in step S536, the dictionary assignment circuit 104 increases the match counter cm by 1 (cm = cm + 1) (step S538).

[0135] The dictionary assignment circuit 104 determines whether the match counter cm is equal to the number of matches MN (step S542).

[0136] If the match counter cm is not equal to the number of matches MN (No. in step S542), the dictionary assignment circuit 104 reads the next match symbol in the match symbol sequence output from the literal / match separation circuit 102 from the buffer memory and determines whether the offset contained in the match symbol is greater than the second size (step S532).

[0137] If the match counter cm is equal to the number of matches MN (Yes in step S542), the dictionary assignment circuit 104 determines whether the far-field match counter Fcm is greater than the number of full-size dictionaries (1 in the example in Figure 7) (step S546). The number of full-size dictionaries is stored in the dictionary assignment circuit 104 when designing the dictionary expansion circuit 52.

[0138] In the example in Figure 7, if the distant match counter Fcm is 2 or more, that is, if the match symbol sequence stored in the buffer memory contains two or more unprocessed match symbols with offsets greater than the second size, the result of step S546 is Yes. If the distant match counter Fcm is greater than the number of full-size dictionaries, it is not possible to simultaneously assign two or more unprocessed match symbols with offsets greater than the second size to one full-size dictionary 110-1. Therefore, if the distant match counter Fcm is greater than the number of full-size dictionaries (Yes in step S546), the dictionary assignment circuit 104 outputs the match symbol at the beginning of the unprocessed match symbols in the match symbol sequence stored in the buffer memory to the dictionary reference circuit 106 (step S548).

[0139] The dictionary assignment circuit 104 subtracts 1 from the far-range match counter Fcm (step S552).

[0140] The dictionary assignment circuit 104 issues a stall command (step S554) that stops all operations of the literal / match separation circuit 102, the dictionary assignment circuit 104, and the decode circuit 108, as well as the dictionary lookup circuit 106's write operation to the dictionary (however, the dictionary lookup circuit 106's read operation from the dictionary (dictionary lookup operation) is not stopped).

[0141] The dictionary lookup circuit 106 reads a literal symbol of the size of the match length from the reference address of the full-size dictionary 110-1 based on the offset and match length of a single match symbol received from the dictionary assignment circuit 104, and outputs the literal symbol as dictionary lookup data to the decode circuit 108 (step S556).

[0142] After this, all circuits of the dictionary expansion circuit 52 stop operating and wait until the next cycle (step S557). In the next cycle, the dictionary allocation circuit 104 determines whether the far-field match counter Fcm is greater than or equal to the number of full-size dictionaries (step S546). If the far-field match counter Fcm is greater than the number of full-size dictionaries, steps S548, S552, S554, S556, and S557 are executed. In the example in Figure 7, if the match symbol sequence stored in the buffer memory contains two or more unprocessed match symbols with offsets greater than the second size, the full-size dictionary 110-1 is referenced once per cycle for one unprocessed match symbol with an offset greater than the second size.

[0143] In the example in Figure 7, if the far-field match counter Fcm is 1, that is, if the match symbol sequence stored in the buffer memory contains one unprocessed match symbol with an offset greater than the second size, the result of step S546 is No. In this case, the unprocessed match symbols in the match symbol sequence stored in the buffer memory include one match symbol located at the beginning with an offset greater than the second size, and at least one match symbol located second or later with an offset not greater than the second size. If the far-field match counter Fcm is equal to or less than the full-size dictionary size (No in step S546), the dictionary allocation circuit 104 outputs all unprocessed match symbols in the match symbol sequence stored in the buffer memory to the dictionary lookup circuit 106 (step S558).

[0144] The dictionary lookup circuit 106 looks up the full-size dictionary 110-1 based on the first match symbol in the match symbol sequence received from the dictionary assignment circuit 104, and also looks up neighbor dictionaries 110-2, ... based on the second and subsequent match symbols, simultaneously reading up multiple literal symbols from the reference addresses of multiple dictionaries 110-1, 110-2, ... and simultaneously outputting the multiple literal symbols as multiple dictionary lookup data to the decoding circuit 108 (step S562).

[0145] The decoding circuit 108 assigns the dictionary reference data (literal symbols) to the uncompressed data sequence 31 in an arrangement based on the starting byte position information of the match symbols used to read the dictionary reference data (step S564).

[0146] The decoding circuit 108 assigns literal symbols to the uncompressed data sequence 31 in an arrangement based on byte position information (step S566).

[0147] The decoding circuit 108 outputs dictionary reference data (literal symbols) and an uncompressed data sequence 31 to which the literal symbols are assigned (step S568).

[0148] In the dictionary-style decompression circuit 52 according to this embodiment, the sizes of the multiple dictionaries 110-1 to 110-N that store the history of previously output uncompressed data are non-uniform. In the dictionary-style decompression circuit 52, dictionaries are referenced based on the offset of the match symbol, and the uncompressed data corresponding to the match symbol is read from the dictionary. The storage size of dictionaries 110-1 to 110-N is determined by the maximum offset value. The maximum offset value that the dictionary-style decompression circuit 52 should support is determined according to the corresponding compression algorithm. Among the multiple dictionaries 110-1 to 110-N, there is at least one full-size dictionary that supports the maximum offset value. At least one neighbor dictionary other than the full-size dictionary (in this embodiment, the second dictionary 110-2 to the Nth dictionary 110-N) stores the uncompressed data sequence for the first period. At least one full-size dictionary (in this embodiment, the first dictionary 110-1) stores the uncompressed data sequence for the first and second periods. The size of the neighbor dictionary is smaller than the size of the full-size dictionary. This reduces the total size of multiple dictionaries 110-1 to 110-N, thereby reducing the circuit size of the dictionary-style expansion circuit 52 and improving throughput.

[0149] If the offset of a match symbol points to data in the second period, it is not possible to refer to the neighbor dictionary based on the match symbol. For this reason, the dictionary expansion circuit 52 includes a dictionary assignment circuit 104. The dictionary assignment circuit 104 determines, based on the offset of the match symbol, whether the dictionary referenced by the dictionary reference circuit 106 should be a full-size dictionary or a neighbor dictionary.

[0150] If the number of match symbols whose offsets point to data in the second period is greater than the number of entries in the full-size dictionary, parallel referencing of the full-size dictionary is not possible. In this case, one full-size dictionary reference is performed per cycle for one match symbol, and the full-size dictionary reference is performed over multiple cycles. Although the match symbols generated by data compression depend on the data being compressed, the probability that the offset of a match symbol points to data in the first period is higher than the probability that the offset of the match symbol points to data in the second period. Therefore, according to the dictionary-type decompression circuit 52 of this embodiment, the circuit size can be reduced while suppressing a decrease in throughput.

[0151] Figure 11 is a block diagram illustrating an example of a dictionary-style expansion circuit 52A according to a comparative example. The dictionary-style expansion circuit 52A includes multiple dictionaries 110A-1 to 110A-N instead of multiple dictionaries 110-1 to 110-N, and does not include a dictionary assignment circuit 104. The size of each of the multiple dictionaries 110A-1 to 110A-N is the same as the size of the first dictionary 110-1 according to the embodiment. That is, the dictionary-style expansion circuit 52A according to the comparative example includes N full-size dictionaries 110A-1 to 110A-N, and does not include a neighbor dictionary.

[0152] Figure 12 shows experimental results illustrating the throughput sufficiency of the comparative example, the embodiment, and the second comparative example supporting only one dictionary lookup. The comparative example includes N full-size dictionaries, as shown in Figure 11. The embodiment includes one full-size dictionary and (N-1) neighbor dictionaries, as shown in Figure 7. The second comparative example has one dictionary, which is a full-size dictionary. The size of the full-size dictionary is 32 KiB, and the size of the neighbor dictionary is 2 KiB.

[0153] Figure 12 shows the throughput sufficiency rate when the requested throughput is 2, 4, and 8 bytes / cycle. The throughput sufficiency rate is the actual throughput divided by the requested throughput. Here, it is assumed that data compressed using a compression algorithm with a minimum match length of 3, similar to the gzip algorithm, is decompressed. The data used for dictionary compression consisted of four datasets commonly used as benchmarks for compressed data: the Calgary corpus, Maximum Compression, Canterbury corpus, and Silesia corpus. The number of dictionary lookups occurring simultaneously, i.e., the number of dictionary reads required, is 1, 2, and 3 for requested throughputs of 2, 4, and 8 bytes / cycle, respectively.

[0154] In the second comparative example, when the requested throughput exceeded the minimum match length of 3, reaching 4 (bytes / cycle), the number of simultaneous dictionary lookups decreased to 2, and the throughput sufficiency rate dropped to 97%. This trend became more pronounced with increasing requested throughput, and when the requested throughput reached 8 (bytes / cycle), the throughput sufficiency rate fell to 80%.

[0155] To achieve the required throughput, i.e., a throughput satisfaction rate of 100%, it is desirable to use a comparative example that supports all simultaneous dictionary lookups. However, since the comparative example includes N full-size dictionaries, it has the problem of increasing the circuit size.

[0156] In the data decompression device according to this embodiment, the number of full-size dictionaries is 1, and the remaining dictionaries are neighbor dictionaries of a smaller size. Therefore, when the required throughput increases, the increase in the total dictionary size is kept smaller compared to the comparative example, while maintaining a higher throughput sufficiency compared to Comparative Example 2.

[0157] [Example of dictionary structure] Examples of each dictionary 110 according to the embodiment will be described.

[0158] First, we will explain an example in which each dictionary 110 is composed of an SRAM (also called 1RW-SRAM) equipped with one write / read port.

[0159] Figure 13 is a diagram illustrating an example of dictionaries 110-1 to 110-N according to the embodiment. Each of dictionaries 110-1 to 110-N is composed of one 1RW-SRAM 602. Each of dictionaries 110-1 to 110-N is connected to the dictionary reference circuit 106 via a write / read port. The write / read port includes multiple terminals to which the CLK signal, CE signal, WE signal, address, and write data are input, and a terminal to which read data is output. The CLK signal is a clock representing the read / write timing. The CE signal is a chip enable signal indicating that the 1RW-SRAM 602 is enabled. The WE signal is a write enable signal specifying a write or read operation of the 1RW-SRAM 602.

[0160] An address specifies the storage location of data within the 1RW-SRAM602. There are n storage locations, specified by addresses 0 through n-1. A single address specifies a storage location where multiple bytes of data (called a word) are stored. The data width of a word depends on the throughput. If the throughput is 8 bytes / cycle, the byte width of one word is 8, and 8 bytes of data are stored in one address.

[0161] Since the 1RW-SRAM602 has one write / read port, a write or read operation to the 1RW-SRAM602 is performed once per clock cycle.

[0162] Figure 14 is a diagram illustrating an example of reading from a dictionary 110 consisting of a 1RW-SRAM 602 according to an embodiment. Assume that the byte width of one word is 8. Eight bytes of data are stored at eight byte positions in each address. In Figure 14, 0, 1, ... in each address represent byte positions. The dictionary lookup circuit 106 can read eight bytes of data from any address in one cycle. However, the offset that defines the reference address which becomes the dictionary read address is in units of one byte, not eight bytes. In this case, the reference address included in the dictionary lookup command is a byte position. The dictionary lookup circuit 106 needs to read eight bytes of data from an arbitrary byte position in a certain address. When reading eight bytes of data from an arbitrary byte position in a certain address, it may not be possible to read eight bytes of data in one cycle. If the byte position at the start of the read within the address is a byte position that is a multiple of eight, the dictionary lookup circuit 106 can read eight bytes of data in one cycle. However, if the byte position at the start of the read is not a multiple of 8, the dictionary lookup circuit 106 is unable to read 8 bytes of data in one cycle.

[0163] Next, we will describe another example of a dictionary in which the dictionary lookup circuit 106 can read 8 bytes of data from any byte position in one cycle.

[0164] Figure 15 is a diagram illustrating another example of dictionaries 110-1 to 110-N according to the embodiment. Each of dictionaries 110-1 to 110-N consists of two 1RW-SRAMs 602-0 and 602-1. 1RW-SRAM 602-0 is connected to the dictionary reference circuit 106 via write / read port 0. 1RW-SRAM 602-1 is connected to the dictionary reference circuit 106 via write / read port 1.

[0165] The first 8 bytes of data are stored at address 0 (byte positions 0-7) of 1RW-SRAM602-0. The next 8 bytes of data are stored at address 0 (byte positions 8-15) of 1RW-SRAM602-1. Similarly, the data is stored alternately in 8-byte chunks at each address of 1RW-SRAM602-0 and 602-1.

[0166] When the dictionary lookup circuit 106 reads data from each dictionary 110, it starts reading from either 1RW-SRAM 602-0 or 602-1 depending on the byte position at the start of the read. If the byte position at the start of the read is included in 1RW-SRAM 602-0, the dictionary lookup circuit 106 reads data from address Aa of 1RW-SRAM 602-0, and then reads data from address Ab (=Aa) of 1RW-SRAM 602-1. If the byte position at the start of the read is included in 1RW-SRAM 602-1, the dictionary lookup circuit 106 reads data from address Ab of 1RW-SRAM 602-1, and then reads data from address Aa (=Ab+1) of 1RW-SRAM 602-0. In other words, depending on whether the byte position at the start of the read operation falls within 1RW-SRAM602-0 or 602-1, the address of the second 1RW-SRAM602 to be read is obtained by adding 0 or 1 to the address of the first 1RW-SRAM602 to be read.

[0167] Assume the byte position at the start of the read is 29 (decimal). If the dictionary size is 2 KiB, the byte unit address is 11 bits, and the binary representation of 29 is "00000011101". The upper 7 bits of the start byte position, "0000001", represent the address of 1RW-SRAM602, the lower 3 bits, "101", represent the start byte position within the word, and the 8th bit from the most significant indicates whether the read start byte position is contained in 1RW-SRAM602-0 or 602-1. A "1" in the 8th bit indicates that the read start byte position is contained in 1RW-SRAM602-1. A "0" in the 8th bit indicates that the read start byte position is contained in 1RW-SRAM602-0. Since the 8th bit is "1", the upper 7 bits "0000001" represent address 1 of 1RW-SRAM602-1. The dictionary lookup circuit 106 reads 3 bytes of data from byte position 29 at address 1 of 1RW-SRAM 602-1, and 5 bytes of data from the first byte position 32 at address 2 (=1+1) of 1RW-SRAM 602-0. This allows the desired 8 bytes of data to be read from the 16 bytes of data stored at the two addresses of the two 1RW-SRAMs, 602-0 and 602-1.

[0168] If the byte position at the start of the read is 3 (binary representation "00000000011"), the dictionary lookup circuit 106 reads 5 bytes of data from byte position 3 at address 0 of 1RW-SRAM602-0, and reads 3 bytes of data from the first byte position 8 at address 0 (=0) of 1RW-SRAM602-1. This allows the desired 8 consecutive bytes of data to be read from the 16 bytes of data stored at one address of the two 1RW-SRAMs, 602-0 and 602-1.

[0169] By configuring each dictionary 110 with two 1RW-SRAMs, 602-0 and 602-1, the dictionary lookup circuit 106 can read 8 bytes of data from any byte position in one cycle.

[0170] Next, we will explain an example of configuring a dictionary using multi-port SRAM.

[0171] Figure 16 is a diagram illustrating yet another example of dictionaries 110-1 to 110-N according to the embodiment. Each of dictionaries 110-1 to 110-N consists of one multi-port SRAM 606 (also referred to as 1R1W-SRAM) having one write port and one read port. The data width of the 1R1W-SRAM 606 is at least the number of bytes equivalent to the throughput. The write port includes multiple terminals to which the WCLK signal, WEN signal, write address, and write data are input, respectively. The WCLK signal is a clock representing the write timing. The WEN signal is a write enable signal indicating that writing to the 1R1W-SRAM 606 is enabled. The write address specifies the storage location in the 1R1W-SRAM 606 where the data is written. The read port includes multiple terminals to which the RCLK signal, REN signal, and read address are input, respectively, and a terminal to which read data is output. The RCLK signal is a clock representing the read timing. The REN signal is a read-enable signal that indicates that reading from 1R1W-SRAM606 is enabled. The read address specifies the storage location of the data to be read within 1R1W-SRAM606.

[0172] Since the 1R1W-SRAM606 has one write port and one read port, the dictionary lookup circuit 106 can perform one write operation and one read operation of the 1R1W-SRAM606 simultaneously in one cycle. Because the clock is also separated into a WCLK signal for writing and an RCLK signal for reading, the dictionary lookup circuit 106 can also perform the write and read operations of the 1R1W-SRAM606 based on clocks of different operating frequencies.

[0173] To enable the reading of a number of bytes equivalent to the throughput from any byte position in the dictionary 110, which is composed of 1R1W-SRAM606, in one cycle, the dictionary 110 can be composed of two 1R1W-SRAM606, as shown in Figure 15.

[0174] Figure 17 illustrates yet another example of dictionaries 110-1 to 110-N according to the embodiment. Each of dictionaries 110-1 to 110-N consists of a multi-port SRAM (also referred to as 2RW-SRAM) 612 having two write / read ports. The data width of the 2RW-SRAM 612 is at least the number of bytes equivalent to the throughput. Each of the two write / read ports includes multiple terminals to which the CLK signal, CE signal, WE signal, address, and write data are input, and a terminal to which read data is output.

[0175] Since the 2RW-SRAM612 has two write / read ports, the dictionary lookup circuit 106 can perform one write operation and one read operation on the 2RW-SRAM612 simultaneously in one cycle, two write operations simultaneously in one cycle, or two read operations simultaneously in one cycle. Since the clock is also divided into CLK0 and CLK1 signals for the two ports, the dictionary lookup circuit 106 can also perform write or read operations on the two ports of the 2RW-SRAM612 based on clocks of different operating frequencies.

[0176] Since the 2RW-SRAM612 can perform two read operations simultaneously in one cycle, the dictionary lookup circuit 106 can read a number of bytes equivalent to the throughput from any byte position in the dictionary 110, which is composed of the 2RW-SRAM612, in one cycle.

[0177] Figure 18 is a diagram illustrating another example of the multiport SRAM of the embodiment. Another example of SRAM is an SRAM (also referred to as 2R1W-SRAM)616 with one write port and two read ports. The data width of the 2R1W-SRAM616 is at least the number of bytes equivalent to the throughput.

[0178] The 2R1W-SRAM616 features one write port and two read ports, allowing for one write operation and two read operations to be performed simultaneously in a single cycle. The clock is also divided into WCLK, RCLK0, and RCLK1 signals for the three ports, enabling one write operation and two read operations to be performed based on clocks with different operating frequencies.

[0179] Figure 19 is a diagram illustrating yet another example of dictionaries 110-1 to 110-N according to the embodiment. Each of dictionaries 110-1 to 110-N is composed of a 2R1W-SRAM616.

[0180] Since the 2R1W-SRAM616 can perform two read operations simultaneously in one cycle, the dictionary lookup circuit 106 can read a number of bytes equivalent to the throughput from any byte position in the 2R1W-SRAM616 in one cycle.

[0181] In the above description, each dictionary 110 is configured with an SRAM dedicated to that dictionary. By using a multi-port SRAM, multiple dictionaries can be configured with a common SRAM, thereby reducing the circuit size. Figure 20 is a diagram illustrating yet another example of dictionaries 110-1 to 110-N according to the embodiment. In the example of Figure 20, any two dictionaries from dictionaries 110-2 to 110-N, for example, the second dictionary 110-2 and the third dictionary 110-3, are configured in common with one 2R1W-SRAM 616. The second dictionary 110-2 uses read port 0 as its read port, and the third dictionary 110-3 also uses read port 0 as its read port. The write port is used in common by the second dictionary 110-2 and the third dictionary 110-3. The configuration of other dictionaries is arbitrary.

[0182] In the example in Figure 20, since there is only one read port each for the second dictionary 110-2 and the third dictionary 110-3, it may not be possible to read 8 consecutive bytes of data from an arbitrary byte position, similar to the example in Figure 13.

[0183] Figure 21 is a diagram illustrating yet another example of dictionaries 110-1 to 110-N according to the embodiment. In the other example, any two dictionaries from dictionaries 110-2 to 110-N, for example, the second dictionary 110-2 and the third dictionary 110-3, are commonly configured by two 2R1W-SRAMs 616-0 and 616-1. Each of the 2R1W-SRAMs 616-0 and 616-1 is connected to the dictionary reference circuit 106 via one write port and two read ports.

[0184] In the example shown in Figure 21, since the second dictionary 110-2 and the third dictionary 110-3 each have two read ports, the dictionary lookup circuit 106 can read 8 bytes of consecutive data from any byte position in both the second dictionary 110-2 and the third dictionary 110-3.

[0185] Next, we will explain an example of constructing dictionary 110 using flip-flops.

[0186] While the data storage principles of flip-flops and SRAMs are almost identical, differences arise when constructing dictionaries. SRAMs are manufactured using hard macros that meticulously design the physical arrangement and layout of their internal elements. In SRAMs, circuit area and power consumption are minimized through optimization. On the other hand, when constructing an SRAM-equivalent circuit using flip-flops, optimization is performed using CAD tools, including peripheral circuits. However, optimization of flip-flops cannot optimize circuit area and power consumption to the same extent as SRAMs. One advantage of flip-flops is that the circuit can be flexibly modified. For example, when constructing an SRAM-equivalent circuit using flip-flops, it is possible to implement a number of write ports and read ports that do not exist in typical SRAMs. For example, while an SRAM can have around two read ports, an SRAM with 10 read ports does not generally exist. In dictionaries constructed with multi-port SRAMs, the type of multi-port SRAM is defined at the design stage by the type and number of ports. However, when constructing an SRAM-equivalent dictionary using flip-flops, the designer can add any number of read and write ports.

[0187] Using flip-flops, it's possible to construct a dictionary where words of several bytes are treated as a single data unit and accessed at a single address, similar to SRAM. SRAM has built-in read / write circuits. However, flip-flops do not have built-in read / write circuits. When constructing a dictionary using flip-flops, a separate read / write circuit must be provided in addition to the flip-flops.

[0188] Figure 22 is a diagram illustrating yet another example of dictionaries 110-1 to 110-N according to the embodiment. In the example of Figure 22, each of dictionaries 110-1 to 110-N includes dictionary circuits 700-0, 700-1, ... 700-(n-1). Each of dictionary circuits 700-0 to 700-(n-1) is assigned one address and stores one word (8 bytes: 64 bits) of data. n is the number of addresses, i.e., the number of words stored by each of dictionaries 110-1 to 110-N, as in the dictionary configured with SRAM shown in Figure 13.

[0189] Figure 23 is a diagram illustrating an example of writing to each of the dictionary circuits 700-0 to 700-(n-1) shown in Figure 22. Each of the dictionary circuits 700-0 to 700-(n-1) includes a writing circuit 710 and a flip-flop circuit 702.

[0190] The flip-flop circuit 702 is composed of 64 flip-flops 704-0, 704-1, ..., 704-63. Each of the flip-flops 704-0 to 704-63 stores 1 bit of data. The clock CLK output from the dictionary lookup circuit 106 is input to the clock terminal of each of the flip-flops 704-0 to 704-63.

[0191] The programming circuit 710 includes an AND gate 712, an address decoder 714, an AND gate 716, and 64 multiplexers 718-0 to 718-63. The inverted signals of the CE and WE signals output from the dictionary lookup circuit 106 are input to the AND gate 712. The address output from the dictionary lookup circuit 106 is input to the address decoder 714. The address decoder 714 outputs a "1" signal if the address specifies the dictionary circuit 700-0 to 700-(n-1). The output of the AND gate 712 and the output of the address decoder 714 are input to the AND gate 716.

[0192] The output of AND gate 716 is input to the control terminals of multiplexers 718-0 to 718-63. The write data for each bit 0 to 63 is input to the first input terminal of each multiplexer 718-0 to 718-63. The output signal Q of flip-flops 704-0 to 704-63 is input to the second input terminal of each multiplexer 718-0 to 718-63. The output signals of each multiplexer 718-0 to 718-63 are input to the input terminal D of flip-flops 704-0 to 704-63. Each multiplexer 718-0 to 718-63 outputs the write data input to the first input terminal when the output signal of AND gate 716 is a "1" signal.

[0193] The write circuit 710, like SRAM, can control the writing of one word of data to flip-flops 704-0 to 704-63 by address. For this reason, the flip-flop circuit 702 is also called an address-writing flip-flop circuit. The n write circuits 710 included in the dictionary circuit correspond to a single write port.

[0194] Figure 24 is a diagram illustrating an example of reading each of the dictionary circuits 700-0 to 700-(n-1) shown in Figure 22. For simplicity of explanation, the address is assumed to be 7 bits, and the total number of addresses n is assumed to be 128. Each of the flip-flop circuits 702-0 to 702-127 outputs the output signal Q of the 64 flip-flops 704-0 to 700-63 in parallel, i.e., one word of data, to the readout circuit 720. The address values ​​of the flip-flop circuits 702-0 to 702-127 are 0 to 127, respectively.

[0195] The readout circuit 720 includes a group of multiplexers with multiple stages (=log2(n)). The number of multiplexers in each stage is half the number of multiplexers in the previous stage. Since n=128, the number of stages in the multiplexer group is 7=log2(128).

[0196] The first stage of the multiplexer group, to which the output signals of the flip-flop circuit 702 are input, contains 64 (=n / 2=128 / 2) multiplexers 732-0 to 732-63. The outputs of two flip-flop circuits 702 with consecutive address values ​​are input to one multiplexer 732. Multiplexer 732 selects one of the two inputs based on the address [0] of bit 0. If address [0] is "0", multiplexer 732 selects the output of the flip-flop circuit 702 with the smaller address value.

[0197] The second stage of multiplexers contains 32 (=n / 4=128 / 4) multiplexers 734-0, ... . The outputs of two multiplexers 732, each connected to four consecutive flip-flop circuits 702, are input to the second stage multiplexer 734. Multiplexer 734 selects one of the two inputs based on the address [1] of bit 1. If address [1] is "0", multiplexer 734 selects the output of the flip-flop circuit 702 with the smaller address value.

[0198] The multiplexers in each stage are configured similarly, with the 7th (final) stage containing 1 (=n / 128=128 / 128) multiplexers 742. The outputs of the two multiplexers in the 6th stage are input to multiplexer 742. Multiplexer 742 selects one of the two inputs based on the address [6] in bit 6. If address [6] is "0", multiplexer 742 selects the output of the flip-flop circuit 702 with the smaller address value.

[0199] The read circuit 720 reads data from the flip-flop circuit 702, which stores each word, selects one word based on each bit of the address, and outputs the selection result as read data. The read circuit 720 is a circuit that corresponds to one read port.

[0200] Next, we will explain an example of constructing a shift register type dictionary using flip-flops.

[0201] Figure 25 is a diagram illustrating another example of writing to each of the dictionaries 110-1 to 110-N shown in Figure 22. Each of the dictionaries 110-1 to 110-N includes a write circuit 710A-0, 710A-1, ... and a flip-flop circuit 702-0, 702-1, ... for each address.

[0202] Each of the flip-flop circuits 702-0, 702-1, ... is the same as the flip-flop circuit 702 shown in Figure 23.

[0203] Each of the writing circuits 710A-0, 710A-1, etc., is the same as the writing circuit 710 shown in Figure 23, but with the address decoder 714 and AND gate 716 removed. In Figure 23, all bits of the write data are written in parallel to the flip-flops 704-0, etc. of each bit in the flip-flop circuit 702 for each address, via the multiplexers 718-0, ... of each bit in the writing circuit 710 for each address. In the example in Figure 25, all bits of the write data are written in parallel to the flip-flops 704-0, ... of each bit in the flip-flop circuit 702-0 for address 0, via the multiplexer 718-0, ... of the writing circuit 710A-0 for address 0. The flip-flops 704-0, ... of each bit in the flip-flop circuit 702-0 output the data they were holding from the Q terminal when data is written to the D terminal, in synchronization with the clock CLK.

[0204] The read data for each bit output from the flip-flop circuit 702-0 at address 0 is written in parallel to the flip-flops 704-0, ... for each bit of the flip-flop circuit 702-1 at address 1, via the multiplexers 718-0, ... for each bit of the write circuit 710A-1 at address 1.

[0205] Similarly, the read data from each bit of the flip-flop circuit 702-i at address i is written to each bit of the flip-flop 704 of the flip-flop circuit 702-(i+1) at address (i+1) via the multiplexer 718 of each bit of the write circuit 710A-(i+1) at address (i+1). In this way, the write data is written to the flip-flop circuit 702-0 at address 0. The data held in each bit of the flip-flop circuit 702 is shifted to the flip-flop circuit 702 of the next address in synchronization with the clock CLK.

[0206] The readout circuits for dictionaries 110-1 to 110-N shown in Figure 25 are the same as the readout circuit 720 shown in Figure 24. In the above explanation, the address for dictionary lookup was defined as the current write address minus the address corresponding to the offset of the match symbol. In the case of a dictionary using a shift register type flip-flop circuit 702A, the most recent data is always written to address 0, so the current write address is address 0. Therefore, the dictionary lookup address is essentially generated based only on the offset.

[0207] A modified example of the embodiment will be described.

[0208] [Example 1] The number of entries in the first dictionary entry 110-1 is not limited to one; it may be two or more.

[0209] [Differentiation 2] In this embodiment, the memory size of each of the neighbor dictionaries 110-2 to 110-N is assumed to be the same as the second size, but they may be different sizes.

[0210] For example, the memory size of at least one dictionary (also called the first neighbor dictionary) that is part of the neighbor dictionaries 110-2 to 110-N may be defined as the second size, and the memory size of at least one dictionary (also called the second neighbor dictionary) that is part of the remaining neighbor dictionaries 110-2 to the Nth dictionary 110-N may be defined as the third size. The order of size is: first size (memory size of full-size dictionary 110-1) > second size > third size.

[0211] Since the neighbor dictionary is divided into two types, the first period of the embodiment, which is the period for writing to the neighbor dictionary, is divided into period 1A and period 1B. Period 1A is the most recent period. Period 1B is the period prior to period 1A. The second period of the modified example corresponds to the second period of the embodiment.

[0212] During period 1A, at least one uncompressed data set decompressed by the dictionary-style decompression circuit 52 is stored in the full-size dictionary 110-1, the first neighbor dictionary, and the second neighbor dictionary. The end of period 1A is the point in time when the latest uncompressed data set decompressed by the dictionary-style decompression circuit 52 is stored in the full-size dictionary 110-1, the first neighbor dictionary, and the second neighbor dictionary.

[0213] At least one uncompressed data file decompressed by the dictionary-style decompression circuit 52 during period 1B is stored in the first dictionary 110-1 and the first neighbor dictionary, but not in the second neighbor dictionary. The end of period 1B is the beginning of period 1A.

[0214] At least one uncompressed data file decompressed by the dictionary-style decompression circuit 52 during the second period prior to the first B period is stored in the full-size dictionary 110-1, but not in the first neighbor dictionary or the second neighbor dictionary. The end of the second period is the beginning of the first B period.

[0215] In other words, the second neighbor dictionary stores the uncompressed data output during the first A period. The first neighbor dictionary stores the uncompressed data output during the first A and first B periods. The full-size dictionary 110-1 stores the uncompressed data output during the first A, first B, and second periods.

[0216] The storage of the uncompressed data that is last stored in the second neighbor dictionary from among the at least one uncompressed data expanded in period 1A, the storage of the uncompressed data that is last stored in the first neighbor dictionary from among the at least one uncompressed data expanded in periods 1A and 1B, and the storage of the uncompressed data that is last stored in the full-size dictionary 110-1 from among the at least one uncompressed data expanded in periods 1A, 1B, and 2, are all performed in the same cycle.

[0217] Thus, the full-size dictionary 110-1 stores the uncompressed data sequence 31, which is the decompression result of the first A period, the first B period, and the second period. The first neighbor dictionary stores the uncompressed data sequence 31, which is the decompression result of the first A period and the first B period. The second neighbor dictionary stores the uncompressed data sequence 31, which is the decompression result of the first A period.

[0218] This modification also allows for the parallel execution of data retrieval from the full-size dictionary 110-1, data retrieval from the first neighbor dictionary, and data retrieval from the second neighbor dictionary.

[0219] Alternatively, the memory sizes of each of the neighbor dictionaries 110-2 to the Nth dictionary 110-N may be different sizes. If we let the memory size of the first dictionary 110-1 be the first size, the memory size of the second dictionary 110-2 be the second size, and so on, until the memory size of the Nth dictionary 110-N is the Nth size, then the order of sizes is: first size > second size > ... > Nth size.

[0220] The first dictionary 110-1 stores uncompressed data, which is the result of decompression over the longest period from the present to the past. The second dictionary 110-2 stores uncompressed data, which is the result of decompression over the second longest period from the present to the past. Similarly, the Nth dictionary 110-N stores uncompressed data 31, which is the result of decompression over the shortest period from the present to the past.

[0221] This modification also allows for parallel execution of data retrieval from the full-size dictionary 110-1 and data retrieval from the second dictionaries 110-2 to 110-N.

[0222] If the memory size of each of the neighbor dictionaries 110-2 to 110-N is one of at least two sizes, the dictionary allocation circuit 104 compares the offset with multiple threshold sizes. For example, after step S532, which compares the offset with the second size in Figure 9, a process to compare the offset with a third size can be added, and the sorting process in step S534 can be changed to a process that sorts the symbols in descending order of offset.

[0223] If the distribution trend of the offsets in the input data is known in advance, and there are multiple ranges for frequently occurring offset distributions, then designing the nearest neighbor dictionary to support multiple offset sizes according to that distribution trend is significant from the perspective of maintaining throughput.

[0224] [Difference 3] The number N of multiple dictionaries 110-1 to 110-N may be less than or equal to the number of dictionary references that can occur simultaneously in the dictionary-style decompression circuit 52. In this case, the throughput sufficiency rate of data decompression will be 100% or less. If a throughput sufficiency rate less than 100% is acceptable, the number N may be reduced.

[0225] [Differentiation Example 4] The dictionary lookup circuit 106 looks up the first dictionary 110-1 to the Nth dictionary 110-N1 for each match symbol in the input match symbol sequence, starting from the first match symbol. Therefore, the dictionary assignment circuit 104 communicates the dictionary assignment result to the dictionary lookup circuit 106 by rearranging the positions of the match symbols in the match symbol sequence. However, the dictionary assignment circuit 104 may also determine the dictionary referenced by the match symbol based on the offset of the match symbol, and output the ID of the determined dictionary to the dictionary lookup circuit 106 by adding it to the match symbol. In this case, the dictionary lookup circuit 106 only needs to look up the dictionary specified by the dictionary ID, regardless of the input order of the match symbols.

[0226] [Difference 5] In this embodiment, since the dictionary lookup circuit 106 includes an interface for writing to the dictionary 110, the uncompressed data sequence 31 output from the decoding circuit 108 is input to the dictionary lookup circuit 106 and written to the dictionary 110 by the dictionary lookup circuit 106. However, a separate writing circuit for the dictionary 110 may be provided in addition to the dictionary lookup circuit 106, and the uncompressed data sequence 31 may be written to multiple dictionaries 110 by the writing circuit without going through the dictionary lookup circuit 106.

[0227] [Modification 6] In one embodiment, as shown in Figure 10, if the number of unprocessed match symbols with an offset greater than the second size (size of the neighboring dictionary) is greater than the number of full-size dictionary entries (Yes in step S546), the compressed data entered in one cycle is decompressed over multiple cycles. In the first or at least one cycle, only the full-size dictionary is referenced, and in the next cycle, both the full-size dictionary and the neighboring dictionary are referenced simultaneously. Modification 6 concerns a change in the timing of neighboring dictionary references.

[0228] Part or all of the neighboring dictionary may be accessed simultaneously with the full-size dictionary lookup in a previous cycle (step S556) rather than in a subsequent cycle (step S562). Figure 26 is a flowchart illustrating an example of the processing of the dictionary-style expansion circuit 52 according to Modification 6. Figure 26 is a modification of a part of Figure 10 illustrating the processing of the embodiment.

[0229] If the distant match counter Fcm is greater than the full-size dictionary size (Yes in step S546), the dictionary allocation circuit 104 outputs to the dictionary lookup circuit 106 at least some of the unprocessed match symbols in the match symbol sequence stored in the buffer memory, including the first match symbol and match symbols with an offset not greater than the second size (size of the neighboring dictionary) (step S548A). "At least some" includes all of them, but in S548A it is written as "some".

[0230] After steps S552 and S554 are performed, the dictionary lookup circuit 106 reads a literal symbol of the size of the match length from the reference addresses of the full-size dictionary 110-1 and neighbor dictionaries 110-2, ... based on the offset and match length of the match symbol received from the dictionary assignment circuit 104, and outputs the literal symbol as dictionary lookup data to the decode circuit 108 (step S556A).

[0231] If the far-field match counter Fcm is not greater than the full-size dictionary size (No. in step S546), the dictionary allocation circuit 104 outputs all unprocessed match symbols in the match symbol sequence stored in the buffer memory to the dictionary lookup circuit 106 (step S558). All unprocessed match symbols include match symbols with offsets greater than the second size and match symbols with offsets less than the second size. If all unprocessed match symbols with offsets less than the second size were output to the dictionary lookup circuit 106 in step S548A, then all unprocessed match symbols in step S558 will consist only of match symbols with offsets greater than the second size.

[0232] The dictionary lookup circuit 106 looks up the full-size dictionary 110-1 based on the first match symbol in the match symbol sequence received from the dictionary assignment circuit 104, and also looks up neighbor dictionaries 110-2, ... based on the second and subsequent match symbols, simultaneously reading up multiple literal symbols from the reference addresses of multiple dictionaries 110-1, 110-2, ... and simultaneously outputting multiple literal symbols as multiple dictionary lookup data to the decoding circuit 108 (step S562). If all unprocessed match symbols with offsets not greater than the second size are output to the dictionary lookup circuit 106 in S548A, then in step S562, neighbor dictionaries 110-2, ... are not referenced, and only the full-size dictionary 110-1 is referenced.

[0233] [Difference 7] Although the data compression device 15 and the data decompression device 16 have been described as being implemented by hardware, at least a portion of each of the data compression device 15 and the data decompression device 16 may be implemented by software executed by a processor, or by a combination of software and hardware. Examples of processors include CPUs, digital signal processors (DSPs), application-specific integrated circuits (ASICs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), microcontrollers, and controllers. Furthermore, examples of processors also include information processing devices such as computers, computer systems configured by multiple computers or servers communicating with each other via a network, or PC clusters in which multiple computers cooperate to perform information processing. In addition, instead of one processor executing a program that implements multiple functions, multiple processors may each implement at least a portion of the multiple functions.

[0234] As described above, the data decompression device 16 according to this embodiment reduces the circuit size by limiting the number of first dictionaries that enable simultaneous referencing of multiple dictionaries to a small number and substituting the remaining dictionaries with smaller neighbor dictionaries. Simply reducing the number of first dictionaries would result in a large decrease in throughput, but the dictionary assignment circuit 104 can suppress the decrease in throughput by assigning either the first dictionary or the neighbor dictionary as the dictionary for referencing the match symbol according to the offset of the match symbol.

[0235] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0236] 1... Information processing system, 2... Host, 3... Memory system, 4... NAND flash memory, 6... Controller, 11... CPU, 15... Data compression device, 16... Data decompression device, 21... Dictionary-style compression circuit, 22... Entropy coding circuit, 51... Entropy decoding circuit, 52... Dictionary-style decompression circuit, 102... Literal / match separation circuit, 104... Dictionary assignment circuit, 106... Dictionary lookup circuit, 108... Decode circuit, 110... Dictionary

Claims

1. A data decompression device for decompressing a compressed data sequence including first compressed data having a first offset obtained by dictionary-style compression, A dictionary having at least one first dictionary and at least one second dictionary that store first uncompressed data corresponding to the first compressed data, An assignment circuit that assigns the first compressed data to at least one dictionary of the at least one first dictionary or the at least one second dictionary, A reference circuit that reads the first uncompressed data from the at least one dictionary to which the first compressed data is assigned, using the first offset, The system comprises a generation circuit that generates an uncompressed data sequence including the first uncompressed data read by the reference circuit, The memory size of each of the at least one first dictionary is greater than the memory size of each of the at least one second dictionary. The first offset indicates the storage location of at least one dictionary of the at least one first dictionary or the at least one second dictionary. If the compressed data sequence includes a second compressed data having a second offset indicating the storage location of at least one of the at least one first dictionary or the at least one second dictionary, The assignment circuit assigns the first compressed data to at least one of the at least one first dictionary or the at least one second dictionary based on the first offset, and assigns the second compressed data to at least one of the at least one first dictionary or the at least one second dictionary, which is different from the dictionary to which the first compressed data was assigned, based on the second offset. The reference circuit performs in parallel the reading of the first uncompressed data using the first offset from the dictionary to which the first compressed data is assigned, and the reading of the second uncompressed data corresponding to the second compressed data using the second offset from the dictionary to which the second compressed data is assigned. The generation circuit generates the uncompressed data sequence, which includes the first uncompressed data and the second uncompressed data. Data decompression device.

2. The first offset indicates the storage location of at least one dictionary of the at least one first dictionary, The second offset indicates a storage location of at least one dictionary of the at least one second dictionary, The assignment circuit assigns the first compressed data to one of the at least one first dictionary and assigns the second compressed data to one of the at least one second dictionary. The data decompression device according to claim 1.

3. The dictionary further includes at least one third dictionary that stores first uncompressed data corresponding to the first compressed data, The memory size of each of the at least one second dictionary is greater than the memory size of each of the at least one third dictionary. The first offset indicates the storage location of at least one dictionary of the at least one first dictionary, the at least one second dictionary, or the at least one third dictionary. If the compressed data sequence includes a second compressed data having a second offset indicating the storage location of at least one of the at least one first dictionary, the at least one second dictionary, or the at least one third dictionary, The assignment circuit assigns the first compressed data to at least one of the at least one first dictionary, the at least one second dictionary, or the at least one third dictionary based on the first offset, and assigns the second compressed data to at least one of the at least one first dictionary, the at least one second dictionary, or the at least one third dictionary, which is different from the dictionary to which the first compressed data was assigned, based on the second offset. The data decompression device according to claim 1.

4. The at least one first dictionary stores at least one uncompressed data that has been decompressed by the data decompression device for a first period, a second period prior to the first period, and a third period prior to the second period. The at least one second dictionary stores at least one uncompressed data that has been decompressed by the data decompression device during the first and second periods. The at least one third dictionary stores at least one uncompressed data that was decompressed during the first period by the data decompression device. The data decompression device according to claim 3, wherein the storage of uncompressed data into the first dictionary that is last stored in the first dictionary among at least one uncompressed data decompressed during the first period, the second period, and the third period, the storage of uncompressed data into the second dictionary that is last stored in the second dictionary among at least one uncompressed data decompressed during the first period and the second period, and the storage of uncompressed data into the third dictionary that is last stored in the third dictionary among at least one uncompressed data decompressed during the third period are all performed in the same cycle.

5. Each of the at least one first dictionary and the at least one second dictionary is composed of static random access memory. The data decompression device according to claim 1.

6. Each of the at least one first dictionary and the at least one second dictionary is composed of a plurality of flip-flops. The data decompression device according to claim 1.

7. At least two of the at least one first dictionary and the at least one second dictionary are composed of elements having multiple read ports and store the same uncompressed data. The data decompression device according to claim 1.

8. The memory capacity of the at least one first dictionary depends on the maximum value of the first offset. The data decompression device according to claim 1.

9. Multiple uncompressed data decompressed by the data decompression device during a first period in the past, including the present, are stored in the at least one first dictionary and the at least one second dictionary. Multiple uncompressed data that the data decompression device decompressed in the second period prior to the first period are not stored in the at least one second dictionary. The data decompression device according to claim 1.

10. At least two of the at least one first dictionary and at least one second dictionary are each composed of at least two static random access memories, each having multiple read ports, and store the same uncompressed data. The data decompression device according to claim 1.

11. The reference circuit writes the first uncompressed data to the at least one first dictionary and the at least one second dictionary, and writes the second uncompressed data to the at least one first dictionary and the at least one second dictionary. The data decompression device according to claim 1.

12. The compressed data sequence includes a plurality of second compressed data sets, each having a second offset indicating the storage location of at least one of the at least one first dictionary or the at least one second dictionary, and the number of offsets among the first offset of the first compressed data set and the second offset of each of the plurality of second compressed data sets that are greater than a threshold corresponding to the storage size of each of the at least one second dictionary is greater than the number of the at least one first dictionary, The assignment circuit assigns to the at least one first dictionary at least one third compressed data set, which is a number of compressed data sets corresponding to the number of at least one first dictionary, from among the first compressed data and the plurality of second compressed data sets, the plurality of compressed data sets whose offset is greater than the threshold, The reference circuit performs the reading of the at least one third uncompressed data corresponding to the at least one third compressed data from the at least one first dictionary to which the at least one third compressed data is assigned. The data decompression device according to claim 1.

13. In an execution cycle one subsequent to the execution cycle in which the reference circuit performs the reading of at least one third uncompressed data, If, among the first compressed data and the plurality of second compressed data, the offset is greater than the threshold, and the number of at least one fourth compressed data, separate from the at least one third compressed data, is less than or equal to the number of at least one first dictionary, The assignment circuit assigns the at least one fourth compressed data to the at least one first dictionary, and assigns the first compressed data and the at least one fifth compressed data from the plurality of second compressed data whose offset is less than or equal to the threshold to the at least one second dictionary. The reference circuit performs in parallel the reading of at least one fourth uncompressed data corresponding to the at least one fourth compressed data from at least one first dictionary to which the at least one fourth compressed data is assigned, and the reading of at least one fifth uncompressed data corresponding to the at least one fifth compressed data from at least one second dictionary to which the at least one fifth compressed data is assigned. The generation circuit generates the uncompressed data sequence which includes at least one third uncompressed data, at least one fourth uncompressed data, and at least one fifth uncompressed data. The data expansion device according to claim 12.

14. The compressed data sequence includes a plurality of second compressed data sets, each having a second offset indicating the storage location of at least one of the at least one first dictionary or the at least one second dictionary, and the number of offsets among the first offset of the first compressed data set and the second offset of each of the plurality of second compressed data sets that are greater than a threshold corresponding to the storage size of each of the at least one second dictionary is greater than the number of the at least one first dictionary, The assignment circuit assigns at least one third compressed data set, which is a number of compressed data sets corresponding to the number of at least one first dictionary, from among the first compressed data and the plurality of second compressed data sets, the offset of which is greater than the threshold, to the at least one first dictionary, and assigns at least a portion of the plurality of compressed data sets whose offset is not greater than the threshold to the at least one second dictionary. The reference circuit performs the following: reading at least one third uncompressed data corresponding to the at least one third compressed data from at least one first dictionary to which the at least one third compressed data is assigned; and reading at least one fourth compressed data corresponding to the multiple compressed data whose offset is not greater than the threshold from at least one second dictionary to which at least a portion of the multiple compressed data whose offset is not greater than the threshold is assigned. The data expansion device according to claim 1.

15. The reference circuit performs in parallel the following: reading the first uncompressed data using the first offset from the dictionary to which the first compressed data is assigned and the address calculated from the current write address; and reading the second uncompressed data using the second offset from the dictionary to which the second compressed data is assigned and the address calculated from the current write address. A data decompression device according to any one of claims 1 to 14.

16. Non-volatile memory and A memory system comprising a controller for writing data to the non-volatile memory and reading data from the non-volatile memory, The controller comprises the data expansion device described in claim 1, The controller is a memory system that writes the compressed data sequence obtained by the dictionary-style compression to the non-volatile memory.

17. The controller further comprises a data compression device that compresses an uncompressed data sequence into a compressed data sequence by the dictionary-based compression method. The memory system according to claim 16.

18. A method for controlling a non-volatile memory configured to store a compressed data sequence including first compressed data having a first offset obtained by dictionary compression, wherein the first offset indicates a storage location in at least one dictionary of at least one first dictionary or at least one second dictionary, and the storage size of each of the at least one first dictionary is greater than the storage size of each of the at least one second dictionary. The aforementioned method, Read the compressed data sequence from the non-volatile memory, The first compressed data included in the read compressed data sequence is assigned to at least one dictionary of the at least one first dictionary or the at least one second dictionary. If the compressed data sequence includes second compressed data having a second offset indicating the storage location of at least one of the at least one first dictionary or the at least one second dictionary, then the second compressed data is further assigned, based on the second offset, to at least one of the at least one first dictionary or the at least one second dictionary, which is different from the dictionary to which the first compressed data is assigned. The following are performed in parallel: reading the first uncompressed data corresponding to the first compressed data using the first offset from the dictionary to which the first compressed data is assigned, and reading the second uncompressed data corresponding to the second compressed data using the second offset from the dictionary to which the second compressed data is assigned. Generate an uncompressed data sequence including the first uncompressed data and the second uncompressed data. method.

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