Apparatus for manufacturing a display device and method for manufacturing a display device

Abstract

The thickness of each layer that is formed in a continuous sequence is measured. [Solution] According to one embodiment, the manufacturing apparatus comprises a deposition chamber equipped with a deposition source configured to radiate material toward a transport path for transporting a processing substrate for a display device, and a measuring unit positioned downstream of the deposition chamber in the transport direction of the processing substrate, wherein the measuring unit comprises a chamber having a transmissive window and connected to the deposition chamber, and a film thickness measuring instrument provided outside the chamber, facing the transmissive window, and configured to optically measure the thickness of the deposition layer of the material deposited on the processing substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a manufacturing apparatus for a display device and a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to the light-emitting layer. In the process of manufacturing the display element, it is required to manage the thickness of each layer of the organic layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Summary of the Invention

Problems to be Solved by the Invention

[0004] The object of the present invention is to provide a manufacturing apparatus for a display device and a method for manufacturing a display device that can measure the thickness of each layer that is formed in a continuous manner. [Means for solving the problem]

[0005] According to one embodiment, the manufacturing apparatus for a display device is The device comprises a deposition chamber equipped with a deposition source configured to radiate material toward a transport path for transporting a processing substrate for a display device, and a measuring unit positioned downstream of the deposition chamber in the transport direction of the processing substrate, wherein the measuring unit comprises a chamber connected to the deposition chamber and having a transmissive window, and a film thickness measuring instrument provided outside the chamber, facing the transmissive window, and configured to optically measure the thickness of the deposition layer of the material deposited on the processing substrate.

[0006] According to one embodiment, the method for manufacturing a display device is: A processing substrate is prepared by forming a lower electrode on the upper part of the substrate, forming an inorganic insulating layer having an opening that overlaps with the lower electrode, and forming a partition wall including a lower part located above the inorganic insulating layer and an upper part located above the lower part and protruding from the side of the lower part, forming an organic layer on the lower electrode in the opening, and the step of forming the organic layer includes transporting the processing substrate into a deposition chamber, depositing a material emitted from a deposition source onto the processing substrate in the deposition chamber while transporting the processing substrate, transporting the processing substrate that has been discharged from the deposition chamber into a chamber of a measurement unit, stopping the processing substrate in the measurement unit, and optically measuring the thickness of the deposited layer of the material deposited on the processing substrate. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP along the line A-B in FIG. 2. [Figure 4] FIG. 4 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 5] FIG. 5 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6] FIG. 6 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 7] FIG. 7 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a diagram showing a configuration example of the display element 20. [Figure 11] FIG. 11 is a diagram showing a configuration example of the manufacturing apparatus 100. [Figure 12] FIG. 12 is a diagram showing a configuration example of the measurement unit 110-1. [Figure 13A] FIG. 13A is a diagram for explaining a method of measuring the thickness of the vapor deposition layer at a plurality of positions. [Figure 13B] FIG. 13B is a diagram for explaining another method of measuring the thickness of the vapor deposition layer at a plurality of positions. [Figure 14A] FIG. 14A is a diagram showing the processing substrate SUB carried into the vapor deposition chamber EV1. [Figure 14B] FIG. 14B is a diagram showing the processing substrate SUB carried into the measurement unit 110-1. [Figure 14C] FIG. 14C is a diagram showing the step of measuring the thickness of the vapor deposition layer. [Figure 15] FIG. 15 is a diagram showing another configuration example of the measurement unit 110-1. [Figure 16] FIG. 16 is a diagram for explaining a method of calculating the thickness of each layer of the vapor deposition layer by the film thickness measuring instrument 120 shown in FIG. 15. [Figure 17]FIG. 17 is a diagram showing another configuration example of the measurement unit 110-1.

Mode for Carrying Out the Invention

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those skilled in the art, obvious appropriate modifications that maintain the gist of the invention are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each figure, components that exhibit the same or similar functions as those previously described with respect to the already shown figures may be assigned the same reference numerals, and detailed descriptions that overlap may be appropriately omitted.

[0009] Note that in the drawings, for ease of understanding as needed, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is called a plan view.

[0010] The display device according to this embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, etc.

[0011] FIG. 1 is a diagram showing a configuration example of the display device DSP. The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0013] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0014] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and drain electrodes is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0017] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0018] The peripheral area SA, although not described in detail here, is provided with terminals for connecting IC chips and flexible printed circuit boards.

[0019] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned in the second direction Y. Sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0022] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs. The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6, like the inorganic insulating layer 5, has openings in the sub-pixels SP1, SP2, and SP3.

[0023] The sub-pixels SP1, SP2, and SP3 each comprise display elements 201, 202, and 203, respectively, as display elements 20.

[0024] The sub-pixel SP1 display element 201 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The display element 201, comprising the lower electrode LE1, the organic layer OR1, and the upper electrode UE1, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0025] The display element 202 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The display element 202, comprising the lower electrode LE2, the organic layer OR2, and the upper electrode UE2, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength range.

[0026] The sub-pixel SP3 display element 203 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The display element 203, comprising the lower electrode LE3, the organic layer OR3, and the upper electrode UE3, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0027] In the example in Figure 2, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect their exact shapes.

[0028] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of a display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of a display element, or to a common electrode.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 (see FIG. 1) of the sub-pixel SP1 through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0030] In the example of FIG. 2, the areas of the openings AP1, AP2, and AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3. In other words, the area of the lower electrode LE1 exposed from the opening AP1 is larger than the area of the lower electrode LE2 exposed from the opening AP2, and the area of the lower electrode LE2 exposed from the opening AP2 is larger than the area of the lower electrode LE3 exposed from the opening AP3.

[0031] FIG. 3 is a schematic cross-sectional view of the display device DSP along the line A-B in FIG. 2.

[0032] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that planarizes the irregularities generated by the circuit layer 11.

[0033] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12 and spaced apart from each other. The inorganic insulating layer 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the aperture AP2 overlaps with the lower electrode LE2, and the aperture AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the inorganic insulating layer 5. Between the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the insulating layer 12 is covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes of the insulating layer 12 are omitted in Figure 3, but correspond to CH1, CH2, and CH3 in Figure 2.

[0034] The partition wall 6 includes a conductive lower part (stem) 61 positioned on the inorganic insulating layer 5, and an upper part (cap) 62 positioned on the lower part 61. The lower part 61 of the partition wall 6 shown on the right side of the figure is located between opening AP1 and opening AP2. The lower part 61 of the partition wall 6 shown on the left side of the figure is located between opening AP2 and opening AP3. The upper part 62 has a greater width than the lower part 61. Both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of partition wall 6 is called an overhang.

[0035] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0036] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0037] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0038] In the example shown in Figure 3, sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0039] The cap layer CP1 is placed on top of the upper electrode UE1. The cap layer CP2 is positioned on top of the upper electrode UE2. The cap layer CP3 is placed on top of the upper electrode UE3.

[0040] The sealing layer SE1 is positioned on top of the cap layer CP1, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE2 is positioned on top of the cap layer CP2, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE3 is positioned on top of the cap layer CP3, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP3.

[0041] In the example shown in Figure 3, portions of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located above the partition wall 6 surrounding the sub-pixel SP1. These portions are separated from the organic layer OR1, the upper electrode UE1, and the portion of the cap layer CP1 located at the aperture AP1 (the portion that constitutes the display element 201). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located above the partition wall 6 surrounding the sub-pixel SP2, and these portions are spaced apart from the portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 located at the aperture AP2 (the portions that constitute the display element 202). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located above the partition wall 6 surrounding the sub-pixel SP3, and these portions are separated from the portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 located at the aperture AP3 (the portions that constitute the display element 203).

[0042] The ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example in Figure 3, the ends of sealing layers SE1 and SE2 located on the partition wall 6 between sub-pixels SP1 and SP2 are spaced apart, and the ends of sealing layers SE2 and SE3 located on the partition wall 6 between sub-pixels SP2 and SP3 are spaced apart.

[0043] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. The sealing layer 14 is covered by a resin layer 15.

[0044] The inorganic insulating layer 5, sealing layers SE1, SE2, SE3, and sealing layer 14 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0045] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper part 62 of the partition wall 6 is made of a conductive material, for example, but may also be made of an insulating material. The lower part 61 is made of a different material from the upper part 62.

[0046] The lower electrodes LE1, LE2, and LE3 are multilayer structures that include, for example, transparent electrodes made of an oxide conductive material such as indium tin oxide (ITO) and metallic electrodes made of a metallic material such as silver.

[0047] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials. In one example, light-emitting layer EM1 is formed from a material that emits light in the blue wavelength range, light-emitting layer EM2 is formed from a material that emits light in the green wavelength range, and light-emitting layer EM3 is formed from a material that emits light in the red wavelength range. Furthermore, each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, another hole blocking layer, an electron transport layer, and an electron injection layer.

[0048] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0049] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0050] Next, the manufacturing method of the display device DSP will be described with reference to Figures 4 to 9. Note that in Figures 4 to 9, the parts below the insulating layer 12 are omitted from the illustration.

[0051] First, a processing substrate SUB is prepared as shown in Figure 4. The process of preparing the processing substrate SUB includes the steps of forming the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 on the insulating layer 12, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively, and forming a partition wall 6 including a lower part 61 located on the inorganic insulating layer 5 and an upper part 62 located on the lower part 61 and protruding from the side surface of the lower part 61. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 having openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed after the partition wall 6 is formed.

[0052] Next, the display element 201 is formed. First, the processing substrate SUB is brought into the manufacturing apparatus (in-line type deposition apparatus) 100, which will be described later. Then, as shown in Figure 5, using the partition wall 6 as a mask, materials for forming each layer, such as the hole injection layer, hole transport layer, electron blocking layer, light-emitting layer (EM1), hole blocking layer, electron transport layer, and electron injection layer, are sequentially deposited on the lower electrode LE1 to form the organic layer OR1. Subsequently, using the partition wall 6 as a mask, a mixture of magnesium and silver is deposited onto the organic layer OR1 to form the upper electrode UE1. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61. Subsequently, using the partition wall 6 as a mask, a high refractive index material for forming the first transparent layer TL1 and a low refractive index material for forming the second transparent layer TL2 are sequentially deposited on the upper electrode UE1 to form the cap layer CP1. These organic layers OR1, upper electrode UE1, and cap layer CP1 are formed continuously while maintaining a vacuum environment.

[0053] Subsequently, the processed substrate SUB is loaded into a CVD (Chemical-Vapor Deposition) apparatus. Then, a sealing layer SE1 is formed so as to continuously cover the cap layer CP1 and the partition wall 6.

[0054] The organic layer OR1, upper electrode UE1, cap layer CP1, and sealing layer SE1 are formed over at least the entire display area DA and are also located on sub-pixels SP2 and SP3 as well as sub-pixels SP1. The organic layer OR1, upper electrode UE1, and cap layer CP1 are separated by an overhanging partition wall 6.

[0055] When the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition, the material released from the deposition source is blocked by the upper part 62. Therefore, a portion of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is laminated on top of the upper part 62. Each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on top of the upper part 62 is spaced apart from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located directly above the lower electrode LE1. The sealing layer SE1 covers the cap layer CP1 directly above the partition wall 6, covers the cap layer CP1 directly above the lower electrode LE1, and is in contact with the partition wall 6.

[0056] Next, as shown in Figure 6, a resist RS patterned to a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the sub-pixel SP1 and a portion of the surrounding partition wall 6.

[0057] Next, as shown in Figure 7, etching is performed using the resist RS as a mask to sequentially remove the encapsulation layer SE1, cap layer CP1, upper electrode UE1, and organic layer OR1 that are exposed from the resist RS. This exposes the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3. Next, the resist RS is removed. This forms the display element 201 on the sub-pixel SP1.

[0058] Next, as shown in Figure 8, the display element 202 is formed. The procedure for forming the display element 202 is the same as the procedure for forming the display element 201. That is, an organic layer OR2 including the light-emitting layer EM2, an upper electrode UE2, a cap layer CP2, and a sealing layer SE2 are formed in order on the lower electrode LE2. After that, a resist is formed on the sealing layer SE2, and the sealing layer SE2, cap layer CP2, upper electrode UE2, and organic layer OR2 are sequentially patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, the display element 202 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0059] Next, as shown in Figure 9, the display element 203 is formed. The procedure for forming the display element 203 is the same as the procedure for forming the display element 201. That is, an organic layer OR3 including the light-emitting layer EM3, an upper electrode UE3, a cap layer CP3, and a sealing layer SE3 are formed in order on the lower electrode LE3. After that, a resist is formed on the sealing layer SE3, and the sealing layer SE3, cap layer CP3, upper electrode UE3, and organic layer OR3 are sequentially patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, the display element 203 is formed on the sub-pixel SP3.

[0060] Subsequently, the resin layer 13, sealing layer 14, and resin layer 15 shown in Figure 3 are formed in order. This completes the DSP display device.

[0061] In the above manufacturing process, we assumed that the display element 201 is formed first, then the display element 202, and finally the display element 203. However, the formation order of the display elements 201, 202, and 203 is not limited to this example.

[0062] Next, we will describe an example configuration of the display element 20.

[0063] Figure 10 shows an example configuration of the display element 20. The display element 20 shown in Figure 10 can correspond to any of the display elements 201, 202, and 203 described above. Here, we will explain using the example where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode.

[0064] The display element 20 includes an organic layer OR (OR1, OR2, OR3) between the lower electrode LE (LE1, LE2, LE3) and the upper electrode UE (UE1, UE2, UE3).

[0065] In the organic layer OR, the hole injection layer HIL, hole transport layer HTL, electron blocking layer EBL, light emission layer EML, hole blocking layer HBL, electron transport layer ETL, and electron injection layer EIL are stacked in this order. Furthermore, the organic layer OR may include other functional layers, such as a carrier generation layer, as needed, in addition to the functional layers described above, or at least one of the functional layers described above may be omitted.

[0066] The light-emitting layer EML corresponds to one of the light-emitting layers EM1, EM2, or EM3 shown in Figure 3.

[0067] The cap layer CP (CP1, CP2, CP3) includes a first transparent layer TL1 and a second transparent layer TL2. The first transparent layer TL1 is located on top of the upper electrode UE. The first transparent layer TL1 is a high refractive index layer having a higher refractive index than the upper electrode UE. The second transparent layer TL2 is located on top of the first transparent layer TL1. The second transparent layer TL2 is a low refractive index layer having a lower refractive index than the first transparent layer TL1. The sealing layer SE (SE1, SE2, SE3) is located on top of the second transparent layer TL2.

[0068] Furthermore, the configuration of the organic layer OR is not limited to a configuration in which the organic layer OR comprises one light-emitting layer EML as shown in the figure, but may also be a configuration in which the organic layer OR comprises multiple light-emitting layers.

[0069] Figure 11 shows an example configuration of the manufacturing apparatus 100.

[0070] The manufacturing apparatus 100 is used, for example, in a process of continuously forming an organic layer OR, an upper electrode UE, and a cap layer CP. The processing substrate SUB that is brought into the manufacturing apparatus 100 has a circuit layer 11, an insulating layer 12, lower electrodes LE1, LE2, LE3, an inorganic insulating layer 5, and a partition wall 6 on a substrate 10.

[0071] The manufacturing apparatus 100 includes a pre-processing section 101, a vapor deposition section 102, and a post-processing section 103.

[0072] The pre-processing unit 101 is equipped with a mechanism for performing various pre-processing treatments on the incoming processing substrate SUB, such as cleaning, drying, and plasma treatment. The pre-processing unit 101 also includes a mechanism for setting the processing substrate SUB in a predetermined transport position and a mechanism for fixing the processing substrate SUB to a dedicated carrier using an electrostatic chuck. Each transport path in the deposition unit 102 is configured to transport the carrier.

[0073] The post-processing unit 103 includes a mechanism for releasing the fixation by the electrostatic chuck and removing the processing board SUB from the carrier, and a mechanism for setting the processing board SUB in a predetermined position.

[0074] In one example, the processing substrate SUB is fed into the pre-processing unit 101 in a horizontal position, and in the pre-processing unit 101, the position of the processing substrate SUB is changed from horizontal to vertical. The processing substrate SUB is then fed into the deposition unit 102 in a vertical position, and in the post-processing unit 103, the position of the processing substrate SUB is changed from vertical to horizontal.

[0075] The deposition unit 102 comprises a plurality of deposition chambers EV1 to EV10, a rotation chamber R11, and a plurality of measurement units 110-1 to 110-10. The pre-processing unit 101, the post-processing unit 103, the plurality of deposition chambers EV1 to EV10, the rotation chamber R11, and the plurality of measurement units 110-1 to 110-10 are connected to each other and maintained under high vacuum.

[0076] The deposition chambers EV1 to EV5 are arranged in a row. Deposition chamber EV1 is connected to the pre-processing unit 101. Measurement unit 110-1 is provided between deposition chamber EV1 and deposition chamber EV2 and is connected to each other. Measurement unit 110-2 is provided between deposition chamber EV2 and deposition chamber EV3 and is connected to each other. Measurement unit 110-3 is provided between deposition chamber EV3 and deposition chamber EV4 and is connected to each other. Measurement unit 110-4 is provided between deposition chamber EV4 and deposition chamber EV5 and is connected to each other. Measurement unit 110-5 is provided between deposition chamber EV5 and rotation chamber R11 and is connected to each other. The transport path T11 is provided across deposition chambers EV1 to EV5 and measurement units 110-1 to 110-5.

[0077] The deposition chambers EV6 to EV10 are arranged in a row. Deposition chamber EV6 is connected to rotation chamber R11. Measurement unit 110-6 is provided between deposition chamber EV6 and deposition chamber EV7 and is connected to each other. Measurement unit 110-7 is provided between deposition chamber EV7 and deposition chamber EV8 and is connected to each other. Measurement unit 110-8 is provided between deposition chamber EV8 and deposition chamber EV9 and is connected to each other. Measurement unit 110-9 is provided between deposition chamber EV9 and deposition chamber EV10 and is connected to each other. Measurement unit 110-10 is provided between deposition chamber EV10 and post-processing unit 103 and is connected to each other. The transport path T12 is provided across deposition chambers EV6 to EV10 and measurement units 110-6 to 110-10.

[0078] In other words, the deposition unit 102 comprises a set of one deposition chamber and one measurement unit positioned downstream of the deposition chamber in the transport direction of the processing substrate SUB. Furthermore, multiple sets are arranged in the deposition unit 102, and the deposition chambers and measurement units are arranged alternately. Note that at least one of the multiple measurement units 110-1 to 110-10 may be omitted.

[0079] The deposition chamber EV1 is equipped with a deposition source S1. The deposition source S1 is configured to emit material toward the transport path T11 for forming a hole injection layer HIL. The deposition chamber EV2 is equipped with a deposition source S2. The deposition source S2 is configured to emit material toward the transport path T11 to form a hole transport layer HTL. The deposition chamber EV3 is equipped with a deposition source S3. The deposition source S3 is configured to emit material toward the transport path T11 for forming the electron block layer EBL. The deposition chamber EV4 is equipped with a deposition source S4. The deposition source S4 is configured to emit material toward the transport path T11 for forming the light-emitting layer EML. The deposition chamber EV5 is equipped with a deposition source S5. The deposition source S5 is configured to emit material toward the transport path T11 for forming a hole block layer (HBL).

[0080] The deposition chamber EV6 is equipped with a deposition source S6. The deposition source S6 is configured to emit material toward the transport path T12 for forming the electron transport layer (ETL). The deposition chamber EV7 is equipped with a deposition source S7. The deposition source S7 is configured to emit material toward the transport path T12 for forming the electron injection layer EIL. The deposition chamber EV8 is equipped with a deposition source S8. The deposition source S8 is configured to radiate material toward the transport path T12 to form the upper electrode UE. The deposition chamber EV9 is equipped with a deposition source S9. The deposition source S9 is configured to emit material toward the transport path T12 for forming the first transparent layer TL1. The deposition chamber EV10 is equipped with a deposition source S10. The deposition source S10 is configured to emit material toward the transport path T12 for forming the second transparent layer TL2.

[0081] The transport paths T11 and T12 are located inside the deposition section 102. The deposition sources S1 to S10 are located outside the transport paths T11 and T12 in the deposition section 102.

[0082] The rotation chamber R11 is configured to transport the processed substrate SUB, which has been transported from the transport path T11, to the transport path T12. The rotation chamber R11 is equipped with a rotation mechanism RM11. The rotation mechanism RM11 holds the processed substrate SUB that has been transported in via the transport path T11 and is configured to be rotatable about a rotation axis A11.

[0083] The manufacturing process in the manufacturing apparatus 100 will be described below.

[0084] The processing substrate SUB, which has the lower electrode LE formed on it, is first brought into the pre-processing unit 101. In the pre-processing unit 101, predetermined pre-processing is performed on the processing substrate SUB.

[0085] Subsequently, the processing substrate SUB is transported to the deposition chamber EV1. In the deposition chamber EV1, material emitted from the deposition source S1 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms a hole injection layer HIL on the lower electrode LE. The processed substrate SUB, removed from the deposition chamber EV1, is fed into the measurement unit 110-1. In the measurement unit 110-1, the thickness of the hole injection layer HIL, which is a deposition layer formed in the deposition chamber EV1, is measured.

[0086] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-1, is transported to the deposition chamber EV2. In the deposition chamber EV2, material emitted from the deposition source S2 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms a hole transport layer HTL on top of the hole injection layer HIL. The processed substrate SUB, removed from the deposition chamber EV2, is fed into the measurement unit 110-2. In the measurement unit 110-2, the thickness of the hole transport layer HTL, which is a deposited layer formed in the deposition chamber EV2, is measured.

[0087] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-2, is transported to the deposition chamber EV3. In the deposition chamber EV3, material emitted from the deposition source S3 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms an electron blocking layer EBL on top of the hole transport layer HTL. The processed substrate SUB, removed from the deposition chamber EV3, is fed into the measurement unit 110-3. In the measurement unit 110-3, the thickness of the electron blocking layer EBL, which is the deposited layer formed in the deposition chamber EV3, is measured.

[0088] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-3, is transported to the deposition chamber EV4. In the deposition chamber EV4, material emitted from the deposition source S4 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms an emissive layer EML on top of the electron blocking layer EBL. The processed substrate SUB, removed from the deposition chamber EV4, is fed into the measurement unit 110-4. In the measurement unit 110-4, the thickness of the light-emitting layer EML, which is a deposited layer formed in the deposition chamber EV4, is measured.

[0089] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-4, is transported to the deposition chamber EV5. In the deposition chamber EV5, the material emitted from the deposition source S5 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms a hole block layer HBL on top of the light-emitting layer EML. The processed substrate SUB, removed from the deposition chamber EV5, is fed into the measurement unit 110-5. In the measurement unit 110-5, the thickness of the hole block layer HBL, which is a deposition layer formed in the deposition chamber EV5, is measured.

[0090] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-5, is placed into the rotation chamber R11. In the rotation chamber R11, the rotation mechanism RM11 holds the placed processing substrate SUB. Then, the rotation mechanism RM11 rotates 180° while holding the processing substrate SUB. Subsequently, the processing substrate SUB is transported to the deposition chamber EV6. In the deposition chamber EV6, material emitted from the deposition source S6 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms an electron transport layer ETL on top of the hole blocking layer HBL. The processed substrate SUB, removed from the deposition chamber EV6, is fed into the measurement unit 110-6. In the measurement unit 110-6, the thickness of the electron transport layer ETL, which is the deposited layer formed in the deposition chamber EV6, is measured.

[0091] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-6, is transported to the deposition chamber EV7. In the deposition chamber EV7, material emitted from the deposition source S7 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms an electron injection layer EIL on top of the electron transport layer ETL. The processed substrate SUB, removed from the deposition chamber EV7, is fed into the measurement unit 110-7. In the measurement unit 110-7, the thickness of the electron injection layer EIL, which is the deposited layer formed in the deposition chamber EV7, is measured.

[0092] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-7, is transported to the deposition chamber EV8. In the deposition chamber EV8, material emitted from the deposition source S8 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms the upper electrode UE on the electron injection layer EIL. The processed substrate SUB, removed from the deposition chamber EV8, is fed into the measurement unit 110-8. In the measurement unit 110-8, the thickness of the upper electrode UE, which is the deposited layer formed in the deposition chamber EV8, is measured.

[0093] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-8, is transported into the deposition chamber EV9. In the deposition chamber EV9, the material emitted from the deposition source S9 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms the first transparent layer TL1 on the upper electrode UE. The processed substrate SUB, removed from the deposition chamber EV9, is fed into the measurement unit 110-9. In the measurement unit 110-9, the thickness of the first transparent layer TL1, which is a deposition layer formed in the deposition chamber EV9, is measured.

[0094] Subsequently, the processing substrate SUB, which has been discharged from the measurement unit 110-9, is transported into the deposition chamber EV10. In the deposition chamber EV10, material emitted from the deposition source S10 is deposited onto the processing substrate SUB as it is transported along the transport path T12. As a result, a second transparent layer TL2 is formed on top of the first transparent layer TL1. The processed substrate SUB, removed from the deposition chamber EV10, is fed into the measurement unit 110-10. In the measurement unit 110-10, the thickness of the second transparent layer TL2, which is a deposition layer formed in the deposition chamber EV10, is measured.

[0095] Subsequently, the processing board SUB, which has been discharged from the measurement unit 110-10, is brought into the post-processing unit 103. In the post-processing unit 103, predetermined post-processing is performed on the processing board SUB. Subsequently, the processed substrate SUB is transported to the CVD apparatus. In the CVD apparatus, an inorganic insulating material is deposited onto the processed substrate SUB. This forms a sealing layer SE that continuously covers the cap layer CP and the partition wall 6.

[0096] With this type of in-line manufacturing apparatus 100, since the measurement unit is adjacent to the downstream side of each deposition chamber, the thickness of the deposition layer formed in each deposition chamber can be measured. Moreover, the thickness measurement can be performed while the processing substrate SUB is inside the deposition unit 102.

[0097] Next, we will describe the measurement unit. The measurement units 110-1 to 110-10 shown in Figure 11 are all configured similarly, and here we will describe the configuration of measurement unit 110-1 among the multiple measurement units.

[0098] Figure 12 shows an example configuration of the measurement unit 110-1.

[0099] The measurement unit 110-1 is located between the deposition chamber EV1 and the deposition chamber EV2. The arrow TA indicates the transport direction of the processing substrate SUB. The measurement unit 110-1 is located downstream of the deposition chamber EV1 along the transport direction TA. The deposition chamber EV2 is located downstream of the measurement unit 110-1 along the transport direction TA.

[0100] In the deposition chamber EV1, material M1 is emitted from the deposition source S1, and in the deposition chamber EV2, material M2 is emitted from the deposition source S2. The processing substrate SUB is transported in the order of deposition chamber EV1, measurement unit 110-1, and deposition chamber EV. In deposition chamber EV1, material M1 is deposited on the processing substrate SUB, forming a deposition layer of material M1. In measurement unit 110-1, the thickness of the deposition layer formed in deposition chamber EV1 is measured. In deposition chamber EV2, material M2 is deposited on the processing substrate SUB, forming a deposition layer of material M2. The deposition source S1 of deposition chamber EV1 and the deposition source S2 of deposition chamber EV2 are both equipped with multiple nozzles arranged in a direction intersecting the transport direction TA. In the illustrated example, the vapor-deposited layer formed in the vapor deposition chamber EV1 is a hole injection layer (HIL), and the thickness of the hole injection layer (HIL) is measured in the measurement unit 110-1.

[0101] The measurement unit 110-1 includes a chamber 110A and film thickness measuring instruments 120 and 130. In the measurement unit 110-1, the processing substrate SUB is temporarily paused, during which time the film thickness measuring instruments 120 and 130 measure the thickness of the deposited layer.

[0102] Chamber 110A is connected to the deposition chambers EV1 and EV2. The interior of chamber 110A is maintained under high vacuum, similar to deposition chambers EV1 and EV2. Chamber 110A has transmissive windows V120, V131, and V132. These transmissive windows V120, V131, and V132 are located on the side facing the deposition layer (hole injection layer HIL in the illustrated example) formed on the processing substrate SUB.

[0103] The film thickness measuring instrument 120 is a spectroscopic interferometer configured to optically measure the thickness of a deposited layer based on the principle of spectral interferometry. The film thickness measuring instrument 120 is located outside the chamber 110A, i.e., in an atmospheric pressure environment, and faces the transmission window V120. Although not described in detail, the film thickness measuring instrument 120 comprises an emission unit that emits light toward the deposited layer and a light receiving unit that receives interference light in the deposited layer. The film thickness measuring instrument 120 analyzes the spectrum of the received interference light and calculates the thickness of the deposited layer based on the wavelength of the light and the optical path length. Such a film thickness measuring instrument 120 is suitable for measuring the total thickness of a multilayer film.

[0104] The film thickness measuring instrument 130 is an ellipsometer configured to optically measure the thickness of a deposited layer using a phase modulation method or a rotational analyzer method. The film thickness measuring instrument 130 is located outside the chamber 110A, i.e., in an atmospheric pressure environment. The film thickness measuring instrument 130 comprises an emission unit 131 that emits light toward the deposited layer from an oblique direction inclined with respect to the normal to the processing substrate SUB, and a light receiving unit 132 that receives reflected light reflected by the deposited layer. The emission unit 131 faces a transmission window V131, and the light receiving unit 132 faces a transmission window V132. The film thickness measuring instrument 130 calculates the thickness of the deposited layer based on the polarization state of the reflected light received by the light receiving unit 132. Such a film thickness measuring instrument 130 is suitable for measuring the thickness of a single layer film.

[0105] According to this configuration example, since the measuring instruments include a film thickness measuring instrument 120 and a film thickness measuring instrument 130, the thickness of the deposited layer can be measured with high accuracy using at least one of the film thickness measuring instrument 120 and the film thickness measuring instrument 130.

[0106] In the example shown in Figure 12, both the film thickness gauge 120 and the film thickness gauge 130 are provided as measuring instruments, but it is sufficient if at least one of the film thickness gauge 120 and the film thickness gauge 130 is provided.

[0107] Figure 13A illustrates a method for measuring the thickness of a vapor-deposited layer at multiple locations. In this example, the vapor-deposited layer is a hole-injection layer (HIL). Here, the film thickness measuring instruments 120 and 130 are collectively referred to as measuring instrument MD. Measuring instrument MD is configured to move in a direction intersecting the transport direction TA of the processing substrate SUB, and measures the thickness of the deposited layer at multiple positions while moving. In the illustrated example, for the processing substrate SUB loaded into chamber 110A, measuring instrument MD measures the thickness of the deposited layer at multiple positions, for example, three or more positions. By measuring the thickness of the deposited layer at multiple positions, the variation in the thickness of the deposited layer within the plane of the processing substrate SUB can be calculated.

[0108] Figure 13B illustrates another method for measuring the thickness of a deposited layer at multiple locations. In this example, the deposited layer is a hole injection layer (HIL). The example shown in Figure 13B differs from the example shown in Figure 13A in that multiple measuring instruments MDa, MDb, MDc… are arranged at intervals in a direction intersecting the transport direction TA. According to this example, the thickness of the deposited layer can be measured at multiple locations in a short time without requiring a movement mechanism for the measuring instrument MD.

[0109] Next, we will explain the process of measuring the thickness of the vapor-deposited layer.

[0110] Figure 14A shows the processing substrate SUB being transported into the deposition chamber EV1. The processing substrate SUB is transported in the transport direction TA. The material emitted from the deposition source S1 is deposited onto the transported processing substrate SUB. Figure 14B shows the processing board SUB that has been brought into the measurement unit 110-1. Figure 14C shows the process of measuring the thickness of the vapor-deposited layer. The processing substrate SUB, having reached the measurement unit 110-1, is stopped. With the processing substrate SUB stopped, the film thickness measuring instruments 120 and 130 measure the thickness of the vapor-deposited layer. At this time, the thickness of the vapor-deposited layer is measured at multiple locations, as shown in Figure 13A or Figure 13B.

[0111] Figure 15 shows another example of the configuration of the measurement unit 110-1. The configuration example shown in Figure 15 differs from the configuration example shown in Figure 12 in that each measurement unit, including the measurement unit 110-1, is equipped with a film thickness measuring instrument 120, while the film thickness measuring instrument 130 is omitted. As described above, the film thickness measuring instrument 120 is suitable for measuring the total thickness of multilayer films. Therefore, the thickness of the deposited film formed in each deposition chamber can be obtained, for example, by the method described below.

[0112] Figure 16 is a diagram illustrating the method for calculating the thickness of each layer of the vapor-deposited layer using the film thickness measuring instrument 120 shown in Figure 15.

[0113] For example, the film thickness measuring instrument 120 of the measurement unit 110-1 has in advance stored the thickness T0 of the lower electrode LE for the processing substrate SUB that is loaded into the deposition chamber EV1 in its memory unit. As shown in the upper part of Figure 16, immediately after the hole injection layer HIL is formed as a vapor-deposited layer, the thickness T1 measured by the film thickness measuring instrument 120 of the measurement unit 110-1 is the total thickness of the lower electrode LE and the hole injection layer HIL. The film thickness measuring instrument 120 then calculates the thickness T_HIL of the hole injection layer HIL as the difference between thickness T1 and thickness T0.

[0114] The film thickness measuring instrument 120 of the measurement unit 110-2 stores in its memory the total thickness T1 of the lower electrode LE and hole injection layer HIL for the processing substrate SUB that is loaded into the deposition chamber EV2. As shown in the middle section of Figure 16, immediately after the hole transport layer HTL is formed as a vapor-deposited layer, the thickness T2 measured by the film thickness measuring instrument 120 of the measurement unit 110-2 is the total thickness of the lower electrode LE, the hole injection layer HIL, and the hole transport layer HTL. The film thickness measuring instrument 120 then calculates the thickness T_HTL of the hole transport layer HTL as the difference between thickness T2 and thickness T1.

[0115] The film thickness measuring instrument 120 of the measurement unit 110-3 stores in its memory the total thickness T2 of the lower electrode LE, hole injection layer HIL, and hole transport layer HTL for the processing substrate SUB that is loaded into the deposition chamber EV3. As shown in the lower part of Figure 16, immediately after the electron blocking layer EBL is formed as a vapor-deposited layer, the thickness T3 measured by the film thickness measuring instrument 120 of the measurement unit 110-3 is the total thickness of the lower electrode LE, hole injection layer HIL, hole transport layer HTL, and electron blocking layer EBL. The film thickness measuring instrument 120 then calculates the thickness T_EBL of the electron blocking layer EBL as the difference between thickness T3 and thickness T2.

[0116] Thus, even in a configuration example where each measurement unit is equipped with a film thickness measuring instrument 120 and the film thickness measuring instrument 130 is omitted, the thickness of the deposited layer formed in each deposition chamber can be measured in the same manner as in the above configuration example.

[0117] Figure 17 shows another example of the configuration of the measurement unit 110-1. The configuration example shown in Figure 17 differs from the configuration example shown in Figure 12 in that each measurement unit, including the measurement unit 110-1, is equipped with a film thickness measuring instrument 130, while the film thickness measuring instrument 120 is omitted. As described above, the film thickness measuring instrument 130 is suitable for measuring the total thickness of a single-layer film. Therefore, in addition to obtaining the same effects as in the above configuration example, the configuration of the measuring instrument can be simplified, and the cost of the manufacturing equipment can be reduced.

[0118] As described above, according to this embodiment, it is possible to provide a manufacturing apparatus for a display device and a method for manufacturing a display device that can measure the thickness of each layer that is formed continuously.

[0119] All manufacturing apparatuses and manufacturing methods that can be appropriately designed and implemented by those skilled in the art based on the manufacturing apparatuses and manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0120] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0121] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0122] DSP…display device 10…board 5…Inorganic insulating layer AP1, AP2, AP3…Openings 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3... subpixels 20, 201, 202, 203... Display elements (organic EL elements) LE, LE1, LE2, LE3...lower electrode UE, UE1, UE2, UE3...upper electrode OR, OR1, OR2, OR3…Organic layer 100...Manufacturing equipment T11, T12...Conveyor paths EV1~EV10... Evaporation chambers S1~S10... Evaporation sources 110-1~110-10…Measurement section 110A…Chamber 120, 130…Film thickness gauge

Claims

1. A deposition chamber comprising a deposition source configured to discharge material toward a transport path for transporting processing substrates for display devices, The deposition chamber comprises a measuring unit positioned downstream of the processing substrate in the transport direction, The aforementioned measuring unit is A chamber having a transparent window and connected to the deposition chamber, A manufacturing apparatus for a display device, comprising: a film thickness measuring instrument provided outside the chamber, facing the transparent window, and configured to optically measure the thickness of the deposited layer of the material deposited on the processing substrate.

2. The manufacturing apparatus for the display device according to claim 1, wherein the film thickness measuring instrument comprises at least one of a spectroscopic interferometer and an ellipsometer.

3. The manufacturing apparatus for a display device according to claim 1, wherein the film thickness measuring instrument is configured to measure the thickness of the deposited layer at a plurality of positions along a direction intersecting the transport direction of the processing substrate.

4. The set of the deposition chamber and the measurement unit is a plurality of units. The deposition chambers and the measurement unit are arranged alternately along the transport path. The apparatus for manufacturing a display device according to claim 1, wherein in each of the deposition chambers, the deposition source is configured to emit different materials from each other.

5. A processing substrate is prepared in which a lower electrode is formed on the upper part of the substrate, an inorganic insulating layer having an opening that overlaps with the lower electrode is formed, and a partition wall is formed including a lower part located above the inorganic insulating layer and an upper part located above the lower part and protruding from the side surface of the lower part. A layer is formed on the lower electrode in the aforementioned opening. The aforementioned step of forming the foundation is: The aforementioned processing substrate is brought into the deposition chamber, In the deposition chamber, while transporting the processing substrate, a material emitted from the deposition source is deposited onto the processing substrate. The processed substrate removed from the deposition chamber is brought into the chamber of the measurement unit. A method for manufacturing a display device, comprising the step of stopping the processing substrate in the measurement unit and optically measuring the thickness of the vapor-deposited layer of the material deposited on the processing substrate.

6. The method for manufacturing a display device according to claim 5, wherein the measurement is performed using at least one of a spectroscopic interferometer and an ellipsometer.

7. The method for manufacturing a display device according to claim 5, wherein, in the measurement, the thickness of the vapor-deposited layer is measured at a plurality of positions along a direction intersecting the transport direction of the processing substrate.

8. After the above-mentioned part is formed, An upper electrode is formed on the aforementioned organic layer, A cap layer is formed on the upper electrode, The steps for forming the organic layer, the upper electrode, and the cap layer are deposition steps using the partition wall as a mask. The method for manufacturing a display device according to claim 5, wherein the organic layer, the upper electrode, and the cap layer formed directly above the upper part of the partition wall are spaced apart from the organic layer, the upper electrode, and the cap layer formed directly above the lower electrode in the opening.

9. Furthermore, after forming the cap layer, a sealing layer is formed with an inorganic insulating material. The method for manufacturing a display device according to claim 8, wherein the sealing layer covers the cap layer above the partition wall and the cap layer directly above the lower electrode, and is in contact with the partition wall.

10. Furthermore, after forming the sealing layer, a patterned resist is formed on the sealing layer. A method for manufacturing a display device according to claim 9, wherein the sealing layer, the cap layer, the upper electrode, and the organic layer exposed from the resist are sequentially removed by etching.

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