Memory system and method for controlling the memory system

Abstract

This invention provides a memory system and its control method that implements PLP (Power Loss Protection) functionality within the device's warranty period and improves the reliability and performance of the device to the extent possible. [Solution] The memory system includes a memory device, a memory controller, a power supply circuit 30, and a power storage device 40. The memory controller controls the memory device. The power supply circuit supplies power to the memory device and the memory controller based on power supplied from an external power source. The power storage device is capable of storing electrical energy and supplies electrical energy to the memory device and the memory controller via the power supply circuit when the power supply from the external power source is interrupted. The memory controller further applies either a first write mode or a second write mode with different power consumption to the write operation on the memory device, depending on the power storage capacity of the power storage device.

Description

Technical Field

[0001] Embodiments relate to a memory system and a method of controlling the memory system.

Background Art

[0002] A NAND-type flash memory (also referred to as a flash memory) capable of storing data non-volatily is known. Also known is a memory system including a flash memory. The memory system stores data related to writing data to the flash memory in a volatile memory. When the power supplied to the memory system stops unexpectedly or its voltage value decreases, the data stored in the volatile memory is lost. To avoid this, there is a memory system having a PLP (Power Loss Protection) function.

[0003] A flash memory includes a plurality of memory cell transistors. It is possible to store multi-level data in one memory cell transistor. A plurality of write modes for writing multi-level data to the flash memory have been considered. Each of the plurality of write modes has a different amount of data related to writing data to the flash memory. Therefore, depending on the write mode, the amount of data stored in the volatile memory may also be different.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Providing a memory system and a method of controlling the memory system capable of improving reliability and performance.

Means for Solving the Problems

[0006] The memory system of the embodiment includes a memory device, a memory controller, a power supply circuit, and a power storage device. The memory device is configured to store data non-volatilely. The memory controller is configured to control the memory device. The power supply circuit is configured to generate power to drive the memory device and the memory controller based on power supplied from an external power source and to supply the generated power to the memory device and the memory controller. The power storage device is capable of storing electrical energy and is configured to supply electrical energy to the memory device and the memory controller via the power supply circuit when the power supply from the external power source is interrupted. The memory controller is further configured to apply either a first write mode or a second write mode with different power consumption to the write operation on the memory device, depending on the power storage capacity of the power storage device. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example of the configuration of the memory system according to the first embodiment. [Figure 2] A block diagram showing an example of the hardware configuration of a memory controller in a memory system according to the first embodiment. [Figure 3] A block diagram showing an example of the hardware configuration of a memory device in the memory system according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 5] A schematic diagram showing an example of the threshold voltage distribution of a memory cell transistor in a memory device according to the first embodiment. [Figure 6] A schematic diagram showing an example of the writing sequence of a two-stage program in the memory system according to the first embodiment. [Figure 7]A schematic diagram illustrating the outline of the writing operation using the Foggy-Fine method in the memory system according to the first embodiment. [Figure 8] A schematic diagram showing an overview of the writing operation using the MLC-Fine method in the memory system according to the first embodiment. [Figure 9] A block diagram showing an example of the functional configuration of the memory controller according to the first embodiment. [Figure 10] A graph showing an example of the relationship between the usage period of the energy storage device and the available energy supply in the memory system according to the first embodiment. [Figure 11] A flowchart showing an example of the patrol operation of the memory system according to the first embodiment. [Figure 12] A waveform diagram showing an example of a method for checking the energy storage capacity of an energy storage device in a memory system according to the first embodiment. [Figure 13] A flowchart illustrating a specific example of the patrol operation of the memory system according to the first embodiment. [Figure 14] A flowchart illustrating a specific example of the operation of the memory system according to the first embodiment when logical blocks are supplied. [Figure 15] A flowchart illustrating a specific example of the operation of the memory system during logical page writing according to the first embodiment. [Figure 16] A block diagram showing an example of the hardware configuration of a memory controller in a memory system according to the second embodiment. [Figure 17] A flowchart showing an example of the patrol operation of the memory system according to the second embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, each embodiment will be described with reference to the drawings. Each embodiment exemplifies an apparatus and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual. Illustrations of configurations are omitted as appropriate. Components having substantially the same functions and configurations are given the same reference numerals. Numbers etc. added to the reference signs are referred to by the same reference signs and are used to distinguish between similar elements.

[0009] <1>First Embodiment The first embodiment relates to a memory system 1 configured to select a more preferable data writing method according to the state of a power storage device necessary for realizing a PLP (Power Loss Protection) function. Hereinafter, details of the memory system 1 according to the first embodiment will be described.

[0010] <1-1>Configuration First, the configuration of the memory system 1 according to the first embodiment will be described.

[0011] <1-1-1>Configuration of Memory System 1 FIG. 1 is a block diagram showing an example of the configuration of the memory system 1 according to the first embodiment. As shown in FIG. 1, the memory system 1 can be connected to an external host device 2 and an external power supply 3. The memory system 1 is a storage device such as a memory card, a solid state drive (SSD), or a Universal Flash Storage (UFS) device. The host device 2 is an electronic device such as a personal computer, a portable information terminal, or a server. The host device 2 may simply be referred to as the "host". The external power supply 3 is a power supply source for the memory system 1.

[0012] The memory system 1 includes, for example, a memory controller 10, at least one memory device 20, a power supply integrated circuit (IC) 30, and a power storage device 40.

[0013] The memory controller 10 is a semiconductor integrated circuit configured as, for example, a System On a Chip (SoC), an Application Specific Integrated Circuit (ASIC), or a field-programmable gate array (FPGA). The memory controller 10 has the function of managing and controlling the memory device 20. The memory controller 10 is connected to the host device 2 via the host bus HB. The memory controller 10 is connected to the memory device 20 via the memory bus MB. The memory controller 10 can control the memory device 20 based on instructions received from the host device 2.

[0014] The memory device 20 is a semiconductor memory device configured to store data non-volatilely. The memory device 20 is, for example, a NAND flash memory. In NAND flash memory, the unit of data read and write operations is called a page. The memory device 20 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is associated with one bit line BL and one word line WL. Each bit line BL is assigned a column address. Each word line WL is assigned a page address.

[0015] The power supply IC 30 generates power to drive multiple electrical circuit components of the memory system 1 based on power supplied from an external power supply 3. These multiple electrical circuit components include a memory controller 10 and a memory device 20. The power supply IC 30 then supplies the generated power to each of these electrical circuit components. The power supply IC 30 may also be referred to as a power supply circuit. For example, the power supply IC 30 generates multiple different voltages as power, which become the power supply voltages for each of the multiple electrical circuit components. The power supply IC 30 may also generate power to drive other electrical circuit components (not shown).

[0016] The energy storage device 40 can store electrical energy. The energy storage device 40 is, for example, a rechargeable capacitor or battery. The energy storage device 40 is charged by the power supply IC 30 when power is supplied to the memory system 1 from an external power supply 3. If the energy storage device 40 is a capacitor, any capacitor can be used. For example, the energy storage device 40 may be an electrolytic capacitor, a tantalum capacitor, a multilayer ceramic capacitor, or an electric double-layer capacitor.

[0017] In this specification, data instructed to be written from host device 2 is referred to as "written data," and data read from memory device 20 is referred to as "read data."

[0018] In the memory system 1, the power supply IC 30 switches the power supply source to the multiple electrical circuit components of the memory system 1 from the external power supply 3 to the energy storage device 40 when the power supply from the external power supply 3 is interrupted. As a result, the electrical energy stored in the energy storage device 40 is supplied to at least the memory controller 10 and the memory device 20 via the power supply IC 30. Therefore, the memory controller 10 and the memory device 20 can operate for a while using the electrical energy stored in the energy storage device 40 even after the power supply from the external power supply 3 is interrupted. At this time, the memory controller 10 performs a PLP operation using the electrical energy stored in the energy storage device 40. In the PLP operation, the memory controller 10 saves the data stored in the volatile memory (described later) to the non-volatile memory (memory device 20).

[0019] The power supply IC 30 may also monitor the voltage supplied from the external power supply 3 to detect when the power supply from the external power supply 3 has stopped. For example, if the voltage supplied from the external power supply 3 falls below a predetermined level, the power supply IC 30 determines that a power outage has occurred and sends a power outage signal to the memory controller 10. The power supply IC 30 then switches the power supply source from the external power supply 3 to the energy storage device 40, and the memory controller 10 starts PLP operation.

[0020] Note that the power failure detection mechanism does not necessarily have to be the power supply IC 30. For example, the memory controller 10 may detect the power failure. The cessation of power supply from the external power supply 3 may be notified to the memory system 1 by the host device 2. When the memory controller 10 receives notification of the cessation of power supply from the external power supply 3, it may perform a shutdown operation of the memory system 1, including processing similar to that of the PLP operation, depending on the content of the notification.

[0021] <1-1-2> Hardware configuration of the memory controller 10 Figure 2 is a block diagram showing an example of the hardware configuration of a memory controller 10 included in a memory system 1 according to the first embodiment. As shown in Figure 2, the memory controller 10 includes, for example, a host interface (host I / F) 11, a memory interface (memory I / F) 12, a CPU (Central Processing Unit) 13, an ECC (Error Correction Code) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a buffer memory 17. The host interface 11, memory interface 12, CPU 13, ECC circuit 14, ROM 15, RAM 16, and buffer memory 17 may be connected to an internal bus.

[0022] The host interface 11 controls communication between the host device 2 and the memory controller 10 according to the interface standard. The host interface 11 is connected to the host device 2 via the host bus HB. The host interface 11 supports, for example, SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe. TM (PCI Express), NVMe TM (Non-Volatile Memory Express TM It supports interface standards such as ).

[0023] The memory interface 12 controls communication between the memory controller 10 and the memory device 20 according to the interface standard. The memory interface 12 is connected to the memory device 20 via the memory bus MB. The memory interface 12 supports interface standards such as Toggle DDR and ONFI (Open NAND Flash Interface).

[0024] The CPU 13 controls the overall operation of the memory controller 10. For example, the CPU 13 instructs the memory device 20 via the memory interface 12 to write data according to a write request received via the host interface 11. The CPU 13 also instructs the memory device 20 via the memory interface 12 to read data according to a read request received via the host interface 11. For example, the CPU 13 is a processor capable of executing a program that controls the memory controller 10.

[0025] The ECC circuit 14 is a circuit that performs error correction processing for data. During a write operation, the ECC circuit 14 generates parity for each page of the write data received from the host device 2. The generated parity is added to the write data and written to the memory device 20. During a read operation, the ECC circuit 14 generates a syndrome based on the read data (a pair of data and parity) received from the memory device 20. Then, the ECC circuit 14 detects errors in the read data based on the generated syndrome and corrects the detected errors.

[0026] ROM15 stores programs such as firmware. ROM15 could be, for example, an EEPROM. TM Non-volatile memory such as (Electrically Erasable Programmable Read-Only Memory) is used. The CPU 13 executes various processes by running firmware stored in ROM 15, etc.

[0027] RAM16 is a memory device used as a workspace for the CPU13. RAM16 stores, for example, a look-up table (LUT) for managing the memory area of ​​memory device 20. The LUT includes, for example, information that associates the logical address (logical page) of the data storage location with the physical address. The LUT is rewritten as appropriate according to the operation of memory system 1. The LUT is read from memory device 20 when memory system 1 is powered on. The LUT is stored in memory device 20 when memory system 1 is powered off. The CPU13 may generate a differential of the LUT and back it up to memory device 20 as appropriate. RAM16 is an example of volatile memory. For example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) can be used as RAM16. RAM16 may be implemented outside of the memory controller 10.

[0028] The buffer memory 17 is a storage device that is also used as a temporary storage area. The buffer memory 17 temporarily stores, for example, write data received from the host device 2 and read data received from the memory device 20. The buffer memory 17 is an example of volatile memory. For example, DRAM or SRAM can be used as the buffer memory 17. The buffer memory 17 may be implemented outside the memory controller 10.

[0029] <1-1-3> Hardware configuration of memory device 20 Figure 3 is a block diagram showing an example of the hardware configuration of a memory device 20 provided in a memory system 1 according to the first embodiment. As shown in Figure 3, the memory device 20 includes, for example, a memory cell array 21, an input / output circuit 22, a logic controller 23, a register circuit 24, a sequencer 25, a ready-busy controller 26, a driver circuit 27, a row decoder module 28, and a sense amplifier module 29. Signals transmitted and received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready-busy signal RBn.

[0030] The memory cell array 21 is a collection of multiple memory cell transistors MT (not shown). The memory cell array 21 includes multiple blocks BLK0 to BLKn (where n is an integer of 1 or more). A block BLK is used, for example, as a unit for data erasure operations. Each block BLK is assigned a block address. The memory cell array 21 is provided with multiple bit lines BL0 to BLm (where "m" is an integer of 1 or more) and multiple word lines WL (not shown). Note that a block BLK may be divided into subblocks for management.

[0031] The input / output circuit 22 controls the transmission and reception (input / output) of input / output signals I / O0 to I / O7. The input / output signals I / O may include data DAT, status information, addresses, and commands. The input / output circuit 22 can input and output data DAT between the sense amplifier module 29 and the memory controller 10. The input / output circuit 22 can output status information transferred from the register circuit 24 to the memory controller 10. The input / output circuit 22 can output addresses and commands transferred from the memory controller 10 to the register circuit 24.

[0032] The logic controller 23 controls the input / output circuit 22 and the sequencer 25 based on various control signals input from the memory controller 10. For example, the logic controller 23 enables the memory device 20 based on the control signal CEn. Based on the control signals CLE and ALE, the logic controller 23 notifies the input / output circuit 22 that the input / output signals I / O received by the memory device 20 are a command and an address, respectively. Based on the control signal WEn, the logic controller 23 commands the input / output circuit 22 to receive the input / output signals I / O, and based on the control signal REn, commands the input / output circuit 22 to transmit the input / output signals I / O. Based on the control signal WPn, the logic controller 23 puts the memory device 20 into a protected state.

[0033] The register circuit 24 temporarily stores status, address, and command information. Status is information indicating the operating state of the memory device 20. The status is updated based on the control of the sequencer 25 and transferred to the memory controller 10 via the input / output circuit 22. Address may include block address, page address, column address, etc. Commands include instructions related to various operations of the memory device 20.

[0034] The sequencer 25 controls the overall operation of the memory device 20. Based on the commands and addresses stored in the register circuit 24, the sequencer 25 performs read operations, write operations, erase operations, etc.

[0035] The ready-busy controller 26 generates a ready-busy signal RBn based on the control of the sequencer 25. The ready-busy signal RBn notifies the memory controller 10 whether the memory device 20 is in a ready state or a busy state. The ready state is when the memory device 20 is ready to accept instructions from the memory controller 10. The busy state is when the memory device 20 is unable to accept instructions from the memory controller 10 (or does not process them even if they are received).

[0036] The driver circuit 27 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 27 supplies the generated voltages to the raw decoder module 28, sense amplifier module 29, etc.

[0037] The row decoder module 28 is a circuit used for selecting blocks BLK and supplying voltage to wiring such as word lines WL. The row decoder module 28 includes multiple row decoders RD0 to RDn. Each row decoder RD0 to RDn is associated with a block BLK0 to BLKn. Each row decoder RD can be set to select or deselect its associated block BLK based on its block address.

[0038] The sense amplifier module 29 is a circuit used to supply voltage to each bit line BL and to read data. The sense amplifier module 29 includes multiple sense amplifier units SAU0 to SAUm. Each sense amplifier unit SAU0 to SAUm is associated with multiple bit lines BL0 to BLm. Each sense amplifier unit SAU can determine the data read from the selected memory cell transistor MT based on the voltage of the associated bit line BL.

[0039] In the memory device 20, the set of memory cell array 21, row decoder module 28, and sense amplifier module 29 may be called a plane. A plane includes at least the memory cell array 21. The memory device 20 may have multiple planes. The sequencer 25 may be configured to control each of the multiple planes.

[0040] <1-1-4> Circuit configuration of the memory cell array 21 Figure 4 is a circuit diagram showing an example of the circuit configuration of a memory cell array 21 provided in a memory device 20 according to the first embodiment. Figure 4 shows one of several block BLKs included in the memory cell array 21. As shown in Figure 4, a block BLK is provided with multiple bit lines BL0 to BLm, multiple word lines WL0 to WL(N-1) (where N is an integer of 2 or more), selection gate lines SGD0 to SGD4, selection gate line SGS, and source line SL. The selection gate lines SGD0 to SGD4 and SGS and the word lines WL0 to WL(N-1) are provided for each block BLK. The bit lines BL0 to BLm are shared by multiple block BLKs. The source line SL may be shared by multiple block BLKs or may be provided for each block BLK.

[0041] A block BLK includes, for example, five string units SU0 to SU4. Each string unit SU contains multiple NAND strings NS. Each of the multiple NAND strings NS is associated with a bit line BL0 to BLm. That is, each bit line BL is shared by multiple NAND strings NS that are assigned the same column address across multiple blocks BLK. Each NAND string NS is connected between its associated bit line BL and source line SL.

[0042] Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and selection transistors STD and STS. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and stores data nonvolatilously. The threshold voltage of the memory cell transistor MT can be changed based on the amount of charge injected into the charge storage layer, etc. The selection transistors STD and STS are used to select the block BLK and the string unit SU, respectively.

[0043] In each NAND string NS, the selection transistor STD, memory cell transistors MT(N-1) to MT0, and selection transistor STS are connected in series in this order. Specifically, the drain of selection transistor STD is connected to the associated bit line BL. The source of selection transistor STD is connected to the drain of memory cell transistor MT(N-1). Memory cell transistors MT0 to MT(N-1) are connected in series between selection transistor STD and STS. The drain of selection transistor STS is connected to the source of memory cell transistor MT0. The source of selection transistor STS is connected to the source line SL.

[0044] The selection gate lines SGD0 to SGD4 are associated with string units SU0 to SU4, respectively. Each selection gate line SGD is connected to the gate of each of the multiple selection transistors STD contained in the associated string unit SU. The selection gate line SGS is connected to the gate of each of the multiple selection transistors STS contained in the associated block BLK. The word lines WL0 to WL(N-1) are connected to the control gates of each of the multiple memory cell transistors MT0 to MT(N-1) contained in the associated block BLK, respectively.

[0045] In this specification, a set of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is referred to as a cell unit CU. Furthermore, a set of 1-bit data stored in each of the multiple memory cell transistors MT contained within a cell unit CU is referred to as page data. That is, a "page" corresponds to a set of multiple memory cell transistors MT connected to a common word line WL within the same block BLK. A cell unit CU can store two or more pages of data, depending on the number of bits of data stored in each memory cell transistor MT. In other words, the memory controller 10 can manage the storage area of ​​the memory device 20 in units of cell unit CUs, each composed of multiple memory cell transistors MT capable of storing multiple-bit data (or multi-level data).

[0046] The memory cell array 21 may have a circuit configuration other than that described above. For example, the number of string units SU included in each block BLK, and the number of selection transistors STD and STS included in each NAND string NS, can be designed to any number. A selection gate line SGS may be provided for each string unit SU.

[0047] <1-1-5> Threshold voltage distribution of memory cell transistor MT Figure 5 is a schematic diagram showing an example of the threshold voltage distribution of memory cell transistors MT in a memory device 20 according to the first embodiment. Figures 5(1) to (5) illustrate the threshold voltage distribution of memory cell transistors MT when 1-bit data to 5-bit data are stored in the memory cell transistors MT, respectively. In each figure shown in Figure 5, the horizontal axis corresponds to the threshold voltage (Vth) of the memory cell transistor MT, and the vertical axis corresponds to the number of memory cell transistors MT (NMTs).

[0048] As shown in Figure 5, the threshold voltage distribution of the memory cell transistor MT includes multiple states S. The number of states S varies depending on the number of bits of data stored in each of the multiple memory cell transistors MT contained in the cell unit CU. Since randomization is performed on the data written to each cell unit CU, the memory cell transistors MT are distributed approximately evenly across the multiple states S that are formed.

[0049] When one bit of data is stored in each memory cell transistor MT (1 bit / cell), the threshold voltage distribution of the memory cell transistor MT has two states, S0 and S1, as shown in Figure 5 (1). In 1 bit / cell, two different 1-bit data are assigned to each of the two states, S0 and S1. This type of writing method is also called the SLC (Single-Level Cell) method.

[0050] When 2 bits of data are stored in each memory cell transistor MT (2 bits / cell), the threshold voltage distribution of the memory cell transistor MT has four states S0 to S3, as shown in Figure 5 (2). In 2 bits / cell, two different 2 bits of data are assigned to each of the four states S0 to S3. This type of writing method is also called the MLC (Multi-Level Cell) method.

[0051] When 3 bits of data are stored in each memory cell transistor MT (3 bits / cell), the threshold voltage distribution of the memory cell transistor MT has eight states S0 to S7, as shown in Figure 5 (3). In 3 bits / cell, three different 3 bits of data are assigned to each of the eight states S0 to S7. This type of writing method is also called the TLC (Triple-Level Cell) method.

[0052] When 4 bits of data are stored in each memory cell transistor MT (4 bits / cell), the threshold voltage distribution of the memory cell transistor MT has 16 states S0 to S15, as shown in (4) of Figure 5. In 4 bits / cell, each of the 16 states S0 to S15 is assigned a distinct set of 4 bits of data. This type of writing method is also called the QLC (Quad-Level Cell) method.

[0053] When 5 bits of data are stored in each memory cell transistor MT (5 bits / cell), the threshold voltage distribution of the memory cell transistor MT has 32 states S0 to S31, as shown in (5) of Figure 5. In 5 bits / cell, each of the 32 states S0 to S31 is assigned a distinct set of 5 bits of data. This type of writing method is also called the PLC (Penta-Level Cell) method.

[0054] In each threshold voltage distribution described above, a verify voltage and a read voltage are set between adjacent states S. In a write operation, the memory device 20 repeatedly executes a program operation that increases the threshold voltage of the memory cell transistor MT and a read operation using the verify voltage. Based on the verify voltage, the memory device 20 can determine whether the threshold voltage of the memory cell transistor MT to be programmed has reached the target state S. In addition, in a read operation, the memory device 20 executes the read operation using at least one read voltage. Based on whether the memory cell transistor MT to which the read voltage has been applied has turned on, the memory device 20 can identify the state S corresponding to the threshold voltage of the memory cell transistor MT.

[0055] Note that memory cell transistors MT may store more than 6 bits of data. When memory cell transistors MT store k bits of data (where k is an integer greater than or equal to 1), the threshold voltage distribution of memory cell transistors MT is at least 2 kSeveral states S are provided. In this specification, the case in which the cell unit CU stores 4 pages of data, that is, the case in which the memory cell array 21 stores data using the QLC method, is described as an example. 4 pages of data corresponds to 4 bits of data.

[0056] <1-2> Operation Next, the operation of the memory system 1 according to the first embodiment will be described.

[0057] <1-2-1> Overview of the 2-Stage Program The memory system 1 according to the first embodiment is configured to execute a two-stage program. A two-stage program is a writing operation in which the writing operation of multiple pages of data is performed in two stages when writing multiple pages of data to a single cell unit CU. Hereinafter, the first writing operation in a two-stage program will be referred to as the first-stage program, and the second writing operation will be referred to as the second-stage program. In the first-stage program, the threshold voltage of the memory cell transistor MT is roughly increased according to the data to be written. In the second-stage program, the threshold voltage of the memory cell transistor MT is finely increased according to the data to be written. The second-stage program is executed after the first-stage program is completed and after the first-stage program of the adjacent cell unit CU is completed.

[0058] Specifically, when the first-stage program, which selects word line WLi (where i is a non-negative integer), is executed, the threshold voltage of each memory cell transistor MT connected to word line WLi rises roughly. Then, when the first-stage program, which selects word line WL(i+1), is executed, the threshold voltage distribution of the memory cell transistors MT connected to word line WLi shifts slightly towards the positive voltage side due to inter-cell interference effects. Next, when the second-stage program, which selects word line WLi, is executed, the threshold voltage of each memory cell transistor MT connected to word line WLi rises from the roughly written state by the first-stage program to the desired threshold voltage. The amount of threshold voltage shift in the second-stage program is smaller than in the first-stage program. Therefore, the inter-cell interference effect on word line WLi by the second-stage program, which selects word line WL(i+1), is suppressed.

[0059] The first-stage program may also be called a rough write operation. The second-stage program may also be called a fine write operation. Both the first-stage and second-stage programs involve applying a program voltage multiple times to multiple memory cell transistors MT contained in a selected cell unit CU, stepping up the voltage each time. The step-up size of the program voltage in the rough write operation is larger than the step-up size of the program voltage in the fine write operation.

[0060] The number of bits in the data to be written using the first stage program may be the same as or less than the number of bits in the data to be written using the second stage program. In the following, a two-stage program in which the number of bits in the data to be written using the first and second stage programs are the same will be called the Foggy-Fine method. A two-stage program in which the MLC method is used in the first stage program and a storage method of 3 bits / cell or more is used in the second stage program will be called the MLC-Fine method.

[0061] (1:2 stage program writing order) Figure 6 is a schematic diagram showing an example of the writing sequence of a two-stage program in the memory system 1 according to the first embodiment. Figure 6 shows the combination of word lines WL and string units SU in a certain block BLK, and the order in which the first-stage program and the second-stage program are executed, respectively. In the following description, by selecting one word line WL and one string unit SU, a write operation in which a specific cell unit CU is selected can be performed.

[0062] As shown in Figure 6, first, the memory controller 10 causes the memory device 20 to execute a first-stage program that selects word line WL0 and string units SU0 to SU4 in sequence ("1" to "5" in Figure 6). Next, the memory controller 10 causes the memory device 20 to execute a first-stage program that selects word line WL1 and string units SU0 to SU4 in sequence ("6" to "10" in Figure 6). Next, the memory controller 10 causes the memory device 20 to execute a second-stage program that selects word line WL0 and string units SU0 to SU4 in sequence ("11" to "15" in Figure 6). Next, the memory controller 10 causes the memory device 20 to execute a first-stage program that selects word line WL2 and string units SU0 to SU4 in sequence ("16" to "20" in Figure 6). Next, the memory controller 10 causes the memory device 20 to sequentially execute the second-stage programs that select word line WL1 and string units SU0 to SU4, respectively ("21" to "25" in Figure 6). Similarly, the first-stage programs and second-stage programs are executed alternately thereafter.

[0063] Note that the writing order in a two-stage program may be any other order. In memory system 1, it is sufficient that the second-stage program of each cell unit CU is executed after the first-stage program of the adjacent cell unit CU has been executed. Furthermore, the above explanation illustrates the case where the memory controller 10 performs writing operations in order from the word line WL with the smallest number (from the source line SL side), but it is not limited to this. The memory controller 10 may also be configured to perform writing operations in order from the word line WL with the largest number (from the bit line BL side).

[0064] (2:Foggy-Fine method) Figure 7 is a schematic diagram showing an overview of the writing operation using the Foggy-Fine method in the memory system 1 according to the first embodiment. Figure 7(1) shows the threshold voltage distribution of the memory cell transistor MT in the erase state. Figure 7(2) shows the threshold voltage distribution of the memory cell transistor MT after the first stage program in the Foggy-Fine method has been executed. Figure 7(3) shows the threshold voltage distribution of the memory cell transistor MT after the second stage program in the Foggy-Fine method has been executed.

[0065] As shown in Figure 7(1), in the erase state, the threshold voltages of the multiple memory cell transistors MT within the cell unit CU are distributed in state ER.

[0066] As shown in Figure 7(2), in the first stage program of the Foggy-Fine method, the memory controller 10 uses the four pages of data to be written stored in the buffer memory 17 to cause the memory device 20 to perform a rough write operation. As a result, 16 states F0 to F15 are formed from state ER.

[0067] As shown in Figure 7(3), in the second stage program of the Foggy-Fine method, the memory controller 10 causes the memory device 20 to perform fine-grained write operations using the same 4-page data stored in the buffer memory 17 as in the first stage program. This creates states S0 to S15 from states F0 to F15. States F0 to F15 are distributed lower and more widely than any of the corresponding states S0 to S15. Once the second stage program of the Foggy-Fine method is completed, the 4-page data written to the memory device 20 can be discarded from the buffer memory 17.

[0068] Thus, in the Foggy-Fine method, the four pages of data to be written are stored in the buffer memory 17 until the second-stage program is executed, requiring a large amount of write cache capacity allocated to the buffer memory 17. On the other hand, the Foggy-Fine method can suppress inter-cell interference effects more effectively than other two-stage program methods.

[0069] (3:MLC-Fine method) Figure 8 is a schematic diagram showing an overview of the writing operation using the MLC-Fine method in the memory system according to the first embodiment. Figure 8(1) shows the threshold voltage distribution of the memory cell transistor MT in the erase state. Figure 8(2) shows the threshold voltage distribution of the memory cell transistor MT after the first stage program in the MLC-Fine method has been executed. Figure 8(3) shows the threshold voltage distribution of the memory cell transistor MT after the second stage program in the MLC-Fine method has been executed.

[0070] As shown in Figure 8(1), in the erase state, the threshold voltages of the multiple memory cell transistors MT within the cell unit CU are distributed in state ER. The state in Figure 8(1) is the same as the state in Figure 7(1).

[0071] As shown in Figure 8(2), in the first stage program of the MLC-Fine method, the memory controller 10 uses the two pages of data to be written, which are stored in the buffer memory 17, to perform a rough write operation on the memory device 20. As a result, four states M0 to M3 are formed from state ER. In this example, a read voltage RM1 is set between states M0 and M1. A read voltage RM2 is set between states M1 and M2. A read voltage RM3 is set between states M2 and M3. Once the first stage program of the MLC-Fine method is completed, the two pages of data written to the memory device 20 can be discarded from the buffer memory 17.

[0072] As shown in Figure 8(3), in the second stage program of the MLC-Fine method, the memory controller 10 first reads the data written by the first stage program from the memory device 20. At this time, the memory device 20 performs a read operation using read voltages RM1, RM2, and RM3. Such an operation is also called IDL (Internal Data Read). Then, the memory controller 10 causes the memory device 20 to perform a fine write operation using the two pages of data read by IDL and the two pages of data newly stored in the buffer memory 17. As a result, four states S0 to S3 are formed from state M0. Four states S4 to S7 are formed from state M1. Four states S8 to S11 are formed from state M2. Four states S12 to S15 are formed from state M3. State M0 is distributed similarly to state ER, for example. State M1 is distributed lower and more widely than state S4, for example. State M2 is distributed lower and more widely than state S8, for example. State M3 is, for example, lower and more widely distributed than state S12. When the second stage program in the MLC-Fine scheme is completed, it becomes possible to discard the two pages of data remaining in buffer memory 17 out of the four pages of data to be written.

[0073] Thus, in the MLC-Fine method, buffer memory 17 uses only two pages of data for both the execution of the first-stage program and the execution of the second-stage program. Therefore, the MLC-Fine method can reduce the amount of write cache required.

[0074] <1-2-2> Overview of the writing sequence Next, we will explain the overview of the data writing sequence in memory system 1 using the functional configuration of memory controller 10.

[0075] Figure 9 is a block diagram showing an example of the functional configuration of the memory controller 10 according to the first embodiment. As shown in Figure 9, the memory controller 10 includes a host interface (I / F) control unit 101, a command processing unit 102, a write management unit 103, a write buffer 104, and a NAND interface (I / F) control unit 105.

[0076] The host interface control unit 101 controls communication between the host device 2 and the memory controller 10 using the host interface 11. When the host interface control unit 101 receives a command from the host device 2, it forwards the received command to the command processing unit 102. Also, when the host interface control unit 101 receives write data from the host device 2, it forwards the received write data to the write management unit 103.

[0077] The command processing unit 102 processes commands received from the host device 2. When the command processing unit 102 receives a write command from the host device 2, it instructs the write management unit 103 to perform a write operation based on the write command.

[0078] The write management unit 103 assigns logical pages to the write data based on the received write command and write data. Then, the write management unit 103 sends the write command to the NAND interface control unit 105. The write management unit 103 stores the write data in the write buffer 104. For example, when the write management unit 103 stores the write data in the write buffer 104, it returns a write completion response to the host device 2 via the host interface control unit 101.

[0079] The NAND interface control unit 105 transmits a write command and the write data stored in the write buffer 104 to the memory device 20 during a write operation. If the NAND interface control unit 105 receives read data from the memory device 20 during IDL, it may transfer the read data to the write buffer 104. Also, if the NAND interface control unit 105 receives information from the memory device 20 indicating whether the write operation was completed successfully, it transfers this information to the write management unit 103. If the write operation was not completed successfully, the write management unit 103 assigns the write data to another logical page and executes the write operation again. After the write operation is completed to the memory device 20, the write management unit 103 updates the lookup table (LUT).

[0080] Furthermore, if an unintended power outage occurs in memory system 1, it is necessary to store (make non-volatile) the written data in write buffer 104, which is treated as completed because the host device 2 was notified of the completion of the write operation, in memory device 20. This PLP operation, including this operation, ensures the write data in write buffer 104 is guaranteed.

[0081] <1-2-3> Writing method setting operation The memory system 1 according to the first embodiment performs a patrol operation periodically. In conjunction with the patrol operation, the memory system 1 checks the available energy (capacity) of the energy storage device 40. Based on the capacity of the energy storage device 40, the memory system 1 switches the writing method of the memory system 1.

[0082] (1: Relationship between the usage period of the energy storage device 40 and the available energy supply) Figure 10 is a graph showing an example of the relationship between the service life and available energy of the energy storage device 40 in the memory system 1 according to the first embodiment. Figure 10 shows the aging degradation of the energy storage device 40 when an electrolytic capacitor is used as the energy storage device 40. As shown in Figure 10, the available energy of the energy storage device 40 is E1 when the service life is Y1. When the service life reaches Y2, the available energy of the energy storage device 40 decreases from E1 to E2. If the product warranty period of the memory system 1 is Y2, the energy storage device 40 needs to be configured to have an energy storage capacity that can perform the desired PLP operation when the service life is Y2. The desired PLP operation refers to a PLP operation that can make the amount of data that should be made non-volatile non-volatile.

[0083] In memory system 1, the energy required for PLP operation is greater in the Foggy-Fine method than in the MLC-Fine method. For example, if the available energy supplied by the energy storage device 40 is E1 or higher, memory system 1 can complete the desired PLP operation when the power is lost, regardless of whether the Foggy-Fine method or the MLC-Fine method is used. On the other hand, if the available energy supplied by the energy storage device 40 falls below E1, memory system 1 may not be able to complete the PLP operation in the Foggy-Fine method when the power is lost. For example, memory system 1 may be able to complete the desired PLP operation in the Foggy-Fine method when the available energy supplied by the energy storage device 40 falls only slightly below E1, but as the available energy supplied by the energy storage device 40 continues to decrease, it will no longer be able to perform the desired PLP operation in the Foggy-Fine method. On the other hand, even if the available energy supplied by the energy storage device 40 falls below E1, the memory system 1, using the MLC-Fine method, can complete the desired PLP operation until the end of the product warranty period.

[0084] If the writing method to the memory device 20 is static, the writing methods available in the memory system 1 are set according to the available energy supplied by the energy storage device 40. For example, in order to achieve PLP operation for the period up to Y2, which is the product warranty period of the memory system 1, the MLC-Fine method must be used. However, considering performance, it is preferable to use the Foggy-Fine method when the available energy supplied by the energy storage device 40 is sufficient (for example, E1 or higher). Therefore, the memory system 1 according to the first embodiment switches the writing method of the memory system 1 based on the available energy supplied by the energy storage device 40 when performing a periodic patrol operation.

[0085] (2: Patrol operation sequence) Figure 11 is a flowchart showing an example of the patrol operation of the memory system 1 according to the first embodiment. The memory system 1 according to the first embodiment starts the series of operations shown in Figure 11 based on a predetermined schedule, i.e., periodically (start).

[0086] During patrol operations, the memory system 1 first measures the energy storage capacity (available energy supply) of the energy storage device 40 (ST10).

[0087] Next, the memory system 1 checks whether the energy storage capacity of the energy storage device 40 is above a threshold (ST11).

[0088] If the energy storage capacity is above the threshold (ST11: YES), the memory system 1 is set to the first write mode (ST12).

[0089] If the energy storage capacity is below the threshold (ST11:NO), memory system 1 is set to the second write mode (ST13).

[0090] Once processing ST12 or ST13 is complete, the memory system 1 terminates the series of operations shown in Figure 11.

[0091] The first writing mode should use a writing method that requires more energy (power consumption) than the second writing mode and provides higher reliability of the written data. The first writing mode may, for example, support the Foggy-Fine method. The second writing mode may, for example, support the MLC-Fine method.

[0092] In memory system 1, the entity performing the patrol operation may be the memory controller 10, or it may be a collaboration between the memory controller 10 and the power supply IC 30. The power supply IC 30 may be configured to periodically measure the energy storage capacity and transmit information regarding the energy storage capacity of the energy storage device 40 to the memory controller 10. In this case, the memory controller 10 sets memory system 1 to either the first write mode or the second write mode based on the information regarding the energy storage capacity of the energy storage device 40 received from the power supply IC 30. The patrol operation is performed, for example, once every 15 minutes based on the OCP (Open Compute Project) standard.

[0093] (3: How to check the energy storage capacity) Figure 12 is a waveform diagram showing an example of a method for checking the energy storage capacity of the energy storage device 40 in the memory system 1 according to the first embodiment. In the graph shown in Figure 12, the horizontal axis represents time, and the vertical axis represents the charging voltage of the energy storage device 40. When measuring the energy storage capacity of the energy storage device 40, for example, before time t1, the power supply IC 30 first checks whether the charging voltage of the energy storage device 40 is equal to or greater than the threshold voltage VL. If the charging voltage of the energy storage device 40 is not equal to or greater than the threshold voltage VL, the power supply IC 30 charges the energy storage device 40. In this example, the charging voltage of the energy storage device 40 after charging is shown as VH.

[0094] Then, at time t1, the power supply IC 30 forcibly discharges the energy storage device 40 with a constant current until the charging voltage of the energy storage device 40 falls below the threshold voltage VL. In this example, at time t2, the charging voltage of the energy storage device 40 has dropped to VL. In this case, the power supply IC 30 measures the discharge time of the energy storage device 40 based on times t1 and t2. Then, the power supply IC 30 can calculate the energy storage capacity of the energy storage device 40 based on the obtained discharge time, the value of the constant current (discharge current), the threshold voltage VL, and the following equation (1). Power storage capacity = (discharge current x discharge time) / VL (1)

[0095] <1-2-4>Specific Examples The following describes specific examples of patrol operation and write control in the memory system 1 according to the first embodiment.

[0096] (1: Patrol operation) Figure 13 is a flowchart illustrating a specific example of the patrol operation of the memory system 1 according to the first embodiment. In this example, an electrolytic capacitor is used as the energy storage device 40. The memory system 1 starts the series of operations shown in Figure 13 based on a predetermined schedule (start).

[0097] During patrol operation, for example, the power supply IC 30 first measures the capacitance of the electrolytic capacitor (energy storage device 40) (ST20). For measuring the capacitance, the method described with reference to Figure 12 is used, for example.

[0098] Then, the memory controller 10 or the power supply IC 30 checks whether the capacitance of the electrolytic capacitor is above a threshold value (ST21).

[0099] If the capacitor capacity is above a threshold (ST21:YES), the memory controller 10 sets its operating mode to Foggy-Fine mode, in which the Foggy-Fine method is applied to the write operation (ST22).

[0100] If the capacitor capacity is below the threshold (ST21:NO), the memory controller 10 sets its own operating mode to MLC-Fine mode, in which the MLC-Fine method is applied to the write operation (ST23).

[0101] Once processing ST22 or ST23 is complete, the memory system 1 terminates the series of operations shown in Figure 13.

[0102] (2: When supplying logical blocks) Figure 14 is a flowchart showing a specific example of the operation of the memory system 1 according to the first embodiment when a logical block is supplied. A logical block is allocated for each block BLK. When the memory controller 10 receives a write command and write data from the host device 2, it starts the series of operations shown in Figure 14 as the operation when a logical block is supplied (start).

[0103] When a logical block is supplied, the memory controller 10 first checks the operating mode (ST30). This operating mode indicates the writing method, such as Foggy-Fine mode or MLC-Fine mode.

[0104] If the operating mode is Foggy-Fine mode, the memory controller 10 sets the write method attribute of the logical block to Foggy-Fine (ST31).

[0105] When the operating mode is MLC-Fine mode, the memory controller 10 sets the write method attribute of the logical block to MLC-Fine (ST32).

[0106] Once processing ST31 or ST32 is complete, the memory controller 10 terminates the series of operations shown in Figure 14 (terminates).

[0107] (3: When writing a logical page) Figure 15 is a flowchart illustrating a specific example of the operation of a memory system during logical page writing according to the first embodiment. When the memory controller 10 writes multiple page data, which are stored in the buffer memory 17 and to which logical pages have been allocated, to the memory device 20, it starts the series of operations shown in Figure 15 (start).

[0108] When writing a logical page, the memory controller 10 first checks the write method attribute of the logical block (ST40).

[0109] If the write method attribute is Foggy-Fine, the memory controller 10 performs a Foggy-Fine write to the logical page (ST41). In other words, in the ST41 process, the memory controller 10 selects the page address of the memory device 20 corresponding to the logical page and performs a Foggy-Fine write operation.

[0110] If the write method attribute is MLC-Fine, the memory controller 10 performs an MLC-Fine write operation on the logical page (ST42). In other words, in the ST42 process, the memory controller 10 selects the page address of the memory device 20 corresponding to the logical page and performs an MLC-Fine write operation.

[0111] Once processing ST41 or ST42 is complete, the memory controller 10 terminates the series of operations shown in Figure 15 (terminates).

[0112] <1-3> Effects of the First Embodiment As described above, the memory system 1 according to the first embodiment is configured to utilize multiple writing methods with different reliability characteristics (e.g., Foggy-Fine / MLC-Fine). In the MLC-Fine method, the amount of data stored in the memory device 20 is reduced during PLP operation, which requires storing all of the write cache in the memory device 20 (making it non-volatile). Therefore, the MLC-Fine method can suppress the energy (power consumption) required for PLP operation more effectively than the Foggy-Fine method. The memory controller 10 is equipped with firmware that has a function to determine an appropriate writing method to the memory device 20 according to the energy storage capacity of the energy storage device 40, and can dynamically switch the writing method to the memory device 20 according to the determination result.

[0113] As a result, the memory system 1 can utilize the Foggy-Fine method when the energy storage device 40 has not deteriorated over time, thereby improving write performance and reliability. Furthermore, if the energy storage device 40 has deteriorated over time, the memory system 1 can utilize the MLC-Fine method to guarantee the completion of PLP operation during power outages, thereby avoiding the loss of written data.

[0114] Therefore, the memory system 1 according to the first embodiment can realize the PLP function within the device warranty period and improve the reliability and performance of the device to the extent possible. The operation of changing the writing method described in the first embodiment is more effective when the number of states formed is large. For example, when the QLC method is used, it is preferable to use the Foggy-Fine method which achieves both high performance and high reliability, and by applying the operation described in the first embodiment, a greater effect can be obtained.

[0115] <2> Second Embodiment The second embodiment relates to a memory system 1 configured to select a more preferred data writing method based on the usage time of the memory system 1. The details of the memory system 1 according to the second embodiment will be described below, mainly focusing on the differences from the first embodiment.

[0116] <2-1> Composition Figure 16 is a block diagram showing an example of the hardware configuration of the memory controller 10a in the memory system 1 according to the second embodiment. As shown in Figure 16, the memory controller 10a has a configuration in which a timer 18 is added to the memory controller 10 according to the first embodiment. The timer 18 is configured to count the operating time of the memory system 1. The other configurations of the memory system 1 according to the second embodiment are the same as those of the first embodiment.

[0117] <2-2> Operation Figure 17 is a flowchart showing an example of the patrol operation of the memory system 1 according to the second embodiment. The memory system 1 according to the second embodiment starts the series of operations shown in Figure 17 based on a predetermined schedule (start).

[0118] During patrol operation, the memory controller 10a first checks the count time of the timer 18 (ST50).

[0119] Next, the memory controller 10a checks whether the timer 18's count time is above a threshold (ST51). This threshold is set, for example, to the limit of time at which the energy storage capacity of the energy storage device 40 is estimated to be able to utilize the Foggy-Fine method during PLP operation.

[0120] If the count time is greater than or equal to the threshold (ST51: YES), memory system 1 is set to the first write mode (ST12).

[0121] If the count time is below the threshold (ST51:NO), memory system 1 is set to the second write mode (ST13).

[0122] Once processing ST12 or ST13 is complete, the memory controller 10a terminates the series of operations shown in Figure 17 (terminates).

[0123] Other operations of the memory system 1 according to the second embodiment are the same as those of the first embodiment.

[0124] <2-3> Effects of the second embodiment As described above, the data writing method may be changed based on the operating time of the memory system 1. Even in such a case, the memory system 1 according to the second embodiment can realize the PLP function within the device warranty period and improve the reliability and performance of the device to the extent possible, similar to the first embodiment.

[0125] <3> others In the memory controller 10 of the above embodiment, an MPU (Micro Processing Unit) may be used instead of the CPU 13. Furthermore, each of the processes described in the above embodiment may be performed by a dedicated hardware circuit, a processor that executes a program (firmware), or a combination thereof. In this specification, “connection” means an electrical connection and does not exclude the use of other elements in between.

[0126] Other embodiments are described below.

[0127] (Note 1) A memory device configured to store data in a non-volatile manner, A memory controller configured to control the aforementioned memory device, A power supply circuit configured to generate power to drive the memory device and the memory controller based on power supplied from an external power source, and to supply the generated power to the memory device and the memory controller, The system includes a power storage device capable of storing electrical energy, configured to supply electrical energy to the memory device and the memory controller respectively when the power supply from the external power source is interrupted, The memory controller is further configured to apply either a first write mode or a second write mode, which have different power consumption levels, to the write operation to the memory device, depending on the power storage capacity of the power storage device. Memory system.

[0128] (Note 2) The above memory device comprises a cell unit composed of multiple memory cells, each capable of storing multiple bits of data. The above memory controller further manages the storage area of ​​the above memory device in units of the above cell units, and the above storage area includes a contiguous first cell unit and a second cell unit. The above writing operation includes a first-stage program and a second-stage program for each of the above cell units. The memory controller further executes the first stage program for the first cell unit, the first stage program for the second cell unit, and the second stage program for the second cell unit in the order described above during the write operation. The memory system described in Appendix 1.

[0129] (Note 3) The above memory cell is configured to store N bits of data (where N is an integer greater than or equal to 3). The above memory controller further, In the first writing mode described above, the first stage program performs a rough writing operation of N bits of data, and the second stage program performs a detailed writing operation of N bits of data. In the second writing mode described above, the first stage program is configured to perform a rough write operation of M bits of data (where M is an integer between 1 and N, inclusive), and the second stage program is configured to perform a fine write operation of N bits of data. The memory system described in Appendix 2.

[0130] (Note 4) Each of the above first-stage program and the above second-stage program includes the operation of applying a program voltage multiple times to multiple memory cells contained in the selected cell unit while stepping up the voltage. The step-up size of the program voltage in a general writing operation is larger than the step-up size of the program voltage in a fine writing operation. The memory system described in Appendix 3.

[0131] (Note 5) The memory controller further reads the data written to the selected cell unit in the first stage program before performing a fine-grained write operation of N-bit data to the selected cell unit in the second stage program of the second write mode, and uses the read data in the fine-grained write operation of N-bit data. The memory system described in Appendix 3.

[0132] (Note 6) The above N is 4. The memory system described in Appendix 3.

[0133] (Note 7) The above M is 2. The memory system described in Appendix 5.

[0134] (Note 8) The memory controller described above is further configured to periodically check the energy storage capacity of the energy storage device. The memory system described in Appendix 1.

[0135] (Note 9) The above-mentioned energy storage device includes an electrolytic capacitor or an electric double-layer capacitor. The memory system described in Appendix 1.

[0136] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0137] 1...Memory system, 2...Host device, 3...External power supply, 10,10a...Memory controller, 11...Host interface, 12...Memory interface, 13...CPU, 14...ECC circuit, 15...ROM, 16...RAM, 17...Buffer memory, 18...Timer, 20...Memory device, 21...Memory cell array, 22...Input / output circuit, 23...Logic controller, 24...Register circuit, 25...Sequencer, 26...Ready / busy controller, 27...Driver circuit, 28...Raw decoder module, 29...Sense amplifier module, 30... Power IC, 40... Energy storage device, 101... Host interface control unit, 102... Command processing unit, 103... Write management unit, 104... Write buffer, 105... NAND interface control unit, S0~S15, ER, F0~F15, M0~M3... State, BLK... Block, SU... String unit, NS... NAND string, MT... Memory cell transistor, STD, STS... Selection transistor, RD... Row decoder, SAU... Sense amplifier unit, SGD, SGS... Selection gate line, WL... Word line, BL... Bit line, SL... Source line

Claims

1. A memory device configured to store data in a non-volatile manner, A memory controller configured to control the aforementioned memory device, A power supply circuit configured to generate power to drive the memory device and the memory controller based on power supplied from an external power source, and to supply the generated power to the memory device and the memory controller, The system includes a power storage device capable of storing electrical energy, configured to supply electrical energy to the memory device and the memory controller via the power supply circuit when the power supply from the external power source is interrupted, The memory controller is further configured to apply either a first write mode or a second write mode, which have different power consumption levels, to the write operation to the memory device, depending on the power storage capacity of the power storage device. Memory system.

2. The memory device comprises a cell unit composed of multiple memory cells, each capable of storing multiple bits of data. The memory controller further manages the storage area of ​​the memory device in units of cell units, and the storage area includes a contiguous first cell unit and a second cell unit. The aforementioned writing operation includes a first-stage program and a second-stage program for each cell unit. The memory controller further executes the first stage program for the first cell unit, the first stage program for the second cell unit, and the second stage program for the second cell unit in the order described above during the write operation. The memory system according to claim 1.

3. The memory cell is configured to store N bits of data (where N is an integer of 3 or more), The aforementioned memory controller further, In the first writing mode, the first stage program performs a rough writing operation of N-bit data, and the second stage program performs a detailed writing operation of N-bit data. In the second writing mode, the first stage program is configured to perform a rough writing operation of M bits of data (where M is an integer between 1 and N, inclusive), and the second stage program is configured to perform a fine writing operation of N bits of data. The memory system according to claim 2.

4. The memory controller is further configured to select the first write mode when the energy storage capacity of the energy storage device is above a threshold, and to select the second write mode when the energy storage capacity of the energy storage device is below a threshold. The memory system according to claim 3.

5. The memory controller further reads the data written to the selected cell unit in the first stage program before performing a fine-grained write operation of N-bit data to the selected cell unit in the second stage program of the second write mode, and uses the read data in the fine-grained write operation of N-bit data. The memory system according to claim 3.

6. A control method for a memory system including a memory device configured to store data nonvolatilously, a power supply circuit configured to generate power to drive the memory device based on power supplied from an external power source and to supply the generated power to the memory device, and a power storage device configured to store electrical energy, When the power supply from the external power source is interrupted, the energy storage device supplies electrical energy to the memory device via the power supply circuit. When power is supplied from the external power supply, the system applies either a first write mode or a second write mode with different power consumption, depending on the power storage capacity of the power storage device, to the write operation to the memory device. A method for controlling a memory system.

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