Memory systems and memory devices

Abstract

Improve the reliability of data retrieval. [Solution] The memory system of the embodiment includes a memory device including a plurality of memory cells for storing data, and a memory controller for controlling the operation of the memory device, wherein the memory device is configured to obtain, in response to a first set of read commands, a first determination result of the threshold voltages of the plurality of memory cells based on a first read level relating to a first threshold voltage distribution, and a second determination result of the threshold voltages of the plurality of memory cells based on a first low-voltage offset read level obtained by offsetting the first read level to the low-voltage side, obtain a first number of mismatches between the first determination result and the second determination result, and calculate a first correction amount for the first read level based on the first number of mismatches.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a memory device.

Background Art

[0002] As a memory system, a solid state drive (SSD) including a memory controller and a memory device is known. The memory device is, for example, a non-volatile memory. The non-volatile memory is, for example, a NAND type flash memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the reliability of data reading.

Means for Solving the Problems

[0005] The memory system of this embodiment includes a memory device including a plurality of memory cells for storing data, and a memory controller for controlling the operation of the memory device, wherein the memory device is configured to obtain, in response to a first set of read commands, a first determination result of the threshold voltages of the plurality of memory cells based on a first read level relating to a first threshold voltage distribution, and a second determination result of the threshold voltages of the plurality of memory cells based on a first low-voltage offset read level obtained by offsetting the first read level to a low voltage side, obtain a first number of mismatches between the first determination result and the second determination result, and calculate a first correction amount for the first read level based on the first number of mismatches. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of the memory system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of the memory system according to the first embodiment. [Figure 3] A circuit diagram showing an example configuration of a memory cell array in a memory device. [Figure 4] A schematic diagram illustrating the relationship between the threshold voltage of a memory cell and the data. [Figure 5] A diagram illustrating the command sequence of the memory system in the first embodiment. [Figure 6] A schematic diagram illustrating the general read operation of the memory system in the first embodiment. [Figure 7] A flowchart illustrating the read operation of the memory system in the first embodiment. [Figure 8] A schematic diagram illustrating the read operation of the memory system in the first embodiment. [Figure 9] A schematic diagram illustrating the read operation of the memory system in the first embodiment. [Figure 10] A schematic diagram illustrating the read operation of the memory system in the first embodiment. [Figure 11]Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 12] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 13] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 14] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 15] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 16] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 17] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 18] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 19] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 20] Schematic diagram for explaining the read operation of the memory system according to the first embodiment. [Figure 21] Schematic diagram for explaining the memory system according to the second embodiment. [Figure 22] Schematic diagram for explaining the memory system according to the fifth embodiment. [Figure 23] Schematic diagram for explaining the memory system according to the seventh embodiment. [Figure 24] Schematic diagram for explaining the memory system according to the tenth embodiment. [Figure 25] Schematic diagram for explaining the memory system according to the eleventh embodiment.

Embodiments for Carrying Out the Invention

[0007] The memory systems and memory devices of the embodiments will be described with reference to Figures 1 to 25. In the following description, elements having the same function and configuration will be denoted by the same reference numeral. In addition, in each of the following embodiments, if components that are denoted by reference numerals with distinguishing numerals / letters at the end (e.g., circuits, wiring, various voltages and signals, etc.) do not need to be distinguished from one another, the reference numerals / letters at the end will be omitted.

[0008] (Embodiment) (1) First Embodiment Referring to Figures 1 to 20, the memory system, memory device, and control method of the memory system according to the first embodiment will be described.

[0009] (a) Configuration example An example of the configuration of the memory system of this embodiment will be described with reference to Figures 1 to 6.

[0010] (a-1) Overall configuration Figure 1 is a block diagram showing an example configuration of the information processing system 9.

[0011] As shown in Figure 1, the information processing system 9 includes the memory system 1 and host 2 of this embodiment.

[0012] Memory system 1 is a device that stores data. Memory system 1 may be, for example, an SSD (solid state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM It is a card. Memory system 1 is connectable to host 2 via host bus HBS. Memory system 1 performs processing based on requests (commands or host commands) received from host 2 or spontaneous processing requests generated within memory system 1.

[0013] Host 2 is a computing device that controls memory system 1. Host 2 may be, for example, a personal computer, a server, a mobile device, an in-vehicle device, or a digital camera.

[0014] (a-1-1) Internal configuration of the memory system The memory system 1 includes a memory controller 10 and a memory device 30. The memory device 30 is, for example, a non-volatile memory. More specifically, the memory device 30 is a non-volatile semiconductor memory such as a NAND flash memory. Hereinafter, the memory device 30 will be referred to as non-volatile memory 30 or NAND memory 30.

[0015] The memory controller 10 is a device that controls the NAND memory 30. The memory controller 10 is connected to the host 2 via the host bus HBS. The memory controller 10 receives requests from the host 2 via the host bus HBS. The type of host bus HBS depends on the application applied to the memory system 1. If the memory system 1 is an SSD, the host bus HBS may be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM It conforms to the Peripheral Component Interconnect Express (CSI) standard. If memory system 1 is a UFS device, the host bus HBS conforms to the M-PHY standard. If memory system 1 is a USB memory, the host bus HBS conforms to the USB standard. If memory system 1 is an SD TM If it is a card, the host bus HBS is SD TM To comply with standards.

[0016] The memory controller 10 controls the NAND memory 30 via the NAND bus NBS based on requests received from the host 2 or spontaneous processing requests generated within the memory system 1. The NAND bus NBS conforms to, for example, the Toggle NAND Flash Interface standard or the Open NAND Flash Interface standard.

[0017] The NAND memory 30 is a device for storing data. The NAND memory 30 includes multiple memory cells. Each of the multiple memory cells stores data nonvolatilously according to the threshold voltage of the memory cell. The NAND memory 30 stores the data received from the memory controller 10 nonvolatilously in the multiple memory cells. The NAND memory 30 outputs the data read from the multiple memory cells to the memory controller 10.

[0018] (a-1-2) Memory controller An example of the internal configuration of the memory controller 10 will be described below.

[0019] As shown in Figure 1, the memory controller 10 includes a host interface (host I / F) circuit 11, a processor 12, a buffer memory 13, an ECC (error checking and correcting) circuit 14, a ROM (read-only memory) 15, a RAM (random access memory) 16, and a NAND interface (NAND I / F) circuit 17. The memory controller 10 may be configured as, for example, a SoC (system-on-a-chip). The memory controller 10 may be composed of multiple chips. The functions of each part of the memory controller 10 can be realized by dedicated hardware circuits, a processor that executes a program (firmware), or a combination thereof.

[0020] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus HBS.

[0021] The processor 12 is the control circuit of the memory controller 10. The processor 12 is, for example, a CPU (central processing unit). The processor 12 controls the operation of the entire memory controller 10 by executing a program (firmware) stored in the ROM 15. For example, when the processor 12 receives a write request from the host 2, it controls the write operation based on the received write request. For example, when the processor 12 receives a read request from the host 2, it controls the read operation based on the received read request.

[0022] Buffer memory 13 is memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (static random access memory). Buffer memory 13 temporarily stores written data and read data, etc. Written data is data written to NAND memory 30. Read data is data read from NAND memory 30.

[0023] The ECC circuit 14 is a circuit that performs ECC processing for error correction of data. During a data writing operation, the ECC circuit 14 generates error correction codes based on the data to be written in predetermined units. During a data reading operation, the ECC circuit 14 generates a syndrome based on the error correction codes in predetermined units and detects errors. The ECC circuit 14 corrects the detected errors.

[0024] ROM15 is a non-volatile memory. ROM15 is, for example, an EEPROM. TM It is an electrically erasable, programmable, read-only memory. ROM15 stores programs such as firmware.

[0025] RAM16 is volatile memory. RAM16 is, for example, SRAM or DRAM (dynamic random access memory). RAM16 is used as a work area for processor 12. RAM16 stores firmware for managing NAND memory 30 and various management information. RAM16 stores, for example, various tables TBL.

[0026] The NAND interface circuit 17 is responsible for communication between the memory controller 10 and the NAND memory 30. The NAND interface circuit 17 is connected to the NAND memory 30 via the NAND bus NBS. For example, the NAND interface circuit 17 controls the transfer of data, commands, and addresses between the memory controller 10 and the NAND memory 30.

[0027] For example, the NAND memory 30 includes multiple memory chips (memory dies) 300.

[0028] (a-1-3) NAND flash memory Referring to Figure 2, the configuration of the NAND memory 30 will be explained.

[0029] Figure 2 is a block diagram showing an example of the configuration of a NAND memory 30. The NAND memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register circuit 35, a sequencer 36, a driver module 37, a row decoder module 38, a sense amplifier module 39, a data latch circuit 40, an error bit detection circuit 50, and a correction amount calculation circuit 52.

[0030] The memory cell array 31 is a circuit for storing data. The memory cell array 31 includes one or more block BLKs. A block BLK is, for example, a collection of multiple memory cells whose data is erased all at once.

[0031] Multiple bit lines and multiple word lines are provided within the memory cell array 31. Each memory cell is associated, for example, with one bit line and one word line. Details of the memory cell array 31 will be described later.

[0032] The input / output circuit 32 is a circuit that transmits and receives signals and information to and from the memory controller 10. The input / output circuit 32 transmits and receives input / output signals DQ (for example, 8-bit signals DQ0, ..., DQ7) and data strobe signals DQS to and from the memory controller 10. Signal DQ is the actual data transmitted and received between the NAND memory 30 and the memory controller 10. Signal DQ is, for example, a command CMD, an address ADD, status information STS, and data DAT.

[0033] Command CMD includes, for example, instructions that cause the sequencer 36 to perform a read operation, a write operation, or an erase operation.

[0034] Address ADD includes, for example, row addresses and column addresses. Row addresses include block addresses and page addresses (word line addresses). Block addresses, page addresses, and column addresses are used, for example, to select block BLK, word lines, and bit lines, respectively.

[0035] The status information STS is used to notify the memory controller 10 whether the operation has completed successfully or not.

[0036] Data DAT is either written data or read data.

[0037] In the input / output circuit 32, the input / output unit of the signal DQ (hereinafter referred to as the I / O unit) is 8 bits.

[0038] The signal DQS is a clock signal used to control the timing of transmission and reception of the signal DQ. For example, when writing data, the signal DQS is transmitted from the memory controller 10 to the NAND memory 30 along with the signal DQ containing the data to be written. The input / output circuit 32 receives the signal DQ containing the data to be written in synchronization with the signal DQS. When reading data, the signal DQS is transmitted from the input / output circuit 32 to the memory controller 10 along with the signal DQ containing the data to be read. The memory controller 10 receives the signal DQ containing the data to be read in synchronization with the signal DQS. The input / output circuit 32 may also receive the signal DQS from the memory controller 10 via the logic control circuit 33.

[0039] The input / output circuit 32 transmits the command CMD in signal DQ to the register circuit 35. The input / output circuit 32 transmits the address ADD in signal DQ to the register circuit 35. The input / output circuit 32 receives the status information STS from the register circuit 35. The input / output circuit 32 transmits and receives the data DAT in signal DQ to and from the data latch circuit 40.

[0040] The logic control circuit 33 is a circuit that controls the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives control signals from the memory controller 10, such as the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn. Signal CEn is a signal to enable the chip 300 of the NAND memory 30. Signal CLE is a signal that indicates to the NAND memory 30 that the signal DQ received is the command CMD. Signal ALE is a signal that indicates to the NAND memory 30 that the signal DQ received is the address ADD. Signal WEn is a signal that commands the NAND memory 30 to input signal DQ. Signal REn is a signal that commands the NAND memory 30 to output signal DQ. The NAND memory 30 generates signal DQS based on signal REn. The NAND memory 30 outputs signal DQ to the memory controller 10 based on the generated signal DQS.

[0041] The ready / busy control circuit 34 is a circuit that informs the memory controller 10 of the operating status of the sequencer 36. Based on the operating status of the sequencer 36, the ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10. Signal RBn is a signal that indicates whether the NAND memory 30 is in a ready state or a busy state. The signal level of signal RBn is, for example, high level ("H" level) when the NAND memory 30 is in a ready state. The ready state is a state in which the NAND memory 30 can accept a command CMD from the memory controller 10. The signal level of signal RBn is, for example, low level ("L" level) when the NAND memory 30 is in a busy state. The busy state is a state in which the NAND memory 30 cannot accept a command CMD from the memory controller 10.

[0042] The register circuit 35 is a circuit that temporarily stores information. For example, the register circuit 35 temporarily stores command CMD, address ADD, status information STS, and setting information for the NAND memory 30.

[0043] The configuration information includes, for example, information regarding the setting values ​​of various voltages used in the NAND memory 30. The configuration information is stored, for example, in the configuration information register 350.

[0044] For example, the configuration information register 350 includes a register (R_Vit) for the static shift value of the read level during manufacturing testing of the NAND memory 30. The static shift value is a value set at the time of shipment of the memory system to adjust the read level according to product variations. The number of static shift value registers (i) is provided to correspond to the number of read levels used depending on the mode of the number of bits stored by the memory cell. The modes of the number of bits stored by the memory cell will be described in detail later. For example, if the mode of the NAND memory 30 is a mode in which 3 bits of data are stored in the memory cell MC, then "i" is a value between 0 and 7.

[0045] The configuration information register 350 includes a specified shift value register (R_ViSS) that stores the specified shift value of the read level specified by the memory controller 10. The specified shift value is a value that indicates the amount of shift in the read level managed in the table TBL within the memory controller 10. The NAND memory 30 receives the specified shift value from the memory controller 10 and stores the specified shift value in the specified shift value register. The number of specified shift value registers (i) corresponds to the number of read levels, which will be described later.

[0046] The configuration information register 350 includes a dynamic shift value register (R_ViSlfTr) that stores the dynamic shift value of the read level. The dynamic shift value is a value that adjusts the read level. The dynamic shift value is determined by the automatic adjustment read operation described later. The number of dynamic shift value registers (i) corresponds to the number of read levels described later.

[0047] The configuration information register 350 includes a negative offset value register (R_ViOstM). The negative offset value register stores the value of the offset voltage used to set a voltage value lower than the normal voltage value of a certain read level. The number of negative offset value registers (i) depends on the number of read levels, as described later.

[0048] The configuration information register 350 includes a register for positive offset values ​​(R_ViOstP). The register for positive offset values ​​stores the value of the offset voltage used to set a voltage value higher than the normal voltage value of a certain readout level. The number of registers for positive offset values ​​(i) depends on the number of readout levels, as described later.

[0049] Furthermore, the setting information register 350 may include a register (R_Vi_0) that stores the reference voltage value (default value Vi_0) for each readout level.

[0050] The sequencer 36 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 36 controls the operation of the entire NAND memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the raw decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the register circuit 35. For example, the sequencer 36 performs read operations, write operations, and erase operations.

[0051] The driver module 37 is a circuit that generates various voltages used in read, write, and erase operations. Based on the page address stored in the register circuit 35, the driver module 37 applies the generated voltage to the signal line corresponding to the selected word line. The driver module 37 includes multiple charge pumps for generating multiple voltages, each of which is included.

[0052] The row decoder module 38 is a circuit that selects one block BLK in the memory cell array 31 based on the block address stored in the register circuit 35. The row decoder module 38 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0053] During a write operation, the sense amplifier module 39 receives the write data DAT from the input / output circuit 32 via the data latch circuit 40. The sense amplifier module 39 applies a voltage to the bit line based on the received write data DAT. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on whether or not current flows through the bit line or the voltage of the bit line. The sense amplifier module 39 transfers the determination result as read data DAT to the input / output circuit 32 via the data latch circuit 40.

[0054] The data latch circuit 40 temporarily stores the write data or read data. For example, during a write operation, the data latch circuit 40 temporarily stores the write data received from the input / output circuit 32 and transmits it to the sense amplifier module 39. During a read operation, the data latch circuit 40 temporarily stores the data from the sense amplifier module 39 and transmits it to the input / output circuit 32.

[0055] The data latch circuit 40 includes multiple data latches ADL, BDL, ..., XDL. In the following, when the multiple data latches ADL, BDL, ..., XDL are not distinguished, each data latch ADL, BDL, ..., XDL of the data latch circuit 40 will also be referred to as data latch DL. Each data latch DL temporarily stores data of a certain data size in the written data and read data. For example, each data latch DL can store approximately 18 kBytes of data, including one page's worth of data in the NAND memory 30 (16 kBytes of data) and redundant data (approximately 2 kBytes of data). The redundant data includes ECC parity and data used by the memory controller 10, etc. The input and output of data in the data latch DLs can be controlled, for example, by the sequencer 36 or the error bit detection circuit 50 described later. The data in the data latch DLs can be transferred from one data latch DL to another data latch DL under the control of the sequencer 36 or the error bit detection circuit 50.

[0056] The error bit detection circuit 50 is a circuit that detects error bits in data read from the memory cell array 31. The error bit detection circuit 50 detects error bits contained in the data by performing various calculations (for example, exclusive OR operations) using the data in the data latch DL. The error bit detection circuit 50 can count the number of error bits contained in a certain unit (data length) of data. Note that the calculations using the data in the data latch DL may be performed by the sequencer 36.

[0057] The correction amount calculation circuit 52 is a circuit that calculates a dynamic shift value for the read voltage (read level). Based on the error bit detection result by the error bit detection circuit 50, the correction amount calculation circuit 52 calculates a dynamic shift value to set the read level voltage to a more suitable value. The read level is corrected by the calculated dynamic shift value. The correction amount calculation circuit 52 transmits the calculated dynamic shift value to the register circuit 35. For example, the calculated dynamic shift value is stored in the dynamic shift value register (R_ViSlfTr) of the setting information register 350. The correction amount calculation circuit 52 may also include registers that store setting values ​​for various voltages used in the read operation.

[0058] The error bit detection circuit 50 and the correction amount calculation circuit 52 may be provided within the sequencer 36 as a functional block or internal circuit of the sequencer 36.

[0059] (a-1-3-1) Example of a memory cell array circuit The circuit configuration of the memory cell array 31 will be described with reference to Figure 3. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 shows the circuit configuration of block BLK included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31.

[0060] Block BLK includes, for example, five string units SU0, SU1, SU2, SU3, and SU4. Each string unit SU is a set of multiple NAND strings NS that are selected collectively, for example, in a write or read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., BLm-1, respectively, where m is an integer greater than or equal to 1. A NAND string NS is a set of multiple memory cells MC (MC0, ..., MCn-1) connected in series. Each NAND string NS includes, for example, memory cells MC0, MC1, MC2, MC3, ..., MCn-2, MCn-1, select transistor ST1, and select transistor ST2, where n is an integer greater than or equal to 1. A memory cell (also called a memory cell transistor) MC is a field-effect transistor including a control gate and a charge storage layer. Select transistors ST1 and ST2 are switching elements. Each of select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0061] In each NAND string NS, memory cells MC0, ..., MCn-1 are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cells MC0, ..., MCn-1. The drain of select transistor ST2 is connected to the other end of the series-connected memory cells MC0, ..., MCn-1. The source of select transistor ST2 is connected to the source line SL.

[0062] Within the same block BLK, the control gates of memory cells MC0, MC1, MC2, MC3, ..., MCn-2, MCn-1 are commonly connected to word lines WL0, WL1, WL2, WL3, ..., WLn-2, ​​WLn-1 across multiple NAND strings. The gates of select transistors ST1 within string units SU0, SU1, SU2, SU3, SU4 are commonly connected to select gate lines SGD0, SGD1, SGD2, SGD3, SGD4 across multiple NAND strings. The gate of select transistor ST2 included in the same block BLK is commonly connected to select gate line SGS across multiple NAND strings.

[0063] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared by, for example, NAND strings NS to which the same column address is assigned in each string unit SU. The source line SL is shared by, for example, multiple blocks BLK.

[0064] In the following, a collection of memory cells MCs CU that are commonly connected to the same word line WL within a string unit SU is also called a cell unit CU.

[0065] Memory cell cells (MCs) can store one or more bits of data. The mode in which a memory cell MC stores one bit of data is called SLC (Single Level cell) mode. The mode in which a memory cell MC stores two bits of data is called MLC (Multi Level cell) mode. The mode in which a memory cell MC stores three bits of data is called TLC (Triple Level cell) mode. The mode in which a memory cell MC stores four bits of data is called QLC (Quad Level cell) mode. The mode in which a memory cell MC stores five bits of data is called PLC (Penta Level cell) mode.

[0066] In this example, one memory cell (MC) stores 3 bits of data. Hereafter, these 3 bits of data are referred to as the lower bits, middle bits, and upper bits, from least significant to most significant. The set of lower bits held by memory cells belonging to the same cell unit (CU) is called the lower page (or lower data), the set of middle bits is called the middle page (or middle data), and the set of upper bits is called the upper page (or upper data).

[0067] If a single memory cell MC can store 3 bits of data, then 3 pages are allocated to a single word line WL (a single cell unit CU) within a single string unit SU. A "page" can also be defined as a portion of the memory space formed within a cell unit CU. Data writing and reading may be performed on a page-by-page basis or on a cell unit CU basis.

[0068] (a-2) Relationship between the threshold voltage of the memory cell and the data Referring to Figure 4, the relationship between the threshold voltage of the memory cell MC and the data stored in the memory cell in the memory system 1 of this embodiment will be explained.

[0069] Figure 4 is a schematic diagram illustrating the relationship between the threshold voltage distribution of a memory cell MC and the data stored. Figure 4 shows an example where the NAND memory 30 stores data in TLC mode.

[0070] Figure 4(a) shows the possible data, threshold voltage distribution, and voltage used when reading data from each memory cell MC.

[0071] As shown in Figure 4(a), if a memory cell MC can store 3 bits of data, the memory cell MC can take on eight states (threshold voltage distributions) S0, S1, ..., S7 depending on the threshold voltage Vth. These eight states are called, in order from the lowest threshold voltage, the "Er" state S0, the "A" state S1, the "B" state S2, the "C" state S3, the "D" state S4, the "E" state S5, the "F" state S6, and the "G" state S7.

[0072] The read voltage VCGR includes multiple voltages (hereinafter referred to as read levels) V1, V2, V3, V4, V5, V6, and V7, depending on the page being read. The read level is the voltage used to determine whether the threshold voltage of the memory cell MC is above or below a certain voltage. The application of the read level turns the memory cell MC on or off.

[0073] In state "Er" S0, the threshold voltage of the memory cell MC is less than the read level V1, corresponding to the data erasure state. In state "A" S1, the threshold voltage of the memory cell MC is greater than or equal to the read level V1 and less than the read level V2. In state "B" S2, the threshold voltage of the memory cell MC is greater than or equal to the read level V2 and less than the read level V3. In state "C" S3, the threshold voltage of the memory cell MC is greater than or equal to the read level V3 and less than the read level V4. In state "D" S4, the threshold voltage of the memory cell MC is greater than or equal to the read level V4 and less than the read level V5. In state "E" S5, the threshold voltage of the memory cell MC is greater than or equal to the read level V5 and less than the read level V6. In state "F" S6, the threshold voltage of the memory cell MC is greater than or equal to the read level V6 and less than the read level V7. In state "G" S7, the threshold voltage of the memory cell MC is greater than or equal to the read level V7 and less than the voltage VREAD. The relationship between these read levels V1 to V7 and voltage VREAD is V1 <V2<V3<V4<V5<V6<V7<VREADである。

[0074] Of the eight states S0, ..., S7 distributed in this manner, state "G" S7 is the state with the highest threshold voltage of the memory cell. Each state S0, ..., S7 has a range of voltage values ​​associated with the corresponding data. States S1, ..., S7 from "A" to "G" are called program states.

[0075] Voltage VREAD is, for example, the voltage applied to a word line (non-selected word line) WL that is not being read during a read operation. When voltage VREAD is applied to a memory cell MC, the memory cell MC turns on regardless of the data stored in it.

[0076] The threshold voltage distribution is realized by writing 3 bits (3 pages) of data, including the lower bit, middle bit, and upper bit described above, to the memory cell MC in the memory cell array 31. An example of the relationship between the threshold voltage state and the upper bit, middle bit, and lower bit is as follows. “Er” state: “111” (listed in the order of “Upper / Middle / Lower”) "A" State: "110" "B" State: "100" "C" state: "000" "D" State: "010" "E" State: "011" "F" State: "001" “G” State: “101” Thus, in the threshold voltage distribution, only one of the three bits changes between data corresponding to two adjacent states.

[0077] To read the lower bits of a memory cell (MC), a voltage corresponding to the boundary where the value of the lower bit ("0" or "1") changes is used. To read the upper bits of a memory cell (MC), a voltage corresponding to the boundary where the value of the upper bit changes is used. To read the middle bits, a voltage corresponding to the boundary where the value of the middle bit changes is used. Further details will be described later.

[0078] To read the lower bits of the memory cell MC, the NAND memory 30 reads the lower pages of the cell unit CU. As shown in Figure 4(a), the reading of the lower pages is performed using a read voltage of read level V1 that distinguishes between the “Er” state S0 and the “A” state S1, and read level V5 that distinguishes between the “D” state S4 and the “E” state S5.

[0079] To read the middle bit of the memory cell MC, the NAND memory 30 reads the middle page of the cell unit CU. The middle page reading is performed using read voltages V2, which distinguishes between "A" state S1 and "B" state S2; V4, which distinguishes between "C" state S3 and "D" state S4; and V6, which distinguishes between "E" state S5 and "F" state S6.

[0080] To read the higher bits of the memory cell MC, the NAND memory 30 reads the higher pages of the cell unit CU. The reading of the higher pages is performed using a read level V3 that distinguishes between the "B" state S2 and the "C" state S3, and a read level V7 that distinguishes between the "F" state S6 and the "G" state S7, as the read voltage.

[0081] By reading using read level V1, the erased memory cell MC is identified.

[0082] In the following, reading (determination) using read level V1 is also called AR reading. Similarly, reading using each read level V2, V3, V4, V5, V6, and V7 is called BR reading, CR reading, DR reading, ER reading, FR reading, and GR reading, respectively.

[0083] Figure 4(b) is a diagram illustrating the state of the threshold voltage distribution of a memory cell MC.

[0084] After data has been written, as time passes, an error occurs in which the threshold voltage distribution (state) shifts due to interference between memory cells (hereinafter, the stress that causes this error is called data retention or data retention stress). During write and read operations of the NAND memory 30, unintended shifts in the threshold voltage distribution (hereinafter, called program disturb and read disturb, respectively) may occur.

[0085] The characteristics of multiple memory cells MC within the memory cell array 31 tend to vary. For example, the amount of variation and the time of change (write speed) of the threshold voltage of a memory cell MC in response to a certain program voltage value vary. Due to this variation, when a certain voltage value of program voltage is applied, some memory cells that have reached a certain threshold voltage and others that have not reached a certain threshold voltage will be mixed together among the multiple memory cells MCs being written to. As a result, errors may occur in program operation where the threshold voltage of a memory cell MC moves to a state higher than the state corresponding to the data to be written.

[0086] For example, after data is written, a phenomenon may occur where the threshold voltage of a memory cell decreases. Due to this phenomenon, the threshold voltage of the memory cell after data writing may deviate from the value corresponding to the data to be stored, depending on the characteristics of the memory cell (e.g., data retention characteristics). The amount of change in the threshold voltage in this phenomenon after data writing varies depending on the characteristics of the memory cell.

[0087] When the threshold voltage distribution changes due to these various fluctuating factors, adjacent threshold voltage distributions may overlap.

[0088] Due to the overlap of adjacent threshold voltage distributions, the read operation using the above voltages V1, V2, V3, ..., V6, V7 may not correctly read data from memory cells MCs that have threshold voltages within the overlapping region 999.

[0089] For example, if the threshold voltage distribution S1 of state "A" and the threshold voltage distribution S2 of state "B" overlap, memory cells MC in state "A" with a threshold voltage greater than the read level V2 may be mistakenly read as state "B" S2, and memory cells MC in state "B" with a threshold voltage less than the read level V2 may be mistakenly read as state "A" S1. In this way, if the number of bits that are mistakenly read (number of error bits) exceeds the number of correctable bits of the ECC circuit 160, the memory controller 10 will fail to read the correct data from the NAND memory 30.

[0090] The memory system 1 of this embodiment detects errors (error bits) contained in the read data within the NAND memory 30. Based on the error detection result, the memory system 1 of this embodiment calculates a dynamic shift value within the NAND memory 30 to set a more suitable read voltage (read level) for the state within the memory cell array 31 during the read operation.

[0091] In the following, a read operation in which a dynamic shift value of the read level is calculated internally within the NAND memory 30 is called an automatically adjusted read operation. A read operation in which a dynamic shift value is not calculated is called a normal read operation.

[0092] (a-3) Outline of the calculation of the dynamic shift value of the readout level Referring to Figures 5 and 6, an outline of the calculation of the dynamic shift value of the read level in the memory system 1 of this embodiment will be described.

[0093] (a-3-1) Command Sequence Figure 5 is a sequence diagram showing the command set used to read data from the NAND memory 30 in the memory system 1 of this embodiment.

[0094] In the memory system 1 of this embodiment, the memory controller 10 performs the calculation of a dynamic shift value of the read level within the NAND memory 30. The calculation of the dynamic shift value of the read level is based on the detection of errors in the data acquired during the read operation and the result of the error detection. In this case, the memory controller 10 instructs the NAND memory 30 to perform an automatic adjustment read operation.

[0095] When an automatic adjustment read operation is commanded, the memory controller 10 sends the command sets CS0 and CS1 shown in Figure 5(a) to the NAND memory 30.

[0096] As shown in Figure 5(a), the command set CS0 includes prefix commands pCMD0, pCMD1, command RCMD0, address ADD, and command RCMD1. The command set CS0 is a set of signals for instructing the NAND memory 30 to perform an auto-adjusted read operation.

[0097] The prefix command pCMD0, "C4h," is sent from the memory controller 10 to the NAND memory 30. The prefix command pCMD0, "C4h," is a command that instructs the NAND memory 30 to perform data read operations using a normal standard read level, a read level offset to a lower voltage than the normal read level, and a read level offset to a higher voltage than the normal read level.

[0098] A normal, standard read level is referred to below as the standard read level. A read level offset to a lower voltage than a normal read level is referred to below as the negative read level. A read level offset to a higher voltage than a normal read level is referred to below as the positive read level. Furthermore, reading data using the standard read level is referred to below as standard reading. Reading data using the negative read level is referred to below as negative reading. Reading data using the positive read level is referred to below as positive reading.

[0099] After the “C4h” prefix command pCMD0 is sent, the page-specifying prefix command pCMD1 is sent from the memory controller 10 to the NAND memory 30. The “01h” prefix command pCMD1 is a command that specifies a lower page. The “02h” prefix command pCMD1 is a command that specifies a middle page. The “03h” prefix command pCMD1 is a command that specifies a higher page.

[0100] The command RCMD0, with the prefix "00h", is sent from the memory controller 10 to the NAND memory 30 after the prefix commands pCMD0 and pCMD1 have been sent. The command RCMD0, with the prefix "00h", is a command that notifies the NAND memory 30 to perform a read operation on the memory cell array 31.

[0101] The address ADD is sent from the memory controller 10 to the NAND memory 30 after the command RCMD0 is sent. The address ADD is represented, for example, by a data size of 5 cycles.

[0102] The command RCMD1, with the value "30h", is sent from the memory controller 10 to the NAND memory 30 after the address ADD is sent. The command RCMD1, with the value "30h", is a command that instructs the NAND memory 30 to start a read operation.

[0103] In response to the command RCMD1 of "00h", the ready / busy control circuit 34 changes the signal level of the ready / busy signal RBn from "H" level to "L" level.

[0104] The NAND memory 30 performs standard read, negative read, and positive read operations using the command set CS0, which includes the prefix command pCMD0. The NAND memory 30 corrects each read level by adding a shift value to the default value of each read level. The shift value includes a static shift value and a specified shift value.

[0105] Once the read operation in the NAND memory 30 is complete, the ready / busy control circuit 34 changes the signal level of the ready / busy signal RBn from "L" level to "H" level.

[0106] The memory controller 10 sends command set CS1 to the NAND memory 30 after sending command set CS0 in order to instruct the NAND memory 30 to output data to the memory controller 10. Command set CS1 is a set of signals that instructs the NAND memory 30 to output the data obtained by the read operation to the memory controller 10.

[0107] Command set CS1 includes the command RCMD2, address ADD, and command RCMD3.

[0108] After the signal level of the ready busy signal RBn changes from the "L" level to the "H" level, the command RCMD2, "05h", is sent from the memory controller 10 to the NAND memory 30. The command RCMD2, "05h", is a command that instructs the NAND memory 30 to output data to the memory controller 10.

[0109] After sending command RCMD4, address ADD is sent from memory controller 10 to NAND memory 30. Address ADD contains the same address value as address ADD included in command set CS0.

[0110] After sending the address ADD, the command RCMD3 with the value "E0h" is sent from the memory controller 10 to the NAND memory 30. The command RCMD3 with the value "E0h" is a command that instructs the NAND memory 30 to start outputting data to the memory controller 10.

[0111] In response to the command RCMD3 of “E0h”, the ready / busy control circuit 34 changes the signal level of the ready / busy signal RBn from “H” level to “L” level.

[0112] When the NAND memory 30 receives the command set CS1 for outputting read data, the data in a predetermined data latch DL that holds the data read at the standard read level is transferred to an external input / output data latch (XDL). The NAND memory 30 outputs the data DAT in the data latch (XDL) as read data RDT to the memory controller 10 from the input / output circuit 32.

[0113] In this way, the NAND memory 30 sends the read data RDT to the memory controller 10 according to the command set CS1.

[0114] As a result, the read data is sent to the memory controller 10.

[0115] In the memory system 1 of this embodiment, the NAND memory 30 calculates a dynamic shift value of the read level used for the read operation (standard read) in parallel with the transfer of read data RDT from the NAND memory 30 to the memory controller 10. This corrects the read level used for the read operation according to the command sets CS0 and CS1. That is, the read level for normal read operations after the automatic adjustment read operation is set using the calculated dynamic shift value.

[0116] Furthermore, the NAND memory 30 stores the calculated dynamic shift value in the dynamic shift value register of the setting information register 350. The calculated dynamic shift value may also be stored in a temporary code register or in a feature register used by the Set Feature command.

[0117] Furthermore, when the NAND memory 30 receives the prefix command "C4h", if the calculated dynamic shift value is stored in the dynamic shift value register, the dynamic shift value is added to the shift value to correct each read level.

[0118] Figure 5(b) shows the command sets CS0z and CS1 used when the automatic adjustment read operation is performed in the memory system 1 of this embodiment.

[0119] As shown in Figure 5(b), when performing an automatic read operation, the memory controller 10 sends a command set CS0z, which includes the prefix command pCMD2 “C5h”, to the NAND memory 30.

[0120] The memory controller 10 sends the prefix command pCMD2, “C5h”, to the NAND memory 30 as the first command in the command set CS0z. The prefix command pCMD2, “C5h”, is a command that instructs the NAND memory 30 to perform data read operations using the normal read level, the negative read level, and the positive read level. After this, the memory controller 10 sequentially sends the prefix command pCMD1, the command RCMD0, the address ADD, and the command RCMD1 to the NAND memory 30.

[0121] The NAND memory 30 performs standard read, negative read, and positive read operations using the command set CS0z, which includes the prefix command pCMD2. The NAND memory 30 sets each read level by adding a shift value to the default value for each read level. The shift value includes a static shift value and a specified shift value. In this case, even if the calculated dynamic shift value is stored in the register for dynamic shift values, the NAND memory 30 does not include the dynamic shift value in the shift value.

[0122] After the signal level of the ready busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends command set CS1 to the NAND memory 30 to instruct it to output data.

[0123] The NAND memory 30 sends read data RDT to the memory controller 10 according to the command set CS1.

[0124] If a command instructing a normal read operation is received after receiving the prefix command pCMD2 of “C5h”, the NAND memory 30 corrects the read level using the dynamic shift value adjusted by the prefix command pCMD2 of “C5h”. Note that the dynamic shift value adjusted by the prefix command pCMD2 of “C5h” is used only for the first command instructing a normal read operation received after the prefix command pCMD2 of “C5h”. For the second command instructing a normal read operation received after the prefix command pCMD2 of “C5h”, the dynamic shift value adjusted by the prefix command pCMD2 of “C5h” is not used, and instead the dynamic shift value stored in the dynamic shift value register is used. In other words, if a dynamic shift value adjusted by the prefix command pCMD0 of “C4h” exists before the prefix command pCMD2, the dynamic shift value adjusted by the prefix command pCMD0 of “C4h” will be used for read commands other than those immediately following the prefix command pCMD2 of “C5h”.

[0125] Furthermore, the NAND memory 30 stores the calculated dynamic shift value in the dynamic shift value register of the setting information register 350. The calculated dynamic shift value may also be stored in a temporary code register or in a feature register used by the Set Feature command.

[0126] As a result, the memory system 1 of this embodiment can perform read operations using a more appropriate read level.

[0127] Figure 5(c) shows the command sets CS0x and CS1 during normal read operations in the memory system 1 of this embodiment.

[0128] As shown in Figure 5(c), if the NAND memory 30 does not calculate a dynamic shift value of the read level internally during a read operation (i.e., a normal read operation is performed), the memory controller 10 sends a command set CS0x that does not include the prefix command pCMD0 of "C4h" to the NAND memory 30. As a result, the NAND memory 30 performs a read operation using only the standard read level according to the command set CS0x. The NAND memory 30 outputs the read data RDT to the memory controller 10 according to the command set CS1.

[0129] For example, in a normal read operation, if a dynamic shift value for the corresponding address ADD is stored in the setting information register 350, the read level is corrected using a shift value that includes the dynamic shift value calculated by the automatic adjustment read operation. The threshold voltage of the memory cell MC can be determined from the corrected read level.

[0130] As a result, the memory system 1 of this embodiment can perform read operations using a more appropriate read level.

[0131] Furthermore, if the dynamic shift value for the corresponding address ADD is not stored in the configuration information register 350, the NAND memory 30 sets the read level using a shift value that does not include the dynamic shift value and performs the read operation.

[0132] (a-3-2) Automatic adjustment readout operation Figure 6 is a schematic diagram illustrating the general process of reading data from the NAND memory 30 in the memory system 1 of this embodiment, according to the command set CS0 in Figure 5(a).

[0133] In Figure 6, two adjacent threshold voltage distributions, Sa and Sb, are extracted and shown from among multiple threshold voltage distributions corresponding to the data stored in the NAND memory 30.

[0134] In the NAND memory 30, during long-term data storage, data retention stress causes the threshold voltage distribution associated with the data in the memory cell array 31 to shift to the lower voltage side. In this embodiment, it is assumed that the threshold voltage distribution (and multiple read levels) of a given page shift in the same direction.

[0135] As described above, when reading data from the NAND memory 30, the memory system 1 of this embodiment performs, in response to the prefix command pCMD0, a standard read operation which reads data using a standard read level (read voltage) related to a certain threshold voltage distribution, a negative read operation which reads data using a read level slightly lower than the standard read level, and a positive read operation which reads data using a read level slightly higher than the standard read level.

[0136] Multiple negative read levels are set for each of the multiple standard read levels. Multiple positive read levels are also set for each of the multiple standard read levels. Hereinafter, these will be referred to as standard read level VXc, negative read level VXm, and positive read level VXp.

[0137] The difference between the negative read level and the standard read level (offset value: R_ViOstM) is set to approximately 20% of the voltage difference between adjacent standard read levels. For example, the difference between the negative read level and the standard read level is approximately 10 DAC. For example, with respect to the read levels VX(VXc, VXm, VXp) between threshold voltage distribution Sa and threshold voltage distribution Sb, there is a relationship between the negative read level VXm and the standard read level VXc shown by the following equation (FA).

[0138] VXm = VXc - 10DAC ···(FA)

[0139] The difference (offset value: R_ViOstP) between the standard readout level VXc and the positive readout level VXp is also set to approximately 10 DAC. For example, with respect to the readout level VX between threshold voltage distribution Sa and threshold voltage distribution Sb, there is a relationship between the positive readout level VXp and the standard readout level VXc shown by the following equation (FB).

[0140] VXp = VXc + 10DAC ···(FB)

[0141] "DAC" refers to a setting value (digital value) stored in a register within the NAND memory 30, used to set the voltage value (analog value) of the charge pump that generates the voltage applied to the word line WL, etc. For example, 1 DAC corresponds to 10 mV. However, the relationship between the DAC value and the analog voltage value varies depending on the specifications of the NAND memory 30. Depending on the specifications of the memory system, 1 DAC may correspond to 15 mV, etc.

[0142] For example, offset values ​​for each read level in negative and positive read levels are pre-set by a Set Feature command sequence (or by specifying a temporary code). The read level offset values ​​are managed in the table TBL of the memory controller 10 or in the register circuit 35 (or ROM area) of the NAND memory 30. This makes it possible to read data using a voltage value lower than or higher than the standard read level voltage value. A voltage value lower than the standard read level voltage value is equivalent to a negative read level. A voltage value higher than the standard read level voltage value is equivalent to a positive read level.

[0143] In this embodiment, data is read using a negative read level VXm and a positive read level VXp, which have voltage values ​​offset from the standard read level voltage. As a result, even if the threshold voltage of the memory cell MC shifts slightly due to stress applied to the NAND memory 30, the memory system 1 of this embodiment can reduce the number of error bits in the read data by adjusting (offsetting) the read level VX.

[0144] The standard read level VXc associated with the i-th threshold voltage distribution is denoted as the standard read level Vic. In the memory system 1 of this embodiment, when the NAND memory 30 reads data written in TLC mode, it sets the standard read level Vic associated with the i-th threshold voltage distribution based on the setting value of the register (R_ViSlfTr) of the setting information register 350 described above, as shown in the following equation (FC). Note that i is an integer between 1 and 7.

[0145] Vic = ViS + Vi_0 = R_Vit + R_ViSS + R_ViSlfTr + Vi_0 (FC)

[0146] Similarly, the negative read level Vim is set as shown in the following formula (FD).

[0147] Vim = Vic - R_ViOstM = (R_Vit + R_ViSS + R_ViSlfTr + Vi_0) - R_ViOstM ···(FD)

[0148] Furthermore, the positive read level Vip is set as shown in the following formula (FE).

[0149] Vip = Vic + R_ViOstP = (R_Vit + R_ViSS + R_ViSlfTr + Vi_0) + R_ViOstP ···(FE)

[0150] The data acquired by the NAND memory 30 using multiple standard read levels VXc is called standard read data Dc. Standard read data Dc is equivalent to one page of data and is read data RDT. The data obtained by determining the on / off state of the memory cell MC using one of the standard read levels VXc is called the determination result data Dic. In other words, the data read using the standard read level associated with the i-th threshold voltage distribution is represented as determination result data Dic. The data acquired by the NAND memory 30 using multiple negative read levels VXm is called negative read data Dm. Negative read data Dm is equivalent to one page of data. The data read using the negative read level associated with the i-th threshold voltage distribution is represented as determination result data Dim.

[0151] In the NAND memory 30, the error bit detection circuit 50 performs an exclusive OR operation (XOR operation) on the standard read data Dc and the negative read data Dm for each memory cell MC. That is, for a specific memory cell MC, it performs an XOR operation on the result of the judgment at the negative read level and the result of the judgment at the standard read level. Hereinafter, the data showing the result of the XOR operation between the standard read data Dc and the negative read data Dm is called the XOR operation data XDcm. The XOR operation data XDcm related to the i-th threshold voltage distribution, which will be described later, is represented as the XOR operation data XDicm.

[0152] The result of the XOR operation for each memory cell MC between the standard read data Dc and the negative read data Dm will be "0" if the values ​​read from the same memory cell MC for the two data Dc and Dm match, and "1" if the values ​​read from the same memory cell MC do not match.

[0153] The standard read data Dc and the negative read data Dm each represent one page of data (for example, approximately 18 kBytes of data). Therefore, the data representing the result of the XOR operation of the standard read data Dc and the negative read data Dm also represents one page of data.

[0154] The data acquired by the NAND memory 30 using multiple positive read levels VXp is called positive read data Dp. Positive read data Dp represents one page of data. The data read using the positive read level associated with the i-th threshold voltage distribution is represented as positive determination result data Dip.

[0155] In the NAND memory 30, the error bit detection circuit 50 performs an XOR operation on the standard read data Dc and the positive read data Dp for each memory cell MC. The data showing the result of the XOR operation between the standard read data Dc and the positive read data Dp is called the XOR operation data XDcp. The XOR operation data XDcp related to the i-th threshold voltage distribution, which will be described later, is represented as the XOR operation data XDicp.

[0156] The result of the XOR operation for each memory cell MC between the standard read data Dc and the positive read data Dp will be "0" if the values ​​read from the same memory cell MC for the two data Dc and Dp match, and "1" if the values ​​read from the same memory cell MC do not match.

[0157] The positive read data Dp represents one page of data. Therefore, the data showing the result of the XOR operation between the standard read data Dc and the positive read data Dp also represents one page of data.

[0158] The determination result data Dic, Dim, and Dip for each read level Vic, Vim, and Vip related to each threshold voltage are stored in the corresponding data latch among multiple data latches DL. Similarly, the data obtained from various calculations on the read data and determination result data are stored in the corresponding data latch among multiple data latches DL.

[0159] As described above, the data input / output unit (hereinafter referred to as the I / O unit) of the input / output circuit 32 is 8 bits.

[0160] The error bit detection circuit 50 compares the number of "1"s in each bit XOR_M0, XOR_M1, ..., XOR_M7 of the I / O unit data in the XOR operation data XDcm of standard read data Dc and negative read data Dm with the number of "1"s in each bit XOR_P0, XOR_P1, ..., XOR_P7 of the I / O unit data in the XOR operation data XDcp of standard read data Dc and positive read data Dp. In other words, the error bit detection circuit 50 compares the number of mismatches between the bits of standard read data Dc and the bits of negative read data Dm with the number of mismatches between the bits of standard read data Dc and the bits of positive read data Dp.

[0161] Furthermore, the number of times the value of each bit in the standard read data Dc changes from "0" to "1" or from "1" to "0" in each of the threshold voltage distributions S2, S4, and S6 during the reading of the middle page is between 0 and 1. Correspondingly, the value of the error bit detection result (XOR operation data) in the judgment result of each of the threshold voltage distributions S2, S4, and S6 changes from "0" to "1" only when a judgment is made based on the read level in which the value of the standard read data Dc has changed. In other words, if the value of a bit in the detection result changes from "0" to "1", it means that an error has occurred in one of the threshold voltage distributions S2, S4, or S6. Therefore, the number of times the value of the detection result changes from "0" to "1" is at most 1.

[0162] The error bit detection circuit 50 compares the XOR operation data XDcm related to the negative read data Dm with the XOR operation data XDcp related to the positive read data Dp.

[0163] For example, the error bit detection circuit 50 performs calculations using each bit XOR_M0,...,XOR_M7,XOR_P0,...,XOR_P7 of the I / O unit data in the XOR operation data XDcm and XOR operation data XDcp. For example, the error bit detection circuit 50 calculates the difference Delta_M-P between the bits XOR_M0,...,XOR_M7 of the I / O unit data in the XOR operation data XDcm relating to the negative read data Dm and the bits XOR_P0,...,XOR_P7 of the I / O unit data in the XOR operation data XDcp relating to the positive read data Dp, as shown in the following equation (FF).

[0164] Delta_M-P =( XOR_M0 + XOR_M1 + … + XOR_M7 ) - (XOR_P0 + XOR_P1 + … + XOR_P7 ) ···(FF)

[0165] Based on the sign (or sign and magnitude) of the difference Delta_M-P obtained by the error bit detection circuit 50, the correction amount calculation circuit 52 calculates the dynamic shift value of the readout level.

[0166] For example, if the difference Delta_M-P is greater than 0 (Delta_M-P>0), it indicates that there is a greater mismatch between negative read data Dm and standard read data Dc than between positive read data Dp and standard read data Dc. Therefore, when Delta_M-P>0, the correction amount calculation circuit 52 calculates a dynamic shift value so that the read level is shifted to the positive side (high voltage side). The NAND memory 30 adds the calculated dynamic shift value to the shift value and sets the read level.

[0167] For example, if the difference Delta_M-P is less than 0 (Delta_M-P < 0), it indicates that there is more data mismatch between positive read data Dp and standard read data Dc than between negative read data Dm and standard read data Dc. Therefore, when Delta_M-P < 0, the correction amount calculation circuit 52 calculates a dynamic shift value so that the read level is shifted to the negative side (low voltage side). The NAND memory 30 adds the calculated dynamic shift value to the shift value and sets the read level.

[0168] As a result, the memory system 1 of this embodiment can reduce, on average, the number of error bits in the read data obtained by a read operation performed after read level correction compared to before correction.

[0169] For example, when the intersection of two threshold voltage distributions Sa and Sb is set as the read level, the error in the read data is minimized. In the example in Figure 6, the intersection of the two threshold voltage distributions Sa and Sb is located on the higher voltage side than the currently set standard read level VXc. Therefore, it is desirable for the standard read level VXc to be shifted to a higher voltage side than the current standard read level in order to reduce the number of error bits. In this example, when comparing the calculated XOR operation data XDcm and XOR operation data XDcp, the XOR operation data XDcp has fewer "1"s. That is, the difference Delta_M-P is greater than zero. As a result, the NAND memory 30 sets a dynamic shift value so that the standard read level VXc with respect to the threshold voltage distributions Sa and Sb is shifted to a higher voltage side than the current standard read level.

[0170] In threshold voltage distributions other than those Sa and Sb, if the number of discrepancies at negative readout levels tends to be greater than the number of discrepancies at positive readout levels, the difference Delta_M-P for each threshold voltage distribution will be greater than zero. In this case as well, the dynamic shift value should be set so that the readout level of each threshold voltage distribution is shifted to a higher voltage side than the standard readout level.

[0171] The NAND memory 30 stores the set dynamic shift value in the dynamic shift value register of the setting information register 350. Alternatively, the calculated dynamic shift value may be stored in a temporary code register or in a feature register used by the Set Feature command.

[0172] Furthermore, if multiple reading levels are used to read the selected page, it is preferable, as described below, to use the number of "1"s (number of mismatches) in the data accumulated by the OR operation, which is the result of the XOR operation for each reading level, in the final calculation of the dynamic shift value in order to improve the efficiency of the dynamic shift value calculation.

[0173] For example, a data latch DL (e.g., a data latch GDL) stores data that has been accumulated by performing a logical OR operation on the XOR operation of standard read data Dc and negative read data Dm for each read level (threshold voltage distribution). In other words, a data latch DL stores data obtained by performing an OR operation on the XOR operation of standard read data Dc and negative read data Dm for each read level, and then performing an OR operation on this data for multiple read levels. This data is a bitmap data that indicates whether or not there is a mismatch between the standard read data Dc and negative read data Dm in each threshold voltage distribution.

[0174] Similarly, another data latch DL (e.g., a data latch HDL) stores data that is accumulated by an OR operation, where the standard read data Dc and the positive read data Dp are XORed for each read level. This data is a bitmap indicating whether or not there is a mismatch between the standard read data Dc and the positive read data Dp at each threshold voltage distribution.

[0175] Then, the number of "1"s in the accumulated data in one data latch is compared with the number of "1"s in the accumulated data in another data latch. Based on this comparison, a dynamic shift value is set so that the standard read level is shifted in the direction corresponding to the data with fewer "1"s. In this way, the NAND memory 30 adjusts the read level so that the number of error bits in subsequent read operations is reduced.

[0176] As described above, the memory system 1 of this embodiment can improve the reliability of reading data from the NAND memory 30.

[0177] (b) Example of operation An example of the operation of the memory system 1 of this embodiment will be described with reference to Figures 7 to 20. The example of the operation of the memory system 1 of this embodiment concerns the control method for reading data from the memory system 1 of this embodiment and the control method for reading data from the memory device (NAND memory) 30.

[0178] Figure 7 is a flowchart illustrating an example of the operation of the memory system 1 of this embodiment. Figures 8 to 18 are schematic diagrams illustrating an example of the operation of the memory system 1 of this embodiment.

[0179] (b-1) <sp10> As shown in Figure 7, in the memory system 1 of this embodiment, the memory controller 10 commands the NAND flash memory 30 to perform an automatic adjustment read operation. The memory controller 10 sends the command set CS0 shown in Figure 5(a) to the NAND memory 30.

[0180] (b-2) <sp20> NAND memory 30 receives the prefix command pCMD0, prefix command pCMD1, command (00h)RCMD0, address ADD for 5 cycles, and command (30h)RCMD1, all with the prefix "C4h".

[0181] This causes the NAND memory 30 to start an automatic read adjustment operation. The NAND memory 30 reads various setting information for the read operation from the register circuit 35. Based on the setting information, the NAND memory 30 sets the voltage values ​​of multiple read levels used for the automatic read adjustment operation.

[0182] The following describes the case where a middle page is ordered to be read using the prefix command pCMD1, which has the prefix "02h".

[0183] (b-3) <sp21> In the NAND memory 30, the sequencer 36 performs a read operation on the area indicated by address ADD in the memory cell array 31 based on the received command set.

[0184] The NAND memory 30 determines the threshold voltage of the memory cell MC using a standard read level and an offset read level for each of the one or more read levels for the selected page.

[0185] For example, the automatic adjustment read operation (and normal read operation) determines the state of the threshold voltage of the memory cell MC for each read level, starting from the lowest threshold voltage (lowest state). Data indicating the determination result for each read level (hereinafter referred to as determination result data) is sequentially stored in the data latch DL. Various arithmetic operations are performed using the data in the data latch DL. Internal processing of the NAND memory 30 performs data transfer between data latch DLs and data storage within the data latch DLs.

[0186] When a normal read operation of a middle page (a read operation in which a dynamic shift value is not calculated) is performed, the on and off states of multiple memory cells MC included in the selected address (selected word line WL) are determined using standard read levels V2 (V2c), V4 (V4c), and V6 (V6c). The determination result data for each read level V2, V4, and V6 are stored in the corresponding data latch DL in the data latch circuit 40.

[0187] During the automatic read adjustment operation, the NAND memory 30, according to the settings of the memory system 1, determines the threshold voltage of the memory cell using a standard read level and an offset read level (negative read level and positive read level) at multiple read levels corresponding to the selected page.

[0188] For example, each readout level is set as follows, based on the setting value of the setting information in the register circuit 35.

[0189] The default value for the standard readout level V2c with respect to the threshold voltage distribution S2 in standard readout is denoted as "V2_0". The shift value is denoted as "V2S", with the specified shift value being "R_V2SS", the static shift value being "R_V2t", and the dynamic shift value being "R_V2d". The shift value V2S is obtained by adding the specified shift value "R_V2SS", the static shift value "R_V2t", and the dynamic shift value "R_V2d". The standard readout level V2c is set by adding the shift value to the default value "V2_0".

[0190] In the automatic read adjustment operation, standard reads are performed multiple times for each state. The standard read level of the first standard read is denoted as "V2c_1", and the standard read level of the Nth standard read is denoted as "V2c_N". The dynamic shift value of the first standard read is denoted as "V2d_1", and the dynamic shift value of the Nth standard read is denoted as "V2d_N", where N is an integer greater than or equal to 1. In this embodiment, the shift value of the read level in the jth automatic read adjustment operation is denoted as "V2S_j", where j is an integer greater than or equal to 1.

[0191] The shift value V2S, static shift value V2t, and dynamic shift value V2d have the following relationship:

[0192] V2S_j = V2t + V2d_j

[0193] The standard read level V2c and shift value V2S of a standard read operation have the following relationship. For convenience, the default shift value "V2S_0" is assumed to be 0 (zero) here.

[0194] V2S_0 = 0 V2c_0 = V2_0 V2c_j = V2c_(j-1) + V2S_(j-1) = ( V2_0 + V2S_0 ) + ΣV2S_k

[0195] Here, "ΣV2S_k" is the sum of the shift values ​​"V2S_0", "V2S_1", ... "V2S_(j-1)". Hereafter, ΣV2S_k will be referred to as the cumulative shift value.

[0196] For example, consider memory system 1 that has completed two auto-adjusted read operations. The standard read level for the second standard read operation is set by adding the shift value of the read level obtained in the first auto-adjusted read operation to the standard read level of the first standard read operation. In other words, the standard read level for the second standard read operation is set by adding the default value of the standard read level and the default shift value, plus the cumulative shift value up to the second operation.

[0197] The default value for the negative readout level V2m with respect to the threshold voltage distribution S2 in negative readout is denoted as "V2m_0".

[0198] In the automatic adjustment read operation, negative reads are performed multiple times for each state. The negative read level in the first negative read is denoted as "V2m_1", ​​and the negative read level in the Nth negative read is denoted as "V2m_N".

[0199] The negative readout level V2m and offset value have the following relationship with respect to the threshold voltage distribution S2 in negative readout.

[0200] V2m_j = V2m_(j-1) + V2S_(j-1) = (V2c_(j-1) - 10DAC) + V2S_(j-1) = { (V2_0 + V2S ) + ΣV2S_k} - 10DAC = V2c_j - 10DAC

[0201] For example, consider memory system 1 that has completed two automatic read adjustment operations. The negative read level of the second negative read operation is set by adding the shift value of the read level obtained in the first automatic read adjustment operation to the negative read level of the first negative read operation. In other words, the negative read level of the second negative read operation is set by subtracting the offset value of 10DAC from the value of the standard read level of the second operation.

[0202] The default value of the positive readout level V2p for the threshold voltage distribution S2 in positive readout is denoted as "V2p_0".

[0203] In the automatic adjustment read operation, positive reads are performed multiple times for each state. The positive read level in the first positive read is denoted as "V2p_1", and the positive read level in the Nth positive read is denoted as "V2p_N".

[0204] The positive readout level V2p and offset value have the following relationship with respect to the threshold voltage distribution S2 in positive readout.

[0205] V2c_j = V2p_(j-1) + V2S_(j-1) = ( V2c_(j-1) +10DAC) + V2S_(j-1) = { ( V2_0 + V2S ) +ΣV2S_k} + 10DAC = V2c_j + 10DAC

[0206] For example, consider memory system 1 that has completed two automatic read adjustment operations. The value obtained by adding the shift value of the read level obtained in the first automatic read adjustment operation to the positive read level of the first positive read operation is set as the positive read level for the second positive read operation. In other words, the value obtained by adding the offset value of 10DAC to the value of the second standard read level is set as the positive read level for the second positive read operation.

[0207] Similar to the voltage values ​​of each readout level V2c, V2m, and V2p for threshold voltage distribution S2, the voltage values ​​of the readout levels are set for threshold voltage distributions S4 and S6, respectively.

[0208] The default value of the standard readout level V4c for the threshold voltage distribution S4 in standard readout is denoted as "V4_0", and the shift value is denoted as "V4S". The standard readout level for the first standard readout in automatic adjustment readout operation is denoted as "V4c_1".

[0209] The standard readout level V4c and shift value for the threshold voltage distribution S4 in standard readout have the following relationship:

[0210] V4c_j = V4c_(j-1) + V4S + V4S_(j-1) = ( V4_0 + V4S ) + ΣV4S_k

[0211] Here, "ΣV4S_k" is the sum of the shift values ​​"V4S_0", "V4S_1", ... "V4S_(j-1)".

[0212] The negative readout level V4m and offset value for the threshold voltage distribution S4 in negative readout have the following relationship:

[0213] V4m_j = V4c_j - 10DAC

[0214] The positive readout level V4p and offset value have the following relationship with respect to the threshold voltage distribution S4 in positive readout.

[0215] V4p_j = V4c_j + 10DAC

[0216] In standard readout, the default value of the standard readout level V6c for the threshold voltage distribution S6 is denoted as "V6_0", and the shift value is denoted as "V6S". In automatic adjustment readout operation, the standard readout level for the first standard readout is denoted as "V6c_1".

[0217] The standard readout level and shift value for the threshold voltage distribution S6 in normal readout operation have the following relationship.

[0218] V6c_j = V6c_(j-1) + V6S + V6S_(j-1) = ( V6_0 + V6S ) + ΣV6S_k

[0219] Here, "ΣV6S_k" is the sum of the shift values ​​"V6S_0", "V6S_1", ... "V6S_(j-1)".

[0220] The negative readout level V6m and offset value have the following relationship with respect to the threshold voltage distribution S6 in negative readout.

[0221] V6m_j = V6c_j - 10DAC

[0222] The positive readout level V6p and offset value have the following relationship with respect to the threshold voltage distribution S6 in positive readout.

[0223] V6p_j = V6c_j + 10DAC

[0224] For each threshold voltage distribution S2, S4, and S6 in the middle page, the readout level is set using the above formula (calculation process). Standard readout, negative readout, and positive readout are then performed using the set readout level.

[0225] (b-3-1) <Decision processing regarding threshold voltage distribution S2> In this embodiment, the determination of the magnitude of the threshold voltage is performed starting with the determination using the lowest read level. When reading the middle page, in order to determine the state of the threshold voltage distribution S2, the threshold voltage of the memory cell MC with respect to the threshold voltage distribution S2 is determined in the order of negative read level V2m, standard read level V2c, and positive read level V2p.

[0226] Each readout level V2m, V2c, and V2p is sequentially applied to the selected word line WL. Voltage VREAD is applied to the unselected word line WL. The bit line BL is charged.

[0227] Of the two adjacent states, the memory cell MC to the left (lower potential side) from the read level is determined to be "0", and the memory cell MC to the right (higher potential side) is determined to be "1". By applying the selected word line at read level V2 (V2c, V2m, V2p), it is determined whether the threshold voltage of the memory cell MC is equal to or greater than read level V2, or less than read level V2.

[0228] As shown in Figure 8, the judgment result data D2m for the negative read level V2m is stored in the data latch EDL. The judgment result data D2c for the standard read level V2c is stored in the data latch ADL. The judgment result data D2p for the positive read level V2p is stored in the data latch FDL.

[0229] Here, the data latch DL, which stores the judgment result data Dic for the standard readout level Vic, will not be overwritten with other data until the automatic adjustment readout operation is complete. In other words, the data latch ADL stores the judgment result data D2c until the automatic adjustment readout operation is complete.

[0230] As shown in Figure 9, the error bit detection circuit 50 performs an XOR operation for each memory cell MC with respect to the determination result data D2m in the data latch EDL and the determination result data D2c in the data latch ADL. The data XD2cm, which represents the result of the XOR operation between the determination result data D2c at the standard read level V2c and the determination result data D2m at the negative read level V2m (hereinafter referred to as the XOR operation data), is stored in the data latch GDL.

[0231] The XOR calculation data XD2cm is used to verify the agreement or disagreement between the threshold voltage determination result of the memory cell MC using the standard read level V2c and the threshold voltage determination result of the memory cell MC using the negative read level V2m. The XOR calculation data XD2cm will also be referred to as verification data below.

[0232] Here, if the values ​​read from the same memory cell MC match between the determination result data D2c of data latch ADL and the determination result data D2m of data latch EDL, the value of the XOR calculation data XD2cm of data latch GDL is "0". On the other hand, if the values ​​read from the same memory cell MC do not match between the determination result data D2c of data latch ADL and the determination result data D2m of data latch EDL, the value of the XOR calculation data XD2cm of data latch GDL is "1".

[0233] If all the bit values ​​of the judgment result data D2c of data latch ADL and the judgment result data D2m of data latch EDL match, then the value of the XOR operation data XDcm in data latch GDL will be all zero ("all 0").

[0234] As shown in Figure 10, the error bit detection circuit 50 performs an XOR operation on the determination result data D2p in the data latch FDL and the determination result data D2c in the data latch ADL for each corresponding memory cell. The XOR operation data XD2cp, which shows the result of the XOR operation between the determination result data D2c at the standard read level V2c and the determination result data D2p at the positive read level V2p, is stored in the data latch HDL.

[0235] The XOR calculation data XD2cp is used to verify the agreement and disagreement between the determination result of the threshold voltage of the memory cell MC using the standard read level V2c and the determination result of the threshold voltage of the memory cell MC using the positive read level V2p.

[0236] Here, if the values ​​read from the same memory cell MC match between the judgment result data D2c of data latch ADL and the judgment result data D2p of data latch FDL, the value of the XOR calculation data XD2cp of data latch HDL is "0". On the other hand, if the values ​​read from the same memory cell MC do not match between the judgment result data D2c of data latch ADL and the judgment result data D2p of data latch FDL, the value of the XOR calculation data XD2cp of data latch HDL is "1".

[0237] For example, if all the bit values ​​of the judgment result data D2c of data latch ADL and the judgment result data D2p of data latch FDL match, the value of the XOR operation data XDcp in data latch HDL will be all zero ("all 0").

[0238] The judgment result data D2c of the data latch ADL is transferred to, for example, the data latch DDL.

[0239] (b-3-2) <Decision processing regarding threshold voltage distribution S4> As shown in Figure 11, after determining the threshold voltage of the memory cell MC based on the read level V2 (V2c, V2m, V2p), the threshold voltage of the memory cell MC is determined based on the threshold voltage distribution S4. The threshold voltage of the memory cell MC is determined based on the threshold voltage distribution S4 in the following order: negative read level V4m, standard read level V4c, and positive read level V4p.

[0240] Each read level V4m, V4c, and V4p is sequentially applied to the selected word line WL. Voltage VREAD is applied to the unselected word line WL. The bit line BL is charged.

[0241] By applying read levels V4 (V4c, V4m, V4p), it is determined whether the threshold voltage of the memory cell MC is greater than or equal to the threshold voltage distribution S4, or less than the threshold voltage distribution S4.

[0242] The result data D4m for a negative read level V4m (e.g., negative read level V4m_1) is stored in the data latch EDL. The result data D4c for a standard read level V4c (e.g., read level V4c_1) is stored in the data latch BDL. The result data D4p for a positive read level V4p (e.g., positive read level V4p_1) is stored in the data latch FDL.

[0243] Thus, the data latch EDL stores the judgment result data Dim using a negative read level. The data latch FDL stores the judgment result Dip using a positive read level. The data in data latches EDL and FDL is rewritten each time the threshold voltage of the memory cell MC for each threshold voltage distribution is determined.

[0244] As shown in Figure 12, the error bit detection circuit 50 performs an XOR operation on each memory cell MC with respect to the determination result data D4m in the data latch EDL and the determination result data D4c in the data latch BDL. This generates XOR operation data XD4cm, which shows the result of the XOR operation between the determination result data D4c at read level V4c and the determination result data D4m at read V4m.

[0245] The error bit detection circuit 50 performs a logical OR operation between the XOR operation data XD4cm and the XOR operation data XD2cm in the data latch GDL. This generates the operation data OD4cm (hereinafter referred to as OR operation data) which indicates the result of the OR operation.

[0246] The OR operation data OD4cm is stored in the data latch GDL. The XOR operation data XD2cm that was stored in the data latch GDL is overwritten with the OR operation data OD4cm. In this way, the data in the data latch GDL is overwritten by the logical OR operation data ODicm of XOR operation data XDicm with different threshold voltages.

[0247] The OR operation data OD4cm is data (hereinafter also referred to as verification data) used to verify the cumulative number of matches / mismatches between the threshold voltage determination results of the memory cell MC using standard read levels V2c and V4c and the threshold voltage determination results of the memory cell MC using negative read levels V2m and V4m.

[0248] With respect to the OR calculation data OD4cm based on the determination results of threshold voltage distribution S2 and threshold voltage distribution S4, if the determination result at negative read level V2m is equal to the determination result at standard read level V2c, and the determination result at negative read level V4m is equal to the determination result at standard read level V4c, the value of the OR calculation data OD4cm in the data latch GDL will be "0". On the other hand, if the determination result at negative read level V2m is different from the determination result at standard read level V2c, or if the determination result at negative read level V4m is different from the determination result at standard read level V4c, the value of the OR calculation data OD4cm in the data latch GDL will be "1".

[0249] As shown in Figure 13, the error bit detection circuit 50 performs an XOR operation for each corresponding memory cell MC with respect to the determination result data D4p in the data latch FDL and the determination result data D4c in the data latch BDL. This generates XOR operation data XD4cp, which shows the result of the XOR operation between the determination result data D4c at the standard read level V4c and the determination result data D4p at the positive read level V4p.

[0250] The error bit detection circuit 50 performs an OR operation between the XOR operation data XD4cp and the XOR operation data XD2cp in the data latch HDL. This generates OR operation data OD4cp, which indicates the result of the OR operation.

[0251] The OR operation data OD4cp is stored in the data latch HDL. The data in the data latch HDL is overwritten by the OR operation data OD4cp.

[0252] The OR operation data OD4cp is used to verify the cumulative number of matches / mismatches between the threshold voltage determination results of the memory cell MC using standard read levels V2c and V4c and the threshold voltage determination results of the memory cell MC using positive read levels V2p and V4p.

[0253] With respect to the OR operation data OD4cp based on the determination results of threshold voltage distribution S2 and threshold voltage distribution S4, if the determination result at positive read level V2p is equal to the determination result at standard read level V2c, and the determination result at positive read level V4p is equal to the determination result at standard read level V4c, the value of the OR operation data OD4cp in the data latch HDL becomes "0". On the other hand, if the determination result at positive read level V2p is different from the determination result at standard read level V2c, or if the determination result at positive read level V4p is different from the determination result at standard read level V4c, the value of the OR operation data OD4cp in the data latch HDL becomes "1".

[0254] As shown in Figure 14, an XOR operation is performed between the determination result data D4c of the data latch BDL and the determination result data D2c of the data latch ADL. The XOR operation data XD4c, which shows the result of the XOR operation, is stored in the data latch DDL.

[0255] Alternatively, instead of the determination result data D2c in the data latch ADL, XOR operation data XD4c may be generated by performing an XOR operation between the determination result data D2c in the data latch DDL before rewriting and the determination result data D4c in the data latch BDL.

[0256] (b-3-3)<Decision processing regarding threshold voltage distribution S6> As shown in Figure 15, after the determination based on the read level V4 (V4c, V4m, V4p), the threshold voltage of the memory cell MC with respect to the threshold voltage distribution S6 is determined. The threshold voltage of the memory cell MC with respect to the threshold voltage distribution S4 is determined in the following order: negative read level V6m, standard read level V6c, and positive read level V6p.

[0257] Each read level V6m, V6c, and V6p is sequentially applied to the selected word line WL. Voltage VREAD is applied to the unselected word line WL. The bit line BL is charged.

[0258] By applying each read level V6 (V6c, V6m, V6p), it is determined whether the threshold voltage of the memory cell MC is equal to or greater than the threshold voltage distribution S6, or less than the threshold voltage distribution S6.

[0259] The determination result data D6m of the negative read level V6m (for example, read level V6m_1) is stored in the data latch EDL. The determination result data D6c of the standard read level V6c (for example, read level V6m_1) is stored in the data latch CDL. The determination result data D6p of the positive read level V6p (for example, read level V6p_1) is stored in the data latch FDL.

[0260] Thus, the data in the data latches EDL and FDL is rewritten from the determination result of the threshold voltage of the memory cell MC with the threshold voltage distribution S4 to the determination result of the memory cell MC with the threshold voltage distribution S6.

[0261] As shown in FIG. 16, the error bit detection circuit 50 performs an XOR operation on the determination result data D6m in the data latch EDL and the determination result data D6c in the data latch CDL for each corresponding memory cell MC. Thereby, XOR operation data XD6cm indicating the result of the XOR operation between the determination result data D6c of the standard read level V6c and the determination result data D6m of the negative read V6m is generated.

[0262] The error bit detection circuit 50 performs an OR operation on the generated XOR operation data XD6cm and the OR operation data OD4cm in the data latch GDL. Thereby, OR operation data OD6cm is generated.

[0263] The OR operation data OD6cm is stored in the data latch GDL. Thereby, the OR operation data OD4cm stored in the data latch GDL is rewritten to the OR operation data OD6cm.

[0264] The OR operation data OD6cm is used to verify the cumulative number of matches / mismatches between the threshold voltage determination results of the memory cell MC using standard read levels V2c, V4c, and V6c and the threshold voltage determination results of the memory cell MC using negative read levels V2m, V4m, and V6m.

[0265] With respect to the OR calculation data OD6cm based on the determination results of threshold voltage distributions S2, S4, and S6, if the determination result at negative read level V2m is equal to the determination result at standard read level V2c, the determination result at negative read level V4m is equal to the determination result at standard read level V4c, and the determination result at negative read level V6m is equal to the determination result at standard read level V6c, then the value of the OR calculation data OD6cm in the data latch GDL is "0". On the other hand, if the determination result at negative read level V2m is different from the determination result at standard read level V2c, or the determination result at negative read level V4m is different from the determination result at standard read level V4c, or the determination result at negative read level V6m is different from the determination result at standard read level V6c, then the value of the OR calculation data OD6cm in the data latch GDL is "1".

[0266] As shown in Figure 17, the error bit detection circuit 50 performs an XOR operation for each corresponding memory cell MC with respect to the determination result data D6p in the data latch FDL and the determination result data D6c in the data latch CDL. This generates XOR operation data XD6cp, which shows the result of the XOR operation between the determination result data D6c for standard read level V6c and the determination result data D6p for positive read V6p.

[0267] The error bit detection circuit 50 performs an OR operation between the generated XOR operation data XD6cp and the OR operation data OD4cp in the data latch HDL. This generates the OR operation data OD6cp.

[0268] The OR operation data OD6cp is stored in the data latch HDL. The OR operation data OD4cp that was stored in the data latch HDL is overwritten with the OR operation data OD6cp.

[0269] The OR operation data OD6cp is data that shows the cumulative number of matches / mismatches between the threshold voltage determination results of the memory cell MC using standard read levels V2c, V4c, and V6c and the threshold voltage determination results of the memory cell MC using positive read levels V2p, V4p, and V6p.

[0270] With respect to the OR operation data OD6cp based on the determination results of threshold voltage distributions S2, S4, and S6, if the determination result at positive read level V2p is equal to the determination result at standard read level V2c, the determination result at positive read level V4p is equal to the determination result at standard read level V4c, and the determination result at positive read level V6p is equal to the determination result at standard read level V6c, then the value of the OR operation data OD6cp in the data latch HDL becomes "0". On the other hand, if the determination result at positive read level V2p is different from the determination result at standard read level V2c, or the determination result at positive read level V4p is different from the determination result at standard read level V4c, or the determination result at positive read level V6p is different from the determination result at standard read level V6c, then the value of the OR operation data OD6cp in the data latch HDL becomes "1".

[0271] In this way, based on the determination results of the threshold voltage of the memory cell MC using the standard read level and the offset read level, agreement and disagreement of the determination results at each read level are detected.

[0272] (b-4) <sp22> The NAND memory 30 generates read data based on the determination results for each read level related to the selected page.

[0273] As shown in Figure 18, an XOR operation is performed between the determination result data D6c of data latch CDL, the determination result data D4c of data latch BDL, and the determination result data D2c of data latch ADL. The XOR operation data XD6c, which shows the result of the XOR operation, is stored in data latch DDL.

[0274] Furthermore, before writing data XD6c, the data latch DDL stores XOR operation data XD4c, which is the result of the determination data D2c for read level V2c and the result of the determination data D4c for read level V4c. Therefore, instead of the data D2c and D4c of the data latches ADL and BDL, data XD6c may be generated by performing an XOR operation between the data XD4c of the data latch DDL and the data D6c of the data latch CDL.

[0275] The data latch ADL, BDL, and CDL determination result data D2c, D4c, and D6c are determination result data for the three standard read levels V2c, V4c, and V6c of the mid-page.

[0276] Therefore, the standard read data Dc is generated by the XOR operation of the determination result data D2c, D4c, and D6c of the data latches ADL, BDL, and CDL. In other words, the intermediate page read data RDT is generated by the XOR operation of the determination result data D2c, D4c, and D6c of the standard read levels V2c, V4c, and V6c.

[0277] In this way, the read data RDT is acquired by the automatic adjustment read operation of the memory system 1 of this embodiment.

[0278] Furthermore, after the generation of the read data RDT, the following information (data) is stored in each data latch ADL, BDL, ..., GDL.

[0279] The data latch ADL stores the determination result data D2c at the read level V2c for generating the read data RDT of the middle page.

[0280] The data latch BDL stores the determination result data D4c at the read level V4c for generating the read data RDT of the middle page.

[0281] The data latch CDL stores the determination result data D6c at the read level V6c for generating the read data RDT of the middle page.

[0282] The data latch DDL stores the read data RDT of the middle page.

[0283] The data latch EDL stores the determination result data (temporary data) D6m at the negative read level V6m. Here, the temporary data is data that may be rewritten to other data before the automatic adjustment read operation ends.

[0284] The data latch FDL stores the determination result data (temporary data) D6p at the positive read level V6p.

[0285] The data latch GDL stores the data OD6cm for verifying the match / mismatch between the read data Dc at the standard read level Vc and the read data Dm at the negative read level Vm.

[0286] The data latch HDL stores the data OD6cp for verifying the match / mismatch between the read data Dc at the standard read level Vc and the read data Dp at the positive read level Vp.

[0287] The data OD6cm in the data latch GDL is the data obtained by performing an XOR operation for each memory cell MC between the determination result data D2c, D4c, D6c based on the standard read levels V2c, V4c, V6c and the determination result data D2m, D4m, D6m based on the minus read levels V2m, V4m, V6m, and is the data accumulated by performing an OR operation for each memory cell MC. That is, the data OD6cm in the data latch GDL is data indicating whether the read data at the standard read level and the read data at the minus read level match in the determination results at all read levels, or whether there is a determination result at a read level where they do not match.

[0288] The data OD6cp in the data latch HDL is the data obtained by performing an XOR operation for each memory cell MC between the determination result data D2c, D4c, D6c based on the standard read levels V2c, V4c, V6c and the determination result data D2p, D4p, D6p based on the plus read levels V2p, V4p, V6p, and is the data accumulated by performing an OR operation for each memory cell MC. That is, the data OD6cp in the data latch HDL is data indicating whether the read data at the standard read level and the read data at the plus read level match in the determination results at all read levels, or whether there is even one determination result at a read level where they do not match.

[0289] (b-5)<Sp11,Sp23 and Sp12> [[ID=?]]The memory controller 10 commands the NAND memory 30 to output the read data RDT by means of the command set CS1.

[0290] The error bit detection circuit 50 checks whether the read level is an appropriate value (for example, an optimum value) based on the data in the data latch DL.

[0291] FIG. 19 is a schematic diagram for explaining the process for checking the appropriateness of the read level by the error bit detection circuit 50 in the memory system of the present embodiment.

[0292] Note: There seems to be an error in ID=10 where the original text has some Japanese characters which might be incorrect. I've translated it as best as possible assuming it's a misprint and tried to make sense of the context. Also, the "?" in ID=? is because the original text might be incomplete or incorrect in that part. For example, as shown in Figure 19, the error bit detection circuit 50 counts the number of "1"s in the data OD6cm of the data latch GDL and the number of "1"s in the data OD6cp of the data latch HDL. That is, the error bit detection circuit 50 counts the number of mismatched bits between the standard read-level determination result data and the negative read-level determination result data, and the number of mismatched bits between the standard read-level determination result data and the positive read-level determination result data.

[0293] For example, the error bit detection circuit 50 counts the number of mismatched bits in parallel with the output of the read data RDT from the input / output circuit 32 to the memory controller 10.

[0294] As explained using Figure 5(a), the NAND memory 30 outputs read data RDT in 8-bit increments at predetermined timings, starting with the specified address ADD, to the memory controller 10 via the input / output circuit 32, in response to the output commands of the command set CS1 (commands "05h" and "E0h").

[0295] The memory controller 10 receives the read data.

[0296] In this embodiment, the NAND memory 30 independently counts the number of "1" bits in the OR operation data (verification data) OD6cm in the data latch GDL and the OR operation data (verification data) OD6cp in the data latch HDL for each output cycle of the read data RDT.

[0297] Here, the data for which the number of mismatched bits ("1") is counted corresponds to data consisting of an 8-bit signal DQ[7:0] with a data size in I / O units that is output simultaneously.

[0298] However, if high-speed data output makes it difficult to count 8 bits of data at once, the calculation corresponding to signal DQ[7:0] may be performed bit by bit by accumulating the 8 bits of data OD6cm from data latch GDL and the 8 bits of data OD6cp from data latch HDL in parallel.

[0299] Once the output of the read data RDT is complete, the number of "1"s in the OR operation data OD6cm of the data latch GDL and the OR operation data OD6cp of the data latch HDL, corresponding to the output data length (data amount), is determined.

[0300] If the shape of the threshold voltage distribution for each state corresponding to the data in the NAND memory 30 is considered symmetrical, the NAND memory 30 uses the error bit detection circuit 50 to compare the number of "1"s in the verification data OD6cm and OD6cp in the data latch GDL for each bit of the verification data OD6cm and OD6cp corresponding to the data range output from the input / output circuit 32 of the NAND memory 30.

[0301] The NAND memory 30 uses a correction amount calculation circuit 52 to calculate a dynamic shift value based on the measurement results of the verification data OD6cm and OD6cp, such that the read level is shifted to the side of the read level corresponding to the verification data with fewer "1"s in the verification data OD6cm and OD6cp. The read level voltage value is set according to the calculated dynamic shift value. In other words, the NAND memory 30 sets the read level voltage value so that the read level is shifted to the side of the read level corresponding to the verification data with a greater match to the standard read data.

[0302] As a result, the memory system 1 of this embodiment can reduce the number of error bits included in the read data obtained by a read operation performed after read level correction.

[0303] The correction amount calculation circuit 52 calculates a dynamic shift value of the readout level (standard readout level) based on the number of "1"s in the verification data OD6cm and the number of "1"s in the verification data OD6cp within the data latch HDL, in order to correct the voltage value of the readout level.

[0304] For example, the calculation of the dynamic shift value of the read level is performed as follows:

[0305] The comparison between the number of "1"s in the validation data OD6cm within the data latch GDL (hereinafter referred to as "g") and the number of "1"s in the validation data OD6cp within the data latch HDL (hereinafter referred to as "h"), as well as the calculation of the dynamic shift value of the readout level, is performed by obtaining the difference or the ratio.

[0306] In the following, the value indicated by "Delta" corresponds to the comparison result value and the dynamic shift value of the read level reference.

[0307] The comparison based on the acquisition of the difference, and the calculation of the dynamic shift value, are shown in the following equation (F0).

[0308] Delta = g - h ···(F0)

[0309] The comparison based on the acquisition of ratios and the calculation of dynamic shift values ​​are shown in the following equation (F1a).

[0310] Delta = (g+1) / (h+1) ···(F1a)

[0311] Furthermore, the Delta obtained from the ratio can be expressed as shown in the following formula (F1b).

[0312] Delta = log (g+1) / (h+1) ···(F1b)

[0313] When the dynamic shift value Delta is calculated based on a ratio, the addition of 1 to both "g" and "h" is to prevent "g" from being divided by zero when "h" is 0.

[0314] The comparison and calculation of the dynamic shift value may be performed by obtaining the logarithmic ratio. When the comparison and calculation of the dynamic shift value of the error bits are performed by the logarithmic ratio, the dynamic shift value Delta is calculated as shown in the following formula (F2).

[0315] Delta = log {(g+1) / (h+1)} = log(g+1) - log(h+1) ···(F2)

[0316] The addition of 1 to both "g" and "h" here is to prevent the result from becoming "log0".

[0317] Furthermore, by setting the base of the logarithm in "log(g+1) / (h+1)" to "2", when "g" or "h" is represented in binary, the integer part of the log will have the same number of digits as "g+1" and "h+1". Therefore, the dynamic shift value can be approximated by the difference in the number of digits of the binary representations of "g+1" and "h+1". For example, when the dynamic shift value is represented in binary, it can be approximated by the difference in the position of the highest-digit "1" (the leftmost bit position of the "1" in the binary representation).

[0318] Furthermore, in comparing error bits and calculating the dynamic shift value, "g" and "h" may be used as variables and calculated using a bilinear equation. The bilinear equation for calculating the dynamic shift value Delta is shown in the following equation (F3).

[0319] Delta = Cg × g - Ch × h + Cf (F3)

[0320] Here, "Cg" is an integer coefficient for "g", "Ch" is an integer coefficient for "h", and "Cf" is an integer constant. For example, when Cg=1, Ch=1, and Cf=0, equation (F3) is equivalent to equation (F0), which calculates the dynamic shift value based on the difference between "g" and "h".

[0321] In the dynamic shift value Delta, if "g" is equal to "h" in equations (F0) and (F1a) above (i.e., Delta = 0), then no correction is applied to the read level.

[0322] If "g" is greater than "h", the readout level voltage is shifted by a predetermined voltage value (e.g., about 1 DAC) by a dynamic shift value Delta in the direction of higher voltage. If "g" is less than "h", the readout level is shifted by a predetermined voltage value (e.g., about 1 DAC) by a dynamic shift value Delta in the direction of lower voltage.

[0323] The dynamic shift value Delta may be corrected by a number of DACs proportional to the dynamic shift value Delta, or by a number of DACs proportional to the 1 / n power (for example, 1 / 2 power) of the absolute value of the dynamic shift value Delta.

[0324] When the dynamic shift value Delta is determined by the above formula (F2), if the dynamic shift value Delta is greater than 0, the readout level is shifted to the higher voltage side by the number of DACs equal to the integer value of the absolute value of the dynamic shift value Delta (|Delta|). If the dynamic shift value Delta is less than 0, the readout level is shifted to the lower voltage side by the number of DACs equal to the integer value of the absolute value of the dynamic shift value Delta (|Delta|).

[0325] Furthermore, as in the example of the bilinear equation (F3), the readout level may be corrected by a constant multiple of the absolute value |Delta| of the dynamic shift value Delta.

[0326] The dynamic shift value Delta, determined by one of the above formulas (F0), (F1a), (F1b), (F2), or (F3), determines the read level used for the next read operation to the same address page (in this example, the middle page) in the same NAND memory 30 access, and the read level includes the calculated dynamic shift value.

[0327] For example, when the threshold voltage distribution changes due to data retention, a higher threshold voltage distribution tends to result in a larger voltage shift.

[0328] When the readout levels V2(V2c), V4(V4c), and V6(V6c) in the middle page are corrected, for example, the dynamic shift values ​​of the readout levels V2, V4, and V6 associated with each threshold voltage distribution S2, S4, and S6 are determined as follows.

[0329] Dynamic shift value of readout level V2 relative to threshold voltage distribution S2: 1 / 3 × Delta However, the dynamic shift value is the integer part of 1 / 3 × Delta. Dynamic shift value of readout level V4 relative to threshold voltage distribution S4: 1 / 2 Delta However, the dynamic shift value is the integer part of 1 / 2 × Delta. Dynamic shift value of readout level V6 relative to threshold voltage distribution S6: 7 / 5 Delta However, the dynamic shift value is the integer part of 7 / 5 × Delta.

[0330] When the dynamic shift value obtained as a logarithmic ratio of "g" and "h" is applied to the next read operation, the dynamic shift values ​​for read levels V2, V4, and V6 are as follows:

[0331] Here, the initial value of the cumulative shift value V2S for read level V2 is set to "+1". The initial value of the shift value V4S for read level V4 is set to "-2". The shift value V6S for read level V6 is set to "-5".

[0332] In a read operation on a certain mid-sized page, assume that in the first read operation there are 5 "g"s and 132 "h"s, and in the second read operation there are 20 "g"s and 4 "h"s.

[0333] During the first read operation, the standard read levels V2c_1, V4c_1, and V6c_1 are set as follows:

[0334] Readout level V2c related to threshold voltage distribution S2: V2c_1 = V2_0 + V2S Readout level V4c for threshold voltage distribution S4: V4c_1 = V4_0 + V4S Readout level V6c related to threshold voltage distribution S6: V6c_1 = V6_0 + V6S

[0335] The read operation is performed using the read level set in this manner.

[0336] Based on the assumptions "g=5" and "h=132" described above, the dynamic shift value is determined by the logarithmic ratio.

[0337] Delta = log2{(g+1) / (h+1)} = log2(5+1) - log2(132+1) = log2(6) - log2(133) = log2(4+2) - log2(128+5) ···(F4)

[0338] In equation (F4), considering only the integer part, we get "log2(4)=2" and "log2(128)=7". Therefore, the integer part of equation (F4) is expressed as shown in equation (F5) below.

[0339] The integer part of Delta: 2 - 7 = -5 ···(F5)

[0340] Note that the decimal number "6" is represented in binary as "00000110". If the LSB (Least significant bit) is bit[0] (1st digit), then the leftmost "1" in "00000110" is bit[2] (3rd digit). Also, the decimal number "133" is represented in binary as "10000101". The leftmost "1" in "10000101" is bit[7] (8th digit).

[0341] In the example of equation (F5), "g" corresponding to the read level offset to the low voltage side (negative read level) is smaller than "h" corresponding to the read level offset to the high voltage side (positive read level). In other words, the difference (number of mismatches) between the standard read data and the positive read data is greater than the difference (number of mismatches) between the standard read data and the negative read data. Therefore, in the next read operation for the same address, a reduction in the number of error bits can be expected by shifting the read level to the low voltage side.

[0342] Using the dynamic shift value Delta obtained by equation (F5), the corrected read levels V2c_2, V4c_2, and V6c_2 for the second read operation are determined as follows:

[0343] The read level V2c_2 in the second read operation is calculated as shown in the following equation (F6a).

[0344] V2c_2 = V2c_1 + 1 / 2 × Delta = V2c_1 + 1 / 2 × (-5) = V2c_1 - 5 / 2 ···(F6a)

[0345] Considering only the integer part of equation (F6a), the corrected readout level V2c is given by equation (F6b) below.

[0346] V2c_2 = V2c_1 - 2 = V2_0 + V2S -2 = V2_0 + 1 -2 = V2_0 -1 ···(F6b)

[0347] The read level V4c_2 in the second read operation is calculated as shown in the following equation (F7a).

[0348] V4c_2 = V4c_1 + 1 / 3 × Delta = V4c_1 + 1 / 3 × (-5) = V4c_1 - 5 / 3 ···(F7a)

[0349] Considering only the integer part of equation (F7a), the corrected readout level V4c is given by equation (F7b) below.

[0350] V4c_2 = V4c_1 - 1 = V4_0 + V4S -1 = V4_0 - 2 - 1 = V4_0 - 3 ···(F7b)

[0351] The read level V6c_2 in the second read operation is calculated as shown in the following formula (F8a).

[0352] V6c_2 = V6c_1 + 7 / 5 × Delta = V6c_1 + 7 / 5 × (-5) = V6c_1 - 35 / 5 ···(F8a)

[0353] Considering only the integer part of equation (F8a), the corrected readout level V6c is given by equation (F8b) below.

[0354] V6c_2 = V6c_1 - 7 = V6_0 - 5 -7 = V6_0 - 12 ···(F8b)

[0355] When a second read operation is performed on the same mid-level page, a standard read (and offset read) is performed using the standard read levels V2c_2, V4c_2, and V6c_2, which have been corrected based on the above-mentioned equations (F6b), (F7b), and (F8b), as a reference.

[0356] The read operation corresponding to the next read command (for example, the second read operation) is performed using a read level obtained from the default read level and the cumulative shift values ​​(V2S', V4S', V6S'), as shown below. For example, the cumulative shift values ​​V2S', V4S', V6S' include the static shift value, the specified shift value set by the memory controller 10, and the dynamic shift value obtained by the automatic adjustment read operation of the NAND memory 30.

[0357] Readout level V2c for threshold voltage distribution S2: V2c_2 = V2_0 + V2S' Readout level V4c for threshold voltage distribution S4: V4c_2 = V2_0 + V4S' Readout level V6c related to threshold voltage distribution S6: V6c_2 = V6_0 + V2S' From the above assumptions, the number of mismatched bits g and h are "g=20" and "h=4". The dynamic shift value Delta is calculated using a logarithmic ratio as follows:

[0358] Delta = log2{ (g+1) / (h+1)} = log2(20+1) - log2(4+1) = log2(21) - log2(5) = log2(16+5) - log2(4+1) ···(F9)

[0359] In equation (F9), considering only the integer part, we get "log2(16)16=4" and "log2(4)=2". Therefore, the integer part of equation (F9) can be expressed as shown in equation (F10) below.

[0360] The integer part of Delta: 4 - 2 = 2 ···(F10)

[0361] Furthermore, when the decimal number "21" is written in binary, it is "00010101", and the leftmost "1" is bit [4] (5th digit). When the decimal number "5" is written in binary, it is "00000101", and the leftmost "1" is bit [2] (3rd digit).

[0362] In equation (F10), "g" corresponding to the read level offset to the low voltage side (negative read level) is greater than "h" corresponding to the read level offset to the high voltage side (positive read level). In other words, the difference between standard read data and positive read data is smaller than the difference between standard read data and negative read data. Therefore, in the next read operation for the same address, a reduction in the number of error bits can be expected as the read level is shifted to the high voltage side.

[0363] Using the dynamic shift value Delta obtained by equation (F10), the corrected read levels V2c_3, V4c_3, and V6c_3 for the third read operation are determined as follows.

[0364] The read level V2c_2 in the third read operation is calculated as shown in the following equation (F11a).

[0365] V2c_3 = V2c_2 + 1 / 2 × Delta = V2c_2 + 1 / 2 × 2 = V2c_2 + 1 ···(F11a)

[0366] Considering only the integer part of equation (F11a), the corrected readout level V2c is given by equation (F11b) below.

[0367] V2c_3 = V2c_2 +1 = V2_0 -1 +1 = V2_0 ···(F11b)

[0368] The read level V4c_3 in the third read operation is calculated as shown in the following equation (F12a).

[0369] V4c_3 = V4c_2 + 1 / 3 × Delta = V4c_2 + 1 / 3 × 2 = V4c_2 + 2 / 3 ···(F12a)

[0370] Considering only the integer part of equation (F12a), the corrected readout level V4c is given by equation (F12b) below.

[0371] V4c_3 = V4c_2 = V4_0 - 3 ···(F12b)

[0372] The read level V6c_3 in the third read operation is calculated as shown in the following formula (F13a).

[0373] V6c_3 = V6c_2 + 7 / 5 × Delta = V6c_2 + 7 / 5 × 2 = V6c_2 + 14 / 5 ···(F13a)

[0374] Considering only the integer part of equation (F13a), the corrected readout level V6c is given by equation (F13b) below.

[0375] V6c_3 = V6c_2 + 2 = V6_0 - 12 + 2 = V6_0 - 10 ···(F13b)

[0376] Similar to the read levels corrected in response to these automatically adjusting read operations, the read level used in the next read operation is calculated based on the number of error bits in the previous read operation on the same page.

[0377] In this embodiment, the method for comparing "g" and "h" is fixed to one of the various methods described above. However, the comparison method, the method for calculating the dynamic shift value of the threshold voltage, and the coefficients and constants used in calculating the dynamic shift value may be set and selected by setting the configuration register of the NAND memory 30.

[0378] (b-6) <sp24> The NAND memory 30 stores the dynamic shift value of the read level calculated by the correction amount calculation circuit 52 in the register circuit 35.

[0379] In the register circuit 35, the state of the setting information register 350 is updated as shown in Figure 20.

[0380] Figure 20 is a schematic diagram illustrating the setting information regarding the read voltage in the register circuit 35 within the NAND memory 30 in the memory system 1 of this embodiment.

[0381] Figure 20(a) shows the various voltage setting information used for reading the middle page stored in the setting information register 350 during the first read operation.

[0382] As described above, the readout level V2 for threshold voltage distribution S2, the readout level V4 for threshold voltage distribution S4, and the readout level V6 for threshold voltage distribution S6 are used for reading the middle page.

[0383] For each of these read levels V2, V4, and V6, the following values ​​(register information) for the common settings registers are stored in the setting information register 350: static shift values ​​R_V2c, R_V4c, R_V6c, specified shift values ​​R_V2SS, R_V4SS, R_V6SS, negative offset values ​​R_V2OstM, R_V4OstM, R_V6OstM, and positive offset values ​​R_V2OstP, R_V4OstP, R_V6OstP.

[0384] The static shift values ​​R_V2t, R_V4t, and R_V6t are initial values ​​for the read levels set based on the manufacturing tests of the NAND memory 30. For example, the static shift value R_V2t for read level V2 is set to "V2t_0". The static shift value R_V4t for read level V4 is set to "V4t_0". The static shift value R_V6t for read level V6 is set to "V6t_0".

[0385] The specified shift values ​​R_V2SS, R_V4SS, and R_V6SS are the amount of shift in the read level set by the memory controller 10. For example, the specified shift value R_V2SS for read level V2 is set to "V2SS". The specified shift value R_V4SS for read level V4 is set to "V4SS". The specified shift value R_V6SS for read level V6 is set to "V6SS".

[0386] The negative offset values ​​R_V2OstM, R_V4OstM, and R_V6OstM are offset amounts used to generate a read level (negative read level) that is offset (shifted) to the lower voltage side. For example, the negative offset value R_V2OstM for read level V2 is set to 10 (10DAC). The negative offset value R_V4OstM for read level V4 is set to 10 (10DAC). The negative offset value R_V6OstM for read level V6 is set to 10 (10DAC).

[0387] The positive offset values ​​R_V2OstP, R_V4OstP, and R_V6OstP are offset amounts used to generate a readout level (positive readout level) that is offset (shifted) to the high-voltage side. For example, the positive offset value R_V2OstP for readout level V2 is set to 10 (10DAC). The positive offset value R_V4OstP for readout level V4 is set to 10 (10DAC). The positive offset value R_V6OstP for readout level V6 is set to 10 (10DAC).

[0388] In this embodiment, the setting information register 350 stores the dynamic shift values ​​R_V2SlfTr, R_V4SlfTr, and R_V6SlfTr, determined in the NAND memory 30, as register values. The dynamic shift values ​​R_V2SlfTr, R_V4SlfTr, and R_V6SlfTr are values ​​that are updated in accordance with the execution of the automatic adjustment read operation.

[0389] During the first read operation, the dynamic shift values ​​R_V2SlfTr, R_V4SlfTr, and R_V6SlfTr for each read level V2, V4, and V6 are set to zero (0).

[0390] Figure 20(b) shows the various voltage setting information used for reading the middle page stored in the setting information register 350 during the Nth read operation.

[0391] As shown in Figure 20(b), common setting register values ​​such as static shift values ​​R_V2t, R_V4t, R_V6t, specified shift values ​​R_V2SS, R_V4SS, R_V6SS, negative offset values ​​R_V2OstM, R_V4OstM, R_V6OstM, and positive offset values ​​R_V2OstP, R_V4OstP, R_V6OstP are not updated in response to the automatic adjustment read operation.

[0392] The dynamic shift values ​​R_V2SlfTr, R_V4SlfTr, and R_V6SlfTr for each read level V2, V4, and V6 are updated according to the number of automatic adjustment read operations.

[0393] During the Nth automatic read adjustment operation, the dynamic shift value R_V2SlfTr for read level V2 is set to "(1 / 3) × ΣDelta". The dynamic shift value R_V4SlfTr for read level V4 is set to "(1 / 2) × ΣDelta". The dynamic shift value R_V6SlfTr for read level V6 is set to "(7 / 5) × ΣDelta". Here, "ΣDelta" is the sum of the dynamic shift values ​​Delta calculated by each of the first to (N-1) automatic read adjustment operations.

[0394] In this way, when reading a middle page at a certain address, the voltage values ​​of the read levels V2, V4, and V6 are corrected based on the dynamic shift values ​​R_V2SlfTr, R_V4SlfTr, and R_V6SlfTr stored in the setting information register 350.

[0395] Through the above operations, the memory system 1 of this embodiment can calculate the dynamic shift value of the read level within the NAND memory 30.

[0396] In this embodiment, an example is shown of calculating the dynamic shift values ​​of read levels V2, V4, and V6 when reading a middle page. However, the memory system 1 of this embodiment can calculate the dynamic shift values ​​of read levels V1 and V5 used for reading lower pages, and the dynamic shift values ​​of read levels V3 and V7 used for reading upper pages, within the NAND memory 30 by substantially the same operation and control as in the example described above.

[0397] (c) Summary In typical memory systems, the high-speed correction capability of ECC is roughly equivalent to the number of hard bit corrections in LDPC (Low-density parity check) codes or the correction capability of BCH codes. Therefore, the high-speed error bit correction capability is at best around 1% of the data length. For example, if the read amount is 4kByte, the number of correctable bits in approximately 4.5kByte of data including ECC parity is about 450 bits.

[0398] This error of approximately 450 bits includes cases where data written to the higher of two adjacent states is read as data in the lower state, and cases where data written to the lower state is read as data in the higher state.

[0399] For example, if data is written and then left untouched for a long period of time before being read, errors due to data retention stress can be expected.

[0400] The main cause of errors due to data retention stress is the nearly uniform shift in the threshold voltage distribution corresponding to the data within the NAND memory 30. Therefore, in errors caused by data retention stress, there is little distortion or change in the shape of the threshold voltage distribution of the data within the NAND memory 30. Instead, errors are triggered by the phenomenon of the threshold voltage distribution shifting from the high-voltage side to the low-voltage side, and by the phenomenon of the distribution width of the threshold voltage distribution widening (see Figure 4(b)).

[0401] In the phenomenon where the threshold voltage distribution shifts from the high-voltage side to the low-voltage side, the shape of the threshold voltage distribution is largely maintained, and the threshold voltage distribution shifts parallel to the lower voltage side from the original voltage range.

[0402] The phenomenon of the threshold voltage distribution widening is caused by variations in the amount of threshold voltage shift from the high-voltage side to the low-voltage side for each memory cell. Therefore, the shape of the high-voltage side of the threshold voltage distribution is largely preserved, but the shape of the low-voltage side changes in a direction that makes the slope of the threshold voltage distribution gentler. Even with the phenomenon of the threshold voltage distribution widening, the amount of voltage shift can be estimated with near accuracy by assuming that the threshold voltage distribution corresponding to the data changes symmetrically on both the high-voltage and low-voltage sides.

[0403] The memory system 1 of this embodiment reads data from the memory cell MC in the NAND memory 30 using a standard read level and a read level offset from the standard read level. It detects the number of error bits in the read data. The memory system 1 of this embodiment calculates a dynamic shift value of the read level in the NAND memory 30 based on the detection result of the error bits contained in the read data. The memory system 1 of this embodiment performs the next read operation using a read level corrected based on the calculated dynamic shift value.

[0404] As a result, the memory system of this embodiment can reduce the number of error bits in the read data obtained by the read operation.

[0405] As described above, the memory system of this embodiment can improve the reliability of data retrieval.

[0406] (2) Second embodiment Referring to Figure 21, a memory system of a second embodiment will be described.

[0407] Figure 21 is a schematic diagram illustrating the acquisition of data during a read operation of the memory system 1 in the second embodiment.

[0408] In the first embodiment, during the automatic adjustment readout operation, the voltage applied to the selected word line is varied in three stages: a negative readout level, a standard readout level, and a positive readout level.

[0409] For example, negative and positive read data may be obtained by simply applying a standard read level to the selected word line. This can be achieved by shifting the timing at which the sense amplifier module 39 acquires a signal corresponding to the threshold voltage of the memory cell MC into the data latch DL, thereby acquiring a signal corresponding to the threshold voltage of the memory cell MC sensed by applying a read level to the word line WL. Alternatively, this can be achieved by acquiring a signal corresponding to the threshold voltage of the memory cell MC by detecting the current of the bit line BL.

[0410] In the memory system 1 of the second embodiment, in determining the threshold voltage of a memory cell MC with respect to a certain threshold voltage distribution, the read level applied to the selected word line WL-S is the read level VXc for standard readout. Alternatively, the read level applied to the selected word line WL-S may be a read level offset to the higher voltage side from the standard readout level.

[0411] In Figure 21, the vertical axis represents the voltage magnitude, and the horizontal axis represents time. At time t0, the application of the standard readout level VXc to the selected word line WL-S begins. The application of the standard readout level VXc causes the voltage across the selected word line WL-S to rise.

[0412] The memory cell MC responds (turns on / off) to the application of a readout level VXc with respect to a certain threshold voltage distribution. When the memory cell MC is on, current is generated in the bit line BL according to the response speed (driving force) of the memory cell MC, and the potential of the bit line BL changes. When the memory cell MC is off, the bit line BL remains charged, and the voltage does not change.

[0413] At time t1, the sense amplifier module 39 senses the voltage of the memory cell MC and captures the sense result as standard read data into the data latch DL. Time t1 is, for example, 10.00 μs.

[0414] At time ta, which is earlier than time t1, the sense amplifier module 39 senses the voltage of the memory cell MC and inputs the sense result as negative read data into the data latch EDL. Time ta is, for example, 9.95 μs. This results in the acquisition of negative read data (data that is substantially equivalent to negative read data).

[0415] Similarly, at time tb, which is later than time t1, the sense amplifier module 39 senses the voltage of the memory cell MC and captures the sense result as positive read data in the data latch FDL. Time tb is, for example, 10.05 μs. This acquires positive read data (data that is substantially equivalent to positive read data).

[0416] At time t2, the application of the read level VXc is stopped. The determination of the threshold voltage of the memory cell MC based on the read level VXc is terminated.

[0417] Similarly, for each threshold voltage distribution, the timing of the signal sensing is shifted to obtain negative readout data, standard readout data, and positive readout data, respectively.

[0418] Thus, the memory system 1 of the second embodiment can acquire negative and positive read data without applying a read level offset from the standard read level.

[0419] As a result, the read latency of the memory system 1 in the second embodiment can be made approximately the same as the read latency of a memory system that does not perform read level correction during read operations.

[0420] Therefore, according to the second embodiment, the read data can be output from the NAND memory 30 to the memory controller 10 with a latency that is almost the same as that of a normal read operation in which data is read only at the standard read level.

[0421] As described above, the memory system 1 of the second embodiment can obtain substantially the same effects as the first embodiment, while also improving the performance of the memory system.

[0422] (3) Third Embodiment A memory system according to a third embodiment will be described.

[0423] In the first and second embodiments, the number of "1"s in the verification data stored in the data latch GDL and the number of "1"s in the verification data stored in the data latch HDL are counted within a data range (for example, an 8-bit unit) that is output collectively from the NAND memory 30.

[0424] Here, the number of "1"s in the verification data may be counted for the entire data on one page, or for portions larger than the I / O unit.

[0425] In this case as well, the memory system of the third embodiment can obtain substantially the same effects as the memory system of the above-described embodiment.

[0426] (4) Fourth Embodiment A memory system according to a fourth embodiment will be described.

[0427] In the NAND memory 30, various stresses occur that change the threshold voltage distribution.

[0428] If it is sufficient to calculate the dynamic shift value of the readout level based only on errors under specific stresses, for example, when dealing only with data retention, then it is sufficient to consider that the threshold voltage distribution shifts only in the low-voltage direction. In this case, positive readout data corresponding to readout levels offset to the high-voltage side does not necessarily have to be read out.

[0429] In other words, without acquiring positive read data, the number of "1"s (g) obtained from the XOR operation between the standard read data and the negative read data may be measured by acquiring standard read data and negative read data.

[0430] Based on the number of "1"s measured, "g", and the threshold value, "L", it is determined whether or not read level correction by dynamic shift value is necessary and the magnitude of the dynamic shift value for the read level. For example, the threshold is a value that is pre-set when the memory system is shipped. The threshold value "L" is a natural number.

[0431] For example, if "g" is zero (all bits of the standard read data and the negative read data match), the NAND memory 30 determines that correction of the read level by the dynamic shift value is unnecessary. In this case, the dynamic shift value is set to zero, and the read level is corrected by a shift value that includes only the specified shift value and the static shift value. If "g" is greater than or equal to "L", the NAND memory 30 determines that correction of the read level by the dynamic shift value is necessary. If "g" is greater than or equal to zero and less than "L", the NAND memory 30 determines that correction of the read level by the dynamic shift value is unnecessary.

[0432] Based on the above, the NAND memory 30 calculates a dynamic shift value corresponding to the size of "g". The read level is corrected by the shift value, which includes the calculated dynamic shift value.

[0433] In this case as well, the memory system of this embodiment can achieve substantially the same effects as the memory system of the above-described embodiment.

[0434] (5) Fifth embodiment Referring to Figure 22, a memory system of the fifth embodiment will be described.

[0435] Figure 22 is a schematic diagram illustrating the memory system 1 of the fifth embodiment.

[0436] In the first to fourth embodiments, the number of error bits in the data was verified by performing an OR operation on the results of an XOR operation on standard read data, negative read data, and positive read data for each of multiple read levels of a given page (e.g., a middle page).

[0437] As shown in Figure 22, in the fifth embodiment, standard read data RDT, negative read data Dm, and positive read data Dp are generated using the read levels for each threshold voltage of the page to be read.

[0438] Subsequently, data XDm, which shows the result of the XOR operation between the standard read data RDT and the negative read data Dm, and data XDp, which shows the result of the XOR operation between the standard read data RDT and the positive read data Dp, are generated.

[0439] The number of "1"s in each of the generated verification data XDm and XDp is counted by the error bit detection circuit 50.

[0440] In the fifth embodiment, the NAND memory 30 calculates a dynamic shift value for the read level so as to shift the read level in accordance with the verification data XDm,XDp which have fewer "1"s.

[0441] Furthermore, the NAND memory 30 may be configured to set a dynamic shift value that shifts the read level in a predetermined direction based on the expected stress (such as data retention or read disturbance) and the number of "1"s. Regarding the dynamic shift value for data retention, a dynamic shift value proportional to the difference in the number of "1"s is applied to the read level on the low-voltage side. Regarding the dynamic shift value for read disturbance, for example, in lower pages, a dynamic shift value proportional to the difference in the number of "1"s is applied only to the read level V1 of state "A" on the high-voltage side.

[0442] In this case as well, the memory system of this embodiment can achieve substantially the same effects as the memory system of the above-described embodiment.

[0443] (6) Sixth Embodiment A memory system according to the sixth embodiment will be described.

[0444] In the first to fifth embodiments, the dynamic shift value of the read level was calculated using a fractional multiple of the difference Delta between the number of discrepancies between the negative read level determination result and the standard read level determination result and the number of discrepancies between the positive read level determination result and the standard read level determination result.

[0445] To simplify the hardware configuration of the NAND memory 30, the value of the denominator in the fractional multiple used to calculate the difference Delta may be limited to a power of 2.

[0446] By limiting the denominator to a power of 2, the arithmetic unit for implementing the calculation of dynamic shift values ​​within the NAND memory 30 can consist only of shift operations and integer addition.

[0447] To approximate the dynamic shift value of the read level using a 1 / 2 multiplication operation, the following process is performed.

[0448] (Step 1) The denominator of the correction coefficient is multiplied by an integer so that the value of the denominator is set to a value close to a power of 2 that is less than four times the denominator. (Step 2) The same value that was multiplied in the denominator in Step 1 is multiplied in the numerator of the correction coefficient. (Step 3) The value in the denominator of the correction coefficient is replaced with a power of 2 less than four times the value in the denominator, and the value in the numerator of the correction coefficient is the value obtained in Step 2. (Step 4) The fraction obtained in Step 3 is expressed as a sum of 1 / (powers of 2).

[0449] If the dynamic shift value (correction coefficient) in the first embodiment described above is used as an example, the processing of steps 1 to 4 above is shown more specifically as follows.

[0450] Before processing: Dynamic shift value of readout level V2 with respect to threshold voltage distribution S2: (1 / 3) × Delta Dynamic shift value of readout level V4 with respect to threshold voltage distribution S4: (1 / 2) × Delta Dynamic shift value of readout level V6 with respect to threshold voltage distribution S6: (7 / 5) × Delta

[0451] However, the dynamic shift value for each readout level includes only the integer part of the fraction.

[0452] Through the processes described in steps 1 to 4 above, the dynamic shift values ​​for each read level are processed as follows:

[0453] The processes in Step 1 and Step 2 multiply the numerator and denominator of the correction coefficient by "3" for the dynamic shift value "(1 / 3) × Delta" at read level V2. As a result, the parameter for the dynamic shift value at read level V2 becomes "(3 / 9) × Delta".

[0454] Step 3 replaces the "9" in the denominator of the correction coefficient with "8". As a result, the parameter for the dynamic shift value at read level V2 becomes "(3 / 8) × Delta".

[0455] As a result of the processing in step 4, when the correction coefficient is expressed as a sum of 1 divided by a power of 2, the parameter for the dynamic shift value is given as "(1 / 4 + 1 / 8) × Delta".

[0456] As a result, the dynamic shift value at read level V2 is the sum of the value obtained by right-shifting the Delta value (binary value) by 2 bits and the value obtained by right-shifting the Delta value by 3 bits.

[0457] The dynamic shift value "(1 / 2) × Delta" at read level V4 is expressed as 1 divided by a power of 2. Therefore, the processes described in steps 1 through 4 above are not performed on the dynamic shift value at read level V4.

[0458] The dynamic shift value at read level V4 is the value of Delta shifted to the right by one bit.

[0459] The processes in Step 1 and Step 2 multiply the numerator and denominator of the correction coefficient by "3" for the dynamic shift value "(7 / 5) × Delta" at read level V6. As a result, the parameter of the dynamic shift value becomes "(21 / 15) × Delta".

[0460] Step 3 replaces the denominator "15" with "16". As a result, the parameter for the dynamic shift value becomes "(21 / 16) × Delta".

[0461] As a result of the processing in step 4, when the correction coefficients are expressed as a sum of 1 divided by a power of 2, the parameter for the dynamic shift value is given as "(1 + 1 / 4 + 1 / 16) × Delta".

[0462] As a result, the dynamic shift value for read level V6 is the sum of the value obtained by right-shifting Delta by 2 bits and the value obtained by right-shifting Delta by 4 bits.

[0463] In this way, the dynamic shift values ​​for each readout level V2, V4, and V6 are calculated.

[0464] The calculation process for dynamic shift values ​​is not limited to the example above. For example, the calculation process for dynamic shift values ​​may be performed with the approximating denominator fixed at "16".

[0465] (Step 1a) The denominator of the correction coefficient is multiplied by an integer so that the value of the denominator is set to a value close to "16". (Step 2a) The same value that was multiplied in the denominator in Step 1a is multiplied in the numerator of the correction coefficient. (Step 3a) The value in the denominator of the correction coefficient is replaced with "16", and the value in the numerator of the correction coefficient is the value obtained in Step 2a. (Step 4a) The fraction obtained in Step 3a is expressed as a sum of 1 / (powers of 2).

[0466] If the dynamic shift value (correction coefficient) in the first embodiment described above is used as an example, the processing in steps 1a to 4a above is shown more specifically as follows.

[0467] Before processing: Dynamic shift value of readout level V2 with respect to threshold voltage distribution S2: (1 / 3) × Delta Dynamic shift value of readout level V4 with respect to threshold voltage distribution S4: (1 / 2) × Delta Dynamic shift value of readout level V6 with respect to threshold voltage distribution S6: (7 / 5) × Delta

[0468] However, the dynamic shift values ​​for each readout level V2, V4, and V6 include only the integer part of the fraction.

[0469] Through the processing described in steps 1a to 4a above, the dynamic shift values ​​for each read level are processed as follows:

[0470] The processing in steps 1a and 2a multiplies the numerator and denominator of the correction coefficient of the dynamic shift value "(1 / 3) × Delta" at readout level V2 by "5". As a result, the parameter of the dynamic shift value becomes "(5 / 15) × Delta".

[0471] The process in step 3a replaces the denominator of the correction coefficient from "15" to "16". As a result, the parameter of the dynamic shift value becomes "(5 / 16) × Delta".

[0472] As a result of the processing in step 4a, when the correction coefficients are expressed as a sum of 1 divided by a power of 2, the parameter for the dynamic shift value is given as "(1 / 4 + 1 / 16) × Delta".

[0473] As a result, the dynamic shift value at read level V2 is the sum of the value of Delta (the binary value) shifted to the right by 2 bits and the value shifted to the right by 4 bits.

[0474] The dynamic shift value "(1 / 2) × Delta" at read level V4 is expressed as 1 divided by a power of 2. Therefore, the processing in steps 1a to 4a above is not performed on the dynamic shift value at read level V4.

[0475] Therefore, the dynamic shift value at read level V4 is the value of Delta shifted to the right by one bit.

[0476] The processing in steps 1a and 2a multiplies the numerator and denominator of the correction coefficient of the dynamic shift value "(7 / 5) × Delta" at read level V6 by "3". As a result, the parameter of the dynamic shift value becomes "(21 / 15) × Delta".

[0477] Step 3a replaces the denominator of the correction coefficient from "15" to "16". As a result, the parameter for the dynamic shift value becomes "(21 / 16) × Delta".

[0478] As a result of the processing in step 4a, when the correction coefficient is expressed as a sum of 1 divided by a power of 2, the parameter for the dynamic shift value is given as "(1 + 1 / 4 + 1 / 16) × Delta".

[0479] As a result, the dynamic shift value at read level V6 is the sum of the value of Delta shifted 2 bits to the right and the value of Delta shifted 4 bits to the right.

[0480] Thus, the memory system 1 of the sixth embodiment simplifies the configuration of the NAND memory 30 by expressing the dynamic shift value of the read level as a power of 2.

[0481] In this case as well, the memory system 1 of the sixth embodiment can obtain substantially the same effects as the memory systems of the first to fifth embodiments.

[0482] (7-1) Seventh Embodiment Referring to Figure 23, a memory system of the seventh embodiment will be described.

[0483] Figure 23 is a block diagram showing an example configuration of the NAND memory 30 in the memory system 1 of the seventh embodiment.

[0484] Generally, when data is written to multiple addresses in a physical block of NAND memory almost simultaneously, the memory cells (MCs) at the addresses where the data was written are likely to be subjected to similar stress. Therefore, if the block addresses are the same, even if the word line addresses are different, it is highly likely that error bits in the read data can be reduced by using a read operation with a corrected read level.

[0485] As shown in Figure 23, in the memory system 1 of the seventh embodiment, the NAND memory 30 includes an address storage circuit 53 and an address comparison circuit 54.

[0486] The address memory circuit 53 is a circuit that stores addresses ADDx for which read commands of the automatic adjustment read operation have been issued in the past. The address memory circuit 53 may also store a portion of past addresses ADDx (for example, a block address). For example, the block address is included in the MSB (most significant bit) portion of address ADD and past addresses ADDx.

[0487] The address comparison circuit 54 is a circuit that compares the address stored in the address memory circuit 53 with the received address ADD. The address comparison circuit 54 compares a portion of the past address ADDx corresponding to the read command ("C4h") of a past automatic adjustment read operation in the address memory circuit 53 (for example, the upper part of the address corresponding to block BLK of the NAND memory 30) with a portion of the address ADD corresponding to the read command of a read operation performed after the read level correction, and determines whether the addresses match. Furthermore, the address comparison circuit 54 compares the specific part of the past address ADDx corresponding to the read command ("C4h") of a past automatic adjustment read operation in the address memory circuit 53 with the specific part of the address ADD corresponding to the read command of a read operation performed after the read level correction, and determines whether the addresses match. The specific part of the address is included in a portion of the address. The address comparison circuit 54 notifies the sequencer 36 of the determination result obtained by comparing address ADD with the past address ADDx.

[0488] Based on the comparison result notification from the address comparison circuit 54, the sequencer 36 reads the setting information regarding the read level in the setting information register 350. Using the read setting information, the sequencer 36 sets the drive mode of the charge pump of the driver module 37.

[0489] If a portion of address ADD matches a portion of a previous address ADDx, the NAND memory 30 performs a read operation from the area indicated by address ADD using a read level (read voltage) that includes the dynamic shift value obtained by the automatic adjustment read operation.

[0490] If part of address ADD does not match part of a previous address ADDx, the NAND memory 30 performs a read operation from the area indicated by address ADD using the read level before correction by the automatic adjustment read operation.

[0491] If the specific part of address ADD does not match the specific part of a previous address ADDx, the NAND memory 30 reads data from the area indicated by address ADD using a read level based on the register value "ViC = R_Vi_0 + R_Vit + R_ViSS".

[0492] If the specific part of address ADD matches the specific part of a previous address ADDx, the block BLK that stores the data to be read by address ADD is a block BLK for which an automatic adjustment read operation has already been performed. The NAND memory 30 reads data from the area indicated by address ADD using a read level that includes a dynamic shift value based on the register value "ViC = R_Vi_0 + R_ViC + R_ViSS + R_ViS_SlfTr", for example, in the configuration of the setting information register 350 in the first embodiment.

[0493] As described above, in this embodiment, when the block address of the selected address ADD matches the block address of address ADDx in the address storage circuit 53, data is read from the memory cell MC in the block BLK to be read using the read level corrected by the automatic adjustment read. This makes it possible to obtain read data with a small number of error bits.

[0494] The memory system 1 of the seventh embodiment can correct the read level by comparing addresses, thereby improving the efficiency and reliability of read operations.

[0495] (7-2) Modified form of the seventh embodiment Generally, the characteristics of memory cells within the same chip of NAND memory tend to show relatively little difference between blocks, but significant differences between word lines. Within the memory cell array 31, multiple word line memory cells MCs located close together are likely to have similar characteristics. Therefore, in a read operation targeting a word line WL that has not undergone automatic read adjustment, using a corrected read level obtained from a word line WL that is physically close to the target word line WL and has undergone automatic read adjustment is likely to reduce the number of error bits in the read data.

[0496] Therefore, the specific part of the address ADD in the seventh embodiment and the specific part of the past address ADDx may be, for example, a word line address.

[0497] In the memory system 1 of the seventh embodiment, the address storage circuit 53 stores a portion of past address ADDx. The portion of past address ADDx is, for example, a word line address. The word line address is included in the portion between the block address and column address (bit line address) of address ADD and past address ADDx.

[0498] The address comparison circuit 54 compares past address ADDx with address ADD to determine whether or not a part of the address matches.

[0499] In this modified example, if the word line address (or part of the word line address) of the selected address ADD matches the word line address of address ADDx in the address memory circuit 53, data is read from the memory cell MC of the word line WL to be read using the read level corrected by the automatic adjustment read. This makes it possible to obtain read data with a small number of error bits.

[0500] Furthermore, the most significant bits (MSB side) of the word line address may be used to determine whether or not to use the read level corrected by automatic read adjustment.

[0501] Note that the specific part of addresses ADD and ADDx is not limited to the example above. The specific part of addresses ADD and ADDx may also be the part corresponding to the physical address. The specific part of addresses ADD and ADDx may also be obtained by explicitly specifying the address mask register (not shown) using a command such as the Set Feature command.

[0502] As a result, the modified memory system 1 of the seventh embodiment can correct the read level by comparing addresses, thereby improving the efficiency and reliability of the read operation.

[0503] The memory system 1 of this embodiment can achieve substantially the same effects as the memory system of the above-described embodiment.

[0504] (8) Eighth embodiment The memory system of the eighth embodiment will now be described.

[0505] Similar to the first to seventh embodiments, the memory system 1 of this embodiment calculates the dynamic shift value of the read level used when a read operation is performed on a certain address ADD by an automatic adjustment read operation.

[0506] The memory system 1 of this embodiment may perform a read operation in the next cycle for the same address ADD using a read level that includes the dynamic shift value calculated by the automatic adjustment read operation of the previous cycle.

[0507] As a result, the memory system 1 of this embodiment can obtain substantially the same effects as the memory system of the above-described embodiment.

[0508] (9) The ninth embodiment A memory system according to the ninth embodiment will be described.

[0509] In the memory system 1 of the first to eighth embodiments, as described above, the NAND memory 30 performs an XOR operation on standard read data, negative read data, and positive read data for each of the multiple read levels of a page (for example, read levels V2, V4, V6 of the middle page), further performs an OR operation on the data showing the result of the XOR operation, and counts and compares the number of "1"s in the data based on the data resulting from the OR operation.

[0510] In the ninth embodiment, the NAND memory 30 corrects one or more specific read levels without correcting all read levels, based on a comparison of the count of "1"s in the data and the number of "1"s.

[0511] For example, the NAND memory 30 calculates only the dynamic shift value for read level V1 of the two read levels V1 and V5 for reading lower pages during the automatic adjustment read operation for lower pages.

[0512] Under read disturb stress conditions, a large number of errors are detected due to the shift in the threshold voltage of the memory cell MC from the threshold voltage distribution (erase state) S0 to the threshold voltage distribution (A state) S1.

[0513] Therefore, correcting the read level of lower pages is effective by comparing and detecting the error bits ("1" in the data) of the read level V1 with respect to the threshold voltage distribution S1.

[0514] Furthermore, in read disturbances, the number of errors detected when the threshold voltage of a memory cell MC moves from threshold voltage distribution S0 to threshold voltage distribution S1 is overwhelmingly greater than the number of errors detected when the threshold voltage of a memory cell MC moves from threshold voltage distribution S1 to threshold voltage distribution S0.

[0515] Therefore, with respect to the lower page read level V1, the number of errors in which the threshold voltage of the memory cell MC moves from the lower threshold voltage distribution S0 to the higher threshold voltage distribution S1, i.e., the number of error bits (h) at the positive read level V1p offset to the higher voltage side with respect to the standard read level V1c, is greater than the number of error bits (g) at the negative read level V1m offset to the lower voltage side with respect to the standard read level V1c.

[0516] Furthermore, if the threshold voltage of the memory cell MC that should store data corresponding to the threshold voltage distribution S0 shifts to the higher voltage region of the threshold voltage distribution S1 or to a distribution higher than or equal to the threshold voltage distribution S2, the value may not change even if a read operation with a shifted read level is performed. In this case, even if an error bit occurs, it will not be reflected in either "g" or "h".

[0517] Therefore, for certain errors, even if all read levels are corrected, it may not be possible to reduce the number of error bits in the read data.

[0518] Therefore, by correcting only specific read levels, as in the ninth embodiment, the operational load on the NAND memory 30 can be suppressed.

[0519] In the ninth embodiment, either the comparison between negative read data and standard read data, or the comparison between positive read data and standard read data, is not performed. If the shift amount of the read level (dynamic shift value) is excessive, it may not be possible to correct the dynamic shift value in a way that reduces the shift amount of the read level. For this reason, a lower limit may be set for the number of "1"s included in the result of the XOR operation between the standard read data and the read data with the offset read level. In this case, if the number of "1"s (number of error bits) included in the result of the XOR operation (verification data) is less than the lower limit, the read level is not corrected. If the number of "1"s included in the result of the XOR operation is equal to or greater than the lower limit, the read level is corrected. As a result, the memory system of the ninth embodiment can prevent excessive correction of the read level.

[0520] Furthermore, for the same page, if the number of "1"s in the result of the XOR operation between the N+1th standard read data and the offset read data is greater than the number of "1"s in the result of the XOR operation between the Nth standard read data and the offset read data, the read level correction value may be controlled so that the correction value based on the result of the Nth XOR operation is returned to the correction value based on the results of the XOR operations up to the N-1th. This prevents excessive correction of the read level.

[0521] As described above, the memory system of the ninth embodiment can efficiently correct the read level.

[0522] The memory system of the ninth embodiment can achieve substantially the same effects as those of the first to eighth embodiments.

[0523] (10) Tenth Embodiment Referring to Figure 24, a memory system of the tenth embodiment will be described.

[0524] Figure 24 is a block diagram showing an example of the configuration of the data latch of the NAND memory 30 in the memory system 1 of the 10th embodiment.

[0525] In the first to ninth embodiments, in order to reduce the number of hardware such as data latches and / or counters implemented in the NAND memory 30, a process was performed in which the results of an XOR operation on multiple data for each of the multiple read levels were further ORed.

[0526] As shown in Figure 24, the number of data latches DL may be increased to store the determination results for each of the offset read levels.

[0527] For example, the number of read levels for the middle page in TLC mode is three. Since a lower-voltage offset and a higher-voltage offset read level are set for each standard read level, nine data latches DL are mounted within the data latch circuit 40.

[0528] For read level V2 (V2c, V2m, V2p), three data latches ADLc, ADLm, and ADLp are provided. For read level V4 (V4c, V4m, V4p), three data latches BDLc, BDLm, and BDLp are provided. For read level V6 (V6c, V6m, V6p), three data latches CDLc, CDLm, and CDLp are provided.

[0529] Thus, the number of data latches (DLs) increases by a multiple of the read level.

[0530] As in the tenth embodiment, by providing a data latch DL for each readout level, the voltage value can be corrected independently for each readout level.

[0531] In the tenth embodiment, the number of data latches DL is increased in accordance with the number of read levels, so that for each read level, the number of error bits in the result of the XOR operation between the standard read data and the offset read data can be counted when data is output from the NAND memory 30 to the memory controller 10.

[0532] Furthermore, the memory system 1 of the tenth embodiment can also accommodate situations in which, for example, the threshold voltage distribution S1 shifts the read level only to the high voltage side in response to read disturbance, while other threshold voltage distributions shift the read level only to the low voltage side in response to data retention.

[0533] The memory system 1 of the tenth embodiment can flexibly handle the calculation of dynamic shift values ​​for each read level depending on the circumstances under which an error bit is detected.

[0534] As described above, the memory system 1 of the tenth embodiment can obtain the same effects as the first to ninth embodiments.

[0535] (11) Eleventh Embodiment Referring to Figure 25, the memory system of the eleventh embodiment will be described.

[0536] Figure 25 is a schematic diagram illustrating the memory system 1 of the eleventh embodiment.

[0537] In the first to tenth embodiments, for the sake of simplicity, the difference between standard read data and negative read data (results of XOR and OR operations), and the difference between standard read data and positive read data (results of XOR and OR operations) are calculated for the entire page data. The entire page data is, for example, 16 kBytes.

[0538] Generally, it is assumed that the data written to the NAND memory 30 is randomized.

[0539] Therefore, if the differences in the characteristics of memory cells MC depending on their position within the memory cell array 31 can be ignored, the position of the bits output from the input / output circuit 32 within the same page does not need to be the same as the position of the bits used to count error bits.

[0540] The verification data for detecting error bits may be a portion of the page data, for example, data with a size of 4.5 kByte including a 4 kByte data portion and a 0.5 kByte ECC parity portion (e.g., ECC frame data). However, it is preferable that the data size be such that statistical variability is negligible.

[0541] In this embodiment, as shown in Figure 25, for example, each of the data latches EDL, FDL, GDL, and HDL is divided into four regions R0, R1, R2, and R3.

[0542] For example, in a data latch DL, the data of the determination result for the first read level (standard read level or offset read level) is stored in the first 4.5kByte area R0 of the four divided areas R0, R1, R2, and R3. The data of the determination result for the first read level is, for example, the data of the determination result for the read level V2 of the middle page in TLC mode. The data of the determination result for the second read level is stored in the second 4.5kByte area R1. The data of the determination result for the second read level is, for example, the data of the determination result for the read level V4 of the middle page in TLC mode. The data of the determination result for the third read level is stored in the third 4.5kByte area R2. The data of the determination result for the third read level is, for example, the data of the determination result for the read level V6 of the middle page in TLC mode.

[0543] The data read unit may vary depending on the application and / or use. The number of error bits between standard read data and offset read data tends to be proportional to the amount of data read. Therefore, the dynamic shift value of the read level may be adjusted according to the amount of data, either by specifying the amount of data to be read from the memory controller 10 or by counting the amount of data output from the NAND memory 30.

[0544] As described above, the memory system 1 of the 11th embodiment can obtain the same effects as the first to tenth embodiments.

[0545] (12) Others In the memory system of the embodiment described above, the configuration and operation for TLC mode NAND memory are illustrated. However, in the memory system of this embodiment, the NAND memory 30 may store data in MLC mode, QLC mode, or PLC mode. Even if the memory system of this embodiment includes NAND memory other than TLC mode, the memory system of this embodiment can obtain substantially the same effects as the embodiment described above.

[0546] In the embodiment described above, the threshold voltage distribution for each page is determined starting from the lowest read level. However, in the memory system of the embodiment, the threshold voltage distribution may be determined starting from the highest read level.

[0547] In the embodiments described above, the Nth read operation and the N+1th read operation are described as consecutive accesses. The memory system (and its control method) of the embodiments described above may be applied to accesses involving the Nth read operation and the N+1th read operation to a particular page (e.g., a middle page).

[0548] If the page targeted by the Nth read operation (e.g., a middle page) and the page targeted by the N+1th read operation (e.g., a top page) are different, the read level correction value for the page targeted by the N+1th read operation may be estimated based on linear interpolation or extrapolation of the shift values ​​of each read level, using the read level correction value for the page targeted by the Nth read operation.

[0549] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0550] 1: Memory system, 10: Memory controller, 30: NAND flash memory, 31: Memory cell array, 40: Data latch circuit, 50: Error bit detection circuit, 52: Correction amount calculation circuit, 53: Address storage circuit, 54: Address comparison circuit.

Claims

1. A memory device containing multiple memory cells for storing data, A memory controller that controls the operation of the memory device, It is equipped with, The memory device is In response to a first set of read commands, the system obtains a first determination result of the threshold voltages of the plurality of memory cells based on a first read level relating to a first threshold voltage distribution, and a second determination result of the threshold voltages of the plurality of memory cells based on a first low-voltage offset read level obtained by offsetting the first read level to the low-voltage side. The first number of mismatches between the first determination result and the second determination result is obtained, Based on the first mismatch number, a first correction amount for the first readout level is calculated. It is configured in such a way. Memory system.

2. The memory device is A third determination result of the threshold voltage of the plurality of memory cells is obtained based on a first high-voltage offset read level obtained by offsetting the first read level to the high-voltage side, Obtain the second number of mismatches between the first determination result and the third determination result. The first correction amount is calculated according to the relative magnitudes of the first number of mismatches and the second number of mismatches. It is further configured in the following way: The memory system according to claim 1.

3. If the first number of mismatches is greater than the second number of mismatches, the memory device sets the first correction amount to a value that shifts the first read level to the high-voltage side. If the first number of mismatches is less than the second number of mismatches, the memory device sets the first correction amount to a value that shifts the first read level to the low voltage side. The memory system according to claim 2.

4. The memory device calculates the first correction amount based on one of the following: the difference between the first mismatch number and the second mismatch number, the ratio between the first mismatch number and the second mismatch number, the logarithmic ratio between the first mismatch number and the second mismatch number, and a bilinear equation between the first mismatch number and the second mismatch number. The memory system according to claim 2.

5. The memory device calculates the first correction amount in parallel with outputting the data based on the first determination result. The memory system according to claim 1.

6. The memory device is Perform a first exclusive OR operation between the first determination result and the second determination result. Based on the number of "1"s in the result of the first exclusive OR operation, the first mismatch count is obtained. The memory system according to claim 1.

7. The memory device is A fourth determination result of the threshold voltage of the plurality of memory cells based on a second readout level relating to a second threshold voltage distribution different from the first threshold voltage distribution is obtained, and a fifth determination result of the threshold voltage of the plurality of memory cells based on a second low-voltage offset readout level obtained by offsetting the second readout level to the low-voltage side is obtained. Perform a second exclusive OR operation on the fourth determination result and the fifth determination result. Perform a logical OR operation on the result of the first exclusive OR operation and the result of the second exclusive OR operation. Based on the number of "1"s in the result of the logical OR operation, a third mismatch count is obtained between the first, second, fourth, and fifth determination results. Based on the third mismatch number, the first correction amount and the second correction amount for the second readout level are calculated. The memory system according to claim 6.

8. The first set of read commands is: A first command that instructs the calculation of the first correction amount, A second command, which is sent after the first command, instructs the memory device to perform a read operation, including, The memory system according to claim 1.

9. The memory device is A first data latch that stores the first determination result, A second data latch that stores the second determination result, A third data latch that stores the result of a first exclusive OR operation between the first determination result and the second determination result, Further including, The memory system according to claim 1.

10. The memory device is A fourth determination result of the threshold voltage of the plurality of memory cells based on a second readout level relating to a second threshold voltage distribution different from the first threshold voltage distribution is obtained, and a fifth determination result of the threshold voltage of the plurality of memory cells based on a second low-voltage offset readout level obtained by offsetting the second readout level to the low-voltage side is obtained. The fourth determination result is stored in the fourth data latch. The fifth determination result is stored in the second data latch. Perform a second exclusive OR operation on the fourth determination result and the fifth determination result. Perform a logical OR operation on the result of the first exclusive OR operation and the result of the second exclusive OR operation. The result of the logical OR operation is stored in the third data latch. The memory system according to claim 9.

11. The memory device further includes an error bit detection circuit for measuring the first mismatch count. The memory system according to claim 1.

12. The memory device further includes a correction amount calculation circuit that calculates the first correction amount based on the first mismatch number. The memory system according to claim 1.

13. The memory device is An address storage circuit that stores a first address included in the first read command set, An address comparison circuit that compares the first address with a second address included in a second read command set different from the first read command set, It further includes, The memory device determines the threshold voltage of the memory cell using a third read level that includes the first correction amount when the first portion of the first address and the second portion of the second address match. The memory system according to claim 1.

14. The memory device is A first register that stores the offset amount of the first low-voltage side offset readout level, A second register for storing the first correction amount, including, The memory system according to claim 1.

15. Multiple memory cells that store data, A control circuit for controlling the operation of the plurality of memory cells, It is equipped with, The aforementioned control circuit is In response to a first set of read commands, the system obtains a first determination result of the threshold voltages of the plurality of memory cells based on a first read level relating to a first threshold voltage distribution, and a second determination result of the threshold voltages of the plurality of memory cells based on a first low-voltage offset read level obtained by offsetting the first read level to the low-voltage side. The first number of mismatches between the first determination result and the second determination result is obtained, Based on the first mismatch number, a first correction amount for the first readout level is calculated. It is configured in such a way. Memory device.

16. The aforementioned control circuit is A third determination result of the threshold voltage of the plurality of memory cells is obtained based on a first high-voltage offset read level obtained by offsetting the first read level to the high-voltage side, Obtain the second number of mismatches between the first determination result and the third determination result. The first correction amount is calculated according to the relative magnitudes of the first number of mismatches and the second number of mismatches. It is further configured in the following way: The memory device according to claim 15.

17. If the first number of mismatches is greater than the second number of mismatches, the control circuit sets the first correction amount to a value that shifts the first readout level to the high-voltage side. If the first number of mismatches is less than the second number of mismatches, the control circuit sets the first correction amount to a value that shifts the first readout level to the low voltage side. The memory device according to claim 16.

18. The control circuit calculates the first correction amount in parallel with the output of the data based on the first determination result. The memory device according to claim 15.

19. The aforementioned control circuit is Perform a first exclusive OR operation between the first determination result and the second determination result. Based on the number of "1"s in the result of the first exclusive OR operation, the first mismatch count is obtained. The memory device according to claim 15.

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