Memory device and its operating method

Abstract

The present invention provides a memory device and its operating method that prevent disturbance by adjusting the precharge time of the channel film according to the size of the selected memory cell during program operation. [Solution] In a memory system, the memory device 100 includes a voltage generator that generates a program voltage and a path voltage applied to a word line WL, a source line driver that generates a precharge voltage applied to a source line, a page buffer group that generates a program-allowable voltage and a program-prohibited voltage applied to a bit line BL, and a control circuit that sets a reference position that distinguishes between areas where disturbance occurs and areas where it does not occur in memory blocks BLK1 to BLKj, and controls the voltage generator, source line driver and page buffer group to adjust the time for precharging the channel film during program operation according to the result of comparing the position of the selected word line with the reference position.

Description

Technical Field

[0001] The present invention relates to a memory device and an operation method thereof, and more specifically, to a memory device configured to execute a program operation and an operation method thereof.

Background Art

[0002] A memory device configured to store data can include a memory cell array, peripheral circuits, and a control circuit. The memory cell array can include memory blocks, and the memory blocks can include memory cells in which data is stored. The peripheral circuits can be configured to program, read, or erase the memory cells according to the control of the control circuit. The control circuit can control the peripheral circuits so that a program operation, a read operation, or an erase operation is executed in response to a command.

[0003] The memory block can be realized in a 2D structure or a 3D structure according to the array structure of the memory cells.

[0004] In a memory block realized in a 2D structure, the memory cells can be arranged in a direction parallel to the substrate. Therefore, the area of the memory block realized in a 2D structure increases as the number of memory cells increases.

[0005] In a memory block realized in a 3D structure, the memory cells can be arranged in a direction parallel to the substrate and can also be stacked in a direction perpendicular to the substrate. Therefore, the memory block realized in a 3D structure can further include stacked memory cells more than the memory block realized in a 2D structure.

[0006] In a memory block realized in a 3D structure, the memory cells can be stacked along a plug extending in a direction perpendicular to the substrate. The plug can include a channel film and a charge trap film extending in the vertical direction.

[0007] Due to the manufacturing process characteristics of memory devices, the width of the plug can narrow towards the bottom. Therefore, the electrical characteristics of memory cells can vary depending on their location. For example, during the programmed operation of a selected memory cell, a disturbance—a change in the threshold voltage of unselected memory cells—may occur more frequently with smaller memory cells. Such disturbances can reduce the reliability of the memory device. [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] An embodiment of the present invention provides a memory device and its operating method that can prevent disturbance by adjusting the precharge time of the channel film according to the size of the selected memory cell during program operation. [Means for solving the problem]

[0009] A memory device according to an embodiment of the present invention includes a memory block comprising a first selection line, a word line, and a second selection line stacked between a source line and a bit line, a channel film penetrating the first selection line, the word line, and the second selection line, and stacked along the channel film, comprising a first selection transistor connected to the first selection line, a second selection transistor connected to the second selection line, and a memory cell connected to the word line; a voltage generator configured to generate turn-on and turn-off voltages applied to the first and second selection lines, and program and pass voltages applied to the word line; a source line driver configured to generate a precharge voltage applied to the source line; a page buffer group configured to generate program-allowable and program-prohibited voltages applied to the bit line; and a control circuit configured to set a reference position in the memory block that separates a region where disturbance occurs from a region where disturbance does not occur, and to control the voltage generator, the source line driver, and the page buffer group such that the time for precharging the channel film is adjusted during program operation of the memory block according to the result of comparing the position of the selected word line with the reference position.

[0010] The operation method of a memory device according to an embodiment of the present invention includes the steps of: dividing a plurality of word lines stacked between a source line and a bit line into a first group and a second group according to the width of plugs that penetrate the word lines (the width of the plugs included in the second group is narrower than the width of the plugs included in the first group); precharging the channel film included in the plugs; applying a path voltage to the word lines after the precharging of the channel film; and applying a program voltage to a selected word line after the path voltage has been applied to the word lines, wherein if the selected word line is included in the second group, the precharging of the channel film is performed for a first time; and if the selected word line is included in the first group, the precharging of the channel film is performed for a second time, which is shorter than the first time. [Effects of the Invention]

[0011] This technology prevents disturbances during program operation on the memory device, thereby shortening program execution time. [Brief explanation of the drawing]

[0012] [Figure 1] This is a diagram to explain the memory system. [Figure 2] This is a diagram illustrating the basic structure of a memory device. [Figure 3] This is a diagram illustrating the memory device according to the present invention. [Figure 4] This is a diagram illustrating a memory cell array. [Figure 5] This is a circuit diagram illustrating a memory block. [Figure 6] This is a cross-sectional view illustrating the structure of the string. [Figure 7] This is a plan view illustrating the structure of the string. [Figure 8] This is a diagram illustrating the path through which the operating voltage is transmitted. [Figure 9a] This is a diagram for explaining a word line group according to an embodiment of the present invention. [Figure 9b] This is a diagram for explaining a word line group according to an embodiment of the present invention. [Figure 10a] This is a diagram for explaining a programming method according to the first embodiment of the present invention. [Figure 10b] This is a diagram for explaining a programming method according to the first embodiment of the present invention. [Figure 11a] This is a diagram for explaining a programming method according to the second embodiment of the present invention. [Figure 11b] This is a diagram for explaining a programming method according to the second embodiment of the present invention. [Figure 12] This is a diagram for explaining a word line group according to another embodiment of the present invention [Figure 13a] This is a diagram for explaining a programming method according to the third embodiment of the present invention. [Figure 13b] This is a diagram for explaining a programming method according to the third embodiment of the present invention. [Figure 13c] This is a diagram for explaining a programming method according to the third embodiment of the present invention. [Figure 14a] This is a diagram for explaining a programming method according to the fourth embodiment of the present invention. [Figure 14b] This is a diagram for explaining a programming method according to the fourth embodiment of the present invention. [Figure 14c] This is a diagram for explaining a programming method according to the fourth embodiment of the present invention. [Figure 15] This is a diagram for explaining a memory card system to which a memory device according to an embodiment of the present invention is applied. [Figure 16] This is a diagram for explaining a SSD (Solid State Drive) system to which a memory device according to an embodiment of the present invention is applied.

Embodiments for Carrying Out the Invention

[0013] The specific structural or functional descriptions disclosed below are illustrative to illustrate embodiments of the concept of the present invention. Embodiments of the concept of the present invention are not construed as being limited to the embodiments described below and can be modified in various ways and replaced by other equivalent embodiments.

[0014] In the following, terms such as "First" and "Second" may be used to describe various components, but the components are not limited to those terms. The terms are used for the purpose of distinguishing one component from another.

[0015] Figure 1 is a diagram illustrating the memory system.

[0016] Referring to Figure 1, the memory system 1000 may include a memory device 100, a controller 200, and a host 300.

[0017] The memory device 100 can be configured to store data. The memory device 100 can be a non-volatile memory device. A non-volatile memory device is a device that retains stored data even when the power supply is cut off.

[0018] The controller 200 can be configured to communicate between the host 300 and the memory device 100. The controller 200 can be configured to control the memory device 100 in response to requests from the host 300. For example, when the controller 200 receives a request (RQ) for a program from the host 300, it can generate a command (CMD) for the program and transmit the command (CMD) to the memory device 100. When the controller 200 receives a request (RQ) for a read from the host 300, it can generate a command (CMD) for the read and transmit the command (CMD) to the memory device 100. During a read operation, when data (DATA) is output from the memory device 100, the controller 200 can perform an error correction operation on the read data (DATA). In the error correction operation, the read data (DATA) can be decoded in chunks.

[0019] The host 300 can communicate with the memory device 100 via the controller 200 using interface protocols such as PCI-E (Peripheral Component Interconnect - Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), or SAS (serial attached SCSI). The interface protocols are not limited to the examples above and can include various interfaces such as USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics).

[0020] When the host 300 transmits data along with a request RQ corresponding to the program to the controller 200, the controller 200 can generate a command CMD corresponding to the program in response to the request RQ. The command CMD and data DATA corresponding to the program can be transmitted to the memory device 100, and the memory device 100 can program the data in response to the command CMD.

[0021] The memory device 100 according to this embodiment can adjust the channel precharge time according to the size of the memory cells contained in the selected page during the program operation of the selected page of the selected memory block, in order to shorten the time required for program operation and prevent disturbance. Disturbance during program operation refers to the characteristic that the threshold voltage of unselected memory cells is affected by the program operation of the selected memory cells. Therefore, the more disturbance is suppressed, the higher the reliability of the memory device can be. A page can be a group of memory cells linked to the same word line within a memory block. Therefore, different pages contained in the same memory block can be located at different heights. The size of the memory cells can vary depending on the page. The smaller the size of the memory cell, the smaller the size of the channel contained in the memory cell can be. In the program operation according to this embodiment, the program operation can be set so that the channel precharge time increases as the size of the memory cell decreases. The channel precharge stage can be a stage that is executed before the path voltage is applied to the word line. In the channel precharge stage, a positive precharge voltage can be applied to the channel. The program operation can be configured so that the larger the memory cell sites included in the selected page, the shorter the panel precharge time.

[0022] Therefore, according to this embodiment, the channel precharge time can be shortened during the programming of pages with large memory cell sizes, and disturbances can be suppressed during the programming of pages with small memory cell sizes.

[0023] Figure 2 is a diagram illustrating the memory device in general terms.

[0024] Referring to Figure 2, the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control circuit 130.

[0025] The memory cell array 110 can be configured to store data. The peripheral circuit 120 can be configured to perform program, read, or erase operations in response to the control circuit 130. The control circuit 130 can be configured to control the peripheral circuit 120 in response to a command CMD output from the controller (200 in Figure 1). For example, the peripheral circuit 120 can be configured to receive data from the controller 200 in response to the control circuit 130 and to program the received data into a selected memory block of the memory cell array 110.

[0026] The program operation of the selected memory block can be executed on a page-by-page basis. When the selected page is located above the reference position, the control circuit 130 can control the peripheral circuit 120 so as to shorten the channel film precharge time. When the selected page is located below the reference position, the control circuit 130 can control the peripheral circuit 120 so as to lengthen the channel film precharge time. To determine the channel film precharge time, the control circuit 130 can compare the position of the selected page with the reference position before precharging the channel film. The reference position information can be pre-stored in the control circuit 130 during the manufacturing stage of the memory device, and the reference position information can be changed even after the manufacturing stage of the memory device. The reference position can be set by areas in the memory block that are affected by disturbance and areas that are not, or by areas where the plug width is wider than the reference width and areas where it is narrower than the reference width.

[0027] Figure 3 is a diagram illustrating the memory device according to the present invention.

[0028] Referring to Figure 3, the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control circuit 130.

[0029] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj, where 'j' is a positive integer. Each of the first to j-th memory blocks BLK1 to BLKj may contain a memory cell capable of storing data. Each of the first to j-th memory blocks BLK1 to BLKj may be connected to a drain selection line DSL, a word line WL, a source selection line SSL, a source line SL, and a bit line BL. The drain selection line DSL, the word line WL, and the source selection line SSL may be connected to the first to j-th memory blocks BLK1 to BLKj, respectively, while the source line SL and the bit line BL may be connected to the first to j-th memory blocks BLK1 to BLKj in common.

[0030] The first to jth memory blocks, BLK1 to BLKj, can be formed in a three-dimensional structure. A memory block having a three-dimensional structure may include memory cells stacked perpendicularly from the substrate. Depending on the programming method, memory cells can store one bit or two or more bits of data. For example, a method in which one memory cell stores one bit of data is called a single-level cell (SLC) method, and a method in which two or more bits of data are stored is called a multi-level cell (MLC) method. In the multi-level cell (MLC) method, a method in which three bits of data are stored in one memory cell is called a triple-level cell (TLC) method, and a method in which four bits of data are stored is called a quad-level cell (QLC) method. In addition, five or more bits of data can also be stored in one memory cell.

[0031] The peripheral circuit 120 can be configured to perform program operations for storing data in the memory cell array 110, read operations for outputting data stored in the memory cell array 110, and erase operations for erasing data stored in the memory cell array 110, in response to the control circuit 130. For example, the peripheral circuit 120 may include a voltage generator 21, a row decoder 22, a source line driver 23, a page buffer group 24, a column decoder 25, and an input / output circuit 26.

[0032] The voltage generator 21 can generate various operating voltages Vop used for program, read, or erase operations in response to the operation code OPCD. For example, the voltage generator 21 can be configured to generate program voltage, turn-on voltage, turn-off voltage, verify voltage, read voltage, pass voltage, or erase voltage in response to the operation code OPCD. Each of the operating voltages Vop generated by the voltage generator 21 can have various levels. The operating voltages Vop can be applied to the drain selection line DSL, word line WL, and source selection line SSL of the selected memory block via the raw decoder 22. The operating voltages Vop can include program voltage, turn-on voltage, turn-off voltage, verify voltage, read voltage, and pass voltage.

[0033] The program voltage is a voltage applied to a selected word line WL during a program operation and can be used to increase the threshold voltage of the memory cell connected to the selected word line. The turn-on voltage can be applied to a drain selection line DSL or a source selection line SSL and can be used to turn on the drain selection transistor or a source selection transistor. The turn-off voltage can be applied to a drain selection line DSL or a source selection line SSL and can be used to turn off the drain selection transistor or a source selection transistor. The verification voltage can be used during a verification operation to determine whether the threshold voltage of the selected memory cell has risen to a target level. The verification voltage can be set to various levels depending on the target level and can be applied to the selected word line. The read voltage can be applied to a selected word line during a read operation of the selected memory cell. For example, the read voltage can be set to various levels depending on the programming scheme of the selected memory cell. The pass voltage is a voltage applied to an unselected word line WL during a program or read operation and can be used to turn on the memory cell connected to the unselected word line.

[0034] The low decoder 22 can be configured to transmit an operating voltage Vop to a drain selection line DSL, a word line WL, and a source selection line SSL connected to a selected memory block, depending on the low address RADD. For example, the low decoder 22 can be connected to a voltage generator 21 via global lines, and to the first to jth memory blocks BLK1 to BLKj via local lines including a drain selection line DSL, a word line WL, and a source selection line SSL.

[0035] The source line driver 23 can be configured to generate and output a precharge voltage or ground voltage applied to the source line SL in response to the source code SCD. If the first to j-th memory blocks BLK1 to BLKj included in the memory cell array 110 are contained in one plane, the source line SL can be connected in common to the first to j-th memory blocks BLK1 to BLKj contained in the plane. If the first to j-th memory blocks BLK1 to BLKj are contained in two or more planes, the source line SL can be connected to each of the planes, and the source line driver 23 can apply a precharge voltage or ground voltage to the source line SL connected to the selected plane, and apply a ground voltage to the source line SL connected to the unselected plane, or cause the source line SL to float.

[0036] The page buffer group 24 may include page buffers (not shown) connected to the first to j-th memory blocks BLK1 to BLKj via bit lines BL. During program operation, the page buffer group 24 can selectively apply program-allowable voltage and program-prohibited voltage to bit lines BL in response to the page buffer control signal PBSIG. For example, the page buffer group 24 can apply a program-allowable voltage to selected bit lines and a program-prohibited voltage to unselected bit lines. During verification operation, the page buffer group 24 can sense the current or voltage of bit lines BL and store data in memory cells.

[0037] The column decoder 25 can be configured to transmit data between the page buffer group 24 and the input / output circuit 26 in response to the column address CADD. For example, the column decoder 25 can be connected to the page buffer group 24 via column lines CL, and can transmit an enable signal to each of the page buffers (not shown) via column lines CL. The page buffers (not shown) included in the page buffer group 24 can receive or output data via data lines DL in response to the enable signal.

[0038] The input / output circuit 26 can be configured to receive or output commands CMD, addresses ADD, or data via input / output line I / O. For example, the input / output circuit 26 can transmit commands CMD and addresses ADD received from the controller (200 in Figure 1) via input / output line I / O to the control circuit 130, and can transmit data DATA received from the controller (200 in Figure 1) via input / output line I / O to the page buffer group 24. Alternatively, the input / output circuit 26 can output data transmitted from the page buffer group 24 to the controller (200 in Figure 1) via input / output line I / O.

[0039] The control circuit 130 can output an operation code OPCD, a low address RADD, a source code SCD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, if the command CMD input to the control circuit 130 corresponds to a program operation, the control circuit 130 can control the devices included in the peripheral circuit 120 so that the program operation of the memory block selected by address ADD is executed. If the command CMD input to the control circuit 130 corresponds to a read operation, the control circuit 130 can control the devices included in the peripheral circuit 120 so that the read operation of the memory block selected by address is executed and the read data is output. If the command CMD input to the control circuit 130 corresponds to an erase operation, the control circuit 130 can control the peripheral circuit 120 so that the erase operation of the selected memory block is executed.

[0040] During program operation, the control circuit 130 can control the peripheral circuit 120 so that the channels of the selected memory block are precharged before applying a path voltage to the unselected word lines. The reason for precharging the channels is to prevent a decrease in channel boosting of the unselected string, as failure to properly perform channel boosting in the channels of the unselected string can cause a disturbance that changes the threshold voltage of the unselected memory cell.

[0041] Since disturbance is more likely to occur with smaller memory cell sizes, the control circuit 130 in this embodiment can adjust the channel precharge time according to the position of the selected word line. For example, the control circuit 130 can control the peripheral circuit 120 so that the channel precharge time is shortened when the selected word line is located above the reference position. The control circuit 130 can control the peripheral circuit 120 so that the channel precharge time is lengthened when the selected word line is located below the reference position. The channel can be precharged by supplying a precharge voltage to the channel via the source line SL, or by supplying a precharge voltage to the channel via the bit line BL.

[0042] Figure 4 is a diagram illustrating the memory cell array.

[0043] Referring to Figure 4, the memory cell array 110 can include first to j-th memory blocks BLK1 to BLKj. The first to j-th memory blocks BLK1 to BLKj can be spaced apart from each other along the Y direction and can be located between the source line SL and the first to i-th bit lines BL1 to BLi, where 'i' is a positive integer. Each of the first to j-th memory blocks BLK1 to BLKj can be connected to a drain selection line DSL, a word line WL, and a source selection line SSL. An operating voltage (Vop in Figure 3) can be applied via the drain selection line DSL, word line WL, and source selection line SSL connected to the selected memory block from the first to j-th memory blocks BLK1 to BLKj, while the drain selection line DSL, word line WL, and source selection line SSL connected to the remaining unselected memory blocks can be floated.

[0044] In the channel precharge stage according to this embodiment, the channels of the selected memory block can be precharged by a voltage supplied via the source line SL or the first to i-th bit lines BL1 to BLi. When the precharge voltage is supplied to the channel via the source line SL, the channel precharge time can be adjusted by adjusting the time for which the turn-on voltage is applied to the source selection line SSL. The channel precharge time can also be adjusted by adjusting the time for which the turn-on voltage is applied to the drain selection line DSL.

[0045] Figure 5 is a circuit diagram illustrating the memory block.

[0046] Referring to Figure 5, since the memory blocks are configured similarly to each other, the j-th memory block BLKj is used as an example. The j-th memory block BLKj may include a string ST connected between the source line SL and the first to i-th bit lines BL1 to BLi. The string ST is commonly connected to the source line SL, commonly connected to each of the first to i-th bit lines BL1 to BLi, and can be connected to each of the distinct first to i-th bit lines BL1 to BLi. The string ST can be arranged spaced apart from each other along the X and Y directions and can extend along the Z direction. The first to i-th bit lines BL1 to BLi can be arranged spaced apart from each other along the X direction, and each of the first to i-th bit lines BL1 to BLi can extend along the Y direction. The number of source selection transistors SST, first to n-th memory cells M1 to Mn, and drain selection transistors DST included in each string ST may vary depending on the memory device. For example, Figure 3 shows that each string ST contains one source selection transistor SST and one drain selection transistor DST, but it may contain multiple source selection transistors SST and drain selection transistors DST.

[0047] The gates of source selection transistors SST contained in different strings ST can be connected to source selection lines SSL, the gates of the first to nth memory cells M1 to Mn can be connected to the first to nth word lines WL1 to WLn, and the gates of drain selection transistors DST can be connected to the first to fifth drain selection lines DSL1 to DSL5, where 'n' is a positive integer. The number of the first to fifth drain selection lines DSL1 to DSL5 is not limited to the number shown in the diagram.

[0048] Source selection lines SSL can be commonly connected to source selection transistors SST arranged along the X and Y directions, although some source selection lines SSL arranged along the Y direction may be separated from each other. Each of the first to nth word lines WL1 to WLn can be commonly connected to memory cells arranged along the X and Y directions. For example, the nth memory cell Mn arranged along the X and Y directions can be commonly connected to the nth word line WLn, and the nth word lines WLn can be connected to each other. For example, the (n-1)th memory cell M(n-1) arranged along the X and Y directions can be commonly connected to the (n-1)th word line WL(n-1), and the (n-1)th word lines WL(n-1) can be connected to each other. The nth word line WLn and the (n-1)th word line WL(n-1) are separated from each other. A group of memory cells commonly connected to any one of the first to nth word lines WL1 to WLn becomes a page PG. For example, the fourth memory cell M4, which is commonly linked to the fourth word line WL4, becomes one page PG. Program operations can be executed on a page PG basis. If the fourth word line WL4 is a selected word line, the remaining word lines become unselected word lines.

[0049] The first to fifth drain selection lines DSL1 to DSL5 are spaced apart from each other. Each of the first to fifth drain selection lines DSL1 to DSL5 can be connected in common to a drain selection transistor DST arranged in the X direction. Therefore, during program or read operation, memory cells included in the string ST connected to the selected drain selection line from the first to fifth drain selection lines DSL1 to DSL5 can be selected.

[0050] The voltage supplied to source line SL can be applied to the channel of string ST when source selection transistor SST is turned on, and can electrically disconnect source line SL and string ST when source selection transistor SST is turned off. Source selection transistor SST can be turned on when a turn-on voltage is applied to source selection line SSL, and can be turned off when a turn-off voltage is applied. The turn-on voltage can be a positive voltage higher than 0V, and the turn-off voltage can be the ground voltage or a negative voltage lower than 0V. Therefore, when the channel is precharged via source line SL, the precharge time can be changed depending on the time the turn-on voltage is applied to source selection line SSL.

[0051] The voltage supplied to the first to i-th bit lines BL1 to BLi can be applied to the channel of string ST when the drain selection transistor DST is turned on, and when the drain selection transistor DST is turned off, the first to i-th bit lines BL1 to BLi and string ST can be electrically disconnected. Taking the drain selection transistor DST connected to the first drain selection line DSL1 as an example, the drain selection transistor DST can be turned on when a turn-on voltage is applied to the first drain selection line DSL1, and can be turned off when a turn-off voltage is applied. The turn-on voltage applied to the first drain selection line DSL1 can be a positive voltage higher than 0V, and the turn-off voltage can be the ground voltage or a negative voltage lower than 0V. Therefore, when the channel is precharged via the first to i-th bit lines BL1 to BLi, the precharge time can be changed depending on the time the turn-on voltage is applied to the first drain selection line DSL1.

[0052] Figure 6 is a cross-sectional view illustrating the structure of the string, and Figure 7 is a plan view illustrating the structure of the string.

[0053] Referring to Figures 6 and 7, the string ST may include a plug PL that penetrates the source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL, which are stacked spaced apart from each other. The source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL may be formed from metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si). The plug PL may extend along the Z direction between the source line SL and the ith bit line BLi. A bit line contact Cb may be located between the plug PL and the ith bit line BLi.

[0054] The plug PL may include a core pillar CP, a channel layer CH, a tunnel isolation layer TX, a charge trap layer CTL, and a blocking layer BX. The core pillar CP may have a cylindrical, rectangular, or polygonal shape and may be made of an insulating or conductive material. The channel layer CH surrounds the core pillar CP and may be made of polysilicon. The tunnel isolation layer TX surrounds the channel layer CH and may be made of an oxide film. The charge trap layer CTL surrounds the tunnel isolation layer TX and may be made of a nitride film. The blocking layer BX surrounds the charge trap layer CTL and may be made of an oxide film. The lower part of the channel layer CH may be in contact with the source line SL, and the upper part may be in contact with the bit line contact Cb. The bit line contact Cb may be located between the i-th bit line BLi and the plug PL.

[0055] A plug PL extending in the Z direction can have different widths depending on its height due to the characteristics of the manufacturing process. Specifically, the upper width of the plug PL can be wider than the lower width. In other words, the width of the plug PL can become narrower from top to bottom. For example, if the first word line WL1 is located at the bottom and the nth word line WLn is located at the top of the first to nth word lines WL1 to WLn connected to the string ST, and assuming that the part of the plug PL in contact with the nth word line WLn has a first width W1, then the part of the plug PL in contact with the first word line WL1 can have a second width W2 that is narrower than the first width W1.

[0056] Figure 7 shows the planar structure of the plug PL cut in the A1-A2 direction.

[0057] Referring to Figure 7, the plug PL can include a core pillar CP, a channel film CH, a tunnel insulating film TX, a charge trap film CTL, and a blocking film BX. The channel film CH can enclose the core pillar CP. The tunnel insulating film TX can enclose the channel film CH. The charge trap film CTL can enclose the tunnel insulating film TX. The blocking film BX can enclose the charge trap film CTL. The word line WL can enclose the blocking film BX.

[0058] Figure 8 is a diagram illustrating the path through which the operating voltage is transmitted.

[0059] Referring to Figure 8, the voltage generator 21 may include a first selection line driver 1SLD, a word line driver WLD, and a second selection line driver 2SLD.

[0060] The first selection line driver 1SLD can be configured to generate a voltage applied to the source selection line SSL and output the generated voltage via the global source selection line GSSL. For example, the first selection line driver 1SLD can be configured to selectively generate a turn-on voltage Von and a turn-off voltage Voff in response to an operation code OPCD.

[0061] A word line driver (WLD) can be configured to generate a word line voltage (Vwl) to be applied to each word line (WL) and to output the word line voltage (Vwl) via a global word line (GWL). For example, a word line driver (WLD) can be configured to generate a word line voltage (Vwl) to be applied to a selected word line in response to an operation code (OPCD). The word line voltage (Vwl) may include a program voltage and a path voltage.

[0062] The second selection line driver 2SLD can be configured to generate a voltage applied to the drain selection line DSL and output the generated voltage via the global drain selection lines GDSL. For example, the second selection line driver 2SLD can be configured to selectively generate a turn-on voltage Von and a turn-off voltage Voff in response to an operation code OPCD.

[0063] The low decoder 22 can be configured to respond to a low-address RADD by selecting one memory block from among the memory blocks included in the memory cell array 110, connecting the drain selection line DSL and the global drain selection line GDSL connected to the selected memory block, connecting the word line WL and the global word line GWL connected to the selected memory block, and connecting the source selection line SSL and the global source selection line GSSL connected to the selected memory block. Thus, the turn-on voltage Von or turn-off voltage Voff applied to the global drain selection line GDSL can be applied to the drain selection line DSL, the word line voltage Vwl applied to the global word line GWL can be applied to the word line WL, and the turn-on voltage Von or turn-off voltage Voff applied to the global source selection line GSSL can be applied to the source selection line SSL.

[0064] The source line driver 23 can be configured to generate a precharge voltage Vpre or ground voltage Vgnd higher than 0V in response to the source code SCD, and to apply the precharge voltage Vpre or ground voltage Vgnd to the source line SL.

[0065] Figures 9a and 9b are diagrams illustrating a wordline group according to an embodiment of the present invention.

[0066] Referring to Figure 9a, if we take a structure in which the first to eighteenth word lines WL1 to WL18 are connected to a memory block as an example, the first to eighteenth word lines WL1 to WL18 can be divided into a first group 1GR and a second group 2GR. The first and second groups 1GR and 2GR can be divided according to a reference position REF. If the reference position REF is defined between the sixth and seventh word lines WL6 and WL7, then the seventh to eighteenth word lines WL7 to WL18, which are located above the reference position REF, can be included in the first group 1GR, and the first to sixth word lines WL1 to WL6, which are located below the reference position REF, can be included in the second group 2GR. The reference position REF can be set differently depending on the memory device. For example, the reference position REF can be set in a narrow area of ​​the plug PL. For example, the reference position REF can be set according to the disturbance of memory cells included in the plug PL. For example, the boundary between a region where disturbances that could affect the reliability of program operation may occur and a region where disturbances that occur do not affect reliability can be set as the reference position REF. Smaller memory cells (e.g., located within the second group 2GR) may be more vulnerable to disturbances than larger memory cells (e.g., located within the first group 1GR). For example, disturbances may occur when the critical voltage of an unselected memory cell changes while a program operation is being performed on one or more selected memory cells. For example, disturbances may occur when one or more selected and unselected memory cells have relatively small sizes (e.g., when they are linked to a word line located below the reference position REF).

[0067] Referring to Figure 9b, the reference position REF can be defined between the first and second word lines WL1 and WL2. Therefore, the first group 1GR may include the second to 18th word lines WL2 to WL18, and the second group 2GR may include the first word line WL1.

[0068] Figures 10a and 10b are diagrams illustrating a programming method according to a first embodiment of the present invention.

[0069] Figure 10a is a diagram illustrating the programming method when the selected word line Sel_WL is included in the first group (1GR in Figure 9a or Figure 9b) during program operation, and Figure 10b is a diagram illustrating the programming method when the selected word line Sel_WL is included in the second group (2GR in Figure 9a or Figure 9b) during program operation.

[0070] Referring to Figure 10a, the program operation can include a precharge stage PRE, a boosting stage BS, a program stage PGM, and a verification stage VF. In the precharge stage PRE, an operation is performed to increase the potential of the channel film CH. In the boosting stage BS, an operation is performed to further increase the potential of the channel film CH using the pass voltage Vpass. In the program stage PGM, an operation is performed to increase the threshold voltage of the selected memory cell. In the verification stage VF, an operation is performed to determine whether the threshold voltage of the memory cell has risen to the target voltage. The features of this embodiment are in the precharge stage PRE, the boosting stage BS, and the program stage PGM, so the explanation of the verification stage VF after the program stage PGM is omitted.

[0071] When the precharge stage PRE is initiated, a turn-off voltage Voff is applied to the drain selection line DSL, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated. When the precharge voltage Vpre is applied to the source line SL and the turn-on voltage Von is applied to the source selection line SSL, the source selection transistor is turned on, so that the source line SL and the channel film CH can be electrically coupled. Thus, the precharge voltage Vpre applied to the source line SL can be supplied to the channel film CH. As a result, the potential of the channel film CH can have the level of the precharge voltage Vpre.

[0072] The pre-charge stage PRE can be performed during a first time interval T1 in which the turn-on voltage Von is applied to the source selection line SSL. For example, the first time interval T1 may be the time from when the source selection transistor is turned on to when it is turned off.

[0073] Once the pre-charge phase (PRE) is complete, the boosting phase (BS) can be executed.

[0074] When the boosting phase BS is initiated, the turn-off voltage Voff is applied to the source selection line SSL, the program-blocking voltage Vinh or program-allowing voltage Val is applied to the bit line BL, the turn-on voltage Von is applied to the drain selection line DSL, and the pass voltage Vpass may be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The turn-off voltage Voff can be set to ground voltage or 0V. The program-blocking voltage Vinh is a positive voltage higher than 0V and is used to prevent the threshold voltage of unselected memory cells from being raised by the program voltage. The program-allowing voltage Val can be set to ground voltage or 0V.

[0075] When the turn-on voltage Von is applied to the drain selection line DSL, the drain selection transistor can be turned on. When the drain selection transistor is turned on, the channel film CH and the bit line BL are electrically coupled to each other. When the program allowance voltage Val is applied to the bit line BL, the voltage of the channel film CH can be lowered by the program allowance voltage Val. When the program disable voltage Vinh is applied to the bit line BL, the voltage of the channel film CH is not lowered by the program disable voltage Vinh, but can be boosted by the pass voltage Vpass applied to the selected word line Sel_WL and the unselected word line Unsel_WL. Therefore, when the program disable voltage Vinh is applied to the bit line BL, the potential of the channel film CH can be raised to a boosting voltage Vbs that is higher than the precharge voltage Vpre.

[0076] Once the boosting phase (BS) is complete, the program phase (PGM) can be started.

[0077] When the programming stage (PGM) is initiated, a programming voltage Vpgm higher than the pass voltage Vpass can be applied to the selected word line Sel_WL. Memory cells connected to a channel film CH with a potential lower than the precharge voltage Vpre are programmed by the voltage difference between the channel film CH and the selected word line Sel_WL. Memory cells connected to a channel film CH with a boosting voltage Vbs are not programmed by the boosting voltage Vbs.

[0078] When the programming phase (PGM) is completed, the bit line BL, drain selection line DSL, selected word line Sel_WL, unselected word line Unsel_WL, channel membrane CH, source selection line SSL, and source line SL can be discharged. Then, the verification phase (VF) can be performed.

[0079] Referring to Figure 10a, the program operation when the selected word line Sel_WL is included in the first group 1GR is explained. Referring to Figure 10b, the program operation when the selected word line Sel_WL is included in the second group 2GR is explained.

[0080] Referring to Figure 10b, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 10a, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0081] If the selected word line Sel_WL is included in the disturb-vulnerable second group 2GR, the duration for which the precharge stage PRE is performed can be set to a second time T2 that is longer than the first time T1, in order to reduce the effects of the disturbance. The longer the precharge stage PRE is performed, the more sufficiently the precharge voltage Vpre can be transmitted to the channel film CH, so that the boosting of the channel film CH can occur effectively in the boosting stage BS performed after the precharge stage PRE. Therefore, disturbance can be prevented during the programmed operation of the second group 2GR, which has a relatively small memory cell size.

[0082] As described above, if the selected word line Sel_WL is in the first group 1GR, which is not affected by disturb, the time required for program operation can be reduced by shortening the time required for the precharge stage PRE. If the selected word line Sel_WL is in the second group 2GR, which is affected by disturb, the reliability of program operation can be improved by increasing the time required for the precharge stage PRE.

[0083] Figures 11a and 11b are diagrams illustrating a programming method according to a second embodiment of the present invention.

[0084] In the first embodiment described with reference to Figures 10a and 10b, the channel membrane CH was precharged via the source line SL, but in the second embodiment, the channel membrane CH can be precharged via the bit line BL.

[0085] Figure 11a is a diagram illustrating the programming method when the selected word line Sel_WL is included in the first group (1GR in Figure 9a or Figure 9b) during program operation, and Figure 11b is a diagram illustrating the programming method when the selected word line Sel_WL is included in the second group (2GR in Figure 9a or Figure 9b) during program operation.

[0086] Referring to Figure 11a, the program operation can include a precharge stage PRE, a boosting stage BS, a program stage PGM, and a verification stage VF. In the precharge stage PRE, an operation is performed to increase the potential of the channel film CH. In the boosting stage BS, an operation is performed to further increase the potential of the channel film CH using the pass voltage Vpass. In the program stage PGM, an operation is performed to increase the threshold voltage of the selected memory cell. In the verification stage VF, an operation is performed to determine whether the threshold voltage of the memory cell has risen to the target voltage. The features of this embodiment are in the precharge stage PRE, the boosting stage BS, and the program stage PGM, so the explanation of the verification stage VF after the program stage PGM will be omitted.

[0087] When the precharge stage PRE begins, a turn-off voltage Voff is applied to the source selection line SSL, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated. The source line SL can be supplied with either a ground voltage Vgnd or a precharge voltage Vpre. The bit line BL can be supplied with a precharge voltage Vpre. The precharge voltage Vpre applied to the bit line BL may be the same as or different from the precharge voltage Vpre applied to the source line SL. The drain selection line DSL can be supplied with a turn-on voltage Von. When the turn-on voltage Von is applied to the drain selection line DSL, the drain selection transistor is turned on, so that the bit line BL and the channel film CH can be electrically coupled. Therefore, the precharge voltage Vpre applied to the bit line BL can be supplied to the channel film CH. As a result, the potential of the channel film CH can have the level of the precharge voltage Vpre. The precharge stage PRE can be performed for a first time T1 after the precharge voltage Vpre is applied to the bit line BL and the turn-on voltage Von is applied to the drain selection line DSL. For example, the first time T1 may be the time from when the drain selection transistor is turned on until when the program-allowable voltage Val or program-blocking voltage Vinh begins to be applied to the bit line BL.

[0088] Once the pre-charge phase (PRE) is complete, the boosting phase (BS) can be executed.

[0089] When the boosting phase BS begins, a program-blocking voltage Vinh or program-allowing voltage Val is applied to the bit line BL, and a pass voltage Vpass may be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The program-blocking voltage Vinh is a positive voltage higher than 0V and is used to prevent the threshold voltage of the unselected memory cell from being raised by the program voltage. The program-allowing voltage Val can be set to ground voltage or 0V.

[0090] Since the turn-on voltage Von is continuously applied to the drain selection line DSL, the drain selection transistor can be kept in the turn-on state. When the program allowance voltage Val is applied to the bit line BL, the voltage of the channel film CH can be lowered by the program allowance voltage Val. When the program disable voltage Vinh is applied to the bit line BL, the voltage of the channel film CH is not lowered by the program disable voltage Vinh, but can be boosted by the pass voltage Vpass applied to the selected word line Sel_WL and the unselected word line Unsel_WL. Therefore, when the program disable voltage Vinh is applied to the bit line BL, the potential of the channel film CH can be higher than the precharge voltage Vpre, reaching a boosting voltage Vbs.

[0091] Once the boosting phase (BS) is complete, the program phase (PGM) can be started.

[0092] When the programming stage (PGM) is initiated, a programming voltage Vpgm higher than the pass voltage Vpass can be applied to the selected word line Sel_WL. Memory cells connected to a channel film CH with a potential lower than the precharge voltage Vpre are programmed by the voltage difference between the channel film CH and the selected word line Sel_WL. Memory cells connected to a channel film CH with a boosting voltage Vbs are not programmed by the boosting voltage Vbs.

[0093] When the programming phase (PGM) is completed, the bit line BL, drain selection line DSL, selected word line Sel_WL, unselected word line Unsel_WL, channel membrane CH, source selection line SSL, and source line SL can be discharged. Then, the verification phase (VF) can be performed.

[0094] Refer to Figure 11a to explain the program operation when the selected word line Sel_WL is included in the first group 1GR. Refer to Figure 11b to explain the program operation when the selected word line Sel_WL is included in the second group 2GR.

[0095] Referring to Figure 11b, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 11a, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0096] If the selected word line Sel_WL is included in the second group 2GR which is vulnerable to disturbance, the time for which the precharge stage PRE is performed can be set to a second time T2 which is longer than the first time T1 in order to prevent disturbance. The longer the precharge stage PRE is performed, the more the precharge voltage Vpre can be sufficiently transmitted to the channel membrane CH, so that the boosting of the channel membrane CH can be effectively performed in the boosting stage BS which is performed after the precharge stage PRE.

[0097] Therefore, during program operation of the second group 2GR, which has a relatively smaller memory cell size, disturbance in the memory cells can be prevented.

[0098] As described above, if the selected word line Sel_WL is in the first group 1GR, which is not affected by disturb, the time required for program operation can be reduced by shortening the time required for the precharge stage PRE. If the selected word line Sel_WL is in the second group 2GR, which is affected by disturb, the reliability of program operation can be improved by increasing the time required for the precharge stage PRE.

[0099] Figure 12 is a diagram illustrating a wordline group according to another embodiment of the present invention.

[0100] Referring to Figure 12, multiple reference positions can be set. For example, a first and second reference position 1REF and 2REF can be set in a single memory block. The first and second reference positions 1REF and 2REF can be set at different heights.

[0101] Taking a memory block structure in which the first to eighteenth word lines WL1 to WL18 are linked as an example, the first to eighteenth word lines WL1 to WL18 can be divided into the first to third groups 1GR to 3GR. The first to third groups 1GR to 3GR can be divided according to the first and second reference positions 1REF and 2REF. If the first reference position 1REF is defined between the sixth and seventh word lines WL6 and WL7, and the second reference position 2REF is defined between the second and third word lines WL2 and WL3, then the seventh to eighteenth word lines WL7 to WL18, which are located above the first reference position 1REF, can be included in the first group 1GR, the third to sixth word lines WL3 to WL6, which are located between the first reference position 1REF and the second reference position 2REF, can be included in the second group 2GR, and the first and second word lines WL1 and WL2, which are located below the second reference position 2REF, can be included in the third group 3GR. The first and second reference positions 1REF and 2REF can be set differently depending on the memory device. For example, the first and second reference positions 1REF and 2REF can be set in a region where the width of the plug PL is narrow. For example, the first and second reference positions 1REF and 2REF can be set according to the disturbance of the memory cells contained in the plug PL. For example, the first reference position 1REF can be set between a region where disturbances that can affect the reliability of program operation may occur and a region where disturbances that occur do not affect reliability, and the second reference position 2REF can be set in order to distinguish the region where the disturbance has a greater impact within the region where disturbances that can affect the reliability of program operation may occur.

[0102] Figures 13a to 13c are diagrams illustrating a programming method according to a third embodiment of the present invention.

[0103] Figure 13a is a diagram illustrating the programming method when the selected word line Sel_WL is included in the first group (1GR in Figure 12) during program operation, Figure 13b is a diagram illustrating the programming method when the selected word line Sel_WL is included in the second group (2GR in Figure 12) during program operation, and Figure 13c is a diagram illustrating the programming method when the selected word line Sel_WL is included in the third group (3GR in Figure 12) during program operation.

[0104] Referring to Figure 13a, the program operation can include a precharge stage PRE, a boosting stage BS, a program stage PGM, and a verification stage VF. In the precharge stage PRE, an operation is performed to increase the potential of the channel film CH. In the boosting stage BS, an operation is performed to further increase the potential of the channel film CH using the pass voltage Vpass. In the program stage PGM, an operation is performed to increase the threshold voltage of the selected memory cell. In the verification stage VF, an operation is performed to determine whether the threshold voltage of the memory cell has risen to the target voltage. The features of this embodiment are in the precharge stage PRE, the boosting stage BS, and the program stage PGM, so the explanation of the verification stage VF after the program stage PGM is omitted.

[0105] When the precharge stage PRE is initiated, a turn-off voltage Voff is applied to the drain selection line DSL, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated. When the precharge voltage Vpre is applied to the source line SL and the turn-on voltage Von is applied to the source selection line SSL, the source selection transistor is turned on, so that the source line SL and the channel film CH can be electrically coupled. Thus, the precharge voltage Vpre applied to the source line SL can be supplied to the channel film CH. As a result, the potential of the channel film CH can have the level of the precharge voltage Vpre.

[0106] The pre-charge stage PRE can be performed during a first time interval T1 in which the turn-on voltage Von is applied to the source selection line SSL. For example, the first time interval T1 may be the time from when the source selection transistor is turned on to when it is turned off.

[0107] Once the pre-charge phase (PRE) is complete, the boosting phase (BS) can be executed.

[0108] When the boosting phase BS is initiated, the turn-off voltage Voff is applied to the source selection line SSL, the program-blocking voltage Vinh or program-allowing voltage Val is applied to the bit line BL, the turn-on voltage Von is applied to the drain selection line DSL, and the pass voltage Vpass may be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The turn-off voltage Voff can be set to ground voltage or 0V. The program-blocking voltage Vinh is a positive voltage higher than 0V and is used to prevent the threshold voltage of unselected memory cells from being raised by the program voltage. The program-allowing voltage Val can be set to ground voltage or 0V.

[0109] When the turn-on voltage Von is applied to the drain selection line DSL, the drain selection transistor can be turned on. When the drain selection transistor is turned on, the channel film CH and the bit line BL are electrically coupled to each other. When the program allowance voltage Val is applied to the bit line BL, the voltage of the channel film CH can be lowered by the program allowance voltage Val. When the program disable voltage Vinh is applied to the bit line BL, the voltage of the channel film CH is not lowered by the program disable voltage Vinh, but can be boosted by the pass voltage Vpass applied to the selected word line Sel_WL and the unselected word line Unsel_WL. Therefore, when the program disable voltage Vinh is applied to the bit line BL, the potential of the channel film CH can be raised to a boosting voltage Vbs that is higher than the precharge voltage Vpre.

[0110] Once the boosting phase (BS) is complete, the program phase (PGM) can be started.

[0111] When the programming stage (PGM) is initiated, a programming voltage Vpgm higher than the pass voltage Vpass can be applied to the selected word line Sel_WL. Memory cells connected to a channel film CH with a potential lower than the precharge voltage Vpre are programmed by the voltage difference between the channel film CH and the selected word line Sel_WL. Memory cells connected to a channel film CH with a boosting voltage Vbs are not programmed by the boosting voltage Vbs.

[0112] When the programming phase (PGM) is completed, the bit line BL, drain selection line DSL, selected word line Sel_WL, unselected word line Unsel_WL, channel membrane CH, source selection line SSL, and source line SL can be discharged. Then, the verification phase (VF) can be performed.

[0113] Refer to Figure 13a to explain the program operation when the selected word line Sel_WL is included in the first group 1GR. Refer to Figure 13b to explain the program operation when the selected word line Sel_WL is included in the second group 2GR.

[0114] Referring to Figure 13b, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 13a, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0115] If the selected word line Sel_WL is included in the disturb-vulnerable second group 2GR, the duration for which the precharge stage PRE is performed can be set to a second time T2 that is longer than the first time T1, in order to reduce the effects of the disturbance. The longer the precharge stage PRE is performed, the more sufficiently the precharge voltage Vpre can be transmitted to the channel film CH, so that the boosting of the channel film CH can occur effectively in the boosting stage BS performed after the precharge stage PRE. Therefore, disturbance can be prevented during the programmed operation of the second group 2GR, which has a relatively small memory cell size.

[0116] Referring to Figure 13c, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 13b, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0117] If the selected word line Sel_WL is included in the third group 3GR, which is more vulnerable to disturbance than the second group 2GR, the time for which the precharge stage PRE is performed can be set to the third time T3, which is longer than the second time T2, in order to reduce the effects of disturbance. The longer the precharge stage PRE is performed, the more sufficiently the precharge voltage Vpre can be transmitted to the channel film CH, so that the boosting of the channel film CH can occur effectively in the boosting stage BS performed after the precharge stage PRE. Therefore, disturbance can be prevented during the programmed operation of the third group 3GR, which has a relatively small memory cell size.

[0118] As described above, if the selected word line Sel_WL is in the first group 1GR, which is not affected by disturb, the time required for program operation can be reduced by shortening the time required for the precharge stage PRE. If the selected word line Sel_WL is in the second and third groups 2GR and 3GR, which are affected by disturb, the reliability of program operation can be improved by increasing the time required for the precharge stage PRE.

[0119] Figures 14a to 14c are diagrams illustrating a programming method according to a fourth embodiment of the present invention.

[0120] In the third embodiment described with reference to Figures 13a to 13c, the channel membrane CH was precharged via the source line SL, but in the fourth embodiment described with reference to Figures 14a to 14c, the channel membrane CH can be precharged via the bit line BL.

[0121] Figure 14a is a diagram illustrating the programming method when the selected word line Sel_WL is included in the first group (1GR in Figure 12) during program operation, Figure 14b is a diagram illustrating the programming method when the selected word line Sel_WL is included in the second group (2GR in Figure 12) during program operation, and Figure 14c is a diagram illustrating the programming method when the selected word line Sel_WL is included in the third group (3GR in Figure 12) during program operation.

[0122] Referring to Figure 14a, the program operation can include a precharge stage PRE, a boosting stage BS, a program stage PGM, and a verification stage VF. In the precharge stage PRE, an operation is performed to increase the potential of the channel film CH. In the boosting stage BS, an operation is performed to further increase the potential of the channel film CH using the pass voltage Vpass. In the program stage PGM, an operation is performed to increase the threshold voltage of the selected memory cell. In the verification stage VF, an operation is performed to determine whether the threshold voltage of the memory cell has risen to the target voltage. The features of this embodiment are in the precharge stage PRE, the boosting stage BS, and the program stage PGM, so the explanation of the verification stage VF after the program stage PGM is omitted.

[0123] When the precharge stage PRE is initiated, a turn-off voltage Voff is applied to the source selection line SSL, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated. The source line SL can be supplied with either a ground voltage Vgnd or a precharge voltage Vpre. The bit line BL can be supplied with a precharge voltage Vpre. The precharge voltage Vpre applied to the bit line BL may be the same as or different from the precharge voltage Vpre applied to the source line SL. The drain selection line DSL can be supplied with a turn-on voltage Von. When the turn-on voltage Von is applied to the drain selection line DSL, the drain selection transistor is turned on, so that the bit line BL and the channel film CH can be electrically coupled. Therefore, the precharge voltage Vpre applied to the bit line BL can be supplied to the channel film CH. As a result, the potential of the channel film CH can have the level of the precharge voltage Vpre. The precharge stage PRE can be performed for a first time T1 after the precharge voltage Vpre is applied to the bit line BL and the turn-on voltage Von is applied to the drain selection line DSL. For example, the first time T1 may be the time from when the drain selection transistor is turned on until when the program-allowable voltage Val or program-blocking voltage Vinh begins to be applied to the bit line BL.

[0124] Once the pre-charge phase (PRE) is complete, the boosting phase (BS) can be executed.

[0125] When the boosting phase BS begins, a program-blocking voltage Vinh or program-allowing voltage Val is applied to the bit line BL, and a pass voltage Vpass may be applied to the selected word line Sel_WL and the unselected word line Unsel_WL. The program-blocking voltage Vinh is a positive voltage higher than 0V and is used to prevent the threshold voltage of the unselected memory cell from being raised by the program voltage. The program-allowing voltage Val can be set to ground voltage or 0V.

[0126] Since the turn-on voltage Von is continuously applied to the drain selection line DSL, the drain selection transistor can be maintained in the turn-on state. When the program allowance voltage Val is applied to the bit line BL, the voltage of the channel film CH can be lowered by the program allowance voltage Val. When the program disable voltage Vinh is applied to the bit line BL, the voltage of the channel film CH is not lowered by the program disable voltage Vinh, but can be boosted by the pass voltage Vpass applied to the selected word line Sel_WL and the unselected word line Unsel_WL. Therefore, when the program disable voltage Vinh is applied to the bit line BL, the potential of the channel film CH can be higher than the precharge voltage Vpre, reaching a boosting voltage Vbs.

[0127] Once the boosting phase (BS) is complete, the program phase (PGM) can be started.

[0128] When the programming stage (PGM) is initiated, a programming voltage Vpgm higher than the pass voltage Vpass can be applied to the selected word line Sel_WL. Memory cells connected to a channel film CH with a potential lower than the precharge voltage Vpre are programmed by the voltage difference between the channel film CH and the selected word line Sel_WL. Memory cells connected to a channel film CH with a boosting voltage Vbs are not programmed by the boosting voltage Vbs.

[0129] When the programming phase (PGM) is completed, the bit line BL, drain selection line DSL, selected word line Sel_WL, unselected word line Unsel_WL, channel membrane CH, source selection line SSL, and source line SL can be discharged. Then, the verification phase (VF) can be performed.

[0130] Refer to Figure 14a to explain the program operation when the selected word line Sel_WL is included in the first group 1GR. Refer to Figure 14b to explain the program operation when the selected word line Sel_WL is included in the second group 2GR.

[0131] Referring to Figure 14b, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 14a, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0132] If the selected word line Sel_WL is included in the second group 2GR which is vulnerable to disturbance, the time for which the precharge stage PRE is performed can be set to a second time T2 which is longer than the first time T1 in order to prevent disturbance. The longer the precharge stage PRE is performed, the more the precharge voltage Vpre can be sufficiently transmitted to the channel membrane CH, so that the boosting of the channel membrane CH can be effectively performed in the boosting stage BS which is performed after the precharge stage PRE.

[0133] Therefore, during program operation of the second group 2GR, which has a relatively smaller memory cell size, disturbance in the memory cells can be prevented.

[0134] Refer to Figure 14b to explain the program operation when the selected word line Sel_WL is included in the second group 2GR. Refer to Figure 14c to explain the program operation when the selected word line Sel_WL is included in the third group 3GR.

[0135] Referring to Figure 14c, the boosting stage BS, program stage PGM, and verification stage VF are executed in the same manner as described with reference to Figure 14b, except for the time during which the pre-charge stage PRE is performed, so redundant explanations are omitted.

[0136] If the selected word line Sel_WL is included in the third group 3GR which is vulnerable to disturbance, the time for which the precharge stage PRE is performed can be set to a third time T3 which is longer than the second time T2 in order to prevent disturbance. The longer the precharge stage PRE is performed, the more the precharge voltage Vpre can be sufficiently transmitted to the channel membrane CH, so that the boosting of the channel membrane CH can occur effectively in the boosting stage BS which is performed after the precharge stage PRE.

[0137] Therefore, during program operation of the third group 3GR, which has a relatively small memory cell size, disturbance in the memory cell can be prevented.

[0138] As described above, if the selected word line Sel_WL is in the first group 1GR, which is not affected by disturb, the time required for program operation can be reduced by shortening the time required for the precharge stage PRE. If the selected word line Sel_WL is in the second and third groups 2GR and 3GR, which are affected by disturb, the reliability of program operation can be improved by increasing the time required for the precharge stage PRE.

[0139] Figure 15 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present invention is applied.

[0140] Referring to Figure 15, the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0141] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 can be configured to control program, read, or erase operations of the memory device 3200, or to control background operations. The controller 3100 is configured to provide an interface between the memory device 3200 and the host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0142] The controller 3100 can communicate with an external device via the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device via at least one of various communication standards, such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0143] The memory device 3200 may include memory cells and can be configured similarly to the memory device 100 shown in Figure 3. For example, in order to shorten the time required for program operation and prevent disturbance, the memory device 3200 can adjust the channel precharge time according to the size of the memory cells contained in the selected page during program operation of the selected page of the selected memory block.

[0144] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute memory cards such as PC cards (PCMCIA, personal computer memory card international association), CompactFlash cards (CF), SmartMedia cards (SM, SMC), Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and general-purpose flash memory (UFS).

[0145] Figure 16 is a diagram illustrating an SSD (Solid State Drive) system to which a memory device according to an embodiment of the present invention is applied.

[0146] Referring to Figure 16, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 via a signal connector 4001 and receives power input via a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221-422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0147] The controller 4210 can control multiple memory devices 4221-422n in response to signals received from the host 4100. Exemplary, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0148] Multiple memory devices 4221-422n can contain cells capable of storing data. Each of the multiple memory devices 4221-422n can be configured similarly to the memory device 100 shown in Figure 3. For example, at least one of the multiple memory devices 4221-422n can adjust the channel precharge time according to the size of the memory cells contained in the selected page during program operation of the selected page of the selected memory block, in order to reduce the time required for program operation and prevent disturbance.

[0149] The auxiliary power supply unit 4230 is connected to the host 4100 via the power connector 4002. The auxiliary power supply unit 4230 can receive power supply voltage input from the host 4100 and be charged. The auxiliary power supply unit 4230 can provide power supply voltage to the SSD 4200 if the power supply from the host 4100 is not smooth. Exemplarily, the auxiliary power supply unit 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply unit 4230 may be located on the main board and supply auxiliary power to the SSD 4200.

[0150] The buffer memory 4240 operates as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from multiple memory devices 4221-422n, or it can temporarily store metadata (e.g., mapping tables) of the memory devices 4221-422n. The buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or non-volatile memory such as FRAM®, ReRAM, STT-MRAM, or PRAM. [Explanation of Symbols]

[0151] 100 memory devices 110 memory cell array 120 Peripheral Circuits 130 Control circuits 21 Voltage Generator 22 Low Decoders 23 Source Line Driver 24-page buffer group 25-column decoder 26 Input / Output Circuits 1SLD First Select Line Driver 2SLD Second Select Line Driver WLD Wordline Driver

Claims

1. A memory block comprising a first selection line, a word line, and a second selection line stacked between a source line and a bit line, a channel film penetrating the first selection line, the word line, and the second selection line, and stacked along the channel film, comprising a first selection transistor connected to the first selection line, a second selection transistor connected to the second selection line, and a memory cell connected to the word line; A voltage generator configured to generate turn-on and turn-off voltages applied to the first and second selection lines, and to generate program voltages and path voltages applied to the word line; A source line driver configured to generate a precharge voltage applied to the source line; A page buffer group configured to generate a program-allowable voltage and a program-prohibited voltage applied to the bit line; A memory device comprising a control circuit configured to set a reference position in the memory block that distinguishes between areas where disturbance occurs and areas where disturbance does not occur, and to control the voltage generator, the source line driver, and the page buffer group during program operation of the memory block so as to adjust the time for precharging the channel film according to the result of comparing the position of the selected word line with the reference position.

2. The aforementioned control circuit is When the selected word line is positioned above the reference position, the voltage generator, the source line driver, and the page buffer group are controlled so that the channel film is precharged for a first time. The memory device according to claim 1, configured to control the voltage generator, the source line driver, and the page buffer group such that when the selected word line is located below the reference position, the channel film is precharged for a second time shorter than the first time.

3. The aforementioned control circuit is Based on the aforementioned reference position, the word lines in the region where the memory cell size is relatively large are set as the first group. The memory device according to claim 1, configured to set the word lines of regions where the size of the memory cells is relatively small as a reference position to a second group.

4. The aforementioned control circuit is When the selected word line is included in the first group, the voltage generator, the source line driver and the page buffer group are controlled so that the channel film is precharged for a first time. The memory device according to claim 3, configured to control the voltage generator, the source line driver, and the page buffer group so that the channel film is precharged for a second time shorter than the first time, when the selected word line is included in the second group.

5. The aforementioned control circuit is The memory device according to claim 1, configured to control the source line driver so that the precharge voltage is applied to the source line in order to precharge the channel film.

6. The voltage generator is, The memory device according to claim 5, wherein when the precharge voltage is applied to the source line, the device is configured to apply a turn-on voltage to the first selected line in accordance with the control of the control circuit.

7. The memory device according to claim 6, wherein the time for precharging the channel film is the time from the time when the turn-on voltage is first applied to the first selection line to the time when the turn-off voltage is first applied to the first selection line.

8. The voltage generator is, The memory device according to claim 5, configured to apply the turn-off voltage to the second selection line in accordance with the control of the control circuit while the channel film is being precharged.

9. The aforementioned control circuit is The memory device according to claim 1, configured to control the page buffer group so that the precharge voltage is applied to the bit line in order to precharge the channel film.

10. The voltage generator is, The memory device according to claim 9, wherein when the precharge voltage is applied to the bit line, the device is configured to apply a turn-on voltage to the second selection line in accordance with the control of the control circuit.

11. The memory device according to claim 10, wherein the time for precharging the channel film is the time from the time when the turn-on voltage is first applied to the second selection line until the time when the program-allowable voltage or the program-prohibited voltage is first applied to the bit line.

12. The voltage generator is, The memory device according to claim 9, configured to apply the turn-off voltage to the first select line in accordance with the control of the control circuit while the channel film is being precharged.

13. The voltage generator is, A first select line driver configured to generate the turn-on voltage and the turn-off voltage applied to the first select line in accordance with the control of the control circuit; A second select line driver configured to generate the turn-on voltage and the turn-off voltage applied to the second select line in accordance with the control of the control circuit; The memory device according to claim 1, further comprising a word line driver configured to generate the program voltage and the path voltage applied to the word line in accordance with the control of the control circuit.

14. The aforementioned control circuit is The memory device according to claim 1, configured to control the voltage generator so that the path voltage is applied to the word line after the pre-charging of the channel film is completed.

15. The steps include: dividing the multiple word lines stacked between the source line and the bit line into a first group and a second group according to the width of the plugs that penetrate the multiple word lines (the width of the plugs included in the second group is narrower than the width of the plugs included in the first group); The steps include: precharging the channel film contained in the plug; The steps include: precharging the channel film, applying a path voltage to the plurality of word lines; The step includes applying the path voltage to the plurality of word lines, and then applying the program voltage to a selected word line from among the plurality of word lines. When the selected word line is included in the second group, the step of precharging the channel film is performed for a first time. A method of operating a memory device in which, when the selected word line is included in the first group, the step of precharging the channel film is performed for a second time that is shorter than the first time.

16. The step of precharging the channel membrane is as follows: The steps include: applying a precharge voltage to the source line; A method for operating a memory device according to claim 15, comprising the step of electrically connecting the source line and the channel film to each other.

17. The method for operating a memory device according to claim 16, wherein the precharge voltage is set to a positive voltage higher than 0V.

18. The method of operating a memory device according to claim 16, wherein the source line and the channel film are electrically connected to each other by turning on a first selection transistor located between the source line and the channel film.

19. The method for operating a memory device according to claim 16, wherein the time for which the source line and the channel film are electrically connected to each other is set to the first time or the second time.

20. The method of operating a memory device according to claim 16, wherein a second selection transistor located between the bit line and the channel film is turned off while the channel film is being precharged.

21. The step of precharging the channel membrane is as follows: The steps include: applying a precharge voltage to the bit line; A method for operating a memory device according to claim 15, comprising the step of electrically connecting the bit line and the channel film to each other.

22. The method of operating a memory device according to claim 21, wherein the bit line and the channel film are electrically connected to each other by turning on a second selection transistor located between the bit line and the channel film.

23. The method for operating a memory device according to claim 21, wherein the time for which the bit line and the channel film are electrically connected to each other is set to the first time or the second time.

24. The method of operating a memory device according to claim 21, wherein a first selection transistor located between the source line and the channel film is turned off while the channel film is being precharged.

25. In the step of applying a path voltage to the plurality of word lines, The method for operating a memory device according to claim 15, wherein a program-allowing voltage and a program-prohibiting voltage are selectively applied to the bit line.

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