Semiconductor devices and power converters

Abstract

To obtain semiconductor devices and power converters that can improve reliability. [Solution] Device 10 is provided on a semiconductor substrate 1. Metal wiring 4 is provided on the upper surface of the semiconductor substrate 1 and connected to device 10. Passivation film 5 is an inorganic insulating film that covers the corners of the metal wiring 4 and has openings 6 provided on the upper surface of the metal wiring 4. Organic protective film 7 covers the metal wiring 4 exposed through the openings 6.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

Background Art

[0002] In a semiconductor device, a passivation film covers a metal wiring provided on a semiconductor substrate (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventionally, since the passivation film was formed so as to uniformly cover the metal wiring, the passivation film was easily broken due to the influence of thermal stress. In addition, since an organic protective film is provided on the passivation film, when the metal wiring is exposed from the passivation film, an interface is formed with the organic protective film. However, there is a problem that the organic protective film reacts and deteriorates at the interface between the corner of the metal wiring where electric field concentration occurs and the organic protective film, resulting in a decrease in reliability such as moisture resistance or durability.

[0005] The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device and a power conversion device capable of improving reliability.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure is characterized by comprising: a semiconductor substrate on which a device is provided; metal wiring provided on the upper surface of the semiconductor substrate and connected to the device; an inorganic insulating film that covers the corners of the metal wiring and has an opening provided on the upper surface of the metal wiring; and an organic protective film that covers the metal wiring exposed through the opening. [Effects of the Invention]

[0007] In this disclosure, an opening is provided in the passivation film on the upper surface of the metal wiring. This reduces the thermal stress the passivation film receives from the metal wiring, thereby suppressing the occurrence of cracks in the passivation film. Furthermore, the passivation film covers the corners of the metal wiring. As a result, the electric field concentration areas of the metal wiring do not come into contact with the organic protective film, thereby suppressing the deterioration of the organic protective film at the interface between the organic protective film and the metal wiring. Therefore, peeling of the organic protective film can be prevented, improving moisture resistance. As a result, reliability such as durability can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing a semiconductor device according to Embodiment 1. [Figure 2] Figure 1 is a plan view with the organic protective film omitted. [Figure 3] This is a cross-sectional view of the outer periphery of the chip along line I-II in Figure 1, in the direction of the short side. [Figure 4] This is a cross-sectional view of the corner along line III-IV in Figure 1. [Figure 5] This is an enlarged plan view of a modified example of the semiconductor device according to Embodiment 1. [Figure 6] This is a plan view showing a semiconductor device according to Embodiment 2. [Figure 7] This is a plan view showing a semiconductor device according to Embodiment 3. [Figure 8] This is an enlarged plan view of a part of the semiconductor device according to Embodiment 3. [Figure 9]It is a plan view showing a semiconductor device according to Embodiment 4. [Figure 10] It is a cross-sectional view taken along the line I-II of FIG. 9. [Figure 11] It is an enlarged plan view of a part of a modified example of the semiconductor device according to Embodiment 4. [Figure 12] It is a plan view showing a semiconductor device according to Embodiment 5. [Figure 13] It is a plan view showing a semiconductor device according to Embodiment 6. [Figure 14] It is an enlarged plan view of a part of Modified Example 1 of the semiconductor device according to Embodiment 6. [Figure 15] It is an enlarged plan view of a part of Modified Example 2 of the semiconductor device according to Embodiment 6. [Figure 16] It is a plan view showing a semiconductor device according to Embodiment 7. [Figure 17] It is a cross-sectional view taken along the line I-II of FIG. 16. [Figure 18] It is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 8 is applied.

Embodiments for Carrying Out the Invention

[0009] The semiconductor device and the power conversion device according to the embodiments will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0010] Embodiment 1 FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1. FIG. 2 is a plan view in which the organic protective film is omitted in FIG. 1. A source electrode 2 is provided at the central portion of the upper surface of the semiconductor substrate 1. A gate pad 3 and a gate wiring 4 connected thereto are provided in the outer peripheral region around the source electrode 2 on the upper surface of the semiconductor substrate 1. These source electrode 2, gate pad 3, and gate wiring 4 are metal wirings.

[0011] A passivation film 5 is provided on the semiconductor substrate 1, the outer periphery of the source electrode 2, the outer periphery of the gate pad 3, and the gate wiring 4. The passivation film 5 is, for example, a nitride film. The passivation film 5 covers the metal wiring at the termination point and protects the termination region. Openings 6 are provided in the passivation film 5 on the outermost periphery of the gate pad 3 and on the gate wiring 4.

[0012] An organic protective film 7 is provided on the semiconductor substrate 1, the passivation film 5, and the gate wiring 4. The organic protective film 7 protects the semiconductor substrate 1 by covering the areas where the passivation film 5 is not present. The passivation film 5 and the organic protective film 7 provide waterproofing and oxidation prevention effects. However, the central parts of the gate pad 3 and the central parts of the source electrode 2 are not covered by the passivation film 5 and are exposed in order to make electrical contacts such as wire bonds.

[0013] Figure 3 is a cross-sectional view of the outer edge of the chip along line I-II in Figure 1, in the direction of the short side. In the semiconductor substrate 1, an outer region 9 is provided so as to surround the active region 8 through which the main current flows. A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is provided as a device 10 in the active region 8. However, the device 10 may also be a Schottky diode, an IGBT (Insulated Gate Bipolar Transistor), or the like.

[0014] In semiconductor substrate 1, N - A P-type layer 12 is provided on the P-type drift layer 11. An N-type source region 13 is provided on a part of the P-type layer 12. In the outer peripheral region 9 of the semiconductor substrate 1, N - A P-type pressure-resistant holding structure 14 is provided on top of the drift layer 11. - An N-type channel stop region 15 is provided at the outermost periphery of the drift layer 11. - N + A type drain layer 16 is provided.

[0015] In the active region 8 of the semiconductor substrate 1, a gate electrode 18 is formed on the P-type layer 12 via a gate insulating film 17. An insulating oxide film 19 is provided on the outer peripheral region 9 of the semiconductor substrate 1, protecting the semiconductor substrate 1 by covering the P-type breakdown voltage holding structure 14 and a portion of the N-type channel stop region 15. An insulating oxide film 20 is provided so as to cover the semiconductor substrate 1, the gate electrode 18, and the insulating oxide film 19. The insulating oxide films 19 and 20 are, for example, silicon oxide films.

[0016] In the active region 8, a source electrode 2 is provided on the insulating oxide film 20 via a barrier metal 21. The source electrode 2 is connected to the N-type source region 13 through an opening in the insulating oxide film 20. In the outer peripheral region 9, a gate wiring 4 is provided on the insulating oxide film 20 via a barrier metal 21. The gate wiring 4 is connected to the lead-out portion of the gate electrode 18, which is drawn out onto the insulating oxide film 19, through an opening in the insulating oxide film 20. Therefore, the gate wiring 4 and source electrode 2 provided on the upper surface of the semiconductor substrate 1 are electrically connected to the device 10. In addition, a drain electrode 22 is provided on the lower surface of the semiconductor substrate 1, and N + It is connected to the drain layer 16.

[0017] A passivation film 5 covers the semiconductor substrate 1, gate wiring 4, and source electrode 2. An opening 6 is provided in the passivation film 5 along the gate wiring 4 on the upper surface of the gate wiring 4. The passivation film 5 covers the sides of the gate wiring 4 and the outer edge of the upper surface of the gate wiring 4. Multiple openings 6 may be provided on the gate wiring 4. The width of the opening 6 is smaller than the width of the gate wiring 4. An organic protective film 7 covers and protects the gate wiring 4 exposed through the openings 6.

[0018] The thickness of the passivation film 5 is 0.5 μm to 2 μm. The passivation film 5 is formed, for example, by the CVD method. An opening 6 in the passivation film 5 is formed by coating a resist film on the passivation film 5, placing a photomask on top and performing photosensitive treatment, followed by etching.

[0019] Figure 4 is a cross-sectional view of the corner along line III-IV in Figure 1. The structure of the corner of the semiconductor substrate 1 is basically the same as in Figure 3, but the area between the outer edge of the insulating oxide film 20 and the edge of the semiconductor substrate 1 is wider than in Figure 3. Therefore, the corner is susceptible to the effects of thermal stress on the passivation film 5 and the adhesive strength of the organic protective film 7.

[0020] The larger the area of ​​the continuous passivation film 5, the greater the thermal stress it will receive from the gate wiring 4. Therefore, in this embodiment, an opening 6 is provided in the passivation film 5 on the upper surface of the gate wiring 4. This reduces the thermal stress that the passivation film 5 receives from the gate wiring 4 during environmental changes or operation, and suppresses the occurrence of cracks in the passivation film 5. In addition, the shape of the organic protective film 7 that fits into the opening 6 provides an anchoring effect, improving the adhesion of the organic protective film 7.

[0021] Furthermore, the electric field concentrates at the corners between the top and side surfaces of the gate wiring 4. Therefore, the passivation film 5 covers the corners of the gate wiring 4. As a result, the electric field concentration area of ​​the gate wiring 4 does not come into contact with the organic protective film 7, thereby suppressing the deterioration of the organic protective film 7 at the interface between the organic protective film 7 and the gate wiring 4. Thus, peeling of the organic protective film 7 can be prevented, improving moisture resistance. As a result, reliability such as durability can be improved.

[0022] Furthermore, it is preferable that the width w of the narrowest part of the passivation film 5 covering the outer edge of the upper surface of the gate wiring 4 is greater than the thickness of the passivation film 5. This prevents the opening 6 from reaching the corner of the gate wiring 4 and exposing the corner of the gate wiring 4.

[0023] The gate wiring 4 is provided in the outer peripheral region 9 along the outer periphery of the semiconductor substrate 1 in a plan view. Therefore, the opening 6 provided on the upper surface of the gate wiring 4 is provided in the outer peripheral region 9 along the outer periphery of the semiconductor substrate 1 in a plan view. This allows the thermal stress on the passivation film 5 to be mitigated over a wide area. Furthermore, the opening 6 is provided only on the upper surface of the gate wiring 4. This reduces the contact area between the semiconductor substrate 1 and the organic protective film 7, thereby suppressing deterioration of the contact interface.

[0024] The passivation film 5 is, for example, a nitride film, but any inorganic insulating film will suffice. If the passivation film 5 is a silicon nitride film, moisture resistance can be ensured, the effects of the electric field can be suppressed, and the decrease in interfacial strength with the organic protective film 7 can be suppressed.

[0025] Figure 5 is an enlarged plan view of a modified example of the semiconductor device according to Embodiment 1. The openings 6 of the passivation film 5 are wavy in plan view. Therefore, the planar shape of the openings 6 does not have an acute angle smaller than 90 degrees. This eliminates stress concentration areas and further reduces the load on the passivation film 5, thereby further improving reliability.

[0026] Embodiment 2 Figure 6 is a plan view showing a semiconductor device according to Embodiment 2. Openings 6 are provided in the passivation film 5 on the gate wiring 4 only at the corners of the semiconductor substrate 1. By providing openings 6 at the corners where stress tends to concentrate, crack formation in the passivation film 5 can be suppressed. In addition, since the gate wiring 4 other than the corners is covered by the passivation film 5, the area covered and protected by the passivation film 5 can be increased. Other configurations and effects are the same as in Embodiment 1.

[0027] Embodiment 3 Figure 7 is a plan view showing a semiconductor device according to Embodiment 3. Figure 8 is an enlarged plan view of a part of the semiconductor device according to Embodiment 3. An opening 6 is provided in the passivation film 5 along the gate wiring 4. Multiple remaining regions 23 of the passivation film 5 exist inside the opening 6.

[0028] By providing multiple residual regions 23, the area over which the passivation film 5 covers and protects the gate wiring 4 can be increased. Furthermore, the organic protective film 7 enters the openings 6 where the multiple residual regions 23 exist, exhibiting an anchoring effect and further improving the adhesion of the organic protective film 7. Other configurations and effects are the same as in Embodiment 1.

[0029] Embodiment 4 Figure 9 is a plan view showing a semiconductor device according to Embodiment 4. Figure 10 is a cross-sectional view along line I-II in Figure 9. This embodiment differs from Embodiment 1 in the location of the opening 6. The passivation film 5 covers the outer periphery of the source electrode 2. In a plan view, the opening 6 is provided on the outer periphery of the source electrode 2 along the outer periphery of the source electrode 2. This reduces the thermal stress that the passivation film 5 receives from the source electrode 2 during environmental changes or operation, and suppresses the occurrence of cracks in the passivation film 5. In addition, the shape of the organic protective film 7 that fits into the opening 6 provides an anchoring effect, improving the adhesion of the organic protective film 7.

[0030] Furthermore, the electric field concentrates at the corner between the top and side surfaces of the source electrode 2. Therefore, the passivation film 5 covers the corner of the source electrode 2. As a result, the electric field concentration area of ​​the source electrode 2 does not come into contact with the organic protective film 7, thereby suppressing the deterioration of the organic protective film 7 at the interface where the electric field is concentrated. Thus, peeling of the organic protective film 7 can be prevented, improving its moisture resistance. As a result, reliability, such as durability, can be improved.

[0031] Figure 11 is an enlarged plan view of a modified example of the semiconductor device according to Embodiment 4. The openings 6 of the passivation film 5 are wavy in plan view. Therefore, the planar shape of the openings 6 does not have an acute angle smaller than 90 degrees. This eliminates stress concentration areas and further reduces the load on the passivation film 5, thereby further improving reliability.

[0032] Embodiment 5 Figure 12 is a plan view showing a semiconductor device according to Embodiment 5. An opening 6 is provided in the passivation film 5 that covers the outer periphery of the source electrode 2 only at the corner portion of the source electrode 2. By providing an opening 6 at the corner portion where stress tends to concentrate, crack formation in the passivation film 5 can be suppressed. In addition, since the source electrode 2 other than the corner portion is covered by the passivation film 5, the area that the passivation film 5 covers and protects the outer periphery of the source electrode 2 can be increased. Other configurations and effects are the same as in Embodiment 4.

[0033] Embodiment 6 Figure 13 is a plan view showing a semiconductor device according to Embodiment 6. An opening 6 is provided in the passivation film 5 on the outer periphery of the source electrode 2. Multiple remaining regions 23 of the passivation film 5 exist inside the opening 6.

[0034] By providing multiple residual regions 23, the area covered and protected by the passivation film 5 around the outer periphery of the source electrode 2 can be increased. Furthermore, the organic protective film 7 enters the opening 6 where the multiple residual regions 23 exist, exhibiting an anchoring effect and further improving the adhesion of the organic protective film 7. Other configurations and effects are the same as in Embodiment 4.

[0035] Figure 14 is an enlarged plan view of a part of Modification 1 of the semiconductor device according to Embodiment 6. The remaining region 23 is a rectangle. Figure 15 is an enlarged plan view of a part of Modification 2 of the semiconductor device according to Embodiment 6. The remaining region 23 is a triangle. However, if there are sharp points in the remaining region 23, stress will concentrate in those areas. Therefore, it is preferable to round all corners of the remaining region 23. That is, it is preferable that the remaining region 23 be a polygon or a circle without acute angles.

[0036] Embodiment 7 Figure 16 is a plan view showing a semiconductor device according to Embodiment 7. Figure 17 is a cross-sectional view taken along line I-II in Figure 16. The openings 6 are provided on both the upper surface of the gate wiring 4 and the outer periphery of the source electrode 2. The anchoring effect between the two further improves the adhesion of the organic protective film 7, and the large openings 6 further alleviate the thermal stress on the passivation film 5, thereby suppressing the occurrence of cracks in the passivation film 5. The shapes of the two openings 6 may be the same, or different shapes may be combined.

[0037] Furthermore, the semiconductor substrate 1 is not limited to one formed of silicon, but may also be formed of a wide-bandgap semiconductor with a larger bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. Semiconductor devices formed of such wide-bandgap semiconductors can be miniaturized because they have high dielectric strength and allowable current density. By using these miniaturized semiconductor devices, semiconductor modules incorporating them can also be miniaturized and highly integrated. In addition, because the semiconductor device has high heat resistance, the heat sink fins can be miniaturized and the water-cooled section can be air-cooled, allowing for further miniaturization of the semiconductor module. Moreover, because the semiconductor device has low power loss and high efficiency, the semiconductor module can be made more efficient.

[0038] Embodiment 8 This embodiment applies a semiconductor device according to any of the embodiments 1 to 7 described above to a power converter. This disclosure is not limited to a specific power converter, but below, as Embodiment 8, a case in which this disclosure is applied to a three-phase inverter will be described.

[0039] Figure 18 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 8 is applied. The power conversion system includes a power supply 50, a power conversion device 200, and a load 300. The power supply 50 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 50 can be made up of various things, for example, a DC grid, a solar cell, a storage battery, or a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 50 may be made up of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0040] The power converter 200 is a three-phase inverter connected between the power supply 50 and the load 300. It converts the DC power supplied from the power supply 50 into AC power and supplies the AC power to the load 300. The power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0041] Load 300 is a three-phase electric motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is an electric motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0042] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 50 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and has six switching elements and six freewheeling diodes antiparallel to each switching element. A semiconductor device according to any of the embodiments 1 to 7 described above is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0043] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.

[0044] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0045] In the power conversion device according to this embodiment, a semiconductor device according to any of Embodiments 1 to 7 is used as the switching element of the main conversion circuit 201, thereby improving reliability.

[0046] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, the present disclosure may be applied to a DC / DC converter or an AC / DC converter when supplying power to a DC load or the like.

[0047] Furthermore, the power conversion device to which this disclosure is applied is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0048] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. Various aspects of this disclosure are described below as appendices. (Note 1) A semiconductor substrate on which a device is provided, A metal wiring provided on the upper surface of the semiconductor substrate and connected to the device, An inorganic insulating film covering the corners of the metal wiring, a passivation film having an opening provided on the upper surface of the metal wiring, A semiconductor device comprising an organic protective film that covers the metal wiring exposed from the opening. (Note 2) The metal wiring has gate wiring provided in the outer peripheral region of the semiconductor substrate. The semiconductor device according to Appendix 1, characterized in that the opening is provided on the upper surface of the gate wiring. (Note 3) The semiconductor device according to Appendix 2, characterized in that the opening is provided only at the corner portion of the semiconductor substrate in a plan view. (Note 4) The aforementioned metal wiring has a source electrode, The passivation film covers the outer periphery of the source electrode. The semiconductor device according to Appendix 1, characterized in that the opening is provided on the outer periphery of the source electrode. (Note 5) The semiconductor device according to Appendix 4, characterized in that the opening is provided only at the corner portion of the source electrode in a plan view. (Note 6) The aforementioned metal wiring has a gate wire and a source electrode. The passivation film covers the gate wiring and the outer periphery of the source electrode. The semiconductor device according to Appendix 1, characterized in that the opening is provided on both the upper surface of the gate wiring and the outer periphery of the source electrode. (Note 7) A semiconductor device according to any one of the appendices 1 to 6, characterized in that multiple residual regions of the passivation film exist inside the opening. (Note 8) The semiconductor device according to Appendix 7, characterized in that the remaining region is a polygon or circle without acute angles. (Note 9) A semiconductor device according to any one of the appendices 1 to 8, characterized in that the width of the narrowest part of the passivation film covering the outer edge of the upper surface of the metal wiring is greater than the thickness of the passivation film. (Note 10) The semiconductor device according to any one of the appendices 1 to 9, characterized in that the planar shape of the opening does not have an acute angle less than 90 degrees. (Note 11) The semiconductor device according to any one of the appendices 1 to 10, characterized in that the opening is provided only on the upper surface of the metal wiring. (Note 12) The semiconductor device according to any one of the appendices 1 to 11, characterized in that the passivation film is a silicon nitride film. (Note 13) The semiconductor device according to any one of the appendices 1 to 12, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor. (Note 14) A semiconductor device described in any of the appendices 1 to 13, comprising a main conversion circuit that converts and outputs the input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A power conversion device characterized by comprising a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit. [Explanation of Symbols]

[0049] 1 Semiconductor substrate, 2 Source electrode (metal wiring), 4 Gate wiring (metal wiring), 5 Passivation film, 6 Aperture, 7 Organic protective film, 10 Device, 23 Residual area, 200 Power converter, 201 Main converter circuit, 202 Drive circuit, 203 Control circuit

Claims

1. A semiconductor substrate on which a device is provided, A metal wiring provided on the upper surface of the semiconductor substrate and connected to the device, An inorganic insulating film covering the corners of the metal wiring, a passivation film having an opening provided on the upper surface of the metal wiring, A semiconductor device comprising an organic protective film that covers the metal wiring exposed from the opening.

2. The metal wiring has gate wiring provided in the outer peripheral region of the semiconductor substrate. The semiconductor device according to claim 1, characterized in that the opening is provided on the upper surface of the gate wiring.

3. The semiconductor device according to claim 2, characterized in that the opening is provided only at the corner portion of the semiconductor substrate in a plan view.

4. The aforementioned metal wiring has a source electrode, The passivation film covers the outer periphery of the source electrode. The semiconductor device according to claim 1, characterized in that the opening is provided on the outer periphery of the source electrode.

5. The semiconductor device according to claim 4, characterized in that the opening is provided only at the corner portion of the source electrode in a plan view.

6. The aforementioned metal wiring has a gate wire and a source electrode. The passivation film covers the gate wiring and the outer periphery of the source electrode. The semiconductor device according to claim 1, characterized in that the opening is provided on both the upper surface of the gate wiring and the outer periphery of the source electrode.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that a plurality of remaining regions of the passivation film exist inside the opening.

8. The semiconductor device according to claim 7, characterized in that the remaining region is a polygon or circle without acute angles.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that the width of the narrowest part of the passivation film covering the outer edge of the upper surface of the metal wiring is greater than the thickness of the passivation film.

10. The semiconductor device according to any one of claims 1 to 6, characterized in that the planar shape of the opening does not have an acute angle less than 90 degrees.

11. The semiconductor device according to any one of claims 1 to 6, characterized in that the opening is provided only on the upper surface of the metal wiring.

12. The semiconductor device according to any one of claims 1 to 6, characterized in that the passivation film is a silicon nitride film.

13. The semiconductor device according to any one of claims 1 to 6, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor.

14. A semiconductor device according to any one of claims 1 to 6, comprising a main conversion circuit that converts and outputs the input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A power conversion device characterized by comprising a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.

Images