Active matrix substrate and display device

Abstract

An active matrix substrate is provided, comprising multiple oxide semiconductor TFTs with different properties from each other. [Solution] The active matrix substrate comprises a substrate and a plurality of oxide semiconductor TFTs. Each oxide semiconductor TFT has an oxide semiconductor layer including a channel region, a source contact region and a drain contact region, a lower gate electrode and an upper gate electrode. In a plan view, the protrusion width of the lower gate electrode from the upper gate electrode toward the source contact region is called the first protrusion width, the protrusion width of the lower gate electrode from the upper gate electrode toward the drain contact region is called the second protrusion width, and the sum of the first and second protrusion widths is called the third protrusion width. The plurality of oxide semiconductor TFTs include a first TFT and a second TFT whose third protrusion widths are different from each other.

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate comprising oxide semiconductor TFTs. The present invention also relates to a display device comprising such an active matrix substrate. [Background technology]

[0002] Active matrix substrates used in liquid crystal displays, organic electroluminescent (EL) displays, etc., have a display area with multiple pixels and an area other than the display area (non-display area). In the display area, a thin-film transistor (TFT) is provided as a switching element for each pixel. Conventionally, TFTs with an amorphous silicon film as the active layer (hereinafter referred to as "amorphous silicon TFT") and TFTs with a polycrystalline silicon film as the active layer (hereinafter referred to as "polycrystalline silicon TFT") have been widely used.

[0003] In recent years, oxide semiconductors have been proposed as the material for the active layer of TFTs, replacing amorphous silicon and polycrystalline silicon. Such TFTs are called "oxide semiconductor TFTs." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs.

[0004] TFT structures are broadly classified into bottom-gate structures and top-gate structures. Currently, bottom-gate structures are often used in oxide semiconductor TFTs, but the use of top-gate structures has also been proposed (for example, Patent Document 1). In top-gate structures, the gate insulating layer can be made thinner, resulting in high current supply performance. More recently, a double-gate structure has also been proposed in which gate electrodes are provided above and below the active layer (for example, Patent Document 2).

[0005] In some cases, peripheral circuits, including TFTs, are monolithically (integrally) formed in the non-display area of ​​an active matrix substrate. For example, forming the drive circuit monolithically can reduce the size of the non-display area and lower costs by simplifying the mounting process. For instance, gate drive circuits are monolithically formed in the non-display area. In devices with a high demand for narrow bezels, such as smartphones, demultiplexer circuits, also known as Source Shared Driving (SSD) circuits, are sometimes monolithically formed.

[0006] In this specification, the TFTs (or multiple TFTs constituting the pixel circuit in an active matrix substrate used in an organic EL display device) placed at each pixel in the display area are referred to as "pixel TFTs." Furthermore, the TFTs constituting the peripheral circuits located in the non-display area are referred to as "peripheral circuit TFTs."

[0007] In active matrix substrates, from a manufacturing process standpoint, it is preferable that peripheral circuit TFTs also use the same oxide semiconductor film as pixel TFTs and be formed using a common process. Therefore, peripheral circuit TFTs and pixel TFTs usually have the same structure, and their TFT characteristics are almost identical. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2015-109315 [Patent Document 2] Patent No. 6486174 [Overview of the project] [Problems that the invention aims to solve]

[0009] However, the characteristics required for peripheral circuit TFTs and pixel TFTs can differ. Furthermore, even within peripheral circuit TFTs, the required characteristics can vary depending on the application.

[0010] Furthermore, in active matrix substrates used in organic EL display devices, a pixel circuit is provided within each pixel that includes at least two types of pixel TFTs (referred to as a "driving pixel TFT" and a "selecting pixel TFT"). The selecting pixel TFT has the function of selecting pixels by changing the voltage applied to the driving pixel TFT. The driving pixel TFT has the function of supplying the current necessary for light emission. Since the selecting pixel TFT and the driving pixel TFT perform different functions, the characteristics required for each may also differ.

[0011] Thus, in active matrix substrates equipped with multiple TFTs for different applications, it is necessary to fabricate multiple oxide semiconductor TFTs with different properties so that each TFT can possess the characteristics required for its respective application.

[0012] Embodiments of the present invention have been made in view of the above problems, and their object is to provide an active matrix substrate comprising a plurality of oxide semiconductor TFTs having different characteristics from each other. [Means for solving the problem]

[0013] This specification discloses active matrix substrates and display devices as described in the following sections.

[0014] [Item 1] circuit board and Multiple oxide semiconductor TFTs supported on the aforementioned substrate, Equipped with, Each of the aforementioned plurality of oxide semiconductor TFTs is An oxide semiconductor layer including a channel region and source contact regions and drain contact regions located on both sides of the channel region, A lower gate electrode disposed between the substrate and the oxide semiconductor layer, An upper gate electrode is positioned on the opposite side of the lower gate electrode relative to the oxide semiconductor layer, It has, In a plan view, when the protrusion width of the lower gate electrode from the upper gate electrode toward the source contact region side is referred to as the first protrusion width, the protrusion width of the lower gate electrode from the upper gate electrode toward the drain contact region side is referred to as the second protrusion width, and the sum of the first protrusion width and the second protrusion width is referred to as the third protrusion width, the plurality of oxide semiconductor TFTs include a first TFT and a second TFT having different third protrusion widths from each other, and an active matrix substrate.

[0015] [Item 2] The width along the channel length direction of the upper gate electrode of the first TFT and the width along the channel length direction of the upper gate electrode of the second TFT are substantially the same, and the active matrix substrate according to Item 1.

[0016] [Item 3] The third protrusion width of the first TFT is larger than the third protrusion width of the second TFT, and the active matrix substrate according to Item 1 or 2.

[0017] [Item 4] The first protrusion width and the second protrusion width of the first TFT are each 1 μm or more, and the active matrix substrate according to Item 3.

[0018] [Item 5] The first protrusion width and the second protrusion width of the first TFT are each 2 μm or less, and the active matrix substrate according to Item 3 or 4.

[0019] [Item 6] The first protrusion width and the second protrusion width of the second TFT are each 0 μm or less, and the active matrix substrate according to any one of Items 3 to 5.

[0020] [Item 7] Each of the plurality of oxide semiconductor TFTs includes a lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, An upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, It further possesses, In a plan view, when the protrusion width of the upper gate insulating layer from the upper gate electrode toward the source contact region is called the fourth protrusion width, and the protrusion width of the upper gate insulating layer from the upper gate electrode toward the drain contact region is called the fifth protrusion width, The fourth and fifth protrusion widths of the first TFT are each 0.5 μm or less. An active matrix substrate according to any one of items 3 to 6, wherein the fourth and fifth protrusion widths of the second TFT are each 1 μm or more.

[0021] [Item 8] Each of the aforementioned plurality of oxide semiconductor TFTs is A lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, An upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, It further possesses, When the two edges located at both ends of the upper gate insulating layer in the channel length direction are called the first edge and the second edge, and the two edges located at both ends of the lower gate electrode in the channel length direction are called the third edge and the fourth edge, The first and second edges of the upper gate insulating layer of the first TFT are located inward in the channel length direction compared to the third and fourth edges of the lower gate electrode of the first TFT. The active matrix substrate according to any one of items 3 to 7, wherein the first and second edges of the upper gate insulating layer of the second TFT are located outward in the channel length direction than the third and fourth edges of the lower gate electrode of the second TFT.

[0022] [Item 9] The oxide semiconductor layer of the first TFT is formed in the same layer as the oxide semiconductor layer of the second TFT, in the active matrix substrate according to any one of items 3 to 8.

[0023] [Item 10] The oxide semiconductor layer of the first TFT is formed in a separate layer from the oxide semiconductor layer of the second TFT. An active matrix substrate according to any one of items 3 to 8, wherein the mobility of the oxide semiconductor layer of the first TFT is higher than the mobility of the oxide semiconductor layer of the second TFT.

[0024] [Item 11] The active matrix substrate according to any one of items 1 to 10, wherein the plurality of oxide semiconductor TFTs include oxide semiconductor TFTs in which the second protrusion width is greater than the first protrusion width.

[0025] [Item 12] The oxide semiconductor layer is an active matrix substrate according to any one of items 1 to 9, comprising an In-Ga-Zn-O semiconductor.

[0026] [Item 13] The oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT each contain In and / or Sn. The active matrix substrate according to item 10, wherein the sum of the atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the second TFT is smaller than the sum of the atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the first TFT.

[0027] [Item 14] The active matrix substrate according to item 10, wherein both the oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT contain an In-Ga-Zn-O semiconductor, and the atomic ratio of In to all metal elements in the oxide semiconductor layer of the second TFT is lower than the atomic ratio of In to all metal elements in the oxide semiconductor layer of the first TFT.

[0028] [Item 15] A display device comprising an active matrix substrate as described in any of items 1 to 14.

[0029] [Item 16] A liquid crystal display device, as described in item 15.

[0030] [Item 17] The display device described in item 15, which is an organic EL display device. [Effects of the Invention]

[0031] According to embodiments of the present invention, an active matrix substrate comprising a plurality of oxide semiconductor TFTs having different characteristics from each other can be provided. [Brief explanation of the drawing]

[0032] [Figure 1] This is a schematic cross-sectional view showing an active matrix substrate 100 according to an embodiment of the present invention. [Figure 2] This is a schematic plan view of the active matrix substrate 100. [Figure 3] This graph shows the relationship between the first protrusion width PW1 and the second protrusion width PW2 and the mobility μ. [Figure 4] This graph shows the relationship between the first protrusion width PW1 and the second protrusion width PW2, and the source-drain withstand voltage. [Figure 5] This is a cross-sectional view showing an example of an oxide semiconductor TFT 10 in which the first protrusion width PW1 and the second protrusion width PW2 are different. [Figure 6A]This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6B] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6C] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6D] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6E] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6F] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6G] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 6H] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 100. [Figure 7] This is a schematic cross-sectional view of the active matrix substrate 100. [Figure 8] This is a schematic cross-sectional view showing an active matrix substrate 200 according to an embodiment of the present invention. [Figure 9] This is a schematic plan view of the active matrix substrate 200. [Figure 10A] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10B] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10C] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10D] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10E] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10F]This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10G] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10H] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10I] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 10J] This is a cross-sectional view illustrating the manufacturing method of the active matrix substrate 200. [Figure 11] This is a schematic cross-sectional view of the active matrix substrate 200. [Figure 12] This is a schematic plan view illustrating an active matrix substrate 301 for a liquid crystal display device. [Figure 13] This is a schematic plan view illustrating an active matrix substrate 302 for an organic EL display device. [Figure 14] This figure shows an example of a pixel circuit PC on an active matrix substrate 302. [Modes for carrying out the invention]

[0033] The characteristics required for TFTs mounted on an active matrix substrate may differ depending on their application. Examples of suitable TFT characteristics are described below. Note that the applications and required characteristics of TFTs are not limited to the examples below.

[0034] As already explained, in an active matrix substrate used in an organic EL display device, a pixel circuit including at least a driving pixel TFT and a selection pixel TFT is provided within each pixel. From the viewpoint of current control and suitable multi-gradation display, it is preferable that the driving pixel TFT has a relatively smooth (i.e., not steep) Vg (gate voltage)-Id (drain current) characteristic. On the other hand, it is preferable that the selection pixel TFT has high mobility (i.e., a large on-current).

[0035] Even in peripheral circuit TFTs, the required characteristics of the TFT differ depending on the application and function. For example, among peripheral circuit TFTs, TFTs used in demultiplexer circuits (hereinafter referred to as "DMX circuit TFTs") and some TFTs that make up drive circuits (such as output transistors) require relatively large on-currents and thus high mobility.

[0036] Furthermore, among the TFTs in an active matrix substrate, those to which relatively high voltages are applied require high source-drain breakdown voltage.

[0037] Thus, the characteristics required of the TFTs in an active matrix substrate can vary depending on their application. As a result of detailed studies, the inventors of the present invention discovered that the electrical characteristics of a double-gate oxide semiconductor TFT can be controlled and adjusted by changing the relative positional relationship between the upper gate electrode and the lower gate electrode, leading to the present invention. Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to the following embodiments.

[0038] [Embodiment 1] The active matrix substrate 100 of this embodiment will be described with reference to Figures 1 and 2. Figures 1 and 2 are schematic cross-sectional and plan views of the active matrix substrate 100.

[0039] As shown in Figures 1 and 2, the active matrix substrate 100 comprises a substrate 1 and a plurality of oxide semiconductor TFTs 10 supported on the substrate 1. In Figures 1 and 2, one oxide semiconductor TFT (hereinafter referred to as the "first TFT") 10A is shown on the right, and another oxide semiconductor TFT (hereinafter referred to as the "second TFT") 10B is shown on the left.

[0040] Each oxide semiconductor TFT 10 has an oxide semiconductor layer 11, a lower gate electrode 12, an upper gate electrode 13, a source electrode 14, and a drain electrode 15. Each oxide semiconductor TFT 10 also further has a lower gate insulating layer 16 and an upper gate insulating layer 17.

[0041] The oxide semiconductor layer 11 includes a channel region 11c and a source contact region 11s and a drain contact region 11d located on either side of the channel region 11c. The source contact region 11s and the drain contact region 11d are low-resistance regions with lower resistivity than the channel region 11c. Such low-resistance regions can be formed, for example, by performing a resistance reduction treatment on the oxide semiconductor layer 11 using the upper gate electrode 13 as a mask.

[0042] The lower gate electrode 12 is positioned between the substrate 1 and the oxide semiconductor layer 11. In other words, the lower gate electrode 12 is located below the oxide semiconductor layer 11.

[0043] The lower gate insulating layer 16 is provided so as to cover the lower gate electrode 12 and is positioned between the lower gate electrode 12 and the oxide semiconductor layer 11. The lower gate electrode 12 faces the channel region 11c of the oxide semiconductor layer 11 via the lower gate insulating layer 16.

[0044] The upper gate electrode 13 is positioned on the opposite side of the oxide semiconductor layer 11 from the lower gate electrode 12. In other words, the upper gate electrode 13 is located above the oxide semiconductor layer 11.

[0045] The upper gate insulating layer 17 is positioned between the upper gate electrode 13 and the oxide semiconductor layer 11. The upper gate electrode 13 faces the channel region 11c of the oxide semiconductor layer 11 via the upper gate insulating layer 17.

[0046] The source electrode 14 is electrically connected to the source contact region 11s of the oxide semiconductor layer 11. The drain electrode 15 is electrically connected to the drain contact region 11d of the oxide semiconductor layer 11.

[0047] In the illustrated example, an interlayer insulating layer 18 is provided to cover the oxide semiconductor layer 11, the upper gate insulating layer 17, and the upper gate electrode 13, and the source electrode 14 and drain electrode 15 are placed on the interlayer insulating layer 18.

[0048] The interlayer insulating layer 18 and the upper gate insulating layer 17 have source contact holes CHs that expose the source contact region 11s of the oxide semiconductor layer 11 and drain contact holes CHd that expose the drain contact region 11d of the oxide semiconductor layer 11. The source electrode 14 is connected to the source contact region 11s through the source contact holes CHs. The drain electrode 15 is connected to the drain contact region 11d through the drain contact hole CHd.

[0049] In the illustrated example, for both the first TFT10A and the second TFT10B, the width W along the channel length direction of the lower gate electrode 12 is L However, the width W along the channel length direction of the upper gate electrode 13 U It is larger than that. Also, in both the first TFT 10A and the second TFT 10B, in a plan view, the lower gate electrode 12 protrudes from the upper gate electrode 13 on both sides (source contact region 11s side and drain contact region 11d side).

[0050] In the following, the protrusion width PW1 of the lower gate electrode 12 from the upper gate electrode 13 toward the source contact region 11s will be referred to as the "first protrusion width," and the protrusion width PW2 of the lower gate electrode 12 from the upper gate electrode 13 toward the drain contact region 11d will be referred to as the "second protrusion width." Furthermore, the sum of the first protrusion width PW1 and the second protrusion width PW2 (i.e., PW1 + PW2) will be referred to as the "third protrusion width."

[0051] In this embodiment, the third protrusion width of the first TFT10A and the third protrusion width of the second TFT10B are different from each other. This point will be explained in more detail below.

[0052] As shown in Figures 1 and 2, in this embodiment, the width W of the lower gate electrode 12 of the first TFT 10A L However, the width W of the lower gate electrode 12 of the second TFT 10B L It is larger than that. On the other hand, the width D of the upper gate electrode 13 of the first TFT 10A U And the width D of the upper gate electrode 13 of the second TFT 10B. U These are essentially the same. Therefore, the third overhang width of the first TFT10A is greater than the third overhang width of the second TFT10B. More specifically, the first overhang width PW1 of the first TFT10A is greater than the first overhang width PW1 of the second TFT10B, and the second overhang width PW2 of the first TFT10A is greater than the second overhang width PW2 of the second TFT10B.

[0053] The inventors of this application conducted a detailed study of the structure and properties of a double-gate oxide semiconductor TFT and found that the mobility of the oxide semiconductor TFT can be controlled and adjusted by changing the protrusion width of the lower gate electrode (the first, second, and third protrusion widths described above). Specifically, they found that the mobility can be increased by increasing the third protrusion width. In the illustrated example, the third protrusion width of the first TFT 10A is larger than the third protrusion width of the second TFT 10B, so the mobility of the first TFT 10A can be made higher than that of the second TFT 10B.

[0054] Figure 3 shows the results of verifying the effect on mobility μ by changing the first and second protrusion widths PW1 and PW2 (while maintaining the relationship PW1=PW2) for four prototype oxide semiconductor TFTs (Samples 1-4). Samples 1-4 were fabricated in the same manner as described later, referring to Figures 6A-6H. Note that Samples 1 and 4 have slightly different specifications from Samples 2 and 3, which will be explained later.

[0055] Figure 3 shows that as the first and second protrusion widths PW1 and PW2 increase (i.e., as the third protrusion width increases), the mobility μ increases. Thus, it was confirmed that the mobility of the oxide semiconductor TFT 10 can be controlled and adjusted by changing the protrusion widths of the lower gate electrode 12 (first protrusion width PW1, second protrusion width PW2, and third protrusion width).

[0056] Furthermore, Figure 3 shows that when the first protrusion width PW1 and the second protrusion width PW2 are 1 μm or more, the effect of increasing the mobility μ is high. Therefore, from the viewpoint of increasing the mobility of the first TFT10A, it is preferable that the first protrusion width PW1 and the second protrusion width PW2 of the first TFT10A are each 1 μm or more.

[0057] Furthermore, Figure 3 shows that when the first protrusion width PW1 and the second protrusion width PW2 exceed 2 μm, the mobility improvement effect is almost saturated. If the first protrusion width PW1 and the second protrusion width PW2 are too large, leakage current may occur between the lower gate electrode 12 and the source electrode 14, or between the lower gate electrode 12 and the drain electrode 15, for example, if a pinhole occurs in the oxide semiconductor layer 11. Therefore, from the viewpoint of ensuring reliability, it is preferable that the first protrusion width PW1 and the second protrusion width PW2 of the first TFT 10A are each 2 μm or less.

[0058] As can be seen from the plot in Figure 3, where the cases where the first protrusion width PW1 and the second protrusion width PW2 are -0.5 μm are plotted, the first protrusion width PW1 and the second protrusion width PW2 can each take negative values.

[0059] The first protrusion width PW1 is a negative value when, in a plan view, the upper gate electrode 13 protrudes from the lower gate electrode 12 toward the source contact region 11s. In that case, the first protrusion width PW1 is obtained by reversing the sign of the protrusion width of the upper gate electrode 13 from the lower gate electrode 12 toward the source contact region 11s. For example, if the upper gate electrode 13 protrudes 0.5 μm from the lower gate electrode 12 toward the source contact region 11s, the first protrusion width PW1 is -0.5 μm.

[0060] Similarly, the second protrusion width PW2 is negative when, in a plan view, the upper gate electrode 13 protrudes from the lower gate electrode 12 toward the drain contact region 11d. In that case, the second protrusion width PW2 is obtained by reversing the sign of the protrusion width of the upper gate electrode 13 from the lower gate electrode 12 toward the drain contact region 11d. For example, if the upper gate electrode 13 protrudes 0.5 μm from the lower gate electrode 12 toward the drain contact region 11d, the second protrusion width PW2 is -0.5 μm.

[0061] Figures 1 and 2 illustrate the case where the first and second protrusion widths PW1 and PW2 of the second TFT10B are positive values. However, the first and second protrusion widths PW1 and PW2 of the second TFT10B (an oxide semiconductor TFT10 with relatively low mobility) may each be 0 μm or less.

[0062] As explained above, the mobility of the oxide semiconductor TFT 10 can be controlled and adjusted by changing the protrusion width of the lower gate electrode 12 (first protrusion width PW1, second protrusion width PW2, and third protrusion width). Furthermore, the inventors have found that increasing the protrusion width of the lower gate electrode 12 can increase the source-drain breakdown voltage of the oxide semiconductor TFT 10.

[0063] Figure 4 shows the results of verifying the effect on source-drain breakdown voltage for Sample 3 by changing the first protrusion width PW1 and the second protrusion width PW2 (while maintaining the relationship PW1=PW2). From Figure 4, it can be seen that when the first protrusion width PW1 and the second protrusion width PW2 are less than 0 μm, the source-drain breakdown voltage decreases. Therefore, from the viewpoint of ensuring source-drain breakdown voltage, it is preferable that the first protrusion width PW1 and the second protrusion width PW2 of the oxide semiconductor TFT 10, to which a relatively high source-drain voltage is applied, are both 0 μm or more.

[0064] When considering a single oxide semiconductor TFT 10, its first protrusion width PW1 and second protrusion width PW2 may be the same or different. Figure 5 shows an example of an oxide semiconductor TFT 10 in which the first protrusion width PW1 and the second protrusion width PW2 are different. In the example shown in Figure 5, the second protrusion width PW2 is larger than the first protrusion width PW1.

[0065] When a large source-drain voltage is applied to a TFT, causing dielectric breakdown, the semiconductor layer suffers greater damage on the drain side (i.e., the drain contact region) than on the source side (i.e., the source contact region). If, due to layout constraints, it is difficult to increase both the first protrusion width PW1 and the second protrusion width PW2, the reliability of the oxide semiconductor TFT 10 can be improved by making the second protrusion width PW2 larger than the first protrusion width PW1, as illustrated in Figure 5.

[0066] Here, the manufacturing method of the active matrix substrate 100 will be explained with reference to Figures 6A to 6H. Figures 6A to 6H are cross-sectional view steps illustrating the manufacturing method of the active matrix substrate 100.

[0067] First, as shown in Figure 6A, a lower gate electrode 12 is formed on the substrate 1. Specifically, a conductive film for the lower gate (thickness: for example, 50 nm to 500 nm) is formed on the insulating substrate 1 by sputtering or the like, and then the lower gate electrode 12 can be formed by patterning the conductive film for the lower gate. At this time, the width W of the lower gate electrode 12 for the first TFT 10A (shown on the right in Figure 6A) is... L However, the width W of the lower gate electrode 12 for the second TFT 10B (shown on the left in Figure 6A) L The lower gate electrode 12 is formed so that it is larger than the above.

[0068] For example, the substrate 1 can be a glass substrate, a heat-resistant plastic substrate (resin substrate), or the like.

[0069] As the conductive film for the lower gate, a metal film containing an element selected from, for example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy film composed of these elements can be used. Alternatively, a multilayer film containing multiple of these films may be used. Here, a metal film or alloy film containing Cu or Al is used as the conductive film for the lower gate.

[0070] Next, as shown in Figure 6B, a lower gate insulating layer 16 is formed to cover the lower gate electrode 12. The lower gate insulating layer 16 can be formed, for example, by a CVD method. The thickness of the lower gate insulating layer 16 is, for example, 200 nm to 600 nm.

[0071] As the lower gate insulating layer 16, a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxide-nitride (SiOxNy; x>y) layer, a silicon oxide nitride (SiNxOy; x>y) layer, etc., can be used as appropriate. The lower gate insulating layer 16 may have a laminated structure. For example, a silicon nitride layer, a silicon oxide nitride layer, etc. may be formed on the substrate 1 side (lower layer) to prevent the diffusion of impurities from the substrate 1, and a silicon oxide layer, a silicon oxide-nitride layer, etc. may be formed on the layer above (upper layer) to ensure insulation.

[0072] Next, as shown in Figure 6C, an oxide semiconductor layer 11 is formed on the lower gate insulating layer 16. Specifically, the oxide semiconductor layer 11 can be formed by first depositing an oxide semiconductor film using a sputtering method, and then patterning the oxide semiconductor film. Here, an In-Ga-Zn-O based semiconductor film is used as the oxide semiconductor film. The patterning of the oxide semiconductor film can be performed, for example, by wet etching using a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etching solution.

[0073] Next, as shown in Figure 6D, an upper gate insulating layer 17 is formed to cover the lower gate insulating layer 16 and the oxide semiconductor layer 11. The upper gate insulating layer 17 can be formed, for example, by a CVD method. As the upper gate insulating layer 17, for example, an insulating layer similar to the lower gate insulating layer 16 (exemplified as the lower gate insulating layer 16) can be used. Here, a silicon oxide layer is formed as the upper gate insulating layer 17. By using an oxide layer such as a silicon oxide layer as the upper gate insulating layer 17, the oxygen vacancies generated in the channel region 11c of the oxide semiconductor layer 11 can be reduced by the oxide layer, thereby suppressing the reduction of resistance in the channel region 11c. The thickness of the upper gate insulating layer 17 is, for example, 50 nm to 200 nm.

[0074] Next, as shown in Figure 6E, the upper gate electrode 13 is formed on the upper gate insulating layer 17. Specifically, the upper gate electrode 13 can be formed by first forming a conductive film for the upper gate (thickness: for example, 50 nm to 500 nm) on the upper gate insulating layer 17 by sputtering or the like, and then patterning the conductive film for the upper gate. The same conductive film as the conductive film for the lower gate can be used as the conductive film for the upper gate.

[0075] After this, the oxide semiconductor layer 11 may be subjected to a low-resistance treatment. The low-resistance treatment may be, for example, plasma treatment. As a result of the low-resistance treatment, the region of the oxide semiconductor layer 11 that does not overlap with the upper gate electrode 13 becomes a low-resistance region (source contact region 11s and drain contact region 11d) with lower resistivity than the region that overlaps with the upper gate electrode 13 (channel region 11c). Note that the method of the low-resistance treatment is not limited to that exemplified here.

[0076] Next, as shown in Figure 6F, an interlayer insulating layer 18 is formed to cover the upper gate insulating layer 17 and the upper gate electrode 13. The interlayer insulating layer 18 can be formed, for example, by the CVD method. As the interlayer insulating layer 18, inorganic insulating layers such as silicon oxide (SiO2) layers, silicon nitride (SiNx) layers, silicon oxynitride (SiOxNy; x>y) layers, and silicon oxide nitride (SiNxOy; x>y) layers can be used as a single layer or in stacked layers. The thickness of the interlayer insulating layer 18 is, for example, 200 nm to 700 nm. Here, a silicon oxide layer is used as the interlayer insulating layer 18.

[0077] Next, as shown in Figure 6G, source contact holes CHs and drain contact holes CHd are formed in the interlayer insulating layer 18 and the upper gate insulating layer 17. Specifically, the formation of source contact holes CHs and drain contact holes CHd can be carried out by a photolithography process and etching. Etching may be dry etching, for example.

[0078] Next, as shown in Figure 6H, a source electrode 14 is formed on the interlayer insulating layer 18 and in the source contact hole CHs, and a drain electrode 15 is formed on the interlayer insulating layer 18 and in the drain contact hole CHd. Specifically, a conductive film for the source (thickness: for example, 50 nm to 500 nm) is formed on the interlayer insulating layer 18, in the source contact hole CHs, and in the drain contact hole CHd, and then the conductive film for the source is patterned to form the source electrode 14 and the drain electrode 15. The patterning of the conductive film for the source can be done, for example, by dry etching or wet etching. As the conductive film for the source, for example, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing these elements can be used. For example, it may have a three-layer structure such as titanium film-aluminum film-titanium film, or a three-layer structure such as molybdenum film-aluminum film-molybdenum film. Note that the conductive film for the source is not limited to a three-layer structure; it may have a single layer, a two-layer structure, or a multilayer structure of four or more layers. Here, a multilayer film is used with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0079] In this way, an active matrix substrate 100 equipped with the first TFT 10A and the second TFT 10B is obtained.

[0080] In Figure 1 and other figures, an example is shown in which the upper gate insulating layer 17 covers not only the channel region 11c of the oxide semiconductor layer 11 but also the source contact region 11s and the drain contact region 11d (more precisely, the portion of the source contact region 11s that does not overlap with the source contact hole CHs and the portion of the drain contact region 11d that does not overlap with the drain contact hole CHd). However, embodiments of the present invention are not limited to this configuration, and the configuration shown in Figure 7 may also be adopted. In the configuration shown in Figure 7, the upper gate insulating layer 17 is patterned such that it does not cover the source contact region 11s and the drain contact region 11d (more precisely, the portion of the source contact region 11s that does not overlap with the source contact hole CHs and the portion of the drain contact region 11d that does not overlap with the drain contact hole CHd) at least partially.

[0081] In the configuration illustrated in Figure 7, in a plan view, the upper gate insulating layer 17 protrudes slightly from the upper gate electrode 13 towards the source contact region 11s and the drain contact region 11d. Hereinafter, the protrusion width PW4 of the upper gate insulating layer 17 from the upper gate electrode 13 towards the source contact region 11s will be referred to as the "fourth protrusion width," and the protrusion width PW5 of the upper gate insulating layer 17 from the upper gate electrode 13 towards the drain contact region 11d will be referred to as the "fifth protrusion width."

[0082] In the configuration illustrated in Figure 7, the fourth protrusion width PW4 of the first TFT 10A is smaller than the fourth protrusion width PW4 of the second TFT 10B, and the fifth protrusion width PW5 of the first TFT 10A is smaller than the fifth protrusion width PW5 of the second TFT 10B. Furthermore, when the two edges E1 and E2 located at both ends in the channel length direction of the upper gate insulating layer 17 are called the "first edge" and the "second edge," and the two edges E3 and E4 located at both ends in the channel length direction of the lower gate electrode 12 are called the "third edge" and the "fourth edge," the first edge E1 and the second edge E2 of the upper gate insulating layer 17 of the first TFT 10A are located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the first TFT 10A. In contrast, the first edge E1 and the second edge E2 of the upper gate insulating layer 17 of the second TFT 10B are located further outward in the channel length direction than the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the second TFT 10B.

[0083] According to the inventors' research, it has been found that the fourth protrusion width PW4 and the fifth protrusion width PW5 described above can also affect the mobility of the oxide semiconductor TFT 10. Specifically, from the viewpoint of increasing mobility, it is preferable that the fourth protrusion width PW4 and the fifth protrusion width PW5 be small, as the mobility can be increased by having the first edge E1 and the second edge E2 of the upper gate insulating layer 17 located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12. Therefore, when the mobility of the first TFT 10A is to be higher than that of the second TFT 10B, it is preferable that the fourth protrusion width PW4 of the first TFT 10A is smaller than the fourth protrusion width PW4 of the second TFT 10B, and the fifth protrusion width PW5 of the first TFT 10A is smaller than the fifth protrusion width PW5 of the second TFT 10B, as illustrated in Figure 7. Furthermore, it is preferable that the first edge E1 and the second edge E2 of the upper gate insulating layer 17 of the first TFT 10A are located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the first TFT 10A. On the other hand, the first edge E1 and the second edge E2 of the upper gate insulating layer 17 of the second TFT 10B may be located outward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the second TFT 10B.

[0084] Furthermore, samples 1 to 4, whose verification results are shown in Figure 3, have the configuration illustrated in Figure 7. The fourth and fifth protrusion widths PW4 and PW5 of samples 1 and 4 are smaller than those of samples 2 and 3. From Figure 3, it can be seen that the mobility of samples 1 and 4 is higher than that of samples 2 and 3.

[0085] From the viewpoint of increasing the mobility of the first TFT10A, it is preferable that the fourth protrusion width PW4 and the fifth protrusion width PW5 of the first TFT10A are, for example, 0.5 μm or less each. The fourth protrusion width PW4 and the fifth protrusion width PW5 of the second TFT10B may be 1 μm or more each.

[0086] [Embodiment 2] The active matrix substrate 200 of this embodiment will be described with reference to Figures 8 and 9. Figures 8 and 9 are schematic cross-sectional and plan views of the active matrix substrate 200. In the following description, the differences between the active matrix substrate 200 and the active matrix substrate 100 of Embodiment 1 will be the main focus.

[0087] In the active matrix substrate 100 of Embodiment 1, the oxide semiconductor layer 11 of the first TFT 10A is formed in the same layer as the oxide semiconductor layer 11 of the second TFT 10B (i.e., from the same oxide semiconductor film using the same process). In contrast, in the active matrix substrate 200 of this embodiment, the oxide semiconductor layer 11A of the first TFT 10A is formed in a separate layer from the oxide semiconductor layer 11B of the second TFT 10B (i.e., from different oxide semiconductor films using different processes). The mobility of the oxide semiconductor layer 11A of the first TFT 10A is higher than the mobility of the oxide semiconductor layer 11B of the second TFT 10B.

[0088] The lower gate insulating layer 16A of the first TFT 10A has a laminated structure including a lower layer 16l and an upper layer 16u placed on the lower layer 16l. The lower gate insulating layer 16B of the second TFT 10B is formed in the same layer as the lower layer 16l of the lower gate insulating layer 16A.

[0089] The upper gate insulating layer 17B of the second TFT 10B has a laminated structure including a lower layer 17l and an upper layer 17u placed on the lower layer 17l. The lower layer 17l of the upper gate insulating layer 17B is formed in the same layer as the upper layer 16u of the lower gate insulating layer 16A. The upper gate insulating layer 17A of the first TFT 10A is formed in the same layer as the upper layer 17u of the upper gate insulating layer 17B.

[0090] In the active matrix substrate 200 of this embodiment, the first protrusion width PW1 of the first TFT 10A is greater than the first protrusion width PW1 of the second TFT 10B, and the second protrusion width PW2 of the first TFT 10A is greater than the second protrusion width PW2 of the second TFT 10B. Therefore, the third protrusion width of the first TFT 10A is greater than the third protrusion width of the second TFT 10B. As a result, the mobility of the first TFT 10A can be made higher than the mobility of the second TFT 10B.

[0091] Furthermore, in the active matrix substrate 200 of this embodiment, the oxide semiconductor layer 11A of the first TFT 10A is formed in a separate layer from the oxide semiconductor layer 11B of the second TFT 10B, and the mobility of the oxide semiconductor layer 11A of the first TFT 10A is higher than the mobility of the oxide semiconductor layer 11B of the second TFT 10B. Therefore, the difference between the mobility of the first TFT 10A and the mobility of the second TFT 10B can be made even larger.

[0092] The composition, crystal structure, thickness, and formation method of the oxide semiconductor layers 11A and 11B are not particularly limited.

[0093] The compositions of the oxide semiconductor layers 11A and 11B may be different from each other. Here, "different compositions" means that the types or composition ratios of metal elements contained in each layer are different. For example, the oxide semiconductor layers 11A and 11B may each contain In and / or Sn, and the sum of the atomic ratios of In and Sn to all metal elements in oxide semiconductor layer 11B may be smaller than the sum of the atomic ratios of In and Sn to all metal elements in oxide semiconductor layer 11A.

[0094] Alternatively, both oxide semiconductor layers 11A and 11B may be In-Ga-Zn-O based oxide semiconductor layers, and the atomic ratio of In in oxide semiconductor layer 11B may be smaller than the atomic ratio of In in oxide semiconductor layer 11A. In this case, in one of the oxide semiconductor layers 11A and 11B, the atomic ratio of In to the total metal elements may be the same as the atomic ratio of Zn.

[0095] Furthermore, the oxide semiconductor layer 11A may contain Sn, while the oxide semiconductor layer 11B may not contain Sn. Alternatively, the oxide semiconductor layer 11B may contain Sn at a lower concentration than the oxide semiconductor layer 11A. In other words, the atomic ratio of Sn to all metal elements in the oxide semiconductor layer 11B may be smaller than the atomic ratio of Sn in the oxide semiconductor layer 11A.

[0096] As the oxide semiconductor layer 11B, for example, an In-Ga-Zn-O semiconductor layer (In:Ga:Zn=1:1:1, etc.) can be used. As the oxide semiconductor layer 11A, for example, an In-Ga-Zn-O semiconductor layer (In:Ga:Zn=3:1:2, etc.), an In-Sn-Zn-O semiconductor layer, an In-Al-Sn-Zn-O semiconductor layer, an In-W-Zn-O semiconductor layer, an In-Sn-O semiconductor layer, an In-Zn-O semiconductor layer, an In-Ga-Sn-O semiconductor layer, an In-Sn-Ti-Zn-O semiconductor layer, etc. can be used.

[0097] Furthermore, the oxide semiconductor layers 11A and 11B may have different crystal structures. For example, one of the oxide semiconductor layers 11A and 11B may be an amorphous oxide semiconductor layer, and the other may be a crystalline oxide semiconductor layer containing a crystalline portion.

[0098] Even if the ratios of each metal element in oxide semiconductor layers 11A and 11B are the same, it is possible to make the mobilities of these oxide semiconductor layers different by using different deposition methods or conditions. For example, when forming oxide semiconductor layers 11A and 11B with the same ratio of each metal element by sputtering, the atmosphere inside the chamber (e.g., the flow rate ratio of oxygen and Ar supplied to the chamber) may be different. Specifically, when forming oxide semiconductor layer 11B, the flow rate ratio of oxygen to Ar may be set high (e.g., 80%), and when forming oxide semiconductor layer 11A, the flow rate ratio of oxygen to Ar may be set lower than that of oxide semiconductor layer 11B (e.g., 20%). This makes it possible to lower the mobility of oxide semiconductor layer 11B to that of oxide semiconductor layer 11A.

[0099] Here, a method for manufacturing the active matrix substrate 200 will be described while referring to FIGS. 10A to 10H. FIGS. 10A to 10H are cross-sectional process diagrams for explaining the method for manufacturing the active matrix substrate 200.

[0100] First, as shown in FIG. 10A, a lower gate electrode 12 is formed on a substrate 1. Specifically, a conductive film for the lower gate is formed on the insulating substrate 1 by a sputtering method or the like, and then the lower gate electrode 12 can be formed by patterning the conductive film for the lower gate. At this time, the width W of the lower gate electrode 12 for the first TFT 10A (shown on the right side in FIG. 10A) L is made larger than the width W of the lower gate electrode 12 for the second TFT 10B (shown on the left side in FIG. 10A). As the conductive film for the lower gate, a conductive film similar to the conductive film for the lower gate in Embodiment 1 (exemplified as the conductive film for the lower gate) can be used. L Next, as shown in FIG. 10B, a lower layer 16l of the lower gate insulating layer 16A and the lower gate insulating layer 16B are formed by, for example, a CVD method. As the lower layer 16l of the lower gate insulating layer 16A and the lower gate insulating layer 16B, an insulating layer similar to the lower gate insulating layer 16 in Embodiment 1 (exemplified as the lower gate insulating layer 16) can be used.

[0101] Subsequently, as shown in FIG. 10C, an oxide semiconductor layer 11B is formed on the lower gate insulating layer 16B. Specifically, first, an oxide semiconductor film is deposited using a sputtering method, and then the oxide semiconductor layer 11B can be formed by patterning the oxide semiconductor film. Here, an In-Ga-Zn-O-based semiconductor film (In:Ga:Zn = 1:1:1) is used as the oxide semiconductor film.

[0102]

[0103] ​Next, as shown in Figure 10D, the upper layer 16u of the lower gate insulating layer 16A and the lower layer 17l of the upper gate insulating layer 17B are formed, for example, by CVD. Here, silicon oxide layers are formed as the upper layer 16u of the lower gate insulating layer 16A and the lower layer 17l of the upper gate insulating layer 17B.

[0104] Next, as shown in Figure 10E, an oxide semiconductor layer 11A is formed on the lower gate insulating layer 16A. Specifically, the oxide semiconductor layer 11A can be formed by first depositing an oxide semiconductor film using a sputtering method, and then patterning the oxide semiconductor film. Here, an In-Ga-Zn-O semiconductor film is used as the oxide semiconductor film for the oxide semiconductor layer 11A. As can be seen from the explanation already given, for example, by making the atomic ratio of In in the oxide semiconductor layer 11A greater than the atomic ratio of In in the oxide semiconductor layer 11B, the mobility of the oxide semiconductor layer 11A can be made higher than the mobility of the oxide semiconductor layer 11B (i.e., the mobility of the oxide semiconductor layer 11B can be made lower than the mobility of the oxide semiconductor layer 11A).

[0105] Next, as shown in Figure 10F, the upper gate insulating layer 17A and the upper layer 17u of the upper gate insulating layer 17B are formed, for example, by CVD. Here, a silicon oxide layer is formed as the upper gate insulating layer 17A and the upper layer 17u of the upper gate insulating layer 17B.

[0106] Next, as shown in Figure 10G, the upper gate electrode 13 is formed on the upper gate insulating layers 17A and 17B. Specifically, the upper gate electrode 13 can be formed by forming a conductive film for the upper gate on the upper gate insulating layer 17 by sputtering or the like, and then patterning the conductive film for the upper gate. The same conductive film as the conductive film for the lower gate can be used as the conductive film for the upper gate. After this, the oxide semiconductor layers 11A and 11B may be subjected to a resistance reduction treatment.

[0107] Next, as shown in Figure 10H, an interlayer insulating layer 18 is formed to cover the upper gate insulating layers 17A, 17B and the upper gate electrode 13. The interlayer insulating layer 18 can be formed, for example, by the CVD method. Here, a silicon oxide layer is used as the interlayer insulating layer 18.

[0108] Next, as shown in Figure 10I, source contact holes CHs and drain contact holes CHd are formed in the interlayer insulating layer 18 and the upper gate insulating layers 17A and 17B. Specifically, the formation of source contact holes CHs and drain contact holes CHd can be carried out by a photolithography process and etching. Etching may be dry etching, for example.

[0109] Next, as shown in Figure 10J, a source electrode 14 is formed on the interlayer insulating layer 18 and in the source contact hole CHs, and a drain electrode 15 is formed on the interlayer insulating layer 18 and in the drain contact hole CHd. Specifically, a conductive film for the source can be formed on the interlayer insulating layer 18, in the source contact hole CHs and in the drain contact hole CHd, and then the conductive film for the source can be patterned to form the source electrode 14 and the drain electrode 15. As the conductive film for the source, a conductive film similar to the conductive film for the source in Embodiment 1 (as exemplified as the conductive film for the source) can be used.

[0110] In this way, an active matrix substrate 200 equipped with the first TFT 10A and the second TFT 10B is obtained.

[0111] Figure 8 and others illustrate a configuration in which the upper gate insulating layers 17A and 17B cover not only the channel region 11c of the oxide semiconductor layers 11A and 11B but also the source contact region 11s and the drain contact region 11d (more precisely, the portion of the source contact region 11s that does not overlap with the source contact hole CHs and the portion of the drain contact region 11d that does not overlap with the drain contact hole CHd). However, embodiments of the present invention are not limited to such configurations, and the configuration shown in Figure 11 may also be adopted. In the configuration shown in Figure 11, the upper gate insulating layers 17A and 17B are patterned such that they do not cover the source contact region 11s and the drain contact region 11d (more precisely, the portion of the source contact region 11s that does not overlap with the source contact hole CHs and the portion of the drain contact region 11d that does not overlap with the drain contact hole CHd) at least partially.

[0112] In the configuration illustrated in Figure 11, in a plan view, the upper gate insulating layers 17A and 17B protrude slightly from the upper gate electrode 13 toward the source contact region 11s and the drain contact region 11d. The fourth protrusion width PW4 of the first TFT 10A is smaller than the fourth protrusion width PW4 of the second TFT 10B, and the fifth protrusion width PW5 of the first TFT 10A is smaller than the fifth protrusion width PW5 of the second TFT 10B. Furthermore, the first edge E1 and the second edge E2 of the upper gate insulating layer 17A of the first TFT 10A are located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the first TFT 10A. In contrast, the first edge E1 and the second edge E2 of the upper gate insulating layer 17B of the second TFT 10B are located further outward in the channel length direction than the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the second TFT 10B.

[0113] From the viewpoint of increasing mobility, it is preferable that the fourth protrusion width PW4 and the fifth protrusion width PW5 are small, and mobility can be increased by having the first edge E1 and the second edge E2 of the upper gate insulating layer located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12. Therefore, when the mobility of the first TFT 10A is to be higher than that of the second TFT 10B, it is preferable that the fourth protrusion width PW4 of the first TFT 10A is smaller than the fourth protrusion width PW4 of the second TFT 10B, and the fifth protrusion width PW5 of the first TFT 10A is smaller than the fifth protrusion width PW5 of the second TFT 10B, as illustrated in Figure 11. Furthermore, it is preferable that the first edge E1 and the second edge E2 of the upper gate insulating layer 17A of the first TFT 10A are located inward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the first TFT 10A. On the other hand, the first edge E1 and the second edge E2 of the upper gate insulating layer 17B of the second TFT 10B may be located outward in the channel length direction compared to the third edge E3 and the fourth edge E4 of the lower gate electrode 12 of the second TFT 10B.

[0114] From the viewpoint of increasing the mobility of the first TFT10A, it is preferable that the fourth protrusion width PW4 and the fifth protrusion width PW5 of the first TFT10A are, for example, 0.5 μm or less each. The fourth protrusion width PW4 and the fifth protrusion width PW5 of the second TFT10B may be 1 μm or more each.

[0115] [Structure of an active matrix substrate for liquid crystal display devices] The structure of the active matrix substrate 301 for liquid crystal display devices will be described with reference to Figure 12. Figure 12 is a schematic plan view illustrating the active matrix substrate 301.

[0116] As shown in Figure 12, the active matrix substrate 301 has a display area DR and a non-display area (also called the "peripheral area" or "frame area") FR. The display area DR is defined by multiple pixel areas PIX. The multiple pixel areas PIX are arranged in a matrix containing multiple rows and multiple columns. The non-display area FR is located around the display area DR and is an area that does not contribute to the display.

[0117] The display area DR is provided with multiple gate bus lines (gate signal lines) GL extending in the row direction and multiple source bus lines (source signal lines) SL extending in the column direction. The gate bus lines GL and source bus lines SL are supported by the substrate 1.

[0118] Figure 12 shows the equivalent circuit of the pixel region PIX in the first row and second column. Each pixel region PIX is provided with a pixel TFT2 and a pixel electrode PE. The pixel TFT2 is supplied with a scanning signal (gate signal) from the corresponding gate bus line GL and a video signal (source signal) from the corresponding source bus line SL. The pixel TFT2 is an oxide semiconductor TFT having an oxide semiconductor layer as the active layer. The pixel electrode PE is electrically connected to the pixel TFT2. In addition, a common electrode CE is also shown in the equivalent circuit in Figure 12. The common electrode CE may be provided on the active matrix substrate 301 side or on the opposing substrate (color filter substrate) side.

[0119] The active matrix substrate 301 includes a gate driver (gate drive circuit) 40 that drives the gate bus line GL and a source driver (source drive circuit) 50 that drives the source bus line SL. In the example shown in Figure 12, the active matrix substrate 301 further includes a demultiplexer circuit 60. The gate driver 40, source driver 50, and demultiplexer circuit 60 are located in the non-display area FR. The gate driver 40, source driver 50, and demultiplexer circuit 60 are either integrally (monolithically) formed on the active matrix substrate 301 or mounted on the active matrix substrate 301. For example, the gate driver 40 and demultiplexer circuit 60 are monolithically formed on the active matrix substrate 301, and the source driver 50 is mounted on the active matrix substrate 301. The gate driver 40 monolithically formed on the active matrix substrate 301 is sometimes called a "GDM circuit".

[0120] Multiple peripheral circuit TFTs (such as the gate driver 40 mentioned above) that constitute peripheral circuits are arranged in the non-display area FR of the active matrix substrate 301.

[0121] Thus, the active matrix substrate 301 has a plurality of pixel TFTs 2 in the display area DR and a plurality of peripheral circuit TFTs in the non-display area FR. Each of these TFTs may have the same structure as either the first TFT 10 or the second TFT 20 exemplified in Embodiments 1 and 2, depending on the required characteristics. For example, since peripheral circuit TFTs included in the GDM circuit require high mobility, it is preferable that they have the same structure as the first TFT 10. On the other hand, since pixel TFTs 2 do not require as high mobility as the peripheral circuit TFTs of the GDM circuit, they may have the same structure as the second TFT 20.

[0122] The active matrix substrate 301 is suitably used in liquid crystal display devices. A liquid crystal display device equipped with the active matrix substrate 301 further comprises a counter substrate (color filter substrate) arranged opposite the active matrix substrate 301, and a liquid crystal layer provided between the active matrix substrate 301 and the counter substrate.

[0123] [Structure of an active matrix substrate for organic EL display devices] The structure of the active matrix substrate 302 for the organic EL display device will be described with reference to Figure 13. Figure 13 is a schematic plan view showing the active matrix substrate 302.

[0124] The active matrix substrate 302 has multiple pixel regions PIX arranged in a matrix. The active matrix substrate 302 differs from the active matrix substrate 302 for liquid crystal display devices in that each pixel region PIX contains two or more pixel TFTs.

[0125] Figure 14 shows an example of a pixel circuit PC provided in each pixel region PIX of the active matrix substrate 302. The pixel circuit PC shown in Figure 14 includes a driving pixel TFT 3, a selection pixel TFT 4, and a capacitive element (holding capacitor) 5.

[0126] The gate electrode of the selection pixel TFT4 is connected to the gate bus line GL. The source electrode of the selection pixel TFT4 is connected to the source bus line SL. The drain electrode of the selection pixel TFT4 is connected to the gate electrode and capacitive element 5 of the driving pixel TFT3. The source electrode of the driving pixel TFT3 is connected to the current supply line CL. The drain electrode of the driving pixel TFT3 is connected to the OLED (organic light-emitting diode) 6 formed on the active matrix substrate 302.

[0127] When an ON signal is supplied from the gate bus line GL to the gate electrode of the selection pixel TFT4, the selection pixel TFT4 turns ON, and a signal voltage from the source bus line SL (corresponding to the desired luminescence brightness of the OLED6) is applied to the gate electrodes of the capacitive element 5 and the driving pixel TFT3 via the selection pixel TFT4. When the driving pixel TFT3 turns ON due to the signal voltage, current from the current supply line CL flows to the OLED6 via the driving pixel TFT3, causing the OLED6 to emit light.

[0128] According to embodiments of the present invention, multiple oxide semiconductor TFTs with different required characteristics (here, a driving pixel TFT3 and a selection pixel TFT4) can be fabricated within such a pixel circuit PC. From the viewpoint of current control and for suitable multi-gradation display, it is preferable that the driving pixel TFT3 has a relatively smooth (i.e., not steep) Vg (gate voltage)-Id (drain current) characteristic. On the other hand, it is preferable that the selection pixel TFT4 has high mobility (i.e., a large on-current). Therefore, it is preferable to employ the same structure as the first TFT10A already described for the selection pixel TFT4, and the same structure as the second TFT10B already described for the driving pixel TFT3.

[0129] Note that the pixel circuit PC is not limited to the configuration illustrated in Figure 12. The pixel circuit PC may have three or more pixel TFTs.

[0130] Furthermore, the active matrix substrate 300 may also include a GDM circuit. In that case, among the peripheral circuit TFTs included in the GDM circuit, those requiring high mobility may adopt the same structure as the first TFT 10A, while those for which a smooth Vg-Id characteristic is preferable from the viewpoint of current control may adopt the same structure as the second TFT 10B.

[0131] The active matrix substrate 302 is suitably used in organic EL display devices.

[0132] [About oxide semiconductors] The oxide semiconductor (also called a metal oxide or oxide material) contained in the oxide semiconductor layer of an oxide semiconductor TFT may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors in which the c-axis is oriented generally perpendicular to the layer plane.

[0133] The materials, structure, film formation method, and configuration of oxide semiconductor layers having a stacked structure for amorphous oxide semiconductors and the crystalline oxide semiconductors described above are described, for example, in Japanese Patent Application Publication No. 2014-0073911. For reference, all disclosures of Japanese Patent Application Publication No. 2014-0073911 are incorporated herein by reference.

[0134] The oxide semiconductor layer may contain, for example, at least one metal element from among In, Ga, and Zn. In this embodiment, the oxide semiconductor layer includes, for example, an In-Ga-Zn-O semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited, and include, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O semiconductor.

[0135] In-Ga-Zn-O semiconductors may be amorphous or crystalline. Among crystalline In-Ga-Zn-O semiconductors, those in which the c-axis is oriented approximately perpendicular to the layer plane are preferred.

[0136] The crystal structure of crystalline In-Ga-Zn-O semiconductors is disclosed, for example, in Japanese Patent Publication No. 2014-0073911, Japanese Patent Publication No. 2012-134475, and Japanese Patent Publication No. 2014-2090627. For reference, all disclosures of Japanese Patent Publication No. 2012-134475 and Japanese Patent Publication No. 2014-2090627 are incorporated herein by reference. TFTs having an In-Ga-Zn-O semiconductor layer have high mobility (more than 20 times that of a-SiTFTs) and low leakage current (less than 1 / 100th that of a-SiTFTs), and are therefore suitably used as driving TFTs (for example, TFTs included in a driving circuit provided on the same substrate as the display area around a display area containing multiple pixels) and pixel TFTs (TFTs provided on pixels).

[0137] The oxide semiconductor layer may contain other oxide semiconductors instead of the In-Ga-Zn-O system semiconductor. For example, it may contain an In-Sn-Zn-O system semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O system semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, In-W-Zn-O semiconductors, and the like. [Industrial applicability]

[0138] According to embodiments of the present invention, an active matrix substrate comprising multiple oxide semiconductor TFTs having different characteristics from each other can be provided. The active matrix substrate according to embodiments of the present invention is suitably used in display devices such as liquid crystal displays and organic EL displays. [Explanation of Symbols]

[0139] 1 circuit board 2-pixel TFT 3. Drive pixel TFT 4. Pixel TFT for selection 5 Capacitive elements 6 OLED 10. Oxide semiconductor TFT 10A 1st TFT 10B 2nd TFT 11, 11A, 11B Oxide semiconductor layer 11c channel region 11s Source Contact Area 11d Drain Contact Area 12 Lower gate 13 Upper gate 14 Source electrodes 15 Drain electrode 16, 16A, 16B Lower gate insulating layer 16L Lower gate insulation layer 16u upper layer of lower gate insulation layer 17, 17A, 17B Upper gate insulating layer 17L Lower layer of the upper gate insulation layer 17u Upper gate insulating layer 18 Interlayer insulating layer 40 Gate Drivers 50 Source Drivers 60 Demultiplexer Circuit 100, 200, 301, 302 Active Matrix Substrates CHs Source Contact Hole CHd Drain Contact Hole E1 First Edge E2 Second Edge E3 Third Edge E4 4th edge PIX Pixel Area GL Gate Bus Line SL Source Bus Line CL current supply line PE pixel electrode CE Common Electrode DR display area FR hidden area PC Pixel Circuit

Claims

1. circuit board and Multiple oxide semiconductor TFTs supported on the aforementioned substrate, Equipped with, Each of the aforementioned plurality of oxide semiconductor TFTs is An oxide semiconductor layer including a channel region and source contact regions and drain contact regions located on both sides of the channel region, A lower gate electrode disposed between the substrate and the oxide semiconductor layer, An upper gate electrode is positioned on the opposite side of the lower gate electrode relative to the oxide semiconductor layer, It has, In a plan view, when the protrusion width of the lower gate electrode from the upper gate electrode toward the source contact region is called the first protrusion width, the protrusion width of the lower gate electrode from the upper gate electrode toward the drain contact region is called the second protrusion width, and the sum of the first and second protrusion widths is called the third protrusion width, The plurality of oxide semiconductor TFTs include a first TFT and a second TFT, each having a different third protrusion width, in an active matrix substrate.

2. The active matrix substrate according to claim 1, wherein the width of the upper gate electrode of the first TFT along the channel length direction and the width of the upper gate electrode of the second TFT along the channel length direction are substantially the same.

3. The active matrix substrate according to claim 1 or 2, wherein the third protrusion width of the first TFT is greater than the third protrusion width of the second TFT.

4. The active matrix substrate according to claim 3, wherein the first protrusion width and the second protrusion width of the first TFT are each 1 μm or more.

5. The active matrix substrate according to claim 3, wherein the first protrusion width and the second protrusion width of the first TFT are each 2 μm or less.

6. The active matrix substrate according to claim 3, wherein the first protrusion width and the second protrusion width of the second TFT are each 0 μm or less.

7. Each of the aforementioned plurality of oxide semiconductor TFTs is A lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, An upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, It further possesses, In a plan view, when the protrusion width of the upper gate insulating layer from the upper gate electrode toward the source contact region is called the fourth protrusion width, and the protrusion width of the upper gate insulating layer from the upper gate electrode toward the drain contact region is called the fifth protrusion width, The fourth and fifth protrusion widths of the first TFT are each 0.5 μm or less. The active matrix substrate according to claim 3, wherein the fourth and fifth protrusion widths of the second TFT are each 1 μm or more.

8. Each of the aforementioned plurality of oxide semiconductor TFTs is A lower gate insulating layer disposed between the lower gate electrode and the oxide semiconductor layer, An upper gate insulating layer disposed between the upper gate electrode and the oxide semiconductor layer, It further possesses, When the two edges located at both ends of the upper gate insulating layer in the channel length direction are called the first edge and the second edge, and the two edges located at both ends of the lower gate electrode in the channel length direction are called the third edge and the fourth edge, The first and second edges of the upper gate insulating layer of the first TFT are located inward in the channel length direction compared to the third and fourth edges of the lower gate electrode of the first TFT. The active matrix substrate according to claim 3, wherein the first and second edges of the upper gate insulating layer of the second TFT are located outward in the channel length direction than the third and fourth edges of the lower gate electrode of the second TFT.

9. The active matrix substrate according to claim 3, wherein the oxide semiconductor layer of the first TFT is formed in the same layer as the oxide semiconductor layer of the second TFT.

10. The oxide semiconductor layer of the first TFT is formed as a separate layer from the oxide semiconductor layer of the second TFT. The active matrix substrate according to claim 3, wherein the mobility of the oxide semiconductor layer of the first TFT is higher than the mobility of the oxide semiconductor layer of the second TFT.

11. The active matrix substrate according to claim 1 or 2, wherein the plurality of oxide semiconductor TFTs include oxide semiconductor TFTs in which the second protrusion width is greater than the first protrusion width.

12. The active matrix substrate according to claim 1 or 2, wherein the oxide semiconductor layer comprises an In-Ga-Zn-O semiconductor.

13. The oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT each contain In and / or Sn. The active matrix substrate according to claim 10, wherein the sum of the atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the second TFT is smaller than the sum of the atomic ratios of In and Sn to all metal elements in the oxide semiconductor layer of the first TFT.

14. The active matrix substrate according to claim 10, wherein both the oxide semiconductor layer of the first TFT and the oxide semiconductor layer of the second TFT contain an In-Ga-Zn-O semiconductor, and the atomic ratio of In to all metal elements in the oxide semiconductor layer of the second TFT is lower than the atomic ratio of In to all metal elements in the oxide semiconductor layer of the first TFT.

15. A display device comprising an active matrix substrate according to claim 1 or 2.

16. The display device according to claim 15, which is a liquid crystal display device.

17. The display device according to claim 15, which is an organic EL display device.

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