Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. [Solution] A semiconductor structure and a method for forming the same, the structure comprising a substrate, a gate structure located on the substrate, a channel hole located on the substrate and penetrating the gate structure along the longitudinal direction, a sidewall extending along the longitudinal direction between the channel hole sidewall and the gate structure, and a compensation layer filling the gap between the channel hole and the gate structure at the bottom of the sidewall. The present invention helps to improve the operational performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly to semiconductor structures and methods of forming the same.

Background Art

[0002] Semiconductor devices implement integrated circuit (IC) chips on packages to meet the usage conditions of various electronic products. In recent years, in complex scenarios such as the Internet of Things and edge computing, the demand for integrated systems for dedicated processing applications has been continuously increasing. Integrated systems with functions integrated have requirements for the integration of underlying materials. However, conventional semiconductor memories are two-dimensional or planar semiconductor memories, and their integration density is an important factor determining the product price.

[0003] Also, since the integration density is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of micro-pattern formation technology. However, although the integration density of two-dimensional semiconductor memories has been improved, it is still limited because ultra-high-cost equipment is required for pattern miniaturization. Therefore, in order to meet the excellent performance and low cost required by consumers, it is necessary to improve the integration density of semiconductor memories.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved in embodiments of the present invention is to provide a semiconductor structure and a method of forming the same, which are advantageous for improving the operating performance of the semiconductor structure.

Means for Solving the Problems

[0005] To solve the above problems, embodiments of the present invention provide a semiconductor structure comprising a substrate, a gate structure located on the substrate, a channel hole located on the substrate and penetrating the gate structure along the longitudinal direction, a sidewall extending along the longitudinal direction between the channel hole sidewall and the gate structure, and a compensation layer filling the gap between the channel hole and the gate structure at the bottom of the sidewall.

[0006] Selectively, the semiconductor structure further includes a partition layer located between the sidewall and the channel hole sidewall, and the compensation layer is also filled in the gap between the channel hole and the gate structure at the bottom of the partition layer.

[0007] Selectively, the partition layer is a protective layer that covers the sidewall, or the partition layer is an air gap.

[0008] Selectively, the partition layer is a protective layer, and the materials of the protective layer include amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.

[0009] Selectively, the compensation layer is also filled into the gaps formed by the top of the sidewalls and the partition layer.

[0010] Selectively, the sidewall includes a first sidewall covering the gate structure sidewall and a second sidewall covering the first sidewall, wherein at the bottom of the sidewall, the gap to be filled with the compensation layer is surrounded by the bottom of the second sidewall, the bottom of the partition layer, the first sidewall, and the channel hole sidewall. At the top of the sidewall, the gap to be filled with the compensation layer is surrounded by the top of the second sidewall, the partition layer sidewall, and the first sidewall sidewall.

[0011] Selectively, the material for the first sidewall contains silicon nitride, and the material for the second sidewall contains silicon oxide.

[0012] Selectively, silicon nitride is included in the compensation layer material.

[0013] Selectively, the semiconductor structure further includes a top dielectric layer covering the top surface of the gate structure and a bottom dielectric layer located between the gate structure and the substrate, the channel hole further extends through the top and bottom dielectric layers, the sidewall also extends between the channel hole sidewall and the top dielectric layer, and the compensation layer fills the gap between the channel hole and the bottom dielectric layer.

[0014] Selectively, the semiconductor structure further includes a source-drain doped layer located within the substrate, with the source-drain doped layer exposed on the top surface of the substrate, and the channel holes located on the source-drain doped layer and in contact with each other.

[0015] Selectively, a groove is formed on the top side of the channel hole, located at a portion of the channel hole's height, and the semiconductor structure further includes an insulating layer filled within the groove.

[0016] Accordingly, embodiments of the present invention further provide a method for forming a semiconductor structure, which includes providing a substrate on which a gate structure is formed, forming an opening that penetrates the gate structure, forming a sidewall that covers the side wall of the opening, performing a gap compensation treatment at the bottom corner portion of the opening to form a compensation layer that fills the gap at the bottom of the sidewall, and forming a channel hole within the opening that is located on the substrate and penetrates the gate structure.

[0017] The process further includes, selectively, forming a protective layer covering the sidewall before performing gap compensation at the bottom corner of the opening, wherein in the step of performing gap compensation at the bottom corner of the opening, the compensation layer is also filled into the gap at the bottom of the protective layer at the bottom corner of the opening, and in the step of forming a channel hole within the opening that is located on the substrate and penetrates the gate structure, the channel hole is in contact with the protective layer.

[0018] The method includes selectively forming a channel hole within the opening, located on the substrate and penetrating the gate structure, and then further removing the protective layer to form an air gap located between the sidewall and the channel hole sidewall.

[0019] In the step of selectively performing gap compensation treatment at the bottom corner of the opening, the compensation layer is also filled into the gap formed by the top of the sidewall and the protective layer.

[0020] The step of selectively forming a sidewall covering the opening sidewall includes forming a sidewall material layer covering the opening sidewall and bottom and the top of the gate structure, and removing the sidewall material layer from the opening bottom and the top of the gate structure, leaving the sidewall material layer covering the opening sidewall as the sidewall.

[0021] Selectively, in the step of providing a substrate, a top dielectric layer is further formed on the top of the gate structure, and a bottom dielectric layer is further formed between the gate structure and the substrate; in the step of forming an opening that penetrates the gate structure, the opening further penetrates the top dielectric layer and extends to a portion of the thickness of the bottom dielectric layer; in the step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure, the step of removing the bottom dielectric layer to the excess thickness to expose the top surface of the substrate; in the step of performing gap compensation treatment at the bottom corner portion of the opening, the compensation layer is also filled into the gap formed by the bottom dielectric layer and the substrate at the bottom corner portion of the opening.

[0022] The step of selectively forming a sidewall material layer covering the opening sidewall and bottom and the top of the gate structure includes forming a first sidewall material layer covering the opening sidewall and bottom and the top of the gate structure, and forming a second sidewall material layer covering the first sidewall material layer, wherein the step of removing the sidewall material layers of the opening bottom and the top of the gate structure removes the first and second sidewall material layers of the opening bottom and the top of the gate structure, leaving the first sidewall material layer covering the opening sidewall as the first sidewall, leaving the second sidewall material layer covering the opening sidewall as the second sidewall, and the step of performing gap compensation treatment at the corner portion of the opening bottom, wherein the compensation layer is filled into the gap surrounded by the second sidewall bottom, the protective layer bottom, and the first sidewall, and further filled into the gap surrounded by the second sidewall top, the protective layer sidewall, and the first sidewall sidewall.

[0023] The process includes, selectively, forming a protective material layer covering the sidewall material layer before removing the sidewall material layer at the bottom of the opening and the top of the gate structure, and the step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure further includes removing the protective material layer at the bottom of the opening and the top of the gate structure, leaving the protective material layer covering the sidewall as a protective layer.

[0024] The process further includes selectively removing the sidewall material layer at the bottom of the opening and the top of the gate structure using a dry etching process, and then performing a cleaning treatment on the sidewalls after removing the sidewall material layer at the bottom of the opening and the top of the gate structure, before performing gap compensation treatment at the corner portion of the bottom of the opening.

[0025] Optionally, the step of performing gap compensation treatment at the corner portion of the bottom of the opening to form a compensation layer filled in the gap at the bottom of the sidewall includes forming a compensation material layer covering the gap filled at the bottom of the opening, the sidewall of the sidewall of the opening, the top of the gate structure, and the bottom of the sidewall, and removing the compensation material layer covering the bottom of the opening, the sidewall of the sidewall of the opening, and the top of the gate structure, and leaving the compensation material layer filled in the gap at the bottom of the sidewall as the compensation layer.

[0026] Optionally, an atomic layer deposition process or a low-pressure chemical vapor deposition process is adopted to form a compensation material layer filling the gap at the bottom of the opening, the sidewall of the sidewall of the opening, the top of the gate structure, and the bottom of the sidewall.

[0027] Optionally, a wet etching process is used to remove the compensation material layer covering the bottom of the opening, the sidewall of the sidewall of the opening, and the top of the gate structure.

[0028] Optionally, the etching solution for the wet etching process contains a phosphoric acid solution, the mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% - 86wt%, and the process temperature of the wet etching process is 100°C - 160°C.

[0029] Optionally, in the step of providing a substrate, a source-drain doped layer is further formed in the substrate, the source-drain doped layer is exposed on the top surface of the substrate, in the step of forming an opening penetrating the gate structure, an opening is formed above the source-drain doped layer, and in the step of forming a channel hole located on the substrate and penetrating the gate structure in the opening, the channel hole is formed on the source-drain doped layer and is in contact with the source-drain doped layer.

[0030] In the step of selectively forming a channel hole within an opening, located on the substrate and penetrating a gate structure, the channel hole is filled into the opening, or in the step of forming a channel hole within an opening, located on the substrate and penetrating a gate structure, a groove is formed on the top side of the channel hole, located at a portion of the height of the channel hole, and an insulating layer is formed to fill the groove.

[0031] Compared to the prior art, the technical method of the embodiment of the present invention has the following advantages.

[0032] In the semiconductor structure provided in the embodiment of the present invention, the channel hole is located on the substrate and penetrates the gate structure in the longitudinal direction, the sidewall extends longitudinally between the channel hole sidewall and the gate structure, and the compensation layer is filled in the gap between the channel hole and the gate structure at the bottom of the sidewall. In the embodiment of the present invention, by filling the gap between the channel hole and the gate structure at the bottom of the sidewall with the compensation layer, the blocking performance of the gate structure and channel hole at the bottom of the sidewall can be supplemented by the compensation layer, which helps to ensure the insulating effect between the gate structure and the channel hole, thereby reducing the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure satisfies the threshold voltage required for the process, and reducing the probability of drain-induced barrier reduction of the semiconductor structure, thereby helping to ensure the operating performance of the semiconductor structure.

[0033] In the forming method provided in the embodiment of the present invention, an opening is formed that penetrates the gate structure, a sidewall is formed that covers the side wall of the opening, a gap compensation treatment is performed on the bottom corner portion of the opening to form a compensation layer that fills the gap at the bottom of the sidewall, and a channel hole is formed within the opening that is located on the substrate and penetrates the gate structure. In the embodiment of the present invention, by performing a gap compensation treatment on the bottom corner portion of the opening, the compensation layer can be used to supplement the shielding performance between the gate structure and the channel hole at the bottom of the sidewall, which helps to ensure the insulating effect between the gate structure and the channel hole, thereby reducing the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure satisfies the threshold voltage required for the process, and reducing the probability of drain-induced barrier reduction in the semiconductor structure, thereby helping to ensure the operational performance of the semiconductor structure. [Brief explanation of the drawing]

[0034] [Figure 1] Figure 1 is a schematic diagram of the structure corresponding to the semiconductor structure.

[0035] [Figure 2] Figure 2 is a schematic diagram of a structure corresponding to one embodiment of the semiconductor structure in the present invention.

[0036] [Figure 3] Figure 3 is a schematic diagram of another embodiment of the semiconductor structure in the present invention.

[0037] [Figure 4] Figure 4 is a schematic diagram of a structure corresponding to yet another embodiment of the semiconductor structure in the present invention.

[0038] [Figure 5] Figure 5 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 6] Figure 6 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 7] Figure 7 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 8] Figure 8 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 9] Figure 9 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 10] Figure 10 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 11] Figure 11 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention. [Figure 12] Figure 12 is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention.

[0039] [Figure 13] Figure 13 is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method according to the present invention. [Figure 14] Figure 14 is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method according to the present invention. [Figure 15] Figure 15 is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method according to the present invention.

[0040] [Figure 16] Figure 16 is a schematic diagram of the structure corresponding to each step in yet another embodiment of the semiconductor structure formation method according to the present invention. [Modes for carrying out the invention]

[0041] From the background technology, it is clear that guaranteeing the operational performance of semiconductor structures is difficult at present. Here, we analyze the reasons why the operational performance of semiconductor structures has not yet improved when combined with a certain semiconductor structure.

[0042] Figure 1 shows a schematic diagram of the structure corresponding to the semiconductor structure.

[0043] Referring to Figure 1, the semiconductor structure includes a substrate 10 on which a source-drain doped layer 11 is formed, a gate structure 20 located on the substrate 10, a channel hole 61 located on the source-drain doped layer 11 within the substrate 10 and penetrating the gate structure 20 along the longitudinal direction, and a sidewall 46 extending along the longitudinal direction between the sidewall of the channel hole 61 and the gate structure 20.

[0044] In the semiconductor manufacturing process, damage is likely to occur at the bottom of the sidewall 46 during the formation process, resulting in a defect in the sidewall 46 at the bottom of the channel hole 61 (shown as a dotted circle in Figure 1). This leads to poor isolation performance between the channel hole 61 and the gate structure 20 at the bottom of the sidewall 46, resulting in leakage current (Off-state Leakage Current) between the gate structure 20 and the channel hole 61. off Because this is prone to occurring, the threshold voltage (V) of the semiconductor structure t This affects the semiconductor structure, causing drain-induced barrier low (DIBI), which in turn affects the operating performance of the semiconductor structure.

[0045] To solve the technical problems, embodiments of the present invention provide a semiconductor structure comprising a substrate, a gate structure located on the substrate, a channel hole located on the substrate and penetrating the gate structure along the longitudinal direction, a sidewall extending along the longitudinal direction between the channel hole sidewall and the gate structure, and a compensation layer filling the gap between the channel hole and the gate structure at the bottom of the sidewall.

[0046] In the embodiments of the present invention, a compensation layer is filled in the gap between the channel hole and the gate structure at the bottom of the sidewall. This compensation layer can be used to supplement the blocking performance of the gate structure and channel hole at the bottom of the sidewall, thereby helping to ensure the insulating effect between the gate structure and the channel hole. This reduces the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure satisfies the threshold voltage required for the process, and reducing the probability of drain-induced barrier degradation of the semiconductor structure, thereby helping to ensure the operational performance of the semiconductor structure.

[0047] To make the above-mentioned objectives, features, and advantages of the present invention clearer and easier to understand, specific embodiments of the present invention will be described in detail below in conjunction with the drawings.

[0048] Figure 2 is a schematic diagram of a structure corresponding to one embodiment of the semiconductor structure in the present invention.

[0049] Referring to Figure 2, the semiconductor structure includes a substrate 100, a gate structure 200 located on the substrate 100, a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 along the longitudinal direction, a sidewall 460 extending along the longitudinal direction between the sidewall of the channel hole 610 and the gate structure 200, and a compensation layer 510 filling the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460.

[0050] The substrate 100 provides the basis for process operations for the semiconductor structure formation process.

[0051] In this embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. For example, in this embodiment, the material of the substrate 100 is silicon oxide.

[0052] The gate structure 200 is used to control the opening and closing of the transistor channel.

[0053] In this embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of the following: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.

[0054] Channel hole 610 is used as the channel of a transistor.

[0055] Specifically, in this embodiment, the channel hole 610 extends vertically and penetrates the gate structure 200, forming a vertical channel transistor (VCT). The vertical channel design improves the integration density of transistors, allowing more transistors to be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0056] In this embodiment, the material for the channel hole 610 includes silicon, germanium, silicon germanide, or a III-V semiconductor material. For example, in this embodiment, the material for the channel hole 610 is silicon. In other embodiments, the material for the channel hole is determined by the type and performance of the transistor.

[0057] The sidewall 460 is used to separate the gate structure 200 from the channel hole 610.

[0058] In this embodiment, the sidewall 460 includes a first sidewall 440 that covers the sidewall of the gate structure 200 and a second sidewall 450 that covers the sidewall of the first sidewall 440.

[0059] By employing a sidewall 460 consisting of a first sidewall 440 and a second sidewall 450, it is not only possible to ensure the separation effect of the sidewall 460, but the dielectric constant of the sidewall 460 can also be adjusted by the first sidewall 440 and the second sidewall 450.

[0060] Specifically, in this embodiment, the material for the first sidewall 440 contains silicon nitride, and the material for the second sidewall 450 contains silicon oxide.

[0061] In this embodiment, the thickness of the first sidewall 440 is 1 nm to 8 nm, which provides sufficient thickness to the first sidewall 440 and thereby helps to ensure the shielding performance of the sidewall 460, and moreover, the first sidewall 440 does not occupy an excessive amount of space in order to satisfy the integration density of the semiconductor structure.

[0062] In this embodiment, the thickness of the second sidewall 450 is 1 nm to 8 nm, which provides sufficient thickness to the second sidewall 450 and thereby helps to ensure the shielding performance of the sidewall 460, and moreover, the second sidewall 450 does not occupy an excessive amount of space in order to satisfy the integration density of the semiconductor structure.

[0063] The compensation layer 510 is filled in the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460 (shown as a dotted circle in Figure 2), and is used to compensate for the separation effect between the gate structure 200 and the channel hole 610 at the bottom of the sidewall 460.

[0064] In this embodiment, since the compensation layer 510 is filled in the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460, the compensation layer 510 can be used to supplement the blocking performance between the gate structure 200 and the channel hole 610 at the bottom of the sidewall 460. This helps to ensure the insulating effect between the gate structure 200 and the channel hole 610, thereby reducing the probability of leakage current occurring between the gate structure 200 and the channel hole 610, ensuring that the semiconductor structure satisfies the threshold voltage required for the process, and reducing the probability of drain-induced barrier reduction in the semiconductor structure, thereby helping to ensure the operational performance of the semiconductor structure.

[0065] It should be explained that in the semiconductor manufacturing process, the bottom of the sidewall 460 is easily damaged by the process, and gaps are likely to form. Therefore, a compensation layer 510 is filled into the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460.

[0066] In this embodiment, the material of the compensation layer 510 contains silicon nitride.

[0067] By using silicon nitride to form the compensation layer 510, a relatively good shielding effect can be achieved. Moreover, because silicon nitride has relatively high hardness, damage during the semiconductor manufacturing process is relatively small, and the shielding effect of the compensation layer 510 can be guaranteed.

[0068] In this embodiment, the semiconductor structure further includes a partition layer 480 located between the sidewall 460 and the sidewall of the channel hole 610.

[0069] The partition layer 480 is located between the sidewall 460 and the sidewall of the channel hole 610, and the area of ​​the partition layer 480 is used to provide protection to the sidewall 460 during the process of forming the channel hole 610.

[0070] In this embodiment, the compensation layer 510 is also filled in the gap between the channel hole 610 and the gate structure 200 at the bottom of the partition layer 480.

[0071] Specifically, in the semiconductor manufacturing process, when the partition layer 480 covers the sidewall 460, the bottom of the partition layer 480 damages the sidewall 460 during the sidewall 460 formation process. In response, the compensation layer 510 also fills the gap between the channel hole 610 and the gate structure 200 at the bottom of the partition layer 480.

[0072] In this embodiment, the thickness of the partition layer 480 is 3 nm to 12 nm.

[0073] Since the partition layer 480 has a thickness of 3nm to 12nm, it helps to reduce the difficulty of forming the partition layer 480 and also helps to provide sufficient protection to the sidewall 460.

[0074] In this embodiment, the compensation layer 510 is also filled into the gap formed by the top of the sidewall 460 and the partition layer 480.

[0075] It should be explained that in the semiconductor manufacturing process, the top of the sidewall 460 is also exposed from the partition layer 480, so the top of the sidewall 460 is easily damaged by the process and gaps are formed. Therefore, the compensation layer 510 fills the gap enclosed by the top of the sidewall 460 and the partition layer 480.

[0076] Specifically, in this embodiment, at the bottom of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the bottom of the second sidewall 450, the bottom of the partition layer 480, the first sidewall 440, and the side wall of the channel hole 610, and at the top of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the top of the second sidewall 450, the side wall of the partition layer 480, and the side wall of the first sidewall 440.

[0077] It should be explained that in the semiconductor manufacturing process, first, sidewalls 460 covering the sidewalls of the gate structure 200 are formed, and then channel holes 610 are formed between the sidewalls 460. In the manufacturing process of the sidewalls 460, the second sidewall 450 is closer to the process operation area than the first sidewall 440, so the second sidewall 450 is more susceptible to damage. Moreover, the material of the first sidewall 440 contains silicon nitride, while the material of the second sidewall 450 contains silicon oxide, and silicon oxide is more susceptible to damage than silicon nitride, so the top and bottom of the second sidewall 450 are easily damaged and partially removed by the process. Therefore, at the bottom of the sidewall 460, the gap to which the compensation layer 510 is filled is surrounded by the bottom of the second sidewall 450, the bottom of the partition layer 480, the first sidewall 440, and the side wall of the channel hole 610, and at the top of the sidewall 460, the gap to which the compensation layer 510 is filled is surrounded by the top of the second sidewall 450, the side wall of the partition layer 480, and the side wall of the first sidewall 4400.

[0078] In this embodiment, the partition layer 480 is a protective layer 470, and the protective layer 470 covers the side wall of the side wall 460.

[0079] The protective layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 and to reduce damage to the sidewall 460.

[0080] In this embodiment, the material of the protective layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.

[0081] By using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride to form the protective layer 470, a good protective effect can be achieved. Furthermore, by leaving the protective layer 470 on both sides of the channel hole 610, other elements that are prone to contamination are not drawn in, thus helping to ensure the basic operating performance of the transistor.

[0082] In this embodiment, the semiconductor structure further includes a top dielectric layer 320 that covers the top surface of the gate structure 200.

[0083] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.

[0084] In this embodiment, the material of the top dielectric layer 320 is an insulating material and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0085] In response to this, in this embodiment, the sidewall 460 further extends between the sidewall of the channel hole 610 and the top dielectric layer 320.

[0086] In this embodiment, the semiconductor structure further includes a bottom dielectric layer 310 located between the gate structure 200 and the substrate 100.

[0087] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures below it.

[0088] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material and includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0089] In response to this, in this embodiment, the channel hole 610 is further extended to penetrate the top dielectric layer 320 and the bottom dielectric layer 310.

[0090] In this embodiment, the compensation layer 510 is also filled in the gap between the channel hole 610 and the bottom dielectric layer 310.

[0091] In the semiconductor manufacturing process, a protective layer 470 is first formed to cover the sidewall 460, and then a region is formed to create a channel hole 610 that penetrates the bottom dielectric layer 310. During the process, the sidewall of the bottom dielectric layer 310 is also exposed to the outside, and the bottom dielectric layer 310 is partially damaged by the process. Therefore, in the manufacturing process of the compensation layer 510, the compensation layer 510 is also filled into the gap between the channel hole 610 and the bottom dielectric layer 310.

[0092] In this embodiment, the semiconductor structure further includes a source-drain doped layer 110 located within the substrate 100, with the source-drain doped layer 110 exposed on the top surface of the substrate 100.

[0093] The source-drain doping layer 110 is used as either the source or drain region of the transistor. Specifically, the doping type of the source-drain doping layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0094] In this embodiment, the source-drain doping layer 110 is exposed on the top surface of the substrate 100 and is used to bring the channel holes 610 located on the substrate 100 into contact with each other.

[0095] Accordingly, in this embodiment, the channel hole 610 is located on the source-drain doping layer 110 and is in contact with the source-drain doping layer 110.

[0096] Figure 3 is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0097] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment lies in the structure of the channel hole.

[0098] Referring to Figure 3, a groove 620 is formed on the top side of the channel hole 611, located in part of the height of the channel hole 611, and the semiconductor structure further includes an insulating layer 640 that fills the groove 620.

[0099] Since the channel hole 611 is not filled in the area between it and the sidewall 461, and the groove 620 is filled with an insulating layer 640, it is helpful to obtain a top surface of the channel hole 611 with good surface flatness.

[0100] In this embodiment, the material of the insulating layer 640 is an insulating material and includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0101] Figure 4 is a schematic diagram of another embodiment of the semiconductor structure in the present invention.

[0102] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment lies in the structure of the partition layer.

[0103] Referring to Figure 4, the partition layer 482 is an air gap 650.

[0104] The air gap 650, along with the sidewall 462, is used to separate the gate structure 202 from the channel hole 612.

[0105] Specifically, in this embodiment, the positions occupied by the protective layer are formed in advance, the channel holes 612 are formed, and then the protective layer is removed to form the air gap 650.

[0106] In this embodiment, the air gap 650, together with the sidewall 462, separates the gate structure 202 and the channel hole 612. Since air has a low dielectric constant, the air gap 650 and the sidewall 462 work together to separate the gate structure 202 and the channel hole 612, which helps to lower the overall dielectric constant of the separation between the gate structure 202 and the channel hole 612, thereby reducing parasitic capacitance and improving the operating performance of the semiconductor structure.

[0107] Figures 5 to 12 are schematic diagrams of structures corresponding to each step in one embodiment of the semiconductor structure formation method according to the present invention.

[0108] Referring to Figure 5, a substrate 100 is provided, and a gate structure 200 is formed on the substrate 100.

[0109] The substrate 100 provides the basis for process operations for the semiconductor structure formation process.

[0110] In this embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. For example, in this embodiment, the material of the substrate 100 is silicon oxide.

[0111] The gate structure 200 is used to control the opening and closing of the transistor channel.

[0112] In this embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of the following: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.

[0113] In this embodiment, in the step of providing the substrate 100, a top dielectric layer 320 is further formed on the top of the gate structure 200, and a bottom dielectric layer 310 is further formed between the gate structure 200 and the substrate 100.

[0114] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.

[0115] In this embodiment, the material of the top dielectric layer 320 is an insulating material and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0116] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures below it.

[0117] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material and includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0118] In this embodiment, in the step of providing the substrate 100, a source-drain doping layer 110 is further formed inside the substrate 100, and the source-drain doping layer 110 is exposed on the top surface of the substrate 100.

[0119] The source-drain doping layer 110 is used as either the source or drain region of the transistor. Specifically, the doping type of the source-drain doping layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0120] In this embodiment, the source-drain doping layer 110 is exposed on the top surface of the substrate 100 and is used to bring the channel holes later formed on the substrate 100 into contact with each other.

[0121] Continuing to refer to Figure 5, an opening 210 is formed that penetrates the gate structure 200.

[0122] The opening 210 is used to provide space for the formation of subsequent side walls and channel holes.

[0123] In response to this, in this embodiment, in the step of forming an opening 210 that penetrates the gate structure 200, the opening 210 further penetrates the top dielectric layer 320 and extends to a portion of the thickness of the bottom dielectric layer 310.

[0124] The opening 210 extends to a portion of the thickness of the bottom dielectric layer 310, and the remaining portion of the thickness of the bottom dielectric layer 310 covers the top surface of the source-drain doped layer 110, thus providing protection to the source-drain doped layer 110 in the subsequent step of forming the sidewall.

[0125] In this embodiment, in the step of forming an opening 210 that penetrates the gate structure 200, the opening 210 is formed above the source drain dope layer 110.

[0126] By forming an opening 210 above the source-drain doping layer 110, the channel holes that are formed later can be brought into contact with the source-drain doping layer 110.

[0127] Referring to Figures 6 and 7 together, a side wall 460 is formed that covers the side wall of the opening 210.

[0128] The sidewall 460 is used to separate the gate structure 200 from the channel hole that will be formed later.

[0129] Referring to Figure 6, the step of forming a sidewall 460 covering the side wall of the opening 210 includes forming a sidewall material layer 400 covering the side wall and bottom of the opening 210 and the top of the gate structure 200.

[0130] The sidewall material layer 400 is used to form the sidewall 460.

[0131] Specifically, in this embodiment, the step of forming a sidewall material layer 400 that covers the side walls and bottom of the opening 210 and the top of the gate structure 200 includes forming a first sidewall material layer 410 that covers the side walls and bottom of the opening 210 and the top of the gate structure 200.

[0132] The first sidewall material layer 410 is used to form the first sidewall.

[0133] In this embodiment, the material of the first sidewall material layer 410 contains silicon nitride.

[0134] In this embodiment, in the step of forming a first sidewall material layer 410 that covers the side walls and bottom of the opening 210 and the top of the gate structure 200, the thickness of the first sidewall material layer 410 is 1 nm to 8 nm, which helps to give the later-formed first sidewall sufficient thickness, thereby ensuring the shielding performance of the sidewall 460, and moreover, the first sidewall does not occupy an excessive amount of space in order to satisfy the integration density of the semiconductor structure.

[0135] In this embodiment, a second sidewall material layer 420 is formed to cover the first sidewall material layer 410.

[0136] Specifically, the second sidewall material layer 420 conformally covers the first sidewall material layer 410, and the second sidewall material layer 420 is used to form the second sidewall.

[0137] In this embodiment, the material of the second sidewall material layer 420 contains silicon oxide.

[0138] In this embodiment, in the step of forming a second sidewall material layer 420 that covers the first sidewall material layer 410, the thickness of the second sidewall material layer 420 is 1 nm to 8 nm, which helps to ensure sufficient thickness for the second sidewall formed later, thereby guaranteeing the shielding performance of the sidewall 460, and moreover, the second sidewall does not occupy an excessive amount of space in order to satisfy the integration density of the semiconductor structure.

[0139] Referring to Figure 7, the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 has been removed, leaving the sidewall material layer 400 covering the side wall of the opening as the sidewall 460.

[0140] In this embodiment, the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 is removed using a dry etching process.

[0141] Since the dry etching process has the characteristics of anisotropic etching, selecting the dry etching process helps reduce damage to the substrate 100 at the bottom of the opening 210. At the same time, because dry etching has stronger etching directionality, it also helps improve the external shape quality and dimensional accuracy of the sidewall 460.

[0142] Specifically, in this embodiment, in the step of removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the first sidewall material layer 410 and the second sidewall material layer 420 at the bottom of the opening 210 and the top of the gate structure 200 are removed, the first sidewall material layer 410 covering the side wall of the opening 210 is left as the first sidewall 440, and the second sidewall material layer 420 covering the side wall of the opening 210 is left as the second sidewall 450.

[0143] By employing a sidewall 460 consisting of a first sidewall 440 and a second sidewall 450, it is not only possible to ensure the separation effect of the sidewall 460, but the dielectric constant of the sidewall 460 can also be adjusted by the first sidewall 440 and the second sidewall 450.

[0144] Specifically, in this embodiment, the material of the first sidewall 440 contains silicon nitride, and the material of the second sidewall 450 contains silicon oxide.

[0145] In this embodiment, the protective layer 470 covering the sidewall 460 is formed before later performing gap compensation treatment on the corner portion of the bottom of the opening 210.

[0146] The protective layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 and to reduce damage to the sidewall 460.

[0147] In this embodiment, in the step of forming a protective layer 470 that covers the sidewall 460, the material of the protective layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

[0148] By using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride to form the protective layer 470, a good protective effect can be achieved. Furthermore, by leaving the protective layer 470 on both sides of the channel hole after the channel hole is formed, other elements that are prone to contamination are not drawn in, thus helping to ensure the basic operating performance of the transistor.

[0149] Specifically, referring to Figure 6, this includes forming a protective material layer 430 that covers the sidewall material layer 400 before removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200.

[0150] Specifically, the protective material layer 430 conformally covers the sidewall material layer 400, and the protective material layer 430 is used to form the protective layer 470.

[0151] Referring to Figure 7, the step of removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 further includes removing the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200, leaving the protective material layer 430 covering the sidewall 460 as the protective layer 470.

[0152] Specifically, in this embodiment, a dry etching process is used to remove the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200.

[0153] In this embodiment, the step of removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 further includes removing the excess thickness of the bottom dielectric layer 310 to expose the top surface of the substrate 100.

[0154] Specifically, in this embodiment, the excess thickness of the bottom dielectric layer 310 is removed, exposing the top surface of the source-drain doped layer 110 of the substrate 100, in preparation for forming channel holes that will later come into contact with the source-drain doped layer 110.

[0155] Referring to Figure 8, after removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the process further includes cleaning the sidewall 460 before performing gap compensation treatment at the corner portion of the bottom of the opening 210.

[0156] The manufacturing process for forming the sidewall 460 tends to leave residue, particularly at the bottom of the opening 210. In this embodiment, since a dry etching process is used to form the sidewall 460 and the protective layer 470, dry etching residue tends to accumulate in the opening 210. Therefore, the sidewall 460 is cleaned to remove the residue in the opening 210, reducing contamination of the subsequent manufacturing process and providing a good process platform for the subsequent manufacturing process.

[0157] It should be explained that when cleaning the sidewall 460, damage may occur to the top and bottom of the sidewall 460 where the protective layer 470 is exposed. Specifically, the material of the first sidewall 440 is silicon nitride, and the material of the second sidewall 450 is silicon oxide. Since silicon oxide is more easily damaged, the cleaning process removes a portion of the second sidewall 450 at the top of the sidewall 460 and a portion of the second sidewall 450 at the bottom of the sidewall 460. At the same time, the opening 210 also penetrates the bottom dielectric layer 310, meaning that the bottom dielectric layer 310 is also exposed at the opening 210. Therefore, the cleaning process also removes a portion of the bottom dielectric layer 310 at the bottom corner of the opening 210.

[0158] In this example, a diluted hydrofluoric acid (DHF) solution is used as the cleaning solution for the cleaning process.

[0159] The etching rate of diluted hydrofluoric acid solution is relatively slow and stable, which helps to facilitate cleaning and minimize damage to the film layer. It should also be noted that cleaning solutions containing fluorine are prone to causing etching damage to silicon dioxide.

[0160] Specifically, in this embodiment, the volume ratio of water to hydrofluoric acid in the diluted hydrofluoric acid solution is 100:1 to 2000:1.

[0161] In other embodiments, a diluted sulfuric acid peroxide (DSP) mixed solution or an SST-A47 organic solution may be used as the cleaning solution for the cleaning process.

[0162] Referring to Figures 9 and 10 together, gap compensation treatment is performed at the bottom corner portion of the opening 210, forming a compensation layer 510 that fills the gap at the bottom of the sidewall 460 (shown as a dotted circle in Figure 10).

[0163] The compensation layer 510 is filled into the bottom of the sidewall 460 at the bottom corner of the opening 210, after which a channel hole is formed within the opening 210. That is, the compensation layer 510 is used to fill the gap between the later-formed channel hole and the gate structure 200 to compensate for the separation effect between the gate structure 200 at the bottom of the sidewall 460 and the channel hole.

[0164] In this embodiment, by performing gap compensation treatment at the bottom corner portion of the opening 210, the compensation layer 510 can be used to supplement the blocking performance between the gate structure 200 and the channel hole 610 at the bottom of the sidewall 460. This helps to ensure the insulating effect between the gate structure 200 and the channel hole 610, thereby reducing the probability of leakage current occurring between the gate structure 200 and the channel hole 610, ensuring that the semiconductor structure satisfies the threshold voltage required for the process, and reducing the probability of drain-induced barrier reduction in the semiconductor structure, thereby helping to ensure the operational performance of the semiconductor structure.

[0165] In this embodiment, when the sidewall 460 is cleaned, the sidewall 460 is damaged by the exposed protective layer 470 at the bottom of the sidewall 460. Therefore, in the step of performing gap compensation treatment at the bottom corner portion of the opening 210, the compensation layer 510 is further filled into the gap at the bottom of the protective layer 470 at the bottom corner portion of the opening 210.

[0166] In this embodiment, when the sidewall 460 is cleaned, the sidewall 460 is damaged by the top of the sidewall 460 where the protective layer 470 is exposed. Therefore, in the step of performing gap compensation treatment at the bottom corner portion of the opening 210, the compensation layer is also filled into the gap formed by the top of the sidewall 460 and the protective layer 470.

[0167] Specifically, in this embodiment, the material of the second sidewall 450 is silicon oxide and the material of the first sidewall 440 is silicon nitride. Since silicon oxide is easily damaged, a gap is created in a part of the second sidewall 450 after the top and bottom have been removed. Therefore, in the step of performing gap compensation treatment at the bottom corner portion of the opening 210, the compensation layer 510 is filled into the gap surrounded by the bottom of the second sidewall 450, the bottom of the protective layer 470, and the first sidewall 440. Furthermore, the compensation layer 510 is also filled into the gap surrounded by the top of the second sidewall 450, the side wall of the protective layer 470, and the first sidewall 440.

[0168] In this embodiment, when the sidewall 460 is subjected to cleaning, a portion of the bottom dielectric layer 310 at the bottom corner of the opening 210 is also removed during the cleaning process. Therefore, in the step of performing gap compensation processing at the bottom corner of the opening 210, the compensation layer 510 is also filled into the gap formed by the bottom dielectric layer 310 at the bottom corner of the opening 210 and the substrate 100.

[0169] In this embodiment, in the step of forming a compensation layer 510 to fill the gap at the bottom of the sidewall 460, the material of the compensation layer 510 contains silicon nitride.

[0170] By using silicon nitride to form the compensation layer 510, a good shielding effect can be achieved. Moreover, because silicon nitride has relatively high hardness, damage during the semiconductor manufacturing process is relatively small, and the shielding effect of the compensation layer 510 can be guaranteed.

[0171] Specifically, referring to Figure 9, the step of performing gap compensation treatment on the bottom corner portion of the opening 210 and forming a compensation layer 510 to fill the gap at the bottom of the sidewall 460 includes forming a compensation material layer 500 that covers the gaps at the bottom of the opening 210, the sidewall 460 of the side wall of the opening 210, the top of the gate structure 200, and the bottom of the sidewall 460.

[0172] The compensation material layer 500 is used to form the compensation layer 510.

[0173] Specifically, in this embodiment, the compensation material layer 500 is also filled into the gap at the top of the sidewall 460 and the gap in the bottom dielectric layer 310 at the bottom corner portion of the opening 210.

[0174] In this embodiment, in the step of forming a compensating material layer 500 that covers the gaps filled in the bottom of the opening 210, the side walls 460 of the side walls of the opening 210, the top of the gate structure 200, and the bottom of the side walls 460, the thickness of the compensating material layer 500 is 1 nm to 10 nm.

[0175] The compensation material layer 500 has a thickness of 1 nm to 10 nm, which allows the compensation material layer 500 to adequately fill the gaps without causing unnecessary waste of material.

[0176] In this embodiment, an atomic layer deposition (ALD) process is used to form a compensating material layer 500 that covers the gaps filled in the bottom of the opening 210, the side walls 460 of the side walls of the opening 210, the top of the gate structure 200, and the bottom of the side walls 460.

[0177] The compensation material layer 500 formed using the atomic layer deposition process has good thickness uniformity and good step coverage capability, and the compensation material layer 500 can appropriately conformally cover the gaps filled in the bottom of the opening 210, the side walls of the sidewalls 460 covering the side walls of the opening 210, the top of the gate structure 200, and the bottom of the sidewalls 460.

[0178] In other embodiments, a low-pressure chemical vapor deposition (LPCVD) process can be used to form a compensating material layer that covers the gaps filled in the bottom of the opening, the sidewalls of the opening sidewalls, the top of the gate structure, and the bottom of the sidewalls.

[0179] Referring to Figure 10, the bottom of the opening 210, the side walls of the sidewall 460 covering the side walls of the opening 210, and the compensation material layer 500 at the top of the gate structure 200 are removed, while the compensation material layer that fills the gap at the bottom of the sidewall 460 is left as the compensation layer 510.

[0180] Specifically, in this embodiment, the compensation material layer 500 that fills the gap on the top surface of the sidewall 460 and the gap in the bottom dielectric layer 310 at the bottom corner portion of the opening 210 is also left as the compensation layer 510.

[0181] In this embodiment, a wet etching process is used to remove the compensation material layer 500 covering the bottom of the opening 210, the sidewall 460 of the side wall of the opening 210, and the top of the gate structure 200.

[0182] The wet etching process is relatively inexpensive, has simple operating steps, and can achieve a relatively high etching selectivity ratio, thus helping to reduce damage to other film layers during the process of removing the compensating material layer 500 covering the bottom of the opening 210, the sidewalls 460 of the opening 210's sidewalls, and the top of the gate structure 200.

[0183] In this embodiment, the etching solution for the wet etching process includes a phosphoric acid solution.

[0184] Phosphoric acid has a relatively high viscosity, typically 37.10 mPa.s. This means that while the phosphoric acid solution has a relatively high viscosity, it does not easily penetrate gaps and does not react well with the compensating material layer 500 inside the gaps. Therefore, the wet etching process can easily leave the compensating material layer 500 inside the gaps when removing the compensating material layer 500 covering the bottom of the opening 210, the side walls 460 of the side walls of the opening 210, and the top of the gate structure 200, thus aiding in the formation of the compensating layer 510.

[0185] In this example, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 86 wt%.

[0186] The phosphoric acid solution has a mass percentage ratio of 40 wt% to 86 wt%, which helps to cleanly remove the compensating material layer 500 covering the bottom of the opening 210, the side walls 460 of the opening 210's sidewalls, and the top of the gate structure 200, while maintaining a relatively high viscosity, making it easier to leave the compensating material layer 500 in the gaps.

[0187] Specifically, in this embodiment, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 60 wt%.

[0188] By adjusting the mass percentage of phosphoric acid in the phosphoric acid solution to 40 wt% to 60 wt%, the etching rate can be slowed, which helps to make wet etching easier to control.

[0189] In this example, the process temperature for the wet etching process is 100°C to 160°C.

[0190] By setting the process temperature of the wet etching process to 100°C to 160°C, efficient etching is maintained while also preserving relatively good etching quality.

[0191] Specifically, in this embodiment, the process temperature of the wet etching process is 100°C to 130°C.

[0192] Setting the process temperature of the wet etching process to 100°C to 130°C helps to slow down the etching rate and make wet etching easier to control.

[0193] When Figures 11 and 12 are referred to together, a channel hole 610 is formed within the opening 210, located on the substrate 100 and penetrating the gate structure 200.

[0194] Channel hole 610 is used as the channel of a transistor.

[0195] Specifically, in this embodiment, the channel hole 610 extends along the vertical direction and penetrates the gate structure 200, forming a vertical channel transistor (VCT). Through this vertical channel design, the integration density of transistors is improved, allowing more transistors to be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0196] In this embodiment, the material for the channel hole 610 includes silicon, germanium, silicon germanide, or a III-V semiconductor material. For example, in this embodiment, the material for the channel hole 610 is silicon. In other embodiments, the material for the channel hole is determined by the type and performance of the transistor.

[0197] In response to this, in this embodiment, in the step of forming a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 within the opening 210, the channel hole 610 is in contact with the protective layer 470.

[0198] In this embodiment, the top surface of the source-drain doping layer 110 is exposed in the opening 210. Correspondingly, in the step of forming a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 within the opening 210, the channel hole 610 is formed on the source-drain doping layer 110 and is in contact with the source-drain doping layer 110.

[0199] In this embodiment, in the step of forming a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 within the opening 210, the channel hole 610 is filled into the opening 210.

[0200] Specifically, referring to Figure 11, the step of forming a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 within the opening 210 includes forming a channel material layer 600 that fills the opening 210 and covers the top of the top dielectric layer 320.

[0201] The channel material layer 600 is used to form the channel hole 610.

[0202] Referring to Figure 12, the channel material layer 600 is planarized, the channel material layer 600 that is higher than the top dielectric layer 320 is removed, and the channel material layer 600 that filled the opening 210 is left as a channel hole 610.

[0203] Figures 13 to 15 are schematic diagrams of structures corresponding to each step in another embodiment of the semiconductor structure formation method according to the present invention.

[0204] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment lies in the structure of the channel hole.

[0205] Referring to Figures 13 to 15 in combination, in the step of forming a channel hole 611 located on the substrate 101 and penetrating the gate structure 201 within the opening 211, a groove 620 is formed on the top side of the channel hole 611, located in part of the height of the channel hole 611.

[0206] Since the channel hole 611 is not filled in the region between the openings 211, it helps to reduce the probability of depressions occurring on the top surface of the formed channel hole 611.

[0207] In this embodiment, an insulating layer 640 is formed to fill the groove 620.

[0208] The filling of the groove 620 with an insulating layer 640 helps to obtain a top surface of the channel hole 611 with excellent surface flatness.

[0209] In this embodiment, in the step of forming an insulating layer 640 to fill the groove 620, the material of the insulating layer 640 is an insulating material and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0210] Specifically, referring to Figure 13, a channel material layer 601 is formed to cover the side walls and bottom of the opening 211 and the top of the top dielectric layer 321, and a groove 620 is formed to surround the channel material layer 601 within the opening 211.

[0211] The channel material layer 601 is used to form the channel hole 611.

[0212] Referring to Figure 14, an insulating material layer 630 is formed which fills the groove 620 and covers the channel material layer 601.

[0213] The insulating material layer 630 is used to form the insulating layer 640.

[0214] Referring to Figure 15, the insulating material layer 630 and the channel material layer 601 are flattened, the insulating material layer 630 and the channel material layer 601 that are higher than the top dielectric layer 321 are removed, the channel material layer 601 in the opening 211 is left as a channel hole 611, and the insulating material layer 630 in the opening 211 is left as an insulating layer.

[0215] Figure 16 is a schematic diagram of the structure corresponding to each step in yet another embodiment of the semiconductor structure formation method according to the present invention.

[0216] The same parts of this embodiment as those of the previously described embodiment will not be repeated here. The difference between this embodiment and the previously described embodiment is that the protective layer is removed.

[0217] Referring to Figure 16, a channel hole 612 is formed within the opening 212, located on the substrate 102 and penetrating the gate structure 202. Then, the protective layer is removed to form an air gap 650 located between the side wall 462 and the side wall of the channel hole 612.

[0218] The air gap 650, along with the sidewall 462, is used to separate the gate structure 202 from the channel hole 612.

[0219] In this embodiment, the air gap 650, together with the sidewall 462, separates the gate structure 202 and the channel hole 612. Since air has a low dielectric constant, the air gap 650 and the sidewall 462 work together to separate the gate structure 202 and the channel hole 612, which helps to lower the overall dielectric constant of the separation between the gate structure 202 and the channel hole 612, thereby reducing parasitic capacitance and improving the operating performance of the semiconductor structure.

[0220] Although disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the scope of protection of the present invention must be limited to the scope defined in the claims. [Explanation of Symbols]

[0221] 10 circuit boards 11. Source-Drain Doped Layer 20 Gate Structure 46 Sidewall 61 Channel Hole 100 circuit boards 101 circuit board 102 circuit boards 110 Source-Drain Doped Layer 200 gate structure 201 Gate structure 202 Gate structure 210 Aperture 211 Aperture 212 Aperture 310 Bottom dielectric layer 320 Top dielectric layer 321 Top dielectric layer 400 Sidewall material layer 410 First sidewall material layer 420 Second sidewall material layer 430 Protective material layer 440 First sidewall 450 Second sidewall 460 Sidewall 461 Sidewall 462 Sidewall 470 Protective layer 480 partition layers 482 partition layer 500 compensation material layer 510 Compensation layer 600 channel material layer 601 Channel material layer 610 Channel Hole 611 Channel Hole 612 Channel Hole 620 groove 630 Insulating material layer 640 Insulating layer 650 Air Gap

Claims

1. circuit board and A gate structure located on the substrate, A channel hole located on the substrate and penetrating the gate structure along the vertical direction, A side wall extending along the longitudinal direction between the channel hole side wall and the gate structure, A compensation layer is filled in the gap between the channel hole and the gate structure at the bottom of the sidewall, Features including, Semiconductor structure.

2. The semiconductor structure further includes a partition layer located between the sidewall and the channel hole sidewall, The compensation layer is also filled in the gap between the channel hole and the gate structure at the bottom of the partition layer, characterized in that The semiconductor structure according to claim 1.

3. The partition layer is a protective layer that covers the side wall of the side wall. or The partition layer is characterized by being an air gap. The semiconductor structure according to claim 2.

4. The semiconductor structure according to claim 3, characterized in that the partition layer is a protective layer, and the material of the protective layer includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon, silicon oxide and tungsten, or a combination of polycrystalline silicon, silicon oxide and titanium nitride.

5. The semiconductor structure according to claim 2, characterized in that the compensation layer is further filled in the gap formed by the top of the sidewall and the partition layer.

6. The sidewall includes a first sidewall covering the gate structure sidewall and a second sidewall covering the first sidewall sidewall. At the bottom of the sidewall, the gap filled with the compensation layer is surrounded by the bottom of the second sidewall, the bottom of the partition layer, the first sidewall, and the channel hole sidewall. The gap at the top of the sidewall, where the compensation layer is filled, is characterized in that it is surrounded by the top of the second sidewall, the partition layer sidewall, and the first sidewall sidewall. The semiconductor structure according to claim 5.

7. The semiconductor structure according to claim 6, characterized in that the material of the first sidewall contains silicon nitride and the material of the second sidewall contains silicon oxide.

8. The semiconductor structure according to claim 1, characterized in that the material of the compensation layer contains silicon nitride.

9. The semiconductor structure further comprises a top dielectric layer covering the top surface of the gate structure, The gate structure and the substrate are located together, including a bottom dielectric layer. The channel hole extends further, penetrating the top dielectric layer and the bottom dielectric layer. The sidewall further extends between the channel hole sidewall and the top dielectric layer, The compensation layer is further characterized in that it also fills the gap between the channel hole and the bottom dielectric layer. The semiconductor structure according to claim 1.

10. The semiconductor structure further includes a source-drain doped layer located within the substrate, and the source-drain doped layer is exposed on the top surface of the substrate. The channel holes are located on the source-drain doped layer and are in contact with each other. The semiconductor structure according to claim 1.

11. The semiconductor structure according to claim 1, wherein a groove is formed on the top side of the channel hole, located at a part of the height of the channel hole, and the semiconductor structure further includes an insulating layer filled in the groove.

12. To provide a substrate on which a gate structure is formed, To form an opening that penetrates the gate structure, To form a side wall that covers the aforementioned opening side wall, The gap compensation process is performed at the corner portion of the opening bottom to form a compensation layer that fills the gap at the bottom of the sidewall, The invention is characterized by forming a channel hole within the opening that is located on the substrate and penetrates the gate structure, A method for forming semiconductor structures.

13. The method further includes forming a protective layer covering the sidewall before performing gap compensation treatment at the corner portion of the opening bottom, In the step of performing gap compensation treatment at the corner portion of the opening bottom, the compensation layer is also filled into the gap at the bottom of the protective layer at the corner portion of the opening bottom. In the step of forming a channel hole located on the substrate and penetrating the gate structure within the opening, the channel hole is characterized in that it is in contact with the protective layer. The method for forming a semiconductor structure according to claim 12.

14. A method for forming a semiconductor structure according to claim 13, characterized in that, after forming a channel hole located on the substrate and penetrating the gate structure within the opening, the protective layer is further removed to form an air gap located between the sidewall and the channel hole sidewall.

15. The method for forming a semiconductor structure according to claim 13, characterized in that, in the step of performing gap compensation treatment at the corner portion of the bottom of the opening, the compensation layer is also filled into the gap formed by the top of the sidewall and the protective layer.

16. The step of forming a sidewall that covers the opening sidewall includes forming a sidewall material layer that covers the opening sidewall and bottom and the top of the gate structure, This is characterized by removing the sidewall material layer at the bottom of the opening and the top of the gate structure, and leaving the sidewall material layer covering the side wall of the opening as the sidewall. A method for forming a semiconductor structure according to claim 15.

17. In the step of providing the substrate, a top dielectric layer is further formed on the top of the gate structure, and a bottom dielectric layer is further formed between the gate structure and the substrate. In the step of forming an opening that penetrates the gate structure, the opening further penetrates the top dielectric layer and extends to a portion of the thickness of the bottom dielectric layer. The step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure further includes removing the excess thickness of the bottom dielectric layer to expose the top surface of the substrate. In the step of performing gap compensation processing at the bottom corner portion of the opening, the compensation layer is also filled into the gap formed by the bottom dielectric layer and the substrate at the bottom corner portion of the opening. A method for forming a semiconductor structure according to claim 16.

18. The step of forming a sidewall material layer that covers the opening side wall and bottom and the top of the gate structure includes forming a first sidewall material layer that covers the opening side wall and bottom and the top of the gate structure, This includes forming a second sidewall material layer that covers the first sidewall material layer, In the step of removing the sidewall material layer of the opening bottom and the top of the gate structure, the first sidewall material layer and the second sidewall material layer of the opening bottom and the top of the gate structure are removed, leaving the first sidewall material layer covering the opening side wall as the first sidewall, and leaving the second sidewall material layer covering the opening side wall as the second sidewall. In the step of performing gap compensation treatment at the corner portion of the opening bottom, the compensation layer is filled into the gap formed by the bottom of the second sidewall, the bottom of the protective layer, and the first sidewall, and the compensation layer is further filled into the gap formed by the top of the second sidewall, the side wall of the protective layer, and the side wall of the first sidewall. A method for forming a semiconductor structure according to claim 16.

19. Before removing the sidewall material layer at the bottom of the opening and the top of the gate structure, the process further includes forming a protective material layer to cover the sidewall material layer. The step of removing the sidewall material layer at the bottom of the opening and the top of the gate structure further includes removing the protective material layer at the bottom of the opening and the top of the gate structure, and leaving the protective material layer covering the sidewall as the protective layer. A method for forming a semiconductor structure according to claim 16.

20. Using a dry etching process, the sidewall material layer at the bottom of the opening and the top of the gate structure is removed. The method further includes removing the sidewall material layer from the bottom of the opening and the top of the gate structure, and then performing a cleaning treatment on the sidewall before performing gap compensation treatment at the corner portion of the bottom of the opening. A method for forming a semiconductor structure according to claim 19.

21. The step of performing gap compensation treatment at the corner portion of the opening bottom and forming a compensation layer to fill the gap at the bottom of the sidewall includes forming a compensation material layer that covers the gaps at the bottom of the opening, the sidewall of the opening side wall, the top of the gate structure, and the bottom of the sidewall, The method is characterized by removing the compensating material layer covering the bottom of the opening, the sidewall of the opening side wall, and the top of the gate structure, and leaving the compensating material layer that fills the gap at the bottom of the sidewall as the compensating layer. The method for forming a semiconductor structure according to claim 12.

22. A method for forming a semiconductor structure according to claim 21, characterized in that a compensating material layer is formed to cover the gaps filled in the opening bottom, the sidewall of the opening sidewall, the top of the gate structure, and the bottom of the sidewall using an atomic layer deposition process or a low-pressure chemical vapor deposition process.

23. A method for forming a semiconductor structure according to claim 21, characterized by removing the compensation material layer covering the bottom of the opening, the sidewall of the opening side wall, and the top of the gate structure using a wet etching process.

24. The etching solution for the wet etching process includes a phosphoric acid solution. The mass percentage of phosphoric acid in the aforementioned phosphoric acid solution is 40 wt% to 86 wt%, The wet etching process is characterized in that the process temperature is 100°C to 160°C. A method for forming a semiconductor structure according to claim 23.

25. In the step of providing the substrate, a source-drain doped layer is further formed within the substrate, and the source-drain doped layer is exposed on the top surface of the substrate. In the step of forming an opening that penetrates the gate structure, the opening is formed above the source drain dope layer. In the step of forming a channel hole within the opening, located on the substrate and penetrating the gate structure, the channel hole is formed on the source-drain doping layer and is in contact with the source-drain doping layer, The method for forming a semiconductor structure according to claim 12.

26. In the step of forming a channel hole within the opening, located on the substrate and penetrating the gate structure, the channel hole is filled in the opening. Alternatively, in the step of forming a channel hole within the opening that is located on the substrate and penetrates the gate structure, a groove is formed on the top side of the channel hole that is located in part of the height of the channel hole. The groove is filled with an insulating layer, characterized in that The method for forming a semiconductor structure according to claim 12.

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