Multilayer inductor

Abstract

The present invention provides a multilayer inductor that can reduce stray capacitance generated between via conductors included in the lead conductors and the lateral extension portions of the terminal electrodes. [Solution] A laminated inductor 1 comprises terminal electrodes 11 and 12 provided on the end face of a laminated body 2 and extending from the end face to a part of the adjacent side faces 5 to 8, a coil conductor 13 including a circumferential conductor 18 disposed inside the laminated body 2, and a lead conductor 15 drawn out from the end of the coil conductor 13 and connected to the terminal electrode 11. The lead conductor 15 includes an outer via conductor 21 and an inner via conductor 22 that penetrate the nonconductive layer 9 in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the terminal electrode 11 at the end face. When the laminated body 2 is viewed through in the lamination direction of the nonconductive layer 9, the outer via conductor 21 is positioned so that all parts overlap with the circumferential conductor 18, and the inner via conductor 22 is located on the inner diameter side of the circumferential conductor 18.

Description

Technical Field

[0004] ,

[0003] , , , ,

[0001] The present disclosure relates to a laminated inductor in which a coil conductor is disposed inside a laminate formed by laminating a plurality of non-conductive layers made of a non-conductive material, and particularly relates to the structure of a lead-out portion from the coil conductor to a terminal electrode.

Background Art

[0002] For example, in Japanese Patent Application Laid-Open No. 2023-148398 (Patent Document 1), as a technique of interest to the present disclosure, · A laminate having a substantially square prism shape having a first end face and a second end face facing each other and four side faces connecting the first end face and the second end face, and a plurality of non-conductive layers made of a non-conductive material extending parallel to the first end face and the second end face are laminated in the direction in which the side faces extend, · A first terminal electrode and a second terminal electrode provided on the first end face and the second end face, respectively, · A plurality of loop conductors disposed inside the laminate and extending so as to form a part of an annular track along the interface between the non-conductive layers, and a plurality of intermediate via conductors penetrating the non-conductive layers in the thickness direction, and the coil conductor is formed in a form extending along a spiral track by connecting the plurality of loop conductors via the intermediate via conductors, · A first lead-out conductor and a second lead-out conductor respectively drawn from the first end and the second end of the coil conductor opposite to each other and connected to the first terminal electrode and the second terminal electrode, A laminated inductor including is described.

[0003] The above-described first terminal electrode is provided on the first end face of the laminate and is provided so as to extend to a part of the adjacent side face from the first end face, and the second terminal electrode is provided on the second end face of the laminate and is provided so as to extend to a part of the adjacent side face from the second end face.

[0004] Furthermore, each of the first and second lead conductors includes multiple via conductors connected in parallel, penetrating the non-conductive layer in the thickness direction and extending parallel to one another, in order to enable the flow of large currents. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-148398 [Overview of the project] [Problems that the invention aims to solve]

[0006] In the multilayer inductor described above, if we consider the positional relationship between the multiple via conductors in each of the first and second lead conductors and the side extensions that extend to a part of the side surface of the first and second terminal electrodes, we find that all of the multiple via conductors in the lead conductors are positioned near the side extensions of the terminal electrodes, maintaining a nearly constant distance from them.

[0007] Therefore, there is concern that relatively large stray capacitance may occur between the via conductor and the lateral extension portion of the terminal electrode. Such stray capacitance can lead to a deterioration of the high-frequency characteristics of the multilayer inductor.

[0008] Therefore, the object of this disclosure is to provide a multilayer inductor that can reduce the stray capacitance that occurs between the via conductor included in the lead conductor and the lateral extension portion of the terminal electrode. [Means for solving the problem]

[0009] The multilayer inductor according to this disclosure comprises a laminate in which a plurality of nonconductive layers are stacked in the stacking direction. The laminate has a rectangular prism or substantially rectangular prism shape, having a first end face and a second end face that face each other, and four sides connecting the first end face and the second end face. The stacking direction is parallel to the direction in which the first end face and the second end face face each other.

[0010] The multilayer inductor according to this disclosure also includes a first terminal electrode provided on at least a portion of a first end face and extending from the first end face to a portion of at least one adjacent side face, a second terminal electrode provided on at least a portion of a second end face and extending from the second end face to a portion of at least one adjacent side face, and a coil conductor disposed inside the laminate. It is equipped with.

[0011] The above-mentioned coil conductor comprises a plurality of circumferential conductors extending along the interface between nonconductive layers so as to form a part of an annular orbit, and a plurality of intermediary via conductors penetrating the nonconductive layer in the thickness direction, and the plurality of circumferential conductors are connected via the intermediary via conductors so as to extend along a helical orbit.

[0012] The stacked inductor according to this disclosure further comprises a first lead conductor drawn from a first end of the coil conductor and connected to a first terminal electrode, and a second lead conductor drawn from a second end opposite to the first end of the coil conductor and connected to a second terminal electrode.

[0013] To solve the technical problems described above, the multilayer inductor according to this disclosure has the following features.

[0014] The first lead conductor includes a first outer via conductor and a first inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to a first terminal electrode at a first end face.

[0015] The second lead conductor includes a second outer via conductor and a second inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the second terminal electrode at the second end face.

[0016] When the laminate is viewed through in the stacking direction of the non-conductive layers, the first outer via conductor and the second outer via conductor are positioned such that all portions overlap with the circumferential conductor, and the first inner via conductor and the second inner via conductor are characterized in that at least a part thereof is positioned on the inner diameter side of the circumferential conductor.

Advantages of the Invention

[0017] According to the multilayer inductor according to the present disclosure, the lead-out conductor connected to the terminal electrode includes an outer via conductor and an inner via conductor as via conductors, first enabling the flow of a large current.

[0018] Furthermore, when the laminate is viewed through in the stacking direction of the non-conductive layers, the outer via conductor is positioned such that all portions overlap with the circumferential conductor, while the inner via conductor is positioned at least partly on the inner diameter side of the circumferential conductor. Therefore, in the facing of the side extension portion at the terminal electrode and the via conductor in the lead-out conductor, which causes the generation of stray capacitance, the distance from the inner via conductor to the side extension portion at the terminal electrode can be made longer than the distance from the outer via conductor to the side extension portion.

[0019] Therefore, the stray capacitance caused by the facing of the side extension portion at the terminal electrode and the inner via conductor can be reduced compared to the stray capacitance caused by the facing of the side extension portion and the outer via conductor. Thus, the capacitance generated in the multilayer inductor can be reduced overall, and the high-frequency characteristics of the multilayer inductor can be improved.

Brief Description of the Drawings

[0020] [Figure 1] It is a perspective view showing the appearance of the multilayer inductor 1 according to the first embodiment of the present disclosure. [Figure 2] It is a plan view showing a part of the coil conductor 13 and the first lead-out conductor 15 provided in the multilayer inductor 1 shown in FIG. 1, disassembled together with the non-conductive layer 9. [Figure 3]It is a plan view showing the remainder of the coil conductor 13 provided in the laminated inductor 1 shown in FIG. 1 and the second lead-out conductor 16, decomposed for each non-conductive layer 9. [Figure 4] It is a cross-sectional view taken along line A-A in FIG. 2(1), showing an enlarged part of the laminated inductor 1 shown in FIG. 1. [Figure 5] It is for explaining the characteristic configuration of the laminated inductor 1 shown in FIG. 1, and is a view showing the first outer via conductor 21 and the first inner via conductor 22 by looking through the laminate 2 in the stacking direction of the non-conductive layer 9. [Figure 6] It is a view corresponding to FIG. 5, showing the laminated inductor 1a according to the second embodiment of the present disclosure. [Figure 7] It is a view corresponding to FIG. 5, showing the laminated inductor 1b according to the third embodiment of the present disclosure. [Figure 8] It is a view corresponding to FIG. 5, showing the laminated inductor 1c according to the fourth embodiment of the present disclosure. [Figure 9] It is a side view showing the appearance of the laminated inductor 1d according to the fifth embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0021] Referring to FIGS. 1 to 5, the laminated inductor 1 according to the first embodiment of the present disclosure will be described.

[0022] As shown in FIG. 1, the laminated inductor 1 includes a laminate 2 as a component body. The laminate 2 has a quadrangular prism shape having a first end face 3 and a second end face 4 facing each other, and four side faces 5 to 8 connecting the first end face 3 and the second end face 4. The shape of the laminate 2 may be, for example, a substantially quadrangular prism shape with rounded or chamfered edges and corners.

[0023] The laminate 2 has a laminated structure in which multiple nonconductive layers 9 (see Figure 4) are stacked. Each of the nonconductive layers 9 extends parallel to the first end face 3 and the second end face 4, respectively, and is stacked in the direction in which the sides 5 to 8 extend. That is, the multiple nonconductive layers 9 are stacked from the first end face 3 toward the second end face 4, and the first end face 3 and the second end face 4 of the laminate 2 are given by the main surfaces of the nonconductive layers 9 located at each end in the stacking direction.

[0024] The non-conductive layer 9 is made of a non-conductive material that includes, for example, at least one of glass, resin, and ferrite. Furthermore, if the non-conductive layer 9 is made of a molded body such as resin, it may contain a non-magnetic filler such as silica, or a magnetic filler such as ferrite or a metallic magnetic material. In addition, the non-conductive layer 9 may have a composition combining multiple of these glass, ferrite, and resin materials.

[0025] A first terminal electrode 11 and a second terminal electrode 12 are provided on the outer surface of the laminate 2. The first terminal electrode 11 is provided on the first end face 3 of the laminate 2 and extends from the first end face 3 to a portion of each of the adjacent sides 5 to 8. That is, the first terminal electrode 11 has an end face portion 11a on the first end face 3 and a side extension portion 11b on the sides 5 to 8. Similarly, the second terminal electrode 12 is provided on the second end face 4 and extends from the second end face 4 to a portion of each of the adjacent sides 5 to 8. That is, the second terminal electrode 12 has an end face portion 12a on the second end face 4 and a side extension portion 12b on the sides 5 to 8. In this case, the laminated inductor 1 is mounted on the mounting substrate with one of the sides 5 to 8 as the mounting surface.

[0026] Inside the laminate 2, as shown in Figures 2 to 5, a coil conductor 13 and a first lead conductor 15 and a second lead conductor 16 are arranged. The coil conductor 13 is shaped to extend along a helical track, and the axis of the helical track is oriented in the direction in which the first end face 3 and the second end face 4 face each other.

[0027] Figures 2 and 3 show the coil conductor 13 and the first lead conductor 15 and second lead conductor 16 separated into non-conductive layers 9. In Figures 2 and 3, (1) to (14) indicate the stacking order in the laminate 2 from the first end face 3 to the second end face 4.

[0028] As will be explained in detail later, the coil conductor 13 comprises a plurality of circumferential conductors 18 that extend along the interface between the nonconductive layers 9 to each form part of an annular orbit, and a plurality of intermediate via conductors 19 that penetrate the nonconductive layer 9 in the thickness direction, and the plurality of circumferential conductors 18 are connected via the intermediate via conductors 19 to extend along a helical orbit.

[0029] Here, when it is necessary to distinguish each of the multiple nonconductive layers 9, each of the multiple circumferential conductors 18, and each of the multiple intermediary via conductors 19 from one another, a sub-number such as "-1", "-2", "-3", ... is assigned to each reference numeral.

[0030] Furthermore, the first lead conductor 15 includes a first outer via conductor 21 and a first inner via conductor 22 that penetrate the nonconductive layer 9 in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the first terminal electrode 11 at the first end face 3. The second lead conductor 16 includes a second outer via conductor 23 and a second inner via conductor 24 that penetrate the nonconductive layer 9 in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the second terminal electrode 12 at the second end face 4.

[0031] When it is necessary to distinguish each of the multiple first outer via conductors 21, each of the multiple first inner via conductors 22, each of the multiple second outer via conductors 23, and each of the multiple second inner via conductors 24 from one another, a sub-number such as "-1", "-2", "-3", ... is added to each of their reference symbols.

[0032] Furthermore, the first outer via conductor 21, the first inner via conductor 22, the second outer via conductor 23, and the second inner via conductor 24 extend so as to penetrate the multiple nonconductive layers 9 in the thickness direction. A first outer conductor land 25 is provided extending from the first outer via conductor 21 along the interface of the multiple nonconductive layers 9, a first inner conductor land 26 is provided extending from the first inner via conductor 22 along the interface of the multiple nonconductive layers 9, a second outer conductor land 27 is provided extending from the second outer via conductor 23 along the interface of the multiple nonconductive layers 9, and a second inner conductor land 28 is provided extending from the second inner via conductor 24 along the interface of the multiple nonconductive layers 9.

[0033] When it is necessary to distinguish each of the multiple first outer conductor lands 25, each of the multiple first inner conductor lands 26, each of the multiple second outer conductor lands 27, and each of the multiple second inner conductor lands 28 from one another, a sub-number such as "-1", "-2", "-3", ... is added to each of their reference symbols.

[0034] Details of the coil conductor 13 and the lead conductors 15 and 16 will be explained below with reference to Figures 2 to 4.

[0035] As shown in Figure 2(1), the nonconductive layer 9-1 has a first outer conductor land 25-1 and a first inner conductor land 26-1, and the first outer via conductor 21-1 and the first inner via conductor 22-1, which are part of the first lead conductor 15, are arranged so as to overlap the first outer conductor land 25-1 and the first inner conductor land 26-1, respectively. The first outer via conductor 21-1 and the first inner via conductor 22-1 are connected to the end face portion 11a of the first terminal electrode 11, as is clearly shown in Figure 4.

[0036] Note that the positional relationship between the first outer conductor land 25-1 and the first inner conductor land 26-1 with respect to the non-conductive layer 9-1 shown in Figure 2(1) does not match the positional relationship shown in Figure 4. That is, the first outer conductor land 25-1 and the first inner conductor land 26-1 are embedded within the non-conductive layer 9-1, as shown in Figure 4, and therefore should not be visible in Figure 2(1). However, in Figure 2(1), the first outer conductor land 25-1 and the first inner conductor land 26-1 are shown by viewing through the non-conductive layer 9-1 in order to clearly represent the shape and position of various elements. A similar representation method is also used in Figures 2(2) to (7) and Figures 3(8) to (13).

[0037] Next, as shown in Figure 2(2), the non-conductive layer 9-2, located below the non-conductive layer 9-1 (below in the figure; the same applies hereafter), has a first outer conductor land 25-2 and a first inner conductor land 26-2. The first outer via conductor 21-2 and the first inner via conductor 22-2, which are part of the first lead conductor 15, are arranged so as to overlap the first outer conductor land 25-2 and the first inner conductor land 26-2, respectively. As clearly shown in Figure 4, the first outer via conductor 21-2 and the first inner via conductor 22-2 are connected to the first outer conductor land 25-1 and the first inner conductor land 26-1, respectively.

[0038] Next, as shown in Figure 2(3), a first outer conductor land 25-3 and a first inner conductor land 26-3 are arranged in the non-conductive layer 9-3 located below the non-conductive layer 9-2, and a first outer via conductor 21-3 and a first inner via conductor 22-3, which will be part of the first lead conductor 15, are arranged so as to overlap the first outer conductor land 25-3 and the first inner conductor land 26-3, respectively. As clearly shown in Figure 4, the first outer via conductor 21-3 and the first inner via conductor 22-3 are connected to the first outer conductor land 25-2 and the first inner conductor land 26-2, respectively. In addition, a circumferential conductor 18-1, which will be part of the coil conductor 13, extends from the first outer conductor land 25-3 and is arranged in the non-conductive layer 9-3. The circumferential conductor 18-1 is I-shaped, and an intermediate pad 20-1 is formed at its end to provide a wider area. In this disclosure, the circumferential conductor 18 includes the intermediate pad 20.

[0039] As shown in Figures 2(1) to (3), the lateral extension portion 11b of the first terminal electrode 11 is provided so as to surround the nonconductive layers 9-1 to 9-3.

[0040] Next, as shown in Figure 2(4), a circumferential conductor 18-2, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-4 located below the non-conductive layer 9-3. The circumferential conductor 18-2 is L-shaped, and intermediate pads 20-2, 20-3, and 20-4, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-1 and 19-2 are arranged so as to overlap the intermediate pads 20-2 and 20-3, respectively. As clearly shown in Figure 4, the intermediate via conductor 19-1 is connected to the first outer conductor land 25-3 described above. The intermediate via conductor 19-2 is connected to the intermediate pad 20-1 described above. Here, a portion of the circumferential conductor 18-2 is connected in parallel with the circumferential conductor 18-1. This configuration is intended to allow a large current to flow through the coil conductor 13 and is also used in the circumferential conductor described below.

[0041] Next, as shown in Figure 2(5), a circumferential conductor 18-3, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-5 located beneath the non-conductive layer 9-4. The circumferential conductor 18-3 is L-shaped, and intermediate pads 20-5, 20-6, and 20-7, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-3 and 19-4 are arranged so as to overlap the intermediate pads 20-5 and 20-6, respectively. Intermediate via conductors 19-3 and 19-4 are connected to the aforementioned intermediate pads 20-3 and 20-4, respectively. Here, a portion of the circumferential conductor 18-3 is connected in parallel with a portion of the circumferential conductor 18-2.

[0042] Next, as shown in Figure 2(6), a circumferential conductor 18-4, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-6 located beneath the non-conductive layer 9-5. The circumferential conductor 18-4 is L-shaped, and intermediate pads 20-8, 20-9, and 20-10, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-5 and 19-6 are arranged so as to overlap the intermediate pads 20-8 and 20-9, respectively. Intermediate via conductors 19-5 and 19-6 are connected to the aforementioned intermediate pads 20-6 and 20-7, respectively. Here, a portion of the circumferential conductor 18-4 is connected in parallel with a portion of the circumferential conductor 18-3.

[0043] Next, as shown in Figure 2(7), a circumferential conductor 18-5, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-7 located beneath the non-conductive layer 9-6. The circumferential conductor 18-5 is L-shaped, and intermediate pads 20-11, 20-12, and 20-13, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-7 and 19-8 are arranged so as to overlap the intermediate pads 20-11 and 20-12, respectively. Intermediate via conductors 19-7 and 19-8 are connected to the aforementioned intermediate pads 20-9 and 20-10, respectively. Here, a portion of the circumferential conductor 18-5 is connected in parallel with a portion of the circumferential conductor 18-4.

[0044] Next, as shown in Figure 3(8), a circumferential conductor 18-6, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-8 located below the non-conductive layer 9-7. The circumferential conductor 18-6 is L-shaped, and intermediate pads 20-14, 20-15, and 20-16, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-9 and 19-10 are arranged so as to overlap the intermediate pads 20-14 and 20-15, respectively. Intermediate via conductors 19-9 and 19-10 are connected to the aforementioned intermediate pads 20-12 and 20-13, respectively. Here, a portion of the circumferential conductor 18-6 is connected in parallel with a portion of the circumferential conductor 18-5.

[0045] Next, as shown in Figure 3(9), a circumferential conductor 18-7, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-9 located below the non-conductive layer 9-8. The circumferential conductor 18-7 is L-shaped, and intermediate pads 20-17, 20-18, and 20-19, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-11 and 19-12 are arranged so as to overlap the intermediate pads 20-17 and 20-18, respectively. Intermediate via conductors 19-11 and 19-12 are connected to the aforementioned intermediate pads 20-15 and 20-16, respectively. Here, a portion of the circumferential conductor 18-7 is connected in parallel with a portion of the circumferential conductor 18-6.

[0046] Next, as shown in Figure 3(10), a circumferential conductor 18-8, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-10 located beneath the non-conductive layer 9-9. The circumferential conductor 18-8 is L-shaped, and intermediate pads 20-20, 20-21, and 20-22, which provide a larger area, are formed at one end, the bent portion, and the other end, respectively. Intermediate via conductors 19-13 and 19-14 are arranged so as to overlap the intermediate pads 20-20 and 20-21, respectively. Intermediate via conductors 19-13 and 19-14 are connected to the aforementioned intermediate pads 20-18 and 20-19, respectively. Here, a portion of the circumferential conductor 18-8 is connected in parallel with a portion of the circumferential conductor 18-7.

[0047] Next, as shown in Figure 3(11), a circumferential conductor 18-9, which will become part of the coil conductor 13, is arranged in the non-conductive layer 9-11 located below the non-conductive layer 9-10. The circumferential conductor 18-9 is L-shaped, and intermediate pads 20-23, 20-24, and 20-25 are formed at one end, the bent portion, and the other end, respectively, to provide a larger area. Intermediate via conductors 19-15 and 19-16 are arranged so as to overlap the intermediate pads 20-24 and 20-25, respectively. Intermediate via conductors 19-15 and 19-16 are connected to the aforementioned intermediate pads 20-21 and 20-22, respectively. Here, a portion of the circumferential conductor 18-9 is connected in parallel with a portion of the circumferential conductor 18-8.

[0048] Next, as shown in Figure 3(12), a second outer conductor land 27-1 and a second inner conductor land 28-1 are arranged in the non-conductive layer 9-12 located below the non-conductive layer 9-11, and an intermediate via conductor 19-17 is arranged so as to overlap the second outer conductor land 27-1. The intermediate via conductor 19-17 is connected to the intermediate pad 20-25 described above. Also, a circumferential conductor 18-10, which becomes part of the coil conductor 13, is arranged in the non-conductive layer 9-12, extending from the second outer conductor land 27-1. The circumferential conductor 18-10 is I-shaped, and an intermediate pad 20-26 is formed at its end to provide a larger area. An intermediate via conductor 19-18 is arranged so as to overlap the intermediate pad 20-26. The intermediate via conductor 19-18 is connected to the intermediate pad 20-24 described above. Here, the circumferential conductor 18-10 is connected in parallel with a part of the circumferential conductor 18-9.

[0049] Next, as shown in Figure 3(13), the non-conductive layer 9-13 located below the non-conductive layer 9-12 has a second outer conductor land 27-2 and a second inner conductor land 28-2, and the second outer via conductor 23-1 and the second inner via conductor 24-1, which will become part of the second lead conductor 16, are arranged so as to overlap the second outer conductor land 27-2 and the second inner conductor land 28-2, respectively. The second outer via conductor 23-1 and the second inner via conductor 24-1 are connected to the second outer conductor land 27-1 and the second inner conductor land 28-1, respectively.

[0050] Next, as shown in Figure 3(14), the non-conductive layer 9-14 located below the non-conductive layer 9-13 has a second outer conductor land 27-3 and a second inner conductor land 28-3 arranged on it, and the second outer via conductor 23-2 and the second inner via conductor 24-2, which will become part of the second lead conductor 16, are arranged so as to overlap the second outer conductor land 27-3 and the second inner conductor land 28-3, respectively. The second outer via conductor 23-2 and the second inner via conductor 24-2 are connected to the second outer conductor land 27-2 and the second inner conductor land 28-2, respectively. The second outer via conductor 23-2 and the second inner via conductor 24-2 are also connected to the end face portion 12b of the second terminal electrode 12.

[0051] As shown in Figures 3(12) to (14), the lateral extension portion 12b of the second terminal electrode 12 is provided so as to surround the nonconductive layers 9-12 to 9-14.

[0052] Next, with reference to Figure 5, the characteristics of the positions of the outer via conductor 21 and the inner via conductor 22 in the first lead conductor 15 will be described. Figure 5 shows the first outer via conductor 21 and the first inner via conductor 22 in the first lead conductor 15, but the second outer via conductor 23 and the second inner via conductor 24 in the second lead conductor 16 have substantially the same configuration. Therefore, the description of the second outer via conductor 23 and the second inner via conductor 24 will be omitted, and terms such as "first end face," "first terminal electrode," "first lead conductor," "first outer via conductor," and "first inner via conductor" will be simply referred to as "end face," "terminal electrode," "lead conductor," "outer via conductor," and "inner via conductor," respectively.

[0053] Figure 5 shows the laminate 2 viewed through the lamination direction of the nonconductive layer 9, with the coil conductor 13, including the circumferential conductor 18, indicated by a dotted line. The lead conductor 15 includes an outer via conductor 21 and an inner via conductor 22 that penetrate the nonconductive layer 9 in the thickness direction, extend parallel to each other, and are connected to the terminal electrode 11 at the end face 3, as described above.

[0054] As shown in Figure 5, the outer via conductor 21 is positioned so that its entire length overlaps with the circumferential conductor 18, while the inner via conductor 22 is positioned at least partially on the inner diameter side of the circumferential conductor 18. This positioning of the inner via conductor 22 allows the distance from the inner via conductor 22 to the lateral extension portion 11b of the terminal electrode 11 to be longer than the distance from the outer via conductor 21 to the lateral extension portion 11b. Therefore, the stray capacitance caused by the opposition between the lateral extension portion 11b and the inner via conductor 22 of the terminal electrode 11 can be reduced compared to the stray capacitance caused by the opposition between the lateral extension portion 11b and the outer via conductor 21. Consequently, the capacitance generated in the multilayer inductor 1 can be reduced overall, the impedance resonance point can be shifted to the high-frequency side, and the high-frequency noise rejection effect of the multilayer inductor 1 can be improved.

[0055] In this embodiment, the inner via conductor 22 is entirely located on the inner diameter side of the circumferential conductor 18. This can increase the distance from the inner via conductor 22 to the lateral extension portion 11b of the terminal electrode 11, thereby contributing to a further reduction in stray capacitance.

[0056] Furthermore, in this embodiment, the circumferential conductor 18 extends along a substantially square trajectory and has, for example, four corners. The outer via conductor 21 is positioned to coincide with the corners of the circumferential conductor 18. With this configuration, even if the position of the outer via conductor 21 is unintentionally altered during the manufacturing process of the multilayer inductor 1, the connection between the outer via conductor 21 and the circumferential conductor 18 is guaranteed, and the risk of disconnection can be reduced.

[0057] Furthermore, in this embodiment, an outer conductor land 25 extending from the outer via conductor 21 and an inner conductor land 26 extending from the inner via conductor 22 are provided, and the outer conductor land 25 and the inner conductor land 26 are integrated. With this configuration, not only is the printing of the outer conductor land 25 and the inner conductor land 26 simplified, but problems due to wire breakage can be avoided. That is, if the outer conductor land 25 and the inner conductor land 26 are not integrated, if a wire break occurs at any of the multiple outer via conductors 21 and inner via conductors 22 that are connected in the stacking direction, such as due to a missing via conductor, no current will flow there, and the current will concentrate on the side where there is no missing via conductor, which may cause abnormal heat generation. By integrating the outer conductor land 25 and the inner conductor land 26, the above-mentioned problems due to wire breakage can be avoided.

[0058] Furthermore, in this embodiment, the contours of the integrated outer conductor land 25 and inner conductor land 26 have a shape in which a virtual outer circle centered on the outer via conductor 21 and a virtual inner circle centered on the inner via conductor 22 partially overlap each other. With this configuration, the overall area can be reduced compared to a conductor land having the shape of one large virtual circle surrounding both the outer via conductor 21 and the inner via conductor 22. Therefore, the area that blocks the magnetic flux passing through the inner diameter side of the coil conductor 13 can be reduced, and the decrease in impedance due to magnetic flux blocking can be suppressed.

[0059] An example of a manufacturing method for the multilayer inductor 1 described above will be explained.

[0060] A green sheet is prepared to serve as the non-conductive layer 9. The green sheet is obtained by forming a slurry containing magnetic material powder, an organic binder, an organic solvent, a plasticizer, etc., into a sheet. A non-magnetic material such as borosilicate glass material powder may be used instead of the magnetic material powder.

[0061] On the other hand, a conductive paste containing, for example, silver powder is prepared.

[0062] Next, in the first section where the lead conductors 15 and 16 are provided, conductive lands 25-28 are formed by printing conductive paste onto the green sheet, and then via conductors 21-24 are formed. Subsequently, a slurry is printed onto the areas of the green sheet where the conductive lands 25-28 and via conductors 21-24 are not present, in order to absorb the thickness of the conductive lands 25-28 and via conductors 21-24 on the green sheet.

[0063] On the other hand, in the area where the coil conductor 13 is located, a conductive paste is printed onto the green sheet to form the circumferential conductor 18 and the intermediate via conductor 19, and a slurry is printed on the area of ​​the green sheet where the circumferential conductor 18 and the intermediate via conductor 19 do not exist. This process is repeated to obtain the second part in which the coil conductor 13 is located.

[0064] Next, the second part is stacked with the first part in between, compressed in the stacking direction, and cut to a predetermined size to obtain the raw state of the laminate 2.

[0065] Next, the raw laminate 2 is fired and, if necessary, barrel polished to form the terminal electrodes 11 and 12. The terminal electrodes 11 and 12 are formed by baking a conductive paste, and then, if necessary, nickel plating and tin plating are applied.

[0066] In this way, a multilayer inductor 1 is obtained. Note that in an actual multilayer inductor 1, the interfaces between multiple nonconductive layers are often not visible.

[0067] In addition, to form via conductors 19 or 21-24, holes may be formed by irradiating predetermined locations on the green sheet with laser light, and conductive paste may be filled into these holes. In this case, the filling of the conductive paste may be performed simultaneously with the printing of the circumferential conductor 18 or conductive lands 25-28 using the conductive paste.

[0068] Figure 6 is a diagram corresponding to Figure 5, showing a stacked inductor 1a according to a second embodiment of the present disclosure. In Figure 6, elements corresponding to those shown in Figure 5 are denoted by the same reference numerals, and redundant explanations are omitted.

[0069] In the embodiment shown in Figure 6, the cross-sectional area of ​​the outer via conductor 21 is smaller and the cross-sectional area of ​​the inner via conductor 22 is larger compared to the embodiment shown in Figure 5. As a result, the total cross-sectional area of ​​the outer via conductor 21 and the inner via conductor 22 remains the same in the embodiment shown in Figure 6 as in the embodiment shown in Figure 5, so as not to change the current density of the current flowing in the lead conductor 15.

[0070] According to the embodiment shown in Figure 6, the stray capacitance generated between the outer via conductor 21 and the lateral extension portion 11b of the terminal electrode 11 can be reduced compared to the embodiment shown in Figure 5. As a result, the impedance resonance point can be shifted to a higher frequency side, and the high-frequency noise rejection effect of the multilayer inductor 1 can be further improved.

[0071] Furthermore, in the embodiment shown in Figure 6, similar to the embodiment shown in Figure 5, the contours of the integrated outer conductor land 25 and inner conductor land 26 have a shape in which a virtual outer circle centered on the outer via conductor 21 and a virtual inner circle centered on the inner via conductor 22 partially overlap each other, but the inner circle is smaller than the outer circle. With this configuration, the area that blocks the magnetic flux passing through the inner diameter side of the coil conductor 13 can be made smaller compared to the embodiment shown in Figure 5, and the decrease in impedance due to magnetic flux blocking can be suppressed more effectively.

[0072] Figure 7 is a diagram corresponding to Figure 5, showing a stacked inductor 1b according to a third embodiment of the present disclosure. In Figure 7, elements corresponding to those shown in Figure 5 are denoted by the same reference numerals, and redundant explanations are omitted.

[0073] In the embodiment shown in Figure 7, the cross-sectional area of ​​the inner via conductor 22 is smaller compared to the embodiments shown in Figures 5 and 6, respectively.

[0074] With this configuration, the stray capacitance generated between the inner via conductor 22 and the lateral extension portion 11b of the terminal electrode 11 can be reduced compared to the embodiments shown in Figures 5 and 6, respectively.

[0075] Furthermore, the contours of the integrated outer conductor land 25 and inner conductor land 26 have a shape in which a virtual outer circle centered on the outer via conductor 21 and a virtual inner circle centered on the inner via conductor 22 partially overlap each other, but the inner circle is smaller than the outer circle.

[0076] With this configuration, compared to the embodiments shown in Figures 5 and 6, the area that blocks the magnetic flux passing through the inner diameter side of the coil conductor 13 can be made smaller, and the decrease in impedance due to magnetic flux blocking can be suppressed more effectively.

[0077] Figure 8 is a diagram corresponding to Figure 5, showing a stacked inductor 1c according to a fourth embodiment of the present disclosure. In Figure 8, elements corresponding to those shown in Figure 5 are denoted by the same reference numerals, and redundant explanations are omitted.

[0078] In the embodiment shown in Figure 8, compared to the embodiment shown in Figure 5, the inner via conductor 22 has a smaller cross-sectional area and is distributed at multiple locations, for example, two locations.

[0079] With this configuration, the stray capacitance generated between the inner via conductor 22 and the lateral extension portion 11b of the terminal electrode 11 can be reduced compared to the embodiment shown in Figure 5.

[0080] Furthermore, in the embodiment shown in Figure 8, the cross-sectional area of ​​the outer via conductor 21 is made smaller, similar to the embodiment shown in Figure 6. As a result, the stray capacitance generated between the outer via conductor 21 and the lateral extension portion 11b of the terminal electrode 11 can also be reduced compared to the embodiment shown in Figure 5.

[0081] Figure 9 is a side view showing the external appearance of a stacked inductor 1d according to a fifth embodiment of the present disclosure. In Figure 9, elements corresponding to those shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted.

[0082] The embodiment shown in Figure 9 is characterized by the shapes of the first terminal electrode 11 and the second terminal electrode 12. Specifically, the first terminal electrode 11 and the second terminal electrode 12 are provided with end face portions 11a and 12a so as to cover a part of the first end face 3 and a part of the second end face 4 of the laminate 2, respectively, and side extension portions 11b and 12b are provided so as to extend to a part of the side surface 7, but not to the side surface 5, and are provided on the tops of the sides 6 and 8 to form a triangular pattern. In this case, the laminated inductor 1d is mounted on the mounting substrate with the side surface 7 as the mounting surface.

[0083] Even in the embodiment shown in Figure 9, stray capacitance between the lateral extensions 11b and 12b of the first terminal electrode 11 and the second terminal electrode 12 and the via conductor included in the lead conductor becomes a problem, so adopting the characteristic configuration of this disclosure is effective.

[0084] Although the above has been described in relation to several embodiments illustrated in this disclosure, various other modifications are possible within the scope of this disclosure.

[0085] For example, the length of the lead conductor can be arbitrarily changed by altering the number of non-conductive layers stacked, thereby increasing or decreasing the number of consecutive outer via conductors and inner via conductors.

[0086] Furthermore, the number of turns realized in the coil conductor 13 can be arbitrarily changed by changing the number of stacked non-conductive layers. More specifically, the number of turns realized in the coil conductor 13 can be increased by further repeating the stacked structures in Figures 2(4) to (7), and the number of turns realized in the coil conductor 13 can be decreased by omitting the stacked structures in Figures 2(4) to (7). Alternatively, the number of turns can be arbitrarily changed by changing the shape of each individual circumferential conductor that makes up the coil conductor 13.

[0087] Furthermore, in the illustrated embodiment, the circumferential conductors constituting the coil conductor 13 are connected in parallel in the parallel portions to allow for a large current, but a structure in which they are not connected in parallel is also possible.

[0088] Furthermore, the embodiments described herein are illustrative, and partial substitution or combination of configurations is possible between different embodiments.

[0089] This disclosure includes the following embodiments:

[0090] <1> A laminate comprising multiple nonconductive layers stacked in the stacking direction, The laminate has a rectangular prism or substantially rectangular prism shape, having a first end face and a second end face that face each other, and four side faces that connect the first end face and the second end face. The stacking direction is parallel to the direction in which the first end face and the second end face face opposite each other. A first terminal electrode is provided on at least a portion of the first end face and extends from the first end face to a portion of at least one adjacent side surface, A second terminal electrode is provided on at least a portion of the second end face and extends from the second end face to a portion of at least one adjacent side surface, A coil conductor is arranged inside the laminate, Furthermore, The coil conductor comprises a plurality of circumferential conductors extending along the interface between the nonconductive layers to form a portion of an annular orbit, and a plurality of intermediary via conductors penetrating the nonconductive layer in the thickness direction, wherein the plurality of circumferential conductors are connected via the intermediary via conductors, thereby extending along a helical orbit. A first lead conductor is drawn out from the first end of the coil conductor and connected to the first terminal electrode, A second lead conductor is drawn out from the second end of the coil conductor opposite to the first end and connected to the second terminal electrode, Furthermore, The first lead conductor includes a first outer via conductor and a first inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the first terminal electrode at the first end face. The second lead conductor includes a second outer via conductor and a second inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the second terminal electrode at the second end face. When the laminate is viewed through in the lamination direction of the nonconductive layer, the first outer via conductor and the second outer via conductor are positioned so that all portions overlap with the circumferential conductor, and at least a portion of the first inner via conductor and the second inner via conductor are located on the inner diameter side of the circumferential conductor. Multilayer inductor.

[0091] <2> When the laminate is viewed through the nonconductive layer in the lamination direction, the first inner via conductor and the second inner via conductor are all located on the inner diameter side of the circumferential conductor. <1> The multilayer inductor described above.

[0092] <3> The cross-sectional area of ​​the first inner via conductor is greater than the cross-sectional area of ​​the first outer via conductor, and the cross-sectional area of ​​the second inner via conductor is greater than the cross-sectional area of ​​the second outer via conductor. <1> or <2> The multilayer inductor described above.

[0093] <4> The first outer via conductor, the first inner via conductor, the second outer via conductor, and the second inner via conductor extend so as to penetrate the plurality of nonconductive layers in the thickness direction. A first outer conductor land extending from the first outer via conductor along the interface of a plurality of nonconductive layers, A first inner conductor land extending from the first inner via conductor along the interface of a plurality of nonconductive layers, A second outer conductor land extending from the second outer via conductor along the interface of a plurality of nonconductive layers, A second inner conductor land extending from the second inner via conductor along the interface of a plurality of nonconductive layers, Furthermore, <1> or <3> A multilayer inductor as described in any of the following.

[0094] <5> The first outer conductor land and the first inner conductor land are integrated, and the second outer conductor land and the second inner conductor land are integrated. <4> The multilayer inductor described above.

[0095] <6> The contours of the integrated first outer conductor land and the first inner conductor land have a shape in which a virtual first outer circle centered on the first outer via conductor and a virtual first inner circle centered on the first inner via conductor partially overlap each other, and the contours of the integrated second outer conductor land and the second inner conductor land have a shape in which a virtual second outer circle centered on the second outer via conductor and a virtual second inner circle centered on the second inner via conductor partially overlap each other. <5> The multilayer inductor described above.

[0096] <7> The aforementioned virtual first inner circle is smaller than the aforementioned virtual first outer circle, and the aforementioned virtual second inner circle is smaller than the aforementioned virtual second outer circle. <6> The multilayer inductor described above.

[0097] <8> The first inner via conductor and the second inner via conductor are each distributed at multiple locations. <1> or <7> A multilayer inductor as described in any of the following.

[0098] <9> When the laminate is viewed through to the nonconductive layer in the stacking direction, the circumferential conductor has any number of corners, and the first outer via conductor and the second outer via conductor are positioned to overlap with any of the corners in the circumferential conductor. <1> or <8> A multilayer inductor as described in any of the following. [Explanation of Symbols]

[0099] 1,1a,1b,1c,1d Multilayer Inductor 2 Laminate 3,4 Edge non-conductive material layer 5-8 Side 9 Non-conductive layer 11,12 terminal electrode 13 Coil Conductors 15,16 Lead-out conductors 18. Circular conductor 19 Intermediate via conductor 20 Intermediary Pad 21,23 Outer via conductor 22,24 Inner via conductor 25,27 Outer conductor land 26,28 Inner conductor land

Claims

1. A laminate comprising multiple nonconductive layers stacked in the stacking direction, The laminate has a rectangular prism or a substantially rectangular prism shape, having a first end face and a second end face that face each other, and four side faces that connect the first end face and the second end face. The stacking direction is parallel to the direction in which the first end face and the second end face face each other. A first terminal electrode is provided on at least a portion of the first end face and extends from the first end face to a portion of at least one adjacent side surface, A second terminal electrode is provided on at least a portion of the second end face and extends from the second end face to a portion of at least one adjacent side surface, A coil conductor is arranged inside the laminate, Furthermore, The coil conductor comprises a plurality of circumferential conductors extending along the interface between the nonconductive layers to form a portion of an annular orbit, and a plurality of intermediary via conductors penetrating the nonconductive layer in the thickness direction, wherein the plurality of circumferential conductors are connected via the intermediary via conductors to extend along a helical orbit. A first lead conductor is drawn out from the first end of the coil conductor and connected to the first terminal electrode, A second lead conductor is drawn out from the second end of the coil conductor opposite to the first end and connected to the second terminal electrode, Furthermore, The first lead conductor includes a first outer via conductor and a first inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the first terminal electrode at the first end face. The second lead conductor includes a second outer via conductor and a second inner via conductor that penetrate the nonconductive layer in the thickness direction, extend parallel to each other and are connected in parallel, and are connected to the second terminal electrode at the second end face. When the laminate is viewed through in the lamination direction of the nonconductive layer, the first outer via conductor and the second outer via conductor are positioned so that all portions overlap with the circumferential conductor, and at least a portion of the first inner via conductor and the second inner via conductor are located on the inner diameter side of the circumferential conductor. Multilayer inductor.

2. The laminated inductor according to claim 1, wherein when the laminate is viewed through in the direction of the lamination of the nonconductive layer, all portions of the first inner via conductor and the second inner via conductor are located on the inner diameter side of the circumferential conductor.

3. The laminated inductor according to claim 1, wherein the cross-sectional area of ​​the first inner via conductor is greater than the cross-sectional area of ​​the first outer via conductor, and the cross-sectional area of ​​the second inner via conductor is greater than the cross-sectional area of ​​the second outer via conductor.

4. The first outer via conductor, the first inner via conductor, the second outer via conductor, and the second inner via conductor extend so as to penetrate the plurality of nonconductive layers in the thickness direction. A first outer conductor land extending from the first outer via conductor along the interface of a plurality of nonconductive layers, A first inner conductor land extending from the first inner via conductor along the interface of a plurality of nonconductive layers, A second outer conductor land extending from the second outer via conductor along the interface of a plurality of nonconductive layers, A second inner conductor land extending from the second inner via conductor along the interface of a plurality of nonconductive layers, The stacked inductor according to claim 1, further comprising:

5. The laminated inductor according to claim 4, wherein the first outer conductor land and the first inner conductor land are integrated, and the second outer conductor land and the second inner conductor land are integrated.

6. The laminated inductor according to claim 5, wherein the contours of the integrated first outer conductor land and the first inner conductor land have a shape in which a virtual first outer circle centered on the first outer via conductor and a virtual first inner circle centered on the first inner via conductor partially overlap each other, and the contours of the integrated second outer conductor land and the second inner conductor land have a shape in which a virtual second outer circle centered on the second outer via conductor and a virtual second inner circle centered on the second inner via conductor partially overlap each other.

7. The stacked inductor according to claim 6, wherein the virtual first inner circle is smaller than the virtual first outer circle, and the virtual second inner circle is smaller than the virtual second outer circle.

8. The laminated inductor according to claim 1, wherein the first inner via conductor and the second inner via conductor are each distributed at multiple locations.

9. The laminated inductor according to claim 1, wherein when the laminate is viewed through in the direction of the stacking of the nonconductive layers, the circumferential conductor has any number of corners, and the first outer via conductor and the second outer via conductor are positioned to overlap with any of the corners in the circumferential conductor.

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