Receiver and timing control circuit

Abstract

The present invention provides a receiver and timing control circuit that can accurately measure the waiting time for transmitting response frames while keeping the circuit size down. [Solution] A receiver that receives a modulated wave of wireless communication, which includes an instruction frame consisting of an operation command that requests a predetermined operation, as a received signal, and performs a predetermined operation after a predetermined waiting time has elapsed according to the operation command, comprising: a clock generation circuit that generates a clock signal using the received signal; a pause interval detection circuit that detects a pause interval in which the signal level of the received signal is below a reference level; and a timing control circuit 21 that determines the timing when the waiting time has elapsed by counting the clock pulses of the clock signal, wherein if a pause interval is detected during the waiting time, the timing control circuit stops counting the clock pulses, and after the pause interval has elapsed, restarts counting the clock pulses with a starting value that is the count value up to the pause interval plus an interpolated value.

Description

Technical Field

[0001] The present invention relates to a receiver, and particularly to a receiver for receiving a modulated wave of wireless communication.

Background Art

[0002] As a modulation method of wireless communication, ASK modulation (Amplitude Shift Keying) is widely used. In wireless transmission using ASK modulation, 100% ASK modulation is performed according to data, and transmission and reception of an amplitude-modulated carrier signal having a high amplitude section and a low amplitude pause section are performed. A receiver for wireless communication by the ASK modulation method (hereinafter referred to as an ASK receiver) receives, for example, an instruction frame including a response instruction from a transmitter which is a master unit as an ASK modulated wave, and after a standby time has elapsed, transmits a response frame toward the master unit.

[0003] The modulated wave received by the receiver via an antenna is input to a rectifying circuit provided in the receiver and converted into DC power. The DC power obtained by converting the modulated wave is supplied as power supply power to an oscillation circuit and a logic circuit, and is also used for charging an external capacitor connected to the rectifying circuit.

[0004] Further, a pause section detection circuit provided in the receiver performs envelope detection of the modulated wave received via the antenna, and determines the start and end of the pause section in the modulated wave by comparing its voltage amplitude level with a reference voltage. A timing control circuit in the logic circuit receives an input of a clock signal generated in the oscillation circuit, resets a counter in the pause section detected by the pause section detection circuit, and counts the number of clock signals in sections other than the pause section. When the count value of the number of clock signals reaches a predetermined value indicating the end of the standby time, the receiver generates and encodes transmission data, and transmits it to the transmitter as an analog modulated wave through modulation by a load modulation circuit.

[0005] In a receiver with this configuration, charging of the external capacitor occurs during periods other than the idle period. Therefore, even during the idle period, power is continuously supplied to the oscillation circuit and logic circuit by the charge held in the external capacitor. For this reason, even if the idle period arrives while the standby time is being measured, the timing control circuit can continue to count the number of clock cycles.

[0006] In a wireless receiver equipped with a capacitor that serves as a power source during such non-power supply periods, a data carrier system has been proposed that allows for a reduction in the capacitance of the capacitor used in the first power supply unit by separately providing a first power supply unit that supplies power to the signal processing unit and a second power supply unit that supplies power to the transmission unit, and by stopping the operation of the signal processing unit during non-power supply periods (for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 11-53491 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] In receivers with the above configuration, the large number of components such as external capacitors increases the circuit size, leading to a higher cost for implementing the system. On the other hand, if the external capacitor is removed from the above configuration, power is not supplied to the oscillation circuit and timing control circuit during the pause period, causing the generation of the clock signal and the counting of clocks to stop. As a result, the standby time cannot be measured accurately, and the transmission of response frames by the receiver is delayed by the amount of the pause period.

[0009] This invention has been made in view of the above-mentioned problems, and aims to provide a receiver for receiving modulated waves in wireless communication that can perform highly accurate time measurement for transmitting response frames while keeping the circuit size down. [Means for solving the problem]

[0010] The receiver according to the present invention receives a modulated wave of wireless communication as a received signal, which includes an instruction frame consisting of an operation command that requests a predetermined operation, and performs the predetermined operation after a predetermined waiting time has elapsed in accordance with the operation command. The receiver includes a power supply circuit that acquires the received signal via an antenna and generates a DC power supply based on the received signal; a clock generation circuit that generates a clock signal using the received signal; a pause interval detection circuit that detects a pause interval in which the signal level of the received signal is below a reference level; and a timing control circuit that operates based on the DC power supply and determines the timing at which the waiting time has elapsed by counting the clock pulses of the clock signal. The timing control circuit is characterized in that, if the pause interval is detected during the waiting time, it stops counting the clock pulses, and after the pause interval has elapsed, it restarts counting the clock pulses with a starting value that is the count value up to the pause interval plus an interpolated value.

[0011] Furthermore, the timing control circuit according to the present invention is provided in a receiver that receives a modulated wave of wireless communication, which includes an instruction frame consisting of an operation command that requests a predetermined operation, as a received signal, and performs the predetermined operation after a predetermined waiting time has elapsed in accordance with the operation command, and operates based on a DC power supply generated based on the received signal, and determines the timing at which the waiting time has elapsed, and comprises a standby detection circuit that determines whether or not it is the waiting time based on the received signal, an adder that sequentially adds a count value in accordance with the clock pulses of a clock signal generated using the received signal during the waiting time, and a storage unit that stores an interpolated value, wherein the adder, if a pause period occurs during the waiting time in which the signal level of the received signal is below a reference level, stops adding the count value during the pause period, and resumes adding the count value with the value obtained by adding the interpolated value to the count value up to the pause period as a new starting value when the pause period is completed. [Effects of the Invention]

[0012] According to the receiver of the present invention, while keeping the circuit size down, it is possible to accurately measure the waiting time for transmitting a response frame when an ASK modulated wave consisting of an instruction frame including a response command is received. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram showing the configuration of a receiver according to an embodiment of the present invention. [Figure 2] This is a circuit showing the configuration of a timing control circuit according to an embodiment of the present invention. [Figure 3] This graph shows the relationship between the pause interval of the modulated wave and the clock count value in an embodiment of the present invention. [Figure 4] This is a time chart showing the time changes in the count values ​​of each signal and clock count within the timing control circuit during standby time. [Figure 5] This is a block diagram showing the receiver configuration for the comparative example. [Figure 6] It is a circuit showing the configuration of the timing control circuit according to the comparative example. [Figure 7] It is a graph showing the relationship between the pause interval of the modulated wave and the count value of the clock number in the comparative example. [Figure 8] It is a time chart showing the time change of each signal in the timing control circuit and the count value of the clock number during the standby time of the comparative example.

Embodiments for Carrying Out the Invention

[0014] Preferred embodiments of the present invention will be described in detail below. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to substantially the same or equivalent parts.

[0015] FIG. 1 is a block diagram showing the configuration of a receiver 100 according to an embodiment of the present invention. The receiver 100 is a wireless receiver that receives an ASK (Amplitude Shift Keying) modulated wave wirelessly transmitted from a transmitter (not shown). From a transmitter not shown, a 100% ASK modulated wave including an instruction frame for requesting a predetermined operation to the receiver is transmitted.

[0016] In this embodiment, a response command for requesting the transmitter to respond after a predetermined standby time has elapsed is included in the instruction frame. The receiver 100 transmits an ASK modulated wave including a response frame toward the transmitter according to the response command included in the received instruction frame.

[0017] The receiver 100 includes an antenna 11, a rectifier circuit 12, a clock generation circuit 13, a pause interval detection circuit 14, a logic circuit 15, and a load modulation circuit 16.

[0018] The antenna 11 receives the modulated wave S1 transmitted from a transmitter not shown, and supplies it to the rectifier circuit 12, the clock generation circuit 13, and the pause interval detection circuit 14, respectively.

[0019] The rectifier circuit 12 rectifies the modulated wave S1, which is the received signal received via the antenna 11, and converts it into DC power S2. The DC power S2 is supplied to the logic circuit 15 as the power supply for the logic circuit 15.

[0020] The clock generation circuit 13 extracts a clock from the modulated wave S1 received by the antenna 11 and outputs it as a clock signal CLK. During the pause period of the modulated wave S1, since the modulated wave S1 has a low amplitude (i.e., an amplitude level lower than the reference voltage), no clock extraction is performed.

[0021] The pause period detection circuit 14 performs envelope detection on the modulated wave S1 and compares its voltage level with the reference voltage to determine the start and end timing of the pause period in the modulated wave S1. The pause period detection circuit 14 supplies a pause period detection signal S3 indicating the pause period to the logic circuit 15.

[0022] The logic circuit 15 includes a timing control circuit 21, a decoder 22, a received data control circuit 23, a transmit / receive data buffer 24, a CPU 25, a transmit data control circuit 26, and an encoder 27.

[0023] The timing control circuit 21 receives the supply of the clock signal CLK from the clock generation circuit 13 and counts the number of clocks. At this time, the timing control circuit 21 counts the number of clocks of the clock signal CLK in the period other than the pause period based on the pause period detection signal S3. Since no power is supplied to the logic circuit 15 during the pause period and no clock signal is generated by the clock generation circuit 13, the timing control circuit 21 stops counting the number of clocks.

[0024] The decoder 22 decodes the count value CV output by the timing control circuit 21 and generates decoded data DD.

[0025] The received data control circuit 23 performs serial-to-parallel conversion on the decoded data and generates parallel data PD.

[0026] The transmit / receive data buffer 24 stores the generated parallel data PD. This allows the receiver 100 to receive the command frame transmitted from the master transmitter.

[0027] Furthermore, when the decoder 22 receives the last bit indicating the final pause section of the instruction frame, it supplies a last bit detection signal LBS to the timing control circuit 21.

[0028] When the timing control circuit 21 receives the final bit detection signal LBS, it enters a state where it measures the waiting time. That is, the timing control circuit 21 performs a count to measure the waiting time based on the clock pulse of the clock signal CLK.

[0029] While the timing control circuit 21 is measuring the waiting time, the CPU 25 writes the transmission instruction SS for the response frame to the transmit / receive data buffer 24.

[0030] The transmit data control circuit 26 generates transmit data SD according to the transmit instruction SS set in the transmit / receive data buffer 24. The transmit data control circuit 26 generates transmit data SD when the count value of the waiting time in the timing control circuit 21 reaches a predetermined waiting time expiration value, and supplies the generated transmit data SD to the encoder 27.

[0031] The encoder 27 encodes the transmission data SD supplied from the transmission data control circuit 26 and generates encoded data ED. The encoder 27 supplies the generated encoded data ED to the load modulation circuit 16.

[0032] The load modulation circuit 16 modulates the encoded data ED to generate a modulated wave S4. The modulated wave S4 is transmitted via the antenna 11. This provides a response to the master transmitter.

[0033] Figure 2 is a circuit diagram showing the configuration of the timing control circuit 21.

[0034] The synchronization circuit 31 receives the input of the pause section detection signal S3, which is an asynchronous signal, and synchronizes it. The synchronization circuit 31 outputs a pause section completion signal PS when the synchronized pause section ends.

[0035] The standby detection circuit 32 receives the final bit detection signal LBS and determines whether the receiver 100 is in a receiving state or in a standby time measurement state. The standby detection circuit 32 outputs a standby determination signal WS indicating the determination result.

[0036] The AND gate 33 receives a pause section completion signal PS at its first input terminal and a signal with the logic of the standby determination signal WS inverted (a negative logic signal) at its second input terminal, and outputs the logical AND of these signals as the first enable signal EN1.

[0037] The AND gate 34 receives a pause interval completion signal PS at its first input terminal and a standby determination signal WS at its second input terminal, and outputs the logical AND of these signals as an add enable signal AEN.

[0038] The interpolation value register 35 is a register that stores the pause interval interpolation value ICV. The pause interval interpolation value ICV is an interpolation value used to interpolate the count value in the count used for measuring the waiting time stopped during the pause interval. The value of the pause interval interpolation value ICV is predetermined according to the known length of the pause interval in the ASK modulated wave.

[0039] The addition value selector 36 selectively outputs either the pause interval interpolation value ICV read from the interpolation value register 35, or "0", as the addition value AV, in response to the addition enable signal AEN. In this embodiment, the addition value selector 36 outputs the pause interval interpolation value ICV as the addition value AV when the signal level of the addition enable signal AEN is logic level 1, and the value "0" as the addition value AV when the logic level is 0.

[0040] The adder 37 is an adder that adds "1" to the count value CV output from the flip-flop 45, which is the output section of the timing control circuit 21. In this embodiment, the adder 37 outputs the result of adding the count value CV and "1", plus the addition value AV output from the addition value selector 36, as the added count value CVA.

[0041] As described above, the summation value AV, which is the output of the summation value selector 36, becomes either the pause interval interpolation value ICV or "0" depending on the signal level of the summation enable signal AEN. Therefore, when the summation value AV is "0", the value obtained by adding "1" to the count value CV is output as the summed count value CVA. Also, when the summation value AV is the pause interval interpolation value ICV, the value obtained by adding "1" to the count value CV and then adding the pause interval interpolation value ICV is output as the summed count value CVA.

[0042] The selector 41 selectively outputs either the summed count value CVA or "0" in response to the first enable signal EN1.

[0043] As described above, the first enable signal EN1 is a signal consisting of the logical AND of the inverted signal of the pause section completion signal PS and the standby determination signal WS. Therefore, when the pause section completion signal PS is at logical level 1 and the standby determination signal WS is at logical level 0, that is, when the received modulated wave S1 is in the pause section and in the reception state, the first enable signal EN1 is at logical level 1. In response to the first enable signal EN1 at logical level 1, the value "0" among the inputs of selector 41 is selected and output as the first selector output SO1 (i.e., the selector output is initialized).

[0044] On the other hand, if the logic levels of the pause section completion signal PS and the standby determination signal WS are any other combination, the first enable signal EN1 becomes logic level 0, the summed count value CVA from the inputs of selector 41 is selected and output as the first selector output SO1.

[0045] The expiration value register 42 is a register that stores the waiting time expiration value WEV. The waiting time expiration value WEV is predetermined based on the waiting time in a normal modulated wave S1.

[0046] The comparator 43 compares the waiting time expiration value WEV read from the expiration value register 42 with the count value CV output from the flip-flop 45, and outputs a signal representing the comparison result as the second enable signal EN2. In this embodiment, if the count value CV exceeds the waiting time expiration value WEV, the comparator 43 outputs the second enable signal EN2 at logic level 1. If the count value CV is less than or equal to the waiting time expiration value WEV, the comparator 43 outputs the second enable signal EN2 at logic level 0.

[0047] Selector 44 selectively outputs either the first selector output SO1, which is the output of selector 41, or "0" in response to the second enable signal EN2. Specifically, if the second enable signal EN2 is at logic level 1, that is, if the count value CV exceeds the waiting time expiration value WEV, selector 44 outputs "0" as the second selector output SO2 (i.e., initializes the selector output). On the other hand, if the second enable signal EN2 is at logic level 0, that is, if the count value CV is less than or equal to the waiting time expiration value WEV, selector 44 outputs the first selector output SO1, which is the output of selector 41, as the second selector output SO2.

[0048] Flip-flop 45 is a flip-flop circuit that operates by receiving the input of the second selector output SO2, which is the output of selector 44. Flip-flop 45 is initialized when the second selector output SO2 is "0", that is, when the count value CV exceeds the waiting time expiration value WEV. Otherwise, flip-flop 45 outputs the added count value CVA, which is the count value after addition by adder 37, as the count value CV, and the count values ​​CV are added sequentially.

[0049] Next, the operation of the timing control circuit 21 when the receiver 100 receives the modulated wave S1 will be explained with reference to Figures 3 and 4. Here, we will explain as an example the case in which a pause period (i.e., a waiting pause period) is included in the waiting time between the reception of the instruction frame and the transmission of the response frame.

[0050] Figure 3 is a graph showing the relationship between the pause interval of the modulated wave S1 received by the receiver 100 and the clock count value in the timing control circuit 21.

[0051] When the final pause interval of the instruction frame arrives, the timing control circuit 21 resets the clock count value CV. After that, the timing control circuit 21 transitions to a state where it measures the waiting time.

[0052] Figure 4 is a time chart showing the changes in the output signals of each part in the timing control circuit 21 during the waiting time.

[0053] During the waiting period, the timing control circuit 21 performs a count to measure the waiting time. The count value CV is sequentially added according to the timing of the clock pulses of the clock signal CLK.

[0054] If a pause period occurs during the waiting time, the rectifier circuit 12 does not generate DC power S2 and the clock generation circuit 13 does not extract the clock during that pause period. The pause period detection circuit 14 generates a pause period detection signal S3, which is logic level 1 during that pause period, and supplies it to the timing control circuit 21.

[0055] During the downtime, DC power S2 is not supplied, so the timing control circuit 21 does not operate, and the count for measuring the standby time stops.

[0056] When the pause period ends, the generation of DC power S2 by the rectifier circuit 12 and the extraction of the clock by the clock generation circuit 13 resume, and the timing control circuit 21 resumes counting operations for measuring the waiting time.

[0057] Furthermore, after the pause period ends, the pause period completion signal PS output from the synchronization circuit 31 is at logic level 1 for the duration of one cycle of the clock pulse of the clock signal CLK. Since the standby determination signal WS is always at logic level 1, the add enable signal AEN output from the AND gate 34 is also at logic level 1 for one cycle, similar to the pause period completion signal PS. As a result, during that one cycle, the added count value CVA is obtained by adding "1" and the pause period interpolation value ICV to the count value CV of the previous cycle.

[0058] Since both the first enable signal EN1 and the second enable signal EN2 are at logic level 0, the flip-flop 45 takes the value of the added count CVA and outputs it as the count CV for the next cycle. From that next cycle onward, the value of the added value AV becomes "0", so the adder 37 adds only "1" to the count CV and outputs it. This allows for normal counting operation.

[0059] As described above, the timing control circuit 21 of this embodiment stops counting for waiting time measurement during the pause period. When the pause period ends, the timing control circuit 21 restarts counting using the value obtained by adding the pause period interpolation value ICV to the count value CV immediately before the pause as the starting value. This makes it possible to start transmitting the response frame earlier compared to when the pause period interpolation value ICV is not added.

[0060] If the pause interval interpolation value ICV is not added, as shown by the dashed line in Figure 3, the timing at which the count value CV reaches the standby time expiration value WEV will be delayed by the amount of the standby pause interval, and as a result, the timing of the start of transmission of the response frame will be delayed. In contrast, the timing control circuit 21 of this embodiment adds the pause interval interpolation value ICV, which corresponds to the count value that could have been counted if there had been no standby pause interval, so that the count value CV reaches the standby time expiration value WEV at the same timing as when there is no standby pause interval. Therefore, the transmission of the response frame can be started at the same timing as when there is no standby pause interval.

[0061] Furthermore, with the timing control circuit 21 configured in this way, the receiver 100 can transmit a response frame at the same timing as when there is no pause period, even if a pause period occurs during the waiting time, without the need to provide an external capacitor.

[0062] Figure 5 is a block diagram showing the configuration of a comparative example receiver 200, which differs from the receiver 100 of this embodiment in that it is equipped with a capacitor for power supply during the idle period. The receiver 200 has an oscillator circuit 51 and a capacitor 52.

[0063] The oscillator circuit 51 receives DC power S2 from the rectifier circuit 12 and operates using this power source to generate a clock signal CLK.

[0064] Capacitor 52 is charged by receiving DC power S2 from the rectifier circuit 12. The power charged in capacitor 52 is used as the power source for the oscillator circuit 51 and logic circuit 15 during the idle period.

[0065] Figure 6 is a circuit diagram showing the configuration of the timing control circuit 21A in the comparative example receiver 200.

[0066] In the comparative example timing control circuit 21A, there is no configuration equivalent to the interpolation value register 35 in the timing control circuit 21 of the above embodiment, and the adder 37 continuously performs the operation of adding "1" to the count value CV.

[0067] Figure 7 is a graph showing the relationship between the pause interval of the modulated wave S1 received by the comparative example receiver 200 and the clock count value in the timing control circuit 21. Figure 8 is a time chart showing the changes in the output signals of each part in the timing control circuit 21A of the comparative example during the standby time.

[0068] In the comparative example receiver 200, the power charged in the capacitor 52 is supplied to the oscillation circuit 51 and the logic circuit 15, respectively, during the standby pause period. Therefore, even during the standby pause period, the clock pulse of the clock signal CLK is not interrupted, and the count for measuring the standby time by the timing control circuit 21A in the logic circuit 15 continues. As a result, the comparative example receiver 200 can start transmitting the response frame at the same timing as if there were no standby pause period.

[0069] However, the comparative example receiver 200 is equipped with a capacitor 52, resulting in a larger circuit size compared to the receiver 200 of this embodiment, which does not have such a capacitor. Furthermore, the oscillation circuit 51 provided in the comparative example receiver 200 differs from the clock generation circuit 13 in the receiver 100 of this embodiment in that it can generate a clock signal CLK regardless of the reception state of the modulated wave S1, but its circuit size is larger than that of the clock generation circuit 13.

[0070] Therefore, the configuration of the receiver 100 in this embodiment allows for high-precision time measurement for response frame transmission, while maintaining a smaller circuit size compared to the receiver 200 of the comparative example.

[0071] It should be noted that the present invention is not limited to those shown in the above embodiments. For example, in the above embodiments, a clock generation circuit 13 is provided in the receiver 100, and a clock signal CLK is generated by extracting the clock from the received modulated wave S1. However, the method of generating the clock signal CLK is not limited to this, and for example, as in the oscillator circuit 51 provided in the receiver 200 of the comparative example, the clock signal CLK may be generated by receiving DC power S2 from the rectifier circuit 12 instead of extracting the clock from the modulated wave S1. Even with such a configuration, the circuit size can be reduced compared to the receiver 200 of the comparative example because an external capacitor is not provided.

[0072] Furthermore, in the above embodiment, the case was described as an example in which the selector output is initialized by selecting "0" for both the selector 41, which is the first stage selector that switches the output in response to the supply of the first enable signal EN1, and the selector 44, which is the second stage selector that switches the output in response to the supply of the second enable signal EN2. However, the initialization value is not limited to "0".

[0073] Furthermore, in the above embodiment, the case in which the interpolation value register 35 stores the pause interval interpolation value ICV was described as an example. However, the configuration of the storage unit that stores the pause interval interpolation value ICV is not limited to this, and any unit capable of storing a value can be applied. [Explanation of Symbols]

[0074] 100 display device 11 Antennas 12 Rectifier circuit 13. Clock generation circuit 14. Pause detection circuit 15 Logic Circuits 16. Load Modulation Circuit 21 Timing control circuit 22 Decoders 23. Receiving data control circuit 24. Transmit and receive data buffer 25 CPU 26. Transmission data control circuit 27 encoders 31 Synchronization circuit 32 Standby detection circuit 33 AND Gate 34 AND Gate 35 Complementary Value Register 36 Addition Value Selector 37 Adder 41 Selector 42 Expiration Value Register 43 Comparator 44 Selector 45 Flip-flops

Claims

1. A receiver that receives a modulated wave of wireless communication as a received signal, which includes an instruction frame consisting of an operation command requesting a predetermined operation, and performs the predetermined operation after a predetermined waiting time has elapsed in accordance with the operation command, A power supply circuit that acquires the received signal via an antenna and generates a DC power supply based on the received signal, A clock generation circuit that generates a clock signal using the received signal, A pause interval detection circuit that detects pause intervals in which the signal level of the received signal is below a reference level, A timing control circuit that operates based on the DC power supply and determines the timing at which the waiting time elapses by counting the clock pulses of the clock signal, Includes, If the pause period is detected during the waiting time, the timing control circuit stops counting the clock pulses, and after the pause period has elapsed, restarts counting the clock pulses using a starting value obtained by adding an interpolation value to the count value up to the pause period. A receiver characterized by the following features.

2. The modulation method for the aforementioned modulated wave is ASK (Amplitude Shift Keying). The pause interval detection circuit detects the pause interval by comparing the amplitude of the received signal with a reference voltage. The receiver according to feature 1.

3. The instruction frame includes a response instruction that requests the sender to respond after the waiting time has elapsed, The receiver according to claim 1, characterized in that, after the aforementioned waiting time has elapsed, it transmits a modulated wave including a response frame as a transmission signal toward the transmitting side.

4. The receiver according to claim 1, characterized in that the interpolation value is predetermined according to the length of the pause interval and is stored in the timing control circuit.

5. The aforementioned timing control circuit is A storage unit for storing the aforementioned completion value, A standby detection circuit that determines whether or not the standby time has elapsed based on the received signal, An adder that adds a count value for each cycle of the clock pulse of the clock signal, and when the standby detection circuit determines that it is the standby time and the pause interval detection circuit detects the pause interval, adds the interpolation value to the count value in accordance with the completion of the pause interval, The receiver according to claim 1, characterized by having

6. The receiver according to claim 1, characterized in that the clock generation circuit generates the clock signal by extracting the clock from the received signal.

7. A timing control circuit is provided in a receiver that receives a wireless communication modulated wave as a received signal, which includes an instruction frame consisting of an operation command requesting a predetermined operation, and performs the predetermined operation after a predetermined waiting time has elapsed in accordance with the operation command, and which operates based on a DC power supply generated based on the received signal and determines the timing at which the waiting time has elapsed, A standby detection circuit that determines whether or not the standby time has elapsed based on the received signal, During the aforementioned waiting time, an adder sequentially adds count values ​​in accordance with the clock pulses of a clock signal generated using the received signal, A memory unit for storing the completion value, It has, If, during the waiting period, the adder enters a pause period in which the signal level of the received signal falls below a reference level, it stops adding the count value during the pause period, and when the pause period is completed, it resumes adding the count value, using the value obtained by adding the interpolation value to the count value up to the pause period as a new starting value. A timing control circuit characterized by the following features.

8. The system includes a synchronization circuit that receives a pause section detection signal indicating that the pause section has been detected, and generates a pause section completion signal indicating the timing when the pause section has been completed. The adder adds the interpolation value to the count value at a timing based on the pause interval completion signal. The timing control circuit according to feature 7.

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