Indication device

Abstract

To provide a display device that can reduce subpixel size and power consumption. [Solution] A display device according to an embodiment of the present disclosure may include an active layer, a gate insulating film disposed on the active layer and having a first opening, a first electrode electrically connected to at least a portion of a first region of the active layer at the first opening, a second electrode disposed on the gate insulating film, a protective layer disposed on the first electrode and the second electrode and having a second opening, and a pixel electrode disposed on the protective layer and electrically connected to the first electrode at the second opening.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] A display device may include a driving transistor and a storage capacitor for each sub-pixel. Such a display device can change the aperture ratio of a sub-pixel according to the structure of the sub-pixel, and the image quality or resolution of the display panel may change according to the aperture ratio of the sub-pixel. As the resolution of the display device increases, it is necessary to increase the aperture ratio of each sub-pixel.

[0003] However, since the number or type of elements (for example, transistors, storage capacitors, light-emitting elements, etc.) included in each sub-pixel is determined, it may be difficult to optimize the sub-pixel structure to increase the aperture ratio.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present disclosure can provide a display device capable of reducing the size of a sub-pixel circuit unit provided in each sub-pixel by optimizing the structure.

[0005] Embodiments of the present disclosure can provide a display device capable of increasing the size of an aperture in each sub-pixel by reducing the size of the sub-pixel circuit unit through optimizing the structure, thereby improving the light extraction efficiency and reducing the power consumption.

[0006] Embodiments of the present disclosure can provide a display device capable of simplifying the structure of the sub-pixel circuit unit and reducing the size of the sub-pixel circuit unit by applying an overlapping structure of an opening of a protective layer and an opening of a gate insulating film to the sub-pixel circuit unit.

[0007] Embodiments of this disclosure provide a display device that simplifies the structure of the subpixel circuit and reduces its size by applying an unsupervised structure of the protective layer opening and storage capacitor to the subpixel circuit.

[0008] The embodiments of this disclosure provide a display device that can reduce contact resistance compared to a direct connection structure between the pixel electrode and the active layer, by having the pixel electrode electrically connected to the active layer with the electrode of the driving transistor in between within the subpixel circuit to form a current path. [Means for solving the problem]

[0009] Embodiments of the present disclosure can provide a display device comprising: a substrate; an active layer disposed on the substrate and including a channel region, a first region located on one side of the channel region, and a second region located on the other side of the channel region; a gate insulating film disposed on the active layer and having a first opening; a first electrode electrically connected to at least a portion of the first region at the first opening; a second electrode disposed on the gate insulating film and overlapping with the channel region; a protective layer disposed on the first electrode and the second electrode, superimposed on at least a portion of the first electrode and having a second opening that overlaps with at least a portion of the first opening; and a pixel electrode disposed on the protective layer and electrically connected to the first electrode at the second opening.

[0010] Embodiments of the present disclosure can provide a display device comprising a substrate, a drive transistor disposed on the substrate and including an active layer, a first electrode, a second electrode, and a third electrode, a light-emitting element including a pixel electrode electrically connected to the first electrode and a common electrode facing the pixel electrode, and a storage capacitor disposed on the drive transistor and overlapping the channel region of the active layer of the drive transistor. [Effects of the Invention]

[0011] According to embodiments of this disclosure, it is possible to provide a display device that can reduce the size of the subpixel circuit portion provided in each subpixel by optimizing the structure.

[0012] According to embodiments of this disclosure, by optimizing the structure to reduce the size of the subpixel circuit section, the size of the aperture within each subpixel can be increased, thereby providing a display device that can improve the efficiency of light extraction and reduce power consumption.

[0013] According to embodiments of this disclosure, by applying a superposition structure of an opening in the protective layer and an opening in the gate insulating film to the subpixel circuit, it is possible to provide a display device that simplifies the structure of the subpixel circuit and reduces the size of the subpixel circuit.

[0014] According to embodiments of this disclosure, by applying an unsupervised structure of the protective layer opening and storage capacitor to the subpixel circuit section, it is possible to provide a display device that simplifies the structure of the subpixel circuit section and reduces its size.

[0015] According to embodiments of this disclosure, in the subpixel circuit section, the pixel electrodes are electrically connected to the active layer with the electrodes of the driving transistor in between, forming a current path. This provides a display device that can reduce contact resistance compared to a direct connection structure between the pixel electrodes and the active layer. [Brief explanation of the drawing]

[0016] The aforementioned and other purposes, features, and advantages of this disclosure will be more clearly understood by those skilled in the art by a detailed description of embodiments of this disclosure with reference to the accompanying drawings.

[0017] [Figure 1] This is a diagram illustrating a display device according to an embodiment of the present disclosure. [Figure 2] This figure illustrates an example of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 3] This is a diagram for explaining an example of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 4] This is a diagram for explaining another example of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 5] This is a diagram for explaining an embodiment of a subpixel according to an embodiment of the present disclosure. [Figure 6] This is a diagram for explaining an embodiment of a subpixel according to an embodiment of the present disclosure. [Figure 7] This is a diagram for explaining another embodiment of a subpixel according to an embodiment of the present disclosure. [Figure 8] This is a diagram for explaining another embodiment of a subpixel according to an embodiment of the present disclosure. [Figure 9] This is a diagram for explaining yet another embodiment of a subpixel according to an embodiment of the present disclosure. [Figure 10] This is a diagram for explaining yet another embodiment of a subpixel according to an embodiment of the present disclosure.

MODE FOR CARRYING OUT THE INVENTION

[0018] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, they may be given the same reference numerals as much as possible. In addition, when explaining the present disclosure, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted.

[0019] When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include the case of including a plurality unless there are specific descriptions.

[0020] The features of the various embodiments of this specification can be partially or wholly combined or combined with each other, and can operate in conjunction with each other in various technical ways. Each embodiment can be executed independently of each other or in cooperation with each other.

[0021] Also, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the components from other components, and do not limit the essence, order, sequence or number of the components by these terms.

[0022] In the description of the positional relationship of components, when two or more components are described as being "connected", "coupled", "overlapped" or "connected", two or more components can be directly "connected", "coupled", "overlapped" or "connected", but it should be understood that two or more components and other components can also be further "intervened" and "connected", "coupled", "overlapped" or "connected". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", "overlapped" or "connected" to each other.

[0023] In the description of the relationship of the time flow regarding components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or the flow sequence relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it may include non - continuous cases unless "immediately" or "directly" is used.

[0024] On the other hand, when a numerical value regarding a component or its corresponding information (for example, level, etc.) is mentioned, even without a separate explicit description, the numerical value or its corresponding information can be interpreted as including the range of errors that can occur due to various factors (for example, process factors, internal or external impacts, noise, etc.).

[0025] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0027] Referring to Figure 1, the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a drive circuit for driving the display panel 110.

[0028] The drive circuit may include a data drive circuit 120 and a gate drive circuit 130, and may further include a controller 140 that controls the data drive circuit 120 and the gate drive circuit 130.

[0029] The display panel 110 may include a substrate SUB and a plurality of data lines DL and a plurality of gate lines GL arranged on the substrate SUB. The display panel 110 may also include a plurality of subpixels SP connected to the plurality of data lines DL and the plurality of gate lines GL.

[0030] The display panel 110 may include a display area DA on which an image is displayed, and a non-display area NDA located outside the display area DA where no image is displayed. In the display panel 110, the display area DA is provided with a plurality of subpixels SP for displaying an image, and the non-display area NDA may be electrically connected to a data drive circuit 120, a gate drive circuit 130, and a controller 140, or at least one of the data drive circuit 120, gate drive circuit 130, and controller 140 may be mounted there, and pads to which integrated circuits or printed circuits are connected may be provided.

[0031] The data drive circuit 120 is a circuit for driving multiple data lines DL and can supply data signals to multiple data lines DL. The gate drive circuit 130 is a circuit for driving multiple gate lines GL and can supply gate signals to multiple gate lines GL. The controller 140 can supply a data control signal DCS to the data drive circuit 120 to control the operation timing of the data drive circuit 120. The controller 140 can supply a gate control signal GCS to the gate drive circuit 130 to control the operation timing of the gate drive circuit 130.

[0032] The controller 140 can receive input image data from an external source (e.g., a host system 150), scan the received input image data according to the timings implemented in each frame, switch the received input image data to match the format of the data signals used by the data drive circuit 120, supply the switched image data DATA to the data drive circuit 120, and control the data drive to proceed at an appropriate time in response to the scanning of the received input image data.

[0033] The controller 140 can output various gate control signals (GCS), including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE), in order to control the gate drive circuit 130.

[0034] The controller 140 can output various data control signals (DCS), including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), in order to control the data drive circuit 120.

[0035] The controller 140 may be implemented as a separate component from the data drive circuit 120, or it may be implemented as an integrated circuit by being integrated with the data drive circuit 120.

[0036] The data drive circuit 120 receives image data DATA from the controller 140 and drives multiple data lines DL by supplying data voltage to each data line DL. Here, the data drive circuit 120 is also called the source drive circuit.

[0037] Such a data-driven circuit 120 may include one or more source driver integrated circuits (SDICs).

[0038] For example, each source driver integrated circuit (SDIC) may be connected to the display panel 110 using a tape-automated bonding (TAB) method, or to the bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method, or it may be connected to the display panel 110 using a chip-on-film (COF) method.

[0039] The gate drive circuit 130 can output a gate signal at the turn-on level voltage or a gate signal at the turn-off level voltage, depending on the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by sequentially supplying gate signals at the turn-on level voltage to multiple gate lines GL.

[0040] The gate drive circuit 130 may be connected to the display panel 110 by tape automated bonding (TAB), connected to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) method, or connected to the display panel 110 depending on the chip-on-film (COF) method. Alternatively, the gate drive circuit 130 may be of the gate-in-panel (GIP) type and formed in the non-display area NDA of the display panel 110. The gate drive circuit 130 may be placed on the substrate SUB or connected to the substrate SUB. That is, in the case of the GIP type, the gate drive circuit 130 may be placed in the non-display area NDA of the substrate SUB. In the case of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate drive circuit 130 may be connected to the substrate SUB.

[0041] On the other hand, at least one of the data drive circuit 120 and the gate drive circuit 130 may be placed in the display area DA. For example, at least one of the data drive circuit 120 and the gate drive circuit 130 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or completely overlap with the subpixel SP.

[0042] When a specific gate line GL is opened by the gate drive circuit 130, the data drive circuit 120 can convert the image data Data received from the controller 140 into an analog data voltage, and supply the data voltage to multiple data lines DL to drive each subpixel SP with a specific color and brightness.

[0043] The data drive circuit 120 may be connected to one side of the display panel 110 (for example, the top or bottom side). Depending on the drive method, panel design method, etc., the data drive circuit 120 may be connected to both sides of the display panel 110 (for example, the top and bottom sides), or to two or more of the four sides of the display panel 110.

[0044] The gate drive circuit 130 may be connected to one side of the display panel 110 (for example, the left or right side). Depending on the drive method, panel design method, etc., the gate drive circuit 130 may be connected to both sides of the display panel 110 (for example, the left and right sides), or to two or more of the four sides of the display panel 110.

[0045] The controller 140 may be a timing controller used in conventional display technology, a control device that can perform other control functions in addition to the timing controller, a control device different from the timing controller 140, or a circuit within a control device. The controller 140 can be implemented as various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a processor.

[0046] The controller 140 can be mounted on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via the printed circuit board, flexible printed circuit board, etc.

[0047] The display device 100 according to the embodiments of this disclosure may be a display including a backlight unit such as a liquid crystal display device, or it may be a self-emissive display such as an OLED (Organic Light Emitting Diode) display, a Quantum Dot display, or a Micro LED (Micro Light Emitting Diode) display.

[0048] If the display device 100 according to the embodiment of the present disclosure is an OLED display, each subpixel SP may include an organic light-emitting diode (OLED) as a light-emitting element that emits light itself. If the display device 100 according to the embodiment of the present disclosure is a quantum dot display, each subpixel SP may include a light-emitting element made of a quantum dot, which is a semiconductor crystal that emits light itself. If the display device 100 according to the embodiment of the present disclosure is a microLED display, each subpixel SP may include a microlight-emitting diode (Micro LED) made from inorganic material that emits light itself as a light-emitting element.

[0049] The display panel 110 according to the embodiments of this disclosure is a top emission structure or a bottom emission structure, and may optionally be a double-sided emission structure.

[0050] Figures 2 and 3 illustrate an example of a subpixel SP of a display device 100 according to an embodiment of the present disclosure.

[0051] Specifically, Figure 2 shows an example of an equivalent circuit of a subpixel SP according to an embodiment of the present disclosure, and Figure 3 shows a diagram for further illustrating the equivalent circuit of the subpixel SP shown in Figure 2.

[0052] Referring to Figure 2, each of the subpixels SP according to the embodiments of the present disclosure may include a light-emitting element ED and a subpixel circuit section SPC configured to drive the light-emitting element ED.

[0053] Referring to Figure 2, the subpixel circuit section SPC may include a drive transistor DT for driving the light-emitting element ED, a scan transistor SCT for transmitting a data voltage VDATA to the first node N1 of the drive transistor DT, and a storage capacitor Cst positioned between the second node N2 and the third node N3 of the drive transistor DT to maintain a constant voltage for one frame.

[0054] The light-emitting element ED includes a pixel electrode PE and a common electrode CE, and may include a light-emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0055] The pixel electrode PE of the light-emitting element ED is an electrode placed on each subpixel SP, and the common electrode CE may be an electrode placed in common to all subpixels SP. Here, the pixel electrode PE may be the anode electrode, and the common electrode CE may be the cathode electrode. Conversely, the pixel electrode PE may be the cathode electrode, and the common electrode CE may be the anode electrode.

[0056] The common electrode CE of the light-emitting element ED may be connected to a low-voltage line VSSL to which a low-voltage voltage EVSS is applied.

[0057] For example, the light-emitting element (ED) could be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting element.

[0058] The driving transistor DT is a transistor for driving the light-emitting element ED and may include a first node N1, a second node N2, a third node N3, and so on.

[0059] The first node N1 of the drive transistor DRT may be the source node or drain node of the drive transistor DT, and may be electrically connected to the pixel electrode PE of the light-emitting element ED.

[0060] The second node N2 of the drive transistor DT may also be the gate node of the drive transistor DT and may be electrically connected to the source node or drain node of the scan transistor SCT.

[0061] The third node N3 of the drive transistor DT may be the drain node or source node of the drive transistor DT and may be electrically connected to the high-potential voltage line VDDL that supplies the high-potential power supply voltage EVDD.

[0062] On the other hand, the drive transistor DT may have intrinsic characteristic values ​​such as threshold voltage and mobility. When the intrinsic characteristic values ​​of the drive transistor DT change, the current driving capability (current supply performance) of the drive transistor DT changes, which in turn can change the light emission characteristics of the subpixel SP.

[0063] The device characteristics of the drive transistor DT (e.g., threshold voltage, mobility, etc.) may change as the driving time of the drive transistor DT elapses. Furthermore, if the drive transistor DT is irradiated with light, especially if the channel region of the drive transistor DT is irradiated with light, the device characteristics of the drive transistor DRT (e.g., threshold voltage, mobility, etc.) may also change.

[0064] Therefore, as shown in Figure 2, a shield pattern LS can be formed near the drive transistor DT to reduce changes in the element characteristics of the drive transistor DT (e.g., changes in threshold voltage, changes in mobility, etc.). For example, the shield pattern LS can be formed below the active layer of the drive transistor DT.

[0065] In addition to its light-shielding function, the shield pattern LS is formed below the channel region of the drive transistor DT and can function as the body of the drive transistor DT.

[0066] As a result, the shield pattern LS can shield the drive transistor DT from light, and for example, if the display panel 110 has a lower light-emitting structure, it can reduce the reflection of external light. Also, if the shield pattern LS is electrically connected to the first node N1 of the drive transistor DT, it can affect the electric field in the channel region of the drive transistor DT.

[0067] The scan transistor SCT is controlled by a scan gate signal SCAN, which is a type of gate signal, and may be connected between the second node N2 of the drive transistor DT and the data line DL.

[0068] In other words, the scan transistor SCT can be turned on or off according to the scan gate signal SCAN supplied via the scan gate line SCL, which is a type of gate line GL, and can control the connection between the data line DL and the second node N2 of the drive transistor DT.

[0069] The scan transistor SCT is turned on by a scan gate signal SCAN having a turn-on level voltage, and can transmit the data voltage VDATA supplied from the data line DL to the second node N2 of the drive transistor DT.

[0070] Here, if the scan transistor SCT is an n-type transistor, the turn-on level voltage of the scan gate signal SCAN may be a high-level voltage. If the scan transistor SCT is a p-type transistor, the turn-on level voltage of the scan gate signal SCAN may be a low-level voltage.

[0071] A storage capacitor Cst may be connected between the second node N2 and the first node N1 of the drive transistor DT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference across its terminals and plays a role in maintaining the voltage difference across its terminals for a predetermined frame time. Therefore, the subpixel SP can emit light for a predetermined frame time.

[0072] Referring to Figures 2 and 3, the subpixel SP according to the embodiment of the present disclosure includes a light-emitting region (i.e., an aperture; EA) where a light-emitting element ED is located, and a subpixel circuit section SPC where a drive transistor DT and a scan transistor SCT are located, wherein the subpixel circuit section SPC may include a scan transistor region SCTA where a scan transistor SCT is located, and a drive transistor region DTA where a drive transistor DT is located.

[0073] The first electrode E1, second electrode E2, and third electrode E3 of the drive transistor DT may be located in the drive transistor region DTA.

[0074] For example, the first electrode E1 may be the source or drain electrode of the drive transistor DT, the second electrode E2 may be the gate electrode of the drive transistor DT, and the third electrode E3 may be the drain or source electrode of the drive transistor DT.

[0075] Referring to Figure 3, the third electrode E3 located in the drive transistor region DTA can be superimposed on the high-potential voltage line VDDL, and the third electrode E3 can be electrically connected to the high-potential voltage line VDDL at the position where it is superimposed on the high-potential voltage line VDDL.

[0076] In other words, the third electrode E3 can be positioned on the high-potential voltage line VDDL and electrically connected to the high-potential voltage line VDDL.

[0077] Referring to Figures 2 and 3, the light-emitting element ED located in the light-emitting region EA includes a pixel electrode PE, a light-emitting layer EL, and a common electrode CE, where the pixel electrode PE extends from the light-emitting region EA toward the drive transistor region DTA and may overlap with the first electrode E1 and the second electrode E2 of the drive transistor DT.

[0078] On the other hand, the drive transistor region DTA can form a superimposed structure of openings where the openings of the protective layer and the gate insulating film overlap, thereby simplifying the structure of the subpixel circuit section SPC and reducing the size of the subpixel circuit section SPC.

[0079] The superimposed structure of the aperture applied to the subpixel circuit section SPC will be specifically explained in the following embodiments shown in Figures 5 to 10.

[0080] For reference, Figures 5 and 6 illustrate one embodiment of the subpixel SP, Figures 7 and 8 illustrate another embodiment of the subpixel SP, and Figures 9 and 10 illustrate yet another embodiment of the subpixel SP.

[0081] However, the embodiments of this disclosure are not limited thereto, and the configurations described below with reference to Figures 5 to 10 may be applied as a single embodiment of the subpixel SP.

[0082] Figure 4 is a diagram illustrating another example of a subpixel SP of the display device 100 according to an embodiment of the present disclosure.

[0083] Specifically, Figure 4 shows another example of the equivalent circuit of a subpixel SP according to an embodiment of the present disclosure.

[0084] Referring to Figure 4, each of the multiple subpixels SP arranged on the display panel 110 of the display device 100 may further include a sensing transistor SENT.

[0085] The sensing transistor SENT may be controlled by a sensing gate signal SENSE, which is a type of gate signal, and may be connected between the first node N1 of the driving transistor DRT and the reference voltage line RVL. That is, the sensing transistor SENT may be turned on or turned off in response to the sensing gate signal SENSE supplied from the sensing gate line SENL, which is another type of gate line GL, and may control the connection between the reference voltage line RVL and the first node N1 of the driving transistor DT.

[0086] The sensing transistor SENT is turned on by a sensing gate signal SENSE having a turn-on level voltage, and can transmit a reference voltage Vref supplied from a reference voltage line RVL to the first node N1 of the driving transistor DRT.

[0087] Furthermore, the sensing transistor SENT is turned on by a sensing gate signal SENSE having a turn-on level voltage, and can transmit the voltage at the first node N1 of the driving transistor DT to the reference voltage line RVL.

[0088] Here, if the sensing transistor SENT is an n-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the turn-on level voltage of the sensing gate signal SENSE may be a low-level voltage.

[0089] The function of the sensing transistor SENT in transmitting the voltage at the first node N1 of the driving transistor DT to the reference voltage line RVL can be used for driving to sense the characteristic value of the subpixel SP. In this case, the voltage transmitted to the reference voltage line RVL may be a voltage used to calculate the characteristic value of the subpixel SP, or a voltage that reflects the characteristic value of the subpixel SP.

[0090] Each of the drive transistor DT, scan transistor SCT, and sensing transistor SENT may be an n-type transistor or a p-type transistor. In the embodiments of this disclosure, for convenience of explanation, it is illustrated that each of the drive transistor DT, scan transistor SCT, and sensing transistor SENT is an n-type transistor.

[0091] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DT, rather than an internal capacitor Cgs located between the gate node and source node of the drive transistor DT, or an internal capacitor Cgd located between the gate node and drain node of the drive transistor DT.

[0092] The scan gate line SCL and the sensing gate line SENL may be different gate lines GL. In this case, the scan gate signal SCAN and the sensing gate signal SENSE may be separate gate signals, and the on / off timing of the scan transistor SCT and the sensing transistor SENT within a single subpixel SP may be independent. That is, the on / off timing of the scan transistor SCT and the sensing transistor SENT within a single subpixel SP may be the same or different.

[0093] In contrast, the scan gate line SCL and the sensing gate line SENL may be the same gate line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT within one subpixel SP may be connected to the same gate line GL. In this case, the scan gate signal SCAN and the sensing gate signal SENSE may be the same gate signal, and the on / off timing of the scan transistor SCT within one subpixel SP and the on / off timing of the sensing transistor SENT within one subpixel SP may be the same.

[0094] The subpixel SP structures shown in Figures 2 and 4 are examples and can be modified in various ways to further include one or more transistors or one or more capacitors.

[0095] Figures 5 and 6 illustrate one embodiment of a subpixel SP according to the embodiments of this disclosure.

[0096] Specifically, Figure 5 shows a plan view of one embodiment of the drive transistor region DTA provided in the subpixel SP, and Figure 6 shows a cross-sectional view of the drive transistor region DTA along the line A-A' shown in the plan view of Figure 5.

[0097] Referring to Figures 5 and 6, the subpixel SP according to the embodiment of the present disclosure may include a substrate 610, a shield pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the shield pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0098] A subpixel SP may include a gate insulating film 640 disposed on an active layer ACT, a first electrode E1 and a second electrode E2 disposed superimposed on at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1 and the second electrode E2, and a pixel electrode EP of a light-emitting element ED disposed on the protective layer 630.

[0099] The subpixel SP may further include an overcoat layer 650 placed on the protective layer 630.

[0100] The active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH.

[0101] The active layer (ACT) can be implemented as a single layer structure, in which case the active layer (ACT) may include at least one material from IGZO (Indium Gallium Zinc Oxide) and IZO (Indium Zinc Oxide), but the embodiments of this disclosure are not limited thereto.

[0102] The subpixel SP may further include an auxiliary electrode positioned between the active layer ACT and the first electrode E1, the auxiliary electrode may include a transparent conductive oxide.

[0103] For example, transparent conductive oxides may include at least one of the following: IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), IGZO (Indium-Gallium-Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ATO (Antimony Tin Oxide), and FTO (Flourine-doped Transparent Oxides).

[0104] As an example, when an auxiliary electrode is placed between the active layer ACT and the first electrode E1, either the active layer ACT or the auxiliary electrode may contain IGZO (Indium Gallium Zinc Oxide) material, and the other may contain IZO (Indium Zinc Oxide) material, but the embodiments of this disclosure are not limited thereto.

[0105] The active layer ACT may be an active layer (i.e., MACT) in which at least a portion of the region is conductive when no auxiliary electrodes are provided. For example, the active layer ACT may be conductive in at least a portion of the remaining region excluding the region overlapping with the channel region CH, but embodiments of the present disclosure are not limited thereto. The gate insulating film 640 includes a first opening H1, and the first electrode E1 may be electrically connected to at least a portion of the first region CT1 of the active layer ACT at the first opening H1.

[0106] In other words, the first opening H1 of the gate insulating film 640 may include a second connection portion CA2 to which the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected.

[0107] The first electrode E1 may be positioned to be electrically connected to the first region CT1 and to overlap with a portion of the gate insulating film 640.

[0108] For example, the first electrode E1 may be the source electrode or drain electrode of the drive transistor DT.

[0109] The second electrode E2 is positioned on the gate insulating film 640 and may be superimposed on the channel region CH.

[0110] For example, the second electrode E2 may be the gate electrode of the drive transistor DT.

[0111] The protective layer 630 may include a second opening H2 that overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0112] The pixel electrode PE may be electrically connected to the first electrode E1 through the second aperture H2, or it may be electrically connected to the shield pattern LS through the second aperture H2.

[0113] In other words, the second opening H2 may include a first connection part CA1 to which the pixel electrode PE and the first electrode E1 are electrically connected, and a third connection part CA3 to which the pixel electrode PE and the shield pattern LS are electrically connected.

[0114] In other words, at a single opening in the protective layer 630, i.e., the second opening H2, the pixel electrode PE may be electrically connected simultaneously with the first electrode E1 and the shield pattern LS.

[0115] As at least a portion of the first opening H1 and at least a portion of the second opening H2 overlap, at least a portion of the first connecting portion CA1 and at least a portion of the second connecting portion CA2 may overlap with each other.

[0116] The pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS can be electrically connected to each other via the first connection part CA1, the second connection part CA2, and the third connection part CA3 to form a single node, i.e., the first node N1.

[0117] For example, the node comprising the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may be the source node of the drive transistor DT, but the embodiments of this disclosure are not limited thereto.

[0118] The second aperture H2 may not be superimposed on the storage capacitor Cst located in each of the multiple subpixels SP, and the node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may not be superimposed on the storage capacitor Cst.

[0119] Referring to Figures 5 and 6, the storage capacitor Cst can overlap with the channel region CH. In other words, the storage capacitor Cst located in the subpixel SP can overlap with the gate node of the drive transistor DT, i.e., the second node N2.

[0120] The second electrode E2 is one of several capacitor electrodes that make up the storage capacitor Cst, and the pixel electrode PE may be one of several capacitor electrodes that make up the storage capacitor Cst.

[0121] Specifically, the storage capacitor Cst may include a second electrode E2 as the first capacitor electrode, a pixel electrode PE adjacent to the second electrode E2 as the second capacitor electrode, and a protective layer 630 provided between the first capacitor electrode and the second capacitor electrode as the insulator of the storage capacitor Cst.

[0122] Referring to Figures 5 and 6, the active layer ACT includes a first connection part CA1 provided in the second opening H2 and a peripheral region of the second connection part CA2 provided in the first opening H1, and the current path (C / P) in the active layer ACT may be formed in the peripheral region.

[0123] In other words, the embodiments of the present disclosure do not directly connect the vertically superimposed pixel electrodes PE and the active layer ACT, but connect them via a first electrode E1, thereby forming a current path C / P of the active layer ACT around the first opening H1 and the second opening H2. This reduces the size of the subpixel circuit section SPC and prevents drive failures caused by high contact resistance that occur when the pixel electrodes PE and the active layer ACT are directly connected.

[0124] Referring to Figure 5, the second electrode E2, which overlaps with the channel region CH of the active layer ACT, extends to a region that does not overlap with the active layer ACT and can be electrically connected to the source electrode or drain electrode ACT_SC of the scan transistor SCT. For convenience of explanation, the drawing reference numeral "ACT_SC" may be used to indicate the source electrode of the scan transistor SCT.

[0125] The subpixel SP in Figure 5 may further include a third electrode E3 that overlaps the high-potential voltage line VDDL and the second region CT2 of the active layer ACT, extending to the region where the high-potential voltage line VDDL is formed.

[0126] In other words, the third electrode E3 can be electrically connected to at least a portion of the high-potential voltage line VDDL and at least a portion of the second region CT2 of the active layer ACT, thereby allowing the high-potential power supply voltage EVDD to be applied to the second region CT2 via the high-potential voltage line VDDL.

[0127] For example, the third electrode E3 may be the drain electrode or source electrode of the drive transistor.

[0128] If an auxiliary electrode is placed between the active layer ACT and the first electrode E1, an auxiliary electrode may also be placed between the active layer ACT and the third electrode E3.

[0129] As shown in the example in Figure 5, the high-voltage line VDDL and the data line DL can be formed from the same material as the shield pattern LS.

[0130] Furthermore, the scan gate line SCL and the first electrode E1, second electrode E2, and third electrode E3 of the drive transistor DT can be formed from the same material.

[0131] Furthermore, the active layer ACT of the drive transistor DT and the source electrode ACT_SC of the scan transistor SCT may be formed from the same material.

[0132] Figures 7 and 8 illustrate another embodiment of the subpixel SP according to the embodiments of the present disclosure.

[0133] Specifically, Figure 7 is a plan view of another embodiment of the drive transistor region DTA provided in the subpixel SP, showing an enlarged view of the first electrode E1 and second electrode D2 of the drive transistor DT compared to Figure 5, and Figure 8 shows a cross-sectional view of the drive transistor region DTA along the line B-B' shown in the plan view of Figure 7.

[0134] Referring to Figures 7 and 8, a subpixel SP according to an embodiment of the present disclosure may include a substrate 610, a shield pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the shield pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0135] Furthermore, the subpixel SP may include a gate insulating film 640 disposed on the active layer ACT and having a first opening H1, a first electrode E1 disposed superimposed on at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1, and a pixel electrode PE of a light-emitting element ED disposed on the protective layer 630.

[0136] The subpixel SP may further include an overcoat layer 650 placed on the protective layer 630.

[0137] The subpixel SP may further include an auxiliary electrode 800 positioned between the active layer ACT and the first electrode E1, the auxiliary electrode 800 may include a transparent conductive oxide.

[0138] For example, transparent conductive oxides may include at least one of the following: IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), IGZO (Indium-Gallium-Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ATO (Antimony Tin Oxide), and FTO (Flourine-doped Transparent Oxides).

[0139] In one example, either the active layer ACT or the auxiliary electrode may include IGZO (Indium Gallium Zinc Oxide) material, and the other may include IZO (Indium Zinc Oxide) material, but embodiments of the present disclosure are not limited thereto.

[0140] The active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH.

[0141] The first electrode E1 may be electrically connected to at least a portion of the first region CT1 of the active layer ACT at the first opening H1. In other words, the first electrode E1 may be electrically connected to the auxiliary electrode 800 and the active layer ACT at the first opening H1.

[0142] In other words, the first opening H1 of the gate insulating film 640 may include a second connection portion CA2 to which the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected.

[0143] For example, the first electrode E1 may be the source electrode or drain electrode of the drive transistor DT.

[0144] The protective layer 630 is positioned on the first electrode E1 and may include a second opening H2 that overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0145] The pixel electrode PE can be electrically connected to the first electrode E1 through the second aperture H2, and can also be electrically connected to the shield pattern LS through the second aperture H2.

[0146] In other words, the second opening H2 may include a first connection part CA1 to which the pixel electrode PE and the first electrode E1 are electrically connected, and a third connection part CA3 to which the pixel electrode PE and the shield pattern LS are electrically connected.

[0147] In other words, at a single opening in the protective layer 630, namely the second opening H2, the pixel electrode PE can be electrically connected simultaneously with the first electrode E1 and the shield pattern LS.

[0148] The pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS can be electrically connected to each other via the first connection part CA1, the second connection part CA2, and the third connection part CA3 to form a single node, i.e., the first node N1.

[0149] For example, the node comprising the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may be the source node of the drive transistor DT, but the embodiments of this disclosure are not limited thereto.

[0150] The node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may not be superimposed on the storage capacitor Cst located in each of the multiple subpixels SP formed on the substrate.

[0151] According to one embodiment, the first electrode E1 is omitted, and the pixel electrode PE can directly contact the first region CT1 of the active layer ACT. The omission of the first electrode E1 can also be implemented in later embodiments. According to one embodiment, the layer used to form the pixel electrode PE can be patterned to form an electrode that directly contacts the third region CT3 of the active layer ACT.

[0152] Referring to Figure 7, the storage capacitor Cst may be superimposed on the channel region CH, i.e., the second node N2 which is the gate node of the drive transistor DT.

[0153] Referring to Figures 7 and 8, the current path C / P of the active layer ACT may be formed in the region passing through the second connection CT2, which is electrically connected to the first electrode CT and the first region CT1 of the active layer ACT.

[0154] In other words, the embodiments of the present disclosure do not directly connect the vertically superimposed pixel electrode PE and the active layer ACT, but connect them to each other via the first electrode E1 and the auxiliary electrode 800, thereby forming a current path C / P of the active layer ACT in the lower region of the first electrode E1. This reduces the size of the subpixel circuit section SPC and prevents drive failures caused by high contact resistance that occur when the pixel electrode PE and the active layer ACT are directly connected.

[0155] Some regions of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may not be superimposed on the shield pattern LS, and in the regions not superimposed on the shield pattern LS, each of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may have steps.

[0156] In other words, the subpixel SP according to the embodiments of the present disclosure can be implemented in a PAD-free structure in which the shield pattern LS is not located below at least a portion of the area of ​​the second connection portion CA2.

[0157] Figures 9 and 10 illustrate yet another embodiment of the subpixel SP according to the embodiments of the present disclosure.

[0158] Specifically, Figure 9 is a plan view of yet another embodiment of the drive transistor region DTA provided in the subpixel SP, and is shown as a reversed version of the plan view in Figure 7, while Figure 10 shows a cross-sectional view of the drive transistor region DTA along the C-C' line shown in the plan view of Figure 9.

[0159] Referring to Figures 9 and 10, a subpixel SP according to an embodiment of the present disclosure may include a substrate 610, a shield pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the shield pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0160] Furthermore, the subpixel SP may include a gate insulating film 640 disposed on the active layer ACT, a first electrode E1 and a second electrode E2 disposed superimposed on at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1 and the second electrode E2, and a pixel electrode PE of the light-emitting element ED disposed on the protective layer 630.

[0161] The subpixel SP may further include an overcoat layer 650 positioned on the protective layer 630.

[0162] The subpixel SP may further include an auxiliary electrode 800 positioned between the active layer ACT and the first electrode E1, the auxiliary electrode 800 may include a transparent conductive oxide.

[0163] For example, transparent conductive oxides may include at least one of the following: IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), IGZO (Indium-Gallium-Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ATO (Antimony Tin Oxide), and FTO (Flourine-doped Transparent Oxides).

[0164] In one example, the auxiliary electrode may include IGZO (Indium Gallium Zinc Oxide) material and the active layer ACT may include IZO (Indium Zinc Oxide) material, but embodiments of this disclosure are not limited thereto.

[0165] The active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH.

[0166] The gate insulating film 640 includes a first opening H1, and the first electrode E1 is electrically connected to the first region CT1 at the first opening H1 and can be electrically connected to the shield pattern LS.

[0167] In other words, the first opening H1 of the gate insulating film 640 may include a second connection part CA2 to which the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected, and a fourth connection part CA4 to which the first electrode E1 is electrically connected to the shield pattern LS.

[0168] The first electrode E1 is positioned to be electrically connected to the first region CT1, but may also be positioned to overlap with a portion of the gate insulating film 640.

[0169] For example, the first electrode E1 may be the source electrode or drain electrode of the drive transistor DT.

[0170] Referring to Figures 9 and 10, the second electrode E2 is positioned on the gate insulating film 640 superimposed on the channel region CH, where the second electrode E2 may extend to a region not superimposed on the active layer ACT.

[0171] For example, the second electrode E2 may be the gate electrode of the drive transistor DT.

[0172] The protective layer 630 may include a second opening H2 that overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0173] The pixel electrode PE can be electrically connected to the first electrode E1 at the second aperture H2.

[0174] That is, the second opening H2 may include a first connection part CA1 to which the pixel electrode PE and the first electrode E1 are electrically connected, and the second opening H2 may further include a second connection part CA2 and a fourth connection part CA4.

[0175] In other words, at a single opening in the protective layer 630, namely the second opening H2, the pixel electrode PE can be electrically connected simultaneously with the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS.

[0176] As at least a portion of the first opening H1 and at least a portion of the second opening H2 overlap, at least a portion of the first connecting portion CA1 and at least a portion of the second connecting portion CA2 overlap each other, and at least a portion of the first connecting portion CA1 and at least a portion of the fourth connecting portion CA4 may overlap each other.

[0177] The pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS can be electrically connected to each other via the first connection part CA1, the second connection part CA2, and the fourth connection part CA4 to form a single node, i.e., the first node N1.

[0178] For example, the node comprising the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may be the source node of the drive transistor DT, but the embodiments of this disclosure are not limited thereto.

[0179] The node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the shield pattern LS may not be superimposed on the storage capacitor Cst located in each of the multiple subpixels SP.

[0180] The storage capacitor Cst may overlap with the channel region CH. In other words, the storage capacitor Cst located in the subpixel SP may overlap with the gate node of the drive transistor DT, i.e., the second node N2.

[0181] The second electrode E2 is one of several capacitor electrodes that make up the storage capacitor Cst, and the pixel electrode PE may be one of several capacitor electrodes that make up the storage capacitor Cst.

[0182] For example, the storage capacitor Cst may include a second electrode E2 as the first capacitor electrode, a pixel electrode PE adjacent to the second electrode E2 as the second capacitor electrode, and at least a portion of the protective layer 630 provided between the first capacitor electrode and the second capacitor electrode may be included as an insulator for the storage capacitor Cst.

[0183] Referring to Figures 9 and 10, the current path C / P of the active layer ACT may be formed in the region passing through the second connection CT2, which is electrically connected to the first electrode CT and the first region CT1 of the active layer ACT.

[0184] In other words, the embodiments of the present disclosure do not directly connect the vertically superimposed pixel electrode PE and the active layer ACT, but connect them to each other via the first electrode E1 and the auxiliary electrode 800, thereby forming a current path C / P of the active layer ACT in the lower region of the first electrode E1. This reduces the size of the subpixel circuit section SPC and prevents drive failures caused by high contact resistance that occur when the pixel electrode PE and the active layer ACT are directly connected.

[0185] Some regions of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may not be superimposed on the shield pattern LS, and in the regions not superimposed on the shield pattern LS, each of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may have steps. In other words, the subpixel SP according to the embodiments of the present disclosure can be implemented in a PAD-free structure in which at least a portion of the second connection portion CA2 does not have a shield pattern LS positioned below it.

[0186] The embodiments of this disclosure described above can be briefly explained as follows.

[0187] A display device according to an embodiment of the present disclosure may include a substrate; an active layer disposed on the substrate and including a channel region, a first region located on one side of the channel region, and a second region located on the other side of the channel region; a gate insulating film disposed on the active layer and having a first opening; a first electrode electrically connected to at least a portion of the first region at the first opening; a second electrode disposed on the gate insulating film and overlapping with the channel region; a protective layer disposed on the first electrode and the second electrode and having a second opening that overlaps at least a portion of the first electrode and at least a portion of the first opening; and a pixel electrode disposed on the protective layer and electrically connected to the first electrode at the second opening.

[0188] The display device may further include a shield pattern disposed on a substrate and a buffer layer disposed on the substrate and the shield pattern.

[0189] The shielding pattern can be electrically connected to the pixel electrodes at the second aperture.

[0190] The pixel electrodes, the first electrode, the active layer, and the shielding pattern can be electrically connected to each other.

[0191] The display device further includes a storage capacitor disposed on a substrate and containing multiple capacitor electrodes, the storage capacitor not necessarily having to overlap with the second opening.

[0192] One of the multiple capacitor electrodes may be the second electrode, and another of the multiple capacitor electrodes may be the pixel electrode.

[0193] The second electrode may extend into a region that does not overlap with the channel region.

[0194] The active layer includes a first connection portion to which the pixel electrode and the first electrode are electrically connected, and a peripheral region of the second connection portion to which the first electrode and the first region are electrically connected, and the current path in the active layer may be formed in the peripheral region.

[0195] The display device further includes an auxiliary electrode disposed between the active layer and the first electrode, the auxiliary electrode may include a transparent conductive oxide.

[0196] A current path in the active layer may be formed in a region passing through a second connection point where the first electrode and the first region are electrically connected.

[0197] The first electrode can be electrically connected to the shield pattern at the second opening.

[0198] At least a portion of the second connection portion, to which the first electrode and the first region are electrically connected, does not need to be superimposed on the shielding pattern.

[0199] The display device further includes a light-emitting element and a drive transistor for driving the light-emitting element, wherein the first electrode is the source electrode or drain electrode of the drive transistor, and the second electrode is the gate electrode of the drive transistor, and the first electrode and the second electrode may be formed from the same material.

[0200] The display device may further include a high-potential voltage line to which a high-potential voltage is applied, and a third electrode electrically connected between a second region and the high-potential voltage line.

[0201] The first electrode, the second electrode, and the third electrode may contain the same material.

[0202] A display device according to an embodiment of the present disclosure may include a substrate, a drive transistor disposed on the substrate and including an active layer, a first electrode, a second electrode, and a third electrode, a light-emitting element including a pixel electrode electrically connected to the first electrode and a common electrode facing the pixel electrode, and a storage capacitor disposed on the drive transistor and overlapping the channel region of the active layer of the drive transistor.

[0203] The display device may further include a gate insulating film disposed on an active layer and having a first opening; a protective layer disposed on a first electrode and a second electrode and having a second opening that overlaps with at least a portion of the first electrode and at least a portion of the first opening; a first electrode disposed on the protective layer and electrically connected to at least a portion of the active layer at the first opening; and a pixel electrode connected at the second opening.

[0204] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments shown in this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and therefore the scope of the technical concept of this disclosure is not limited by these embodiments. [Explanation of Symbols]

[0205] 610 circuit board 620 buffer layers 630 protective layer 640 Gate Insulator 650 Overcoat Layer ACT Active Layer CH Channel Area CT1 First region CT2 Second Region PE pixel electrode LS Shield Pattern E1 First electrode E2 Second electrode Cst Storage Capacitor H1 First opening H2 Second opening CA1 First connection part CA2 Second connection point CA3 Third connection point

Claims

1. circuit board and The active layer of a transistor is disposed on the substrate and includes a channel region, a first region located on one side of the channel region, and a second region located on the other side of the channel region. A gate insulating film having a first opening is disposed on the active layer, A first electrode is electrically connected to at least a portion of the first region at the first opening, A second electrode is disposed on the gate insulating film and overlaps with the channel region, A protective layer disposed on the first electrode and the second electrode, having a second opening that overlaps with at least a portion of the first electrode and at least a portion of the first opening, A display device comprising a pixel electrode disposed on the protective layer and electrically connected to the first electrode at the second opening.

2. A shield pattern placed on the substrate, The display device according to claim 1, further comprising the substrate and a buffer layer disposed on the shield pattern.

3. The display device according to claim 2, wherein the shield pattern is electrically connected to the pixel electrode at the second opening.

4. The display device according to claim 2, wherein the pixel electrode, the first electrode, the active layer, and the shield pattern are electrically connected to each other.

5. The storage capacitor, which is disposed on the substrate and includes a plurality of capacitor electrodes, The display device according to claim 1, wherein the storage capacitor does not overlap with the second opening.

6. The display device according to claim 5, wherein one of the plurality of capacitor electrodes is the second electrode.

7. The display device according to claim 5, wherein one of the plurality of capacitor electrodes is the pixel electrode.

8. The display device according to claim 5, wherein the second electrode extends to a region that does not overlap with the channel region.

9. The active layer includes a first connection portion to which the pixel electrode and the first electrode are electrically connected, and a peripheral region of the second connection portion to which the first electrode and the first region are electrically connected. The display device according to claim 1, wherein the current path in the active layer is formed in the peripheral region.

10. The system further includes an auxiliary electrode disposed between the active layer and the first electrode, The display device according to claim 1, wherein the auxiliary electrode comprises a transparent conductive oxide.

11. The display device according to claim 10, wherein the current path in the active layer is formed in a region passing through a second connection portion where the first electrode and the first region are electrically connected.

12. The display device according to claim 2, wherein the first electrode is electrically connected to the shield pattern at the second opening.

13. The display device according to claim 2, wherein the first electrode is electrically connected to the first region at a second connection portion, and at least a portion of the second connection portion to which the first electrode and the first region are electrically connected does not overlap with the shield pattern.

14. The aforementioned transistor is a drive transistor for driving a light-emitting element, The display device according to claim 1, wherein the first electrode is the source electrode or drain electrode of the drive transistor, the second electrode is the gate electrode of the drive transistor, and the first electrode and the second electrode are formed of the same material.

15. A high-potential voltage line to which a high potential voltage is applied, The display device according to claim 1, further comprising a third electrode electrically connected between the second region and the high-potential voltage line.

16. The display device according to claim 15, wherein the first electrode, the second electrode, and the third electrode are made of the same material.

17. circuit board and A drive transistor is disposed on the substrate and includes an active layer, a first electrode, a second electrode, and a third electrode. A light-emitting element including a pixel electrode electrically connected to the first electrode and a common electrode facing the pixel electrode, A display device comprising a storage capacitor disposed on the drive transistor and overlapping the channel region of the active layer of the drive transistor.

18. A gate insulating film having a first opening is disposed on the active layer, A protective layer disposed on the first electrode and the second electrode, having a second opening that overlaps with at least a portion of the first electrode and at least a portion of the first opening, The display device according to claim 17, further comprising a first electrode disposed on the protective layer and electrically connected to at least a portion of the active layer at a first opening, and a pixel electrode connected at a second opening.

19. circuit board and A light-shielding pattern arranged on the substrate, The active layer of a transistor includes a channel region that overlaps with the light-shielding pattern on a plan view, a first region located on one side of the channel region, and a second region located on the other side of the channel region. A first electrode electrically connected to the first region, a second electrode overlapping the channel region, a third electrode electrically connected to the second region, The device includes a light-emitting element in which a common electrode is electrically connected to a first power supply voltage line, and a light-emitting layer is located between the common electrode and the pixel electrode. The pixel electrode includes an integrated portion that superimposes with the second electrode to form a storage capacitor, and is in direct contact with the first electrode, superimposed with the common electrode and the light-emitting layer in a plan view, in a display device.

20. An insulating film located between the light-shielding pattern and the channel region, A gate insulating film, located between the second electrode and the active layer, includes a first opening, The display device according to claim 19, further comprising an insulating layer located between the pixel electrode and the second electrode, and including a second opening that overlaps with the first opening in a plan view.

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