Memory device and its operating method

Abstract

To improve the threshold voltage distribution of memory cells. [Solution] The memory device 100 includes a memory cell MC; a peripheral circuit 180 that executes a program operation of the memory cell, verifies the memory cell according to a target voltage Vt and a pre-target voltage Vp lower than the target voltage Vt, and applies a voltage to the bit line connected to the memory cell; and a control circuit 170 that controls the peripheral circuit 180. The control circuit 170 determines, according to the verification result of the memory cell, that the memory cell MC is a program initial cell MCi, a program adjacent cell MCa, or a program completed cell MCc, and controls and adjusts the timing at which the bit line voltage is applied to the bit line connected to the cells MCi, MCa, and MCc. The control circuit 170 controls the peripheral circuit 180 to adjust the timing of the bit line voltage applied to the bit line connected to the program adjacent cell MCa, according to the number of at least one of the cells MCi, MCa, and MCc.

Description

Technical Field

[0001] The present invention relates to a memory device and an operation method thereof, and more specifically, to a memory device configured to execute a program operation and an operation method thereof.

Background Art

[0002] A memory device can include a memory cell array in which data is stored and a peripheral circuit configured to execute a program operation, a read operation, or an erase operation.

[0003] The memory cell array can include memory blocks. Each of the memory blocks can include a plurality of memory cells. Since the memory cells have different electrical characteristics from each other, the time when the memory cells are programmed can be different from each other.

[0004] The peripheral circuit can include a control circuit that controls the operation of the memory device in response to a command transmitted from an external controller, and a circuit configured to execute a program operation, an erase operation, or a read operation in response to the control of the control circuit.

[0005] During the program operation of the selected memory block, due to the program speed difference of the memory cells included in the selected memory block, the threshold voltage distribution of the memory cells can become wider. For example, when a program voltage is applied to the selected word line, the threshold voltage of the memory cells connected to the selected word line can be increased by the program voltage. At this time, the threshold voltage of the memory cells with a relatively fast program speed can be higher than the threshold voltage of the memory cells with a relatively slow program speed, thereby causing the threshold voltage distribution to become wider.

[0006] The wider the threshold voltage distribution, the greater the number of error bits generated during read operations, which can reduce the reliability of the memory device. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] Embodiments of the present invention provide a memory device capable of improving the threshold voltage distribution of memory cells and a method for operating the same. [Means for solving the problem]

[0008] A memory device according to an embodiment of the present invention includes: a memory cell; a peripheral circuit configured to execute a program operation of the memory cell, verify the memory cell according to a target voltage and a pre-target voltage lower than the target voltage, and apply a voltage to a bit line connected to the memory cell; and a control circuit configured to control the peripheral circuit, wherein the control circuit determines the memory cell to be a program initial cell, a program adjacent cell, or a program completion cell according to the verification result of the memory cell, controls and adjusts the timing at which a bit line voltage is applied to the bit lines connected to the program initial cell, the program adjacent cell, and the program completion cell, and controls the peripheral circuit to adjust the timing of the bit line voltage applied to the bit line connected to the program adjacent cell according to the number of at least one of the program initial cell, the program adjacent cell, and the program completion cell.

[0009] The operation method of a memory device according to an embodiment of the present invention includes the steps of: dividing the memory cell into a program initial cell, a program adjacent cell, or a program completed cell according to the verification result of the memory cell during program operation; applying a program allowable voltage to a first bit line corresponding to the program initial cell, selectively applying a second program prohibition voltage and the program allowable voltage to a second bit line corresponding to the program adjacent cell, and applying a first program prohibition voltage to a third bit line corresponding to the program completed cell; and applying a program voltage to a word line connected to the memory cell, wherein the application time of the second program prohibition voltage applied to the second bit line is adjusted according to the number of program initial cells and program adjacent cells. [Effects of the Invention]

[0010] This technology improves the threshold voltage distribution of memory cells during program operation, thereby improving the reliability of the memory device. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram illustrating a memory device. [Figure 2] This is a diagram illustrating the arrangement of the memory cell array and peripheral circuits. [Figure 3] This is a perspective view illustrating memory blocks. [Figure 4] This is a circuit diagram illustrating a memory block. [Figure 5] This diagram illustrates the state of a memory cell in relation to a threshold voltage. [Figure 6] This diagram illustrates the voltage applied to a selected memory block during program operation according to the present invention. [Figure 7] This is a flowchart illustrating the program operation according to the first embodiment of the present invention. [Figure 8] This figure illustrates the verification operation according to an embodiment of the present invention. [Figure 9a] This is a diagram for explaining the program operation according to the first embodiment of the present invention. [Figure 9b] This is a diagram for explaining the program operation according to the first embodiment of the present invention. [Figure 9c] This is a diagram for explaining the program operation according to the first embodiment of the present invention. [Figure 9d] This is a diagram for explaining the program operation according to the first embodiment of the present invention. [Figure 10] This is a flowchart for explaining the program operation according to the second embodiment of the present invention. [Figure 11a] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 11b] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 11c] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 12a] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 12b] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 12c] This is a diagram for explaining the program operation according to the second embodiment of the present invention. [Figure 13a] This is a diagram for explaining the continuously increasing threshold voltage of memory cells during the program operation according to the present invention. [Figure 13b] This is a diagram for explaining the continuously increasing threshold voltage of memory cells during the program operation according to the present invention. [Figure 13c] This is a diagram for explaining the continuously increasing threshold voltage of memory cells during the program operation according to the present invention. [Figure 13d] This is a diagram for explaining the continuously increasing threshold voltage of memory cells during the program operation according to the present invention. ]> [Figure 14] This is a diagram for explaining the memory card system to which the memory device according to the embodiment of the present invention is applied. [Figure 15] This is a diagram for explaining an SSD (Solid State Drive) system to which a memory device according to an embodiment of the present invention is applied.

Embodiment for Carrying Out the Invention

[0012] The specific structural or functional descriptions disclosed below are exemplified for explaining embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention should not be construed as being limited to the embodiments described below, and can be variously modified and replaced with other equivalent embodiments.

[0013] Hereinafter, terms such as first and second can be used to explain various components, but the above components are not limited by the above terms. The above terms are used for the purpose of distinguishing one component from another.

[0014] FIG. 1 is a diagram for explaining a memory device.

[0015] Referring to FIG. 1, the memory device 100 can include a memory cell array 110 in which data is stored and a peripheral circuit 180 that executes program, read, or erase operations.

[0016] The memory cell array 110 can include first to jth memory blocks BLK1 to BLKj in which data is stored. Each of the first to jth memory blocks BLK1 to BLKj includes a plurality of memory cells, and the memory cells can be realized in a two-dimensional structure arranged parallel to the substrate or a three-dimensional structure stacked in a direction perpendicular to the substrate. The first to jth memory blocks BLK1 to BLKj according to this embodiment can be realized in a three-dimensional structure. A drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL can be connected to each of the first to jth memory blocks BLK1 to BLKj.

[0017] The peripheral circuitry 180 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0018] The voltage generation unit 120 can generate and output various operating voltages Vop required for different operations in response to the operation code OPCD. For example, the voltage generation unit 120 can generate and output program voltage, verification voltage, read voltage, pass voltage, erase voltage, compensation voltage, etc. In response to the operation code OPCD, the voltage generation unit 120 can adjust the level of each operating voltage Vop and the output time or cutoff time.

[0019] The low decoder 130 can select one memory block from the first to j-th memory blocks BLK1 to BLKj included in the memory cell array 110 according to the low address RADD, and transmit the operating voltage Vop to the selected memory block.

[0020] The page buffer group 140 can be connected to the memory cell array 110 via bit lines BL. For example, the page buffer group 140 may include page buffers (not shown) connected to each bit line BL. The page buffers can operate simultaneously in response to the page buffer control signal PBSIG and can temporarily store data during program or read operations. For this reason, each page buffer may include multiple latches for temporarily storing data. The number of latches can vary depending on the programming scheme. For example, the page buffers can be designed to differ depending on the number of bits that can be stored in a single memory cell, or depending on the number of verification voltages used during verification operations.

[0021] The column decoder 150 can transmit data DATA between the input / output circuit 160 and the page buffer group 140 according to the column address CADD.

[0022] The input / output circuit 160 can be connected to a controller (not shown) via input / output lines IO. The input / output circuit 160 can input and output commands CMD, addresses ADD, and data DATA via input / output lines IO. For example, the input / output circuit 160 can transmit commands CMD and addresses ADD received via input / output lines IO to the control circuit 170, and can transmit data DATA received via input / output lines IO to the column decoder 150. The input / output circuit 160 can output data DATA received from the column decoder 150 to an external device via input / output lines IO.

[0023] The control circuit 170 can be configured to output an operation code OPCD, a low address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the control circuit 170 can consist of software for performing a program, read, or erase operation in response to a command CMD and an address ADD, and hardware for outputting an operation code OPCD, a low address RADD, a page buffer control signal PBSIG, and a column address CADD in accordance with the software's control.

[0024] The control circuit 170 can be configured to perform program operations using either a single-level cell method or a multi-level cell method. The single-level cell method involves programming one bit of data into a single memory cell. When a program operation is performed using the single-level cell method, the memory cell can be either in an erased state or a programmed state. The multi-level cell method involves programming two or more bits of data into a single memory cell. When a program operation is performed using the multi-level cell method, the memory cell can be either in an erased state or one of several programmed states. For example, if three bits of data are programmed into a single memory cell, the memory cell can be either in an erased state or one of seven distinct programmed states.

[0025] Because memory cells have different electrical characteristics, their programming speeds can also differ. For example, memory cells with a relatively fast programming speed become fast cells, while those with a relatively slow programming speed become slow cells. During programming, the threshold voltage of a fast cell can rise faster than the threshold voltage of a slow cell. Therefore, even if the same programming voltage is applied to a fast cell and a slow cell, their threshold voltages can differ. The greater the difference in threshold voltages, the wider the threshold voltage distribution of the memory cell becomes.

[0026] The control circuit 170 in this embodiment can determine a memory cell as a program initial cell, a program adjacent cell, or a program completion cell, depending on the verification results of the memory cell. The control circuit 170 can adjust the voltage applied to the bit lines connected to the program initial cell, the program adjacent cell, and the program completion cell, and can control the peripheral circuit to adjust the time for which the voltage is applied to the bit lines according to the number of program initial cells and program adjacent cells.

[0027] In this embodiment, the control circuit 170 can control the page buffer group 140 so that, in order to narrow the width of the threshold voltage distribution, it determines the state of the memory cell during program operation of the selected memory block and adjusts the voltage applied to the bit line according to the determination result.

[0028] In this embodiment, the control circuit 170 can control the page buffer group 140 so that, during program operation of a selected memory block, the voltage applied to the bit line is adjusted according to the number of incomplete cells where the verification operation failed or the number of pass cells where the verification operation passed, in order to narrow the width of the threshold voltage distribution. For example, the control circuit 170 can compare a preset reference number with the number of incomplete cells and adjust the voltage applied to the bit line according to the result of the comparison. The reference number is a value stored in the control circuit and can be changed by the memory device.

[0029] Figure 2 is a diagram illustrating the arrangement of the memory cell array and peripheral circuits.

[0030] Referring to Figure 2, the memory device 100 may include peripheral circuits 180 and a memory cell array 110. The peripheral circuits 180 may be located on top of a substrate (not shown), and the memory cell array 110 may be located on top of the peripheral circuits 180. The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Bit lines BL may be located on top of the first to j-th memory blocks BLK1 to BLKj, and source lines SL may be located on the bottom of the first to j-th memory blocks BLK1 to BLKj. Unlike in Figure 2, bit lines BL may be located on the bottom of the first to j-th memory blocks BLK1 to BLKj, and source lines SL may be located on top of the first to j-th memory blocks BLK1 to BLKj.

[0031] Multiple bit lines BL can be arranged spaced apart from each other along the X direction and can extend along the Y direction. The first to j-th memory blocks BLK1 to BLKj can be arranged spaced apart from each other along the Y direction. Source lines SL can be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0032] The first through j-th memory blocks, BLK1 to BLKj, can be configured similarly to each other. A detailed description of any one of these memory blocks is as follows:

[0033] Figure 3 is a perspective view illustrating a memory block.

[0034] Referring to Figure 3, a portion of the memory block BLK is shown. The source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL included in the memory block BLK can be stacked spaced apart from each other along the Z direction. The source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL can be formed from the same conductive material. For example, the source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL can be formed from metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si), but are not limited to these.

[0035] A cell plug CPL can penetrate the source selection line SSL, the first to nth word lines WL1 to WLn, and the drain selection line DSL. Each cell plug CPL may include a core pillar CP, a channel layer CH, a tunnel isolation layer TX, a charge trap layer CTL, and a blocking layer BX. The core pillar CP may have a cylindrical, rectangular, or polygonal shape and may be made of an insulating or conductive material. The channel layer CH encloses the surface of the core pillar CP and may be made of polysilicon. The tunnel isolation layer TX encloses the surface of the channel layer CH and may be made of an oxide film. The charge trap layer CTL encloses the surface of the tunnel isolation layer TX and may be made of a nitride film. The blocking layer BX encloses the surface of the charge trap layer CTL and may be made of an oxide film.

[0036] Figure 4 is a circuit diagram illustrating the memory block.

[0037] Referring to Figure 4, the memory block BLK may include cell strings ST located between the source line SL and the first to i-th bit lines BL1 to BLi. The cell strings ST may be arranged spaced apart from each other along the X and Y directions and may extend along the Z direction. The first to i-th bit lines BL1 to BLi may be arranged spaced apart from each other along the X direction, and each of the first to i-th bit lines BL1 to BLi may extend along the Y direction. Each of the cell strings ST may include a source selection transistor SST, first to sixteenth memory cells MC1 to MC16, and a drain selection transistor DST. The first to sixteenth memory cells MC1 to MC16 may be coupled between the source selection transistor SST and the drain selection transistor DST. The number of source selection transistors SST, first to sixteenth memory cells MC1 to MC16, and drain selection transistor DST shown in Figure 4 may vary depending on the memory device.

[0038] The gates of source selection transistors SSTs located in different cell strings ST can be connected to source selection lines SSL, the gates of the first to sixteenth memory cells MC1 to MC16 can be connected to the first to sixteenth word lines WL1 to WL16, and the gate of the drain selection transistor DST can be connected to the drain selection line DSL. The source selection line SSL can be commonly connected to source selection transistors SSTs arranged along the X and Y directions. Alternatively, source selection lines SSL commonly connected to source selection transistors SSTs arranged in the X direction and source selection lines SSL commonly connected to source selection transistors SSTs arranged in the Y direction can be separated from each other. Each of the first to sixteenth word lines WL1 to WL16 can be commonly connected to memory cells arranged along the X and Y directions. For example, the first memory cell MC1 arranged along the X and Y directions can be commonly connected to the first word line WL1, and the second memory cell MC2 arranged along the X and Y directions can be commonly connected to the second word line WL2. A drain selection line DSL can be commonly connected to drain selection transistors DST arranged in the X direction. Different drain selection lines DSL can be connected to drain selection transistors DST arranged along the Y direction.

[0039] A group of memory cells linked to the same word line becomes a page (PG). Program or read operations can be performed on a page (PG) basis. For example, a group of memory cells linked to a selected word line among the memory cells of a cell string ST linked to a selected drain selection line DSL can become a selected page. During a program operation, the selected page is the page consisting of the memory cells to be programmed. In other words, the selected page can be determined by the drain selection line DSL and the word line.

[0040] Since the program operation of the memory block BLK is executed on a page-by-page basis, word lines connected to the selected page become the selected word line Sel_WL, and word lines connected to the remaining pages become the unselected word line Unsel_WL. For example, if the 11th word line WL11 is the selected word line Sel_WL, then the 1st to 10th word lines WL1 to WL10 and the 12th to 16th word lines WL12 to WL16 are the unselected word lines Unsel_WL.

[0041] Figure 5 is a diagram illustrating the state of a memory cell in relation to the threshold voltage.

[0042] Referring to Figure 5, during program operation, the selected memory cell can become one of the following, depending on the threshold voltage: program initial cell (MCi), program adjacent cell (MCa), or program complete cell (MCc). In Figure 5, the horizontal axis represents voltage, and the vertical axis represents the number of memory cells.

[0043] A programmed cell MCc is a cell whose threshold voltage has risen above the target voltage Vt. A programmed adjacent cell MCa is a cell whose threshold voltage is lower than the target voltage Vt but higher than the pre-target voltage Vp. A programmed initial cell MCi is a cell whose threshold voltage is lower than the pre-target voltage Vp.

[0044] The target voltage Vt can be a reference voltage used to determine whether a memory cell has been programmed to a target programmed state. The pre-target voltage Vp can be set to a voltage lower than the target voltage Vt.

[0045] In the programmed operation of a multilevel cell system, the memory cell is programmed into various states, so multiple target voltages Vt can be set. When multiple target voltages Vt are set, multiple pre-target voltages Vp corresponding to the multiple target voltages Vt can be set. When multiple pre-target voltages Vp are set, the pre-target voltages Vp can be set lower than their corresponding target voltages Vt, and higher than the highest threshold voltage in the threshold voltage distribution of states lower than the target voltage Vt.

[0046] In this embodiment, the state of the memory cell can be classified into a program-initial cell MCi, a program-adjacent cell MCa, or a program-completed cell MCc, depending on the threshold voltage of the memory cell. A program-adjacent cell MCa is a memory cell whose threshold voltage is lower than the target voltage Vt but has risen to near the target voltage Vt. Therefore, in this embodiment, the voltage of the bit line corresponding to the program-adjacent cell MCa is adjusted.

[0047] Figure 6 is a diagram illustrating the voltage applied to the selected memory block during program operation according to the present invention.

[0048] Referring to Figure 6, during the programming of memory block BLK, a program voltage Vpgm can be applied to the selected word line Sel_WL, and a path voltage Vpass can be applied to the unselected word line Unsel_WL. The program voltage Vpgm has a level higher than 0V to raise the threshold voltage of the selected memory cell and can be increased in steps while the program operation is being performed. The path voltage Vpass is a voltage for forming a channel in the string and can be set to a level that allows the memory cell connected to the unselected word line Unsel_WL to turn on.

[0049] A ground voltage (GND) can be applied to the source line SL, and a turn-on voltage (Von) can be applied to the source selection line SSL and the drain selection line DSL. The turn-on voltage (Von) can be set to a level that allows the source selection transistor and the drain selection transistor to turn on.

[0050] A voltage selected from among the program-allowable voltage Val, the first program-blocking voltage 1Vin, and the second program-blocking voltage 2Vin can be applied to each of the first to fourth bit lines BL1 to BL4, depending on the state of the memory cell.

[0051] Assume that the sixth word line WL6 is the selected word line Sel_WL, and that among the memory cells connected to the selected word line Sel_WL, the memory cell corresponding to the first bit line BL1 is the program initial cell MCi, the memory cell corresponding to the second bit line BL2 is the program adjacent cell MCa, the memory cell corresponding to the third bit line BL3 is the program completion cell MCc, and the memory cell corresponding to the fourth bit line BL4 is the unselected cell Unsel_MC.

[0052] Since the voltage difference between the threshold voltage and target voltage of the initial program cell MCi is greater than the voltage difference between the threshold voltage and target voltage of the adjacent program cell MCa, the first bit line BL1 corresponding to the initial program cell MCi can be supplied with the lowest program allowable voltage Val, which is the voltage applied to the bit line. The third bit line BL3 corresponding to the completed program cell MCc and the fourth bit line BL4 corresponding to the unselected cell Unsel_MC can be supplied with the highest first program prohibition voltage 1Vin, which is the voltage applied to the bit line during program operation.

[0053] A second bit line BL2, connected to a string containing a program-adjacent cell MCa, can selectively have at least one of the program-allowable voltage Val and the second program-blocking voltage 2Vin applied to it. For example, the program-allowable voltage Val and the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for set durations. For example, the program-allowable voltage Val can be applied to the second bit line BL2 for a set duration, followed by the second program-blocking voltage 2Vin being applied for a set duration. Alternatively, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a set duration, followed by the program-allowable voltage Val being applied for a set duration. The durations for which the program-allowable voltage Val and the second program-blocking voltage 2Vin are applied to the second bit line BL2 are variable.

[0054] During program operation, the speed at which the programmed adjacent cell MCa is programmed can be adjusted by adjusting the time at which the program allowable voltage Val and the second program prohibition voltage 2Vin are applied to the second bit line BL2 connected to the string containing the programmed adjacent cell MCa. Therefore, the speed at which the threshold voltage of the programmed adjacent cell MCa rises can be adjusted, thereby narrowing the width of the threshold voltage distribution of the memory cell.

[0055] Figure 7 is a flowchart illustrating the program operation according to the first embodiment of the present invention.

[0056] Referring to Figure 7, when the program operation of the selected memory block begins, a program-allowable voltage and a first program-prohibited voltage are selectively applied to the bit lines connected to the selected memory block, and a program voltage can be applied to the selected word line among the word lines connected to the selected memory block (S71). The selected word line is the word line connected to the selected page.

[0057] The program-allowable voltage is a voltage that lowers the channel voltage of the string containing the selected memory cell and can be applied to the selected bit line. The first program-blocking voltage is a voltage that raises the channel voltage of the string containing the unselected memory cell and can be applied to the unselected bit line. The selected bit line is coupled to the selected string containing the selected memory cell, and the unselected bit line is coupled to the unselected string containing the unselected memory cell.

[0058] In step S71, a path voltage can be applied to the unselected word lines among the word lines connected to the selected memory block. The path voltage is a voltage used to turn on the unselected memory cells and form channels in the unselected strings.

[0059] In step S71, after a program voltage is applied to the selected word line for a certain period of time, a verification operation can be performed on the selected memory cell (S72). During the verification operation, a pre-verification operation using a pre-verification voltage and a target verification operation using a target verification voltage can be performed sequentially. The pre-verification voltage can be applied to the selected word line to detect memory cells having a threshold voltage higher than the pre-target voltage. The target verification voltage can be applied to the selected word line to detect memory cells having a threshold voltage higher than the target voltage. The pre-target voltage and target voltage have been explained with reference to Figure 5, so their explanation will be omitted here. In step S72, after the pre-verification operation using the pre-verification voltage is performed, a target verification operation using the target verification voltage can be performed. The detailed verification operation will be explained with reference to Figure 8.

[0060] In step S72, if all pre-verification and target verification operations are passed, the program operation for the selected page ends.

[0061] In step S72, if the target verification operation fails regardless of the result of the pre-verification operation, an operation to determine the state of the memory cells included in the selected page can be performed (S73).

[0062] In step S73, the state of the memory cell can be determined based on the results of the verification operation performed in step S72. For example, the state of the memory cell can be determined according to the results of the pre-verification operation and the target verification operation performed sequentially in step S72.

[0063] Depending on the results of the pre-verification operation, memory cells with a threshold voltage lower than the pre-target voltage and memory cells with a threshold voltage higher than the pre-target voltage can be detected. Depending on the results of the target verification operation, memory cells with a threshold voltage lower than the target voltage and memory cells with a threshold voltage higher than the target voltage can be detected.

[0064] Memory cells with a threshold voltage lower than the pre-target voltage can be classified as program initial cells. Memory cells with a threshold voltage higher than the pre-target voltage and lower than the target voltage can be classified as program adjacent cells. Memory cells with a threshold voltage higher than the target voltage can be classified as program complete cells.

[0065] In step S73, memory cells determined to be initial program cells can be programmed using the method of step S74, memory cells determined to be adjacent program cells can be programmed using the method of step S75, and memory cells determined to be completed programs and unselected memory cells can be prevented from being programmed by step S76.

[0066] If the state of the memory cell is determined in step S73, steps S74, S75, and S76 can be executed simultaneously.

[0067] In step S74, the program voltage is reset to be higher by the step voltage, and the reset program voltage can be applied to the selected word line. For example, a program voltage that is higher by the step voltage than the program voltage used in the previous program loop can be used. The step voltage is the voltage difference that increases the program voltage in the ISPP (incremental step pulse program) method, and can be preset in the memory device. While the program voltage is applied to the selected word line, the program allowable voltage can be applied to the bit line of the memory cell determined to be the initial program cell.

[0068] In step S75, the program voltage is reset to be higher by the step voltage, and the reset program voltage can be applied to the selected word line. While the program voltage is applied to the selected word line, the program allow voltage and the second program prohibit voltage can be selectively applied over time to the bit lines of memory cells determined to be adjacent to the program cell.

[0069] In step S76, the program voltage is reset to be higher by the step voltage, and the reset program voltage can be applied to the selected word line. While the program voltage is applied to the selected word line, a first program disable voltage can be applied to the bit lines of memory cells determined to be programmed complete and to unselected memory cells.

[0070] In step S74, the threshold voltage of the memory cell can rise faster due to the program-tolerant voltage applied to the bit line. In step S75, the threshold voltage of the memory cell can rise slower than the threshold voltage that rises in step S74 due to the program-tolerant voltage and the second program-block voltage selectively applied to the bit line, and the rate of increase can be adjusted. In step S76, since the memory cell is either programmed or an unselected memory cell, the threshold voltage of the memory cell does not rise due to the first program-block voltage applied to the bit line.

[0071] The voltages applied to each line in steps S74, S75, and S76 will be described in detail with reference to Figures 9a to 9d.

[0072] In steps S74, S75, and S76, after the program voltage is applied to the selected word line for a certain period of time, a verification operation can be performed on the selected memory cell (S77). In step S77, the verification operation can be performed in the same manner as the verification operation performed in step S72. If the target verification operation performed in step S77 fails, step S73 can be executed again. If the target verification operation performed in step S77 passes, the program operation of the selected page can be terminated.

[0073] Figure 8 is a diagram illustrating the verification operation according to an embodiment of the present invention.

[0074] Referring to Figure 8, a specific method for the verification operation performed in step S72 or step S77 of Figure 7 is shown. The verification operation can be performed between the first time T1 and the fourth time T4. While the verification operation is being performed, a ground voltage may be applied to the source line, a path voltage may be applied to the unselected word line, and a turn-on voltage may be applied to the drain and source selection lines.

[0075] At time T1, a precharge voltage Vpre can be applied to all bit lines BL#. The precharge voltage Vpre is a positive voltage higher than 0V and can be used to check for changes in the voltage or current of bit lines BL# depending on the state of the memory cell.

[0076] At the second time T2, when the precharge voltage Vpre rises to the target level, a pre-verification voltage Vpv is applied to the selected word line Sel_WL. The pre-verification voltage Vpv is at a lower level than the target verification voltage Vtv. For example, the pre-verification voltage Vpv is used to detect the initial programmed cell, while the target verification voltage Vtv is used to distinguish between programmed adjacent cells and programmed completed cells. A ground voltage may be applied to the source line while the verification operation is being performed.

[0077] While the pre-verification voltage Vpv is applied to the selected word line Sel_WL (T2-T3), the voltage of the bit line connected to a memory cell whose threshold voltage is lower than the pre-target voltage (Vp in Figure 5) can be lower than the pre-charge voltage Vpre. Memory cells connected to bit lines whose voltage is lower in the T2-T3 interval can be detected as the initial programmed cell MCi.

[0078] At time T3, the target verification voltage Vtv is applied to the selected word line Sel_WL. While the target verification voltage Vtv is applied to the selected word line Sel_WL (T3-T4), the voltage of a bit line connected to a memory cell whose threshold voltage is lower than the target voltage (Vt in Figure 5) can be lower than the precharge voltage Vpre. Memory cells connected to bit lines whose voltage is lower in the T3-T4 interval can be classified as programmed adjacent cells MCa. Memory cells connected to bit lines whose precharge voltage Vpre is maintained in the T3-T4 interval can be classified as programmed completed cells MCc.

[0079] As described above, during the verification operation, the pre-verification operation can be performed between the second time T2 and the third time T3, and the target verification operation can be performed between the third time T3 and the fourth time T4. The data sensed during the pre-verification operation and the data sensed during the target verification operation can be stored in a latch included in the page buffer group (140 in Figure 1). Depending on the sensed data stored in the page buffer group 140, the voltage applied to the bit line in the next program loop can be determined.

[0080] The validation operation for the selected page can be passed or failed depending on the result of the target validation operation. For example, a pre-validation operation may be performed to distinguish the program's initial cell MCi, and a target validation operation may be performed to distinguish the program's adjacent cell MCa and the program's completed cell MCc, and to determine whether the validation operation for the selected page passed or failed. Determining whether the validation operation passed or failed is equivalent to determining whether the program operation performed on the selected page was completed or incomplete.

[0081] Figures 9a to 9d are diagrams illustrating the program operation according to the first embodiment of the present invention.

[0082] Referring to Figures 6, 7, and 9a, we assume that the memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and the memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0083] At the first time T1' when the program loop of the selected page begins, a first program voltage of 1Vpgm is applied to the selected word line Sel_WL, a program allow voltage Val is applied to the first to third bit lines BL1 to BL3, and a first program disable voltage of 1Vin is applied to the fourth bit line BL4. A pass voltage may be applied to the unselected word lines, a ground voltage may be applied to the source lines, and a turn-on voltage may be applied to the drain and source selection lines.

[0084] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltage of the selected memory cells can be increased by the first program voltage of 1 Vpgm.

[0085] After a first program voltage of 1 Vpgm is applied for the first to second time intervals T1'-T2', a verification operation of the memory cells contained in the selected page is performed. The verification operation can be performed in the manner described with reference to Figure 8.

[0086] Based on the verification results, as explained with reference to Figure 6, we assume that the memory cell connected to the first bit line BL1 is the program initial cell MCi, the memory cell connected to the second bit line BL2 is the program adjacent cell MCa, and the memory cell connected to the third bit line BL3 is the program completed cell MCc.

[0087] Depending on the results of the verification operation, when the next program loop is started, at the third time T3', the program allow voltage Val is applied to the first bit line BL1, the second program disable voltage 2Vin is applied to the second bit line BL2, and the first program disable voltage 1Vin is applied to the third bit line BL3 and the fourth bit line BL4.

[0088] Since the memory cell connected to the first bit line BL1 is the program initial cell MCi, a program allowance voltage Val is applied to the first bit line BL1 in order to quickly raise the threshold voltage of the program initial cell MCi. The program allowance voltage Val can be the lowest voltage among the voltages set to be applied to the bit line during program operation.

[0089] Since the memory cell connected to the second bit line BL2 is the program-adjacent cell MCa, a second program-block voltage 2Vin is applied to the second bit line BL2 to raise the threshold voltage of the program-adjacent cell MCa later than the program-initial cell MCi. The second program-block voltage 2Vin can be set higher than the program-allowable voltage Val and equal to or lower than the first program-block voltage 1Vin.

[0090] Since the memory cell connected to the third bit line BL3 is the program-completed cell MCc and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, a first program-block voltage of 1Vin is applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the program-completed cell MCc and the unselected memory cell Unsel_MC from becoming any higher. The first program-block voltage of 1Vin can be the highest voltage among the voltages set to be applied to the bit lines during program operation.

[0091] A second program voltage of 2Vpgm can be applied to the selected word line Sel_WL. The second program voltage of 2Vpgm can be set to be a step voltage higher than the first program voltage of 1Vpgm. The second program voltage of 2Vpgm can be set to be applied to the selected word line Sel_WL from the third time T3' to the fifth time T5'.

[0092] The first program disable voltage 1Vin is also applied to the third and fourth bit lines BL3 and BL4 during the third time T3' to the fifth time T5'.

[0093] The second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a shorter period than the time the second program voltage 2Vpgm or the first program-blocking voltage 1Vin is applied. For example, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 during the third time period T3' to the fourth time period T4'. The third to fourth time period T3'-T4' is shorter than the third to fifth time period T3'-T5'. During the fourth to fifth time period T4'-T5', the program-allowable voltage Val can be applied to the second bit line BL2.

[0094] Unlike the embodiment described with reference to Figure 9a, if the second program-block voltage 2Vin is applied to the second bit line BL2 for the same duration as the first program-block voltage 1Vin (T3'-T5'), the time during which the threshold voltage of the adjacent programmed cell MCa is high increases, which can lead to an excessively long program operation time.

[0095] As described with reference to Figure 9a, by applying a second program-blocking voltage 2Vin to the second bit line BL2 during the third to fourth time period T3'-T4', and applying a program-allowing voltage Val to the second bit line BL2 during the fourth to fifth time period T4'-T5', the time during which the threshold voltage of the adjacent programmed cell MCa becomes high can be adjusted, thereby shortening the time required for program operation.

[0096] In the embodiment described with reference to Figure 9a, the time for which the second program-blocking voltage 2Vin is applied to the second bit line BL2 is shorter than the time for which the program-allowing voltage Val is applied to the second bit line BL2. However, the time for which the second program-blocking voltage 2Vin and the program-allowing voltage Val are applied to the second bit line BL2 can be changed in various ways. Various embodiments for adjusting the second program-blocking voltage 2Vin are described below.

[0097] Referring to Figure 9b, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 during the third to fourth time period T3'-T4''. The fourth time period T4'' is earlier than the fourth time period T4' described with reference to Figure 9a. The program-allowing voltage Val can be applied to the second bit line BL2 during the fourth to fifth time period T4''-T5'. The third to fourth time period T3'-T4'' is shorter than the fourth to fifth time period T4''-T5'. In the embodiment described with reference to Figure 9b, the time during which the program-allowing voltage Val is applied to the second bit line BL2 is longer than the time during which the second program-blocking voltage 2Vin is applied, so the program operation time can be shortened compared to the embodiment described with reference to Figure 9a. Except for the time during which the second program-blocking voltage 2Vin and the program-allowing voltage Val are applied to the second bit line BL2, the method of applying voltage to the remaining lines is the same as in the embodiment described with reference to Figure 9a, so redundant explanations are omitted.

[0098] Referring to Figure 9c, during the third to fifth time period T3'-T5', the program allow voltage Val can be applied to the second bit line BL2, followed by the second program disable voltage 2Vin. For example, the program allow voltage Val can be applied to the second bit line BL2 during the third to fourth time period T3'-T4', and the second program disable voltage 2Vin can be applied to the second bit line BL2 during the fourth to fifth time period T4'-T5'. Therefore, during the third to fourth time period T3'-T4', the threshold voltage of the programmed adjacent cell MCa can rise relatively quickly, and during the fourth to fifth time period T4'-T5', the threshold voltage of the programmed adjacent cell MCa can rise relatively slowly. The method of applying voltage to the remaining lines is the same as in the embodiment described with reference to Figure 9a, except for the time during which the program allow voltage Val and the second program disable voltage 2Vin are applied to the second bit line BL2, so redundant explanations are omitted.

[0099] Referring to Figure 9d, during the third to fourth time period T3'-T4'', the program allowable voltage Val can be applied to the second bit line BL2, and during the fourth to fifth time period T4''-T5', the second program disable voltage 2Vin can be applied to the second bit line BL2. Therefore, during the third to fourth time period T3'-T4'', the threshold voltage of the program adjacent cell MCa can rise relatively quickly, and during the fourth to fifth time period T4''-T5', the threshold voltage of the program adjacent cell MCa can rise relatively slowly. Except for the time during which the program allowable voltage Val and the second program disable voltage 2Vin are applied to the second bit line BL2, the method of applying voltage to the remaining lines is the same as in the embodiment described with reference to Figure 9a, so redundant explanations are omitted.

[0100] Figure 10 is a flowchart illustrating the program operation according to a second embodiment of the present invention.

[0101] Referring to Figure 10, when the program operation of the selected memory block begins, a program-allowable voltage can be applied to the selected bit line connected to the selected memory block, and a first program-prohibited voltage can be applied to the unselected bit line (S101).

[0102] Among the word lines connected to the selected memory block, a path voltage can be applied to the unselected word lines (S102), and a program voltage can be applied to the selected word lines (S103). The selected word lines are the word lines connected to the selected pages among the pages contained in the selected memory block.

[0103] In step S103, after a program voltage is applied to the selected word line for a certain period of time, a verification operation of the memory cells contained in the selected page can be performed (S104). The verification operation can be performed in the manner described with reference to Figure 8. For example, as described with reference to Figure 8, a pre-verification operation and a target verification operation can be performed in the verification operation. Thus, the verification operation in step S104 can classify the memory cells contained in the selected page into one of the following: a program initial cell, a program adjacent cell, and a program completion cell.

[0104] In step S104, the number of incomplete cells Nf and the reference number Nr detected from the results of the target verification operation are compared (S105). The number of incomplete cells can be the sum of the number of initial program cells and the number of adjacent program cells. For example, the control circuit (170 in Figure 1) can calculate the number of incomplete cells Nf by adding the number of initial program cells and the number of adjacent program cells based on the data sensed and stored in the page buffer group (140 in Figure 1) during the verification operation. The control circuit 170 can compare the number of incomplete cells Nf with a pre-stored reference number Nr. The reference number Nr can be set differently depending on the memory device. In some embodiments, the number of completed program cells may be counted instead of the number of incomplete cells Nf, in which case the reference number corresponding to the number of pass cells may be different from the reference number Nr corresponding to the incomplete cells.

[0105] The following example describes a method for comparing the number of incomplete cells Nf with the reference number Nr.

[0106] In step S105, if the number Nf of unfinished cells is less than the reference number Nr (Nf < Nr), a program allowable voltage is applied to the bit line connected to the program initial cell, a program allowable voltage and a second program inhibit voltage are sequentially applied to the bit line connected to the program adjacent cell, a first program inhibit voltage is applied to the bit line connected to the program completed cell, a pass voltage is applied to the non-selected word line, and a program voltage is applied to the selected word line (S106). The program voltage applied to the selected word line can be increased by only the step voltage as the number of program loops increases.

[0107] The program allowable voltage and the second program inhibit voltage applied to the bit line connected to the program adjacent cell can be sequentially applied to the bit line while the program voltage is applied to the selected word line. The order and time at which the program allowable voltage and the second program inhibit voltage are applied to the bit line connected to the program adjacent cell can be changed. At this time, assume that the time during which the second program inhibit voltage is applied and maintained to the bit line connected to the program adjacent cell is the first adjustment time.

[0108] In step S105, if the number Nf of unfinished cells is greater than the reference number Nr (Nf > Nr), a program allowable voltage is applied to the bit line connected to the program initial cell, a program allowable voltage and a second program inhibit voltage are sequentially applied to the bit line connected to the program adjacent cell, a first program inhibit voltage is applied to the bit line connected to the program completed cell, a pass voltage is applied to the non-selected word line, and a program voltage is applied to the selected word line (S107). The program voltage applied to the selected word line can be increased by only the step voltage as the number of program loops increases.

[0109] In step S105, if the number of incomplete cells Nf and the reference number Nr are the same, it can be configured to execute either step S106 or step S107.

[0110] In step S107, it is assumed that the second adjustment time is shorter than the first adjustment time for the time during which the second program prohibition voltage is applied to and maintained on the bit line connected to the adjacent program cell.

[0111] After step S106 or step S107 is performed, the verification operation for the selected memory cell can be re-executed (S104). Steps S104 to S107 can be repeated until the verification operation performed in step S104 passes.

[0112] Figures 11a to 11c and 12a to 12c are diagrams illustrating the program operation according to a second embodiment of the present invention.

[0113] Figures 11a and 12a are different embodiments corresponding to step S106 in Figure 10, Figures 11b and 12b are different embodiments corresponding to step S107 in Figure 10, and Figures 11c and 12c are yet another embodiment corresponding to step S107 in Figure 10. That is, if step S106 in Figure 10 is set to be performed as in the embodiment shown in Figure 11a, then step S107 in Figure 10 can be performed as in the embodiment shown in Figure 11b. As another embodiment, if step S106 in Figure 10 is set to be performed as in the embodiment shown in Figure 12a, then step S107 in Figure 10 can be performed as in the embodiment shown in Figure 12b. Figures 11c and 12c show embodiments for adjusting the voltage applied to the bit line for step S106.

[0114] Referring to Figures 6, 10, and 11a, we assume that the memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and the memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0115] At the first time T1' when the program loop of the selected page begins, a first program voltage of 1Vpgm is applied to the selected word line Sel_WL, a program allow voltage Val is applied to the first to third bit lines BL1 to BL3, and a first program disable voltage of 1Vin is applied to the fourth bit line BL4. A pass voltage may be applied to the unselected word lines, a ground voltage may be applied to the source lines, and a turn-on voltage may be applied to the drain and source selection lines.

[0116] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltage of the selected memory cells can be increased by the first program voltage of 1 Vpgm.

[0117] After a first program voltage of 1 Vpgm is applied for the first to second time intervals T1'-T2', a verification operation of the memory cells contained in the selected page is performed. The verification operation can be performed in the manner described with reference to Figure 8.

[0118] Based on the verification results, as explained with reference to Figure 6, we assume that the memory cell connected to the first bit line BL1 is the program initial cell MCi, the memory cell connected to the second bit line BL2 is the program adjacent cell MCa, and the memory cell connected to the third bit line BL3 is the program completed cell MCc.

[0119] Depending on the results of the verification operation, when the next program loop is started, at the third time T3', the program allow voltage Val is applied to the first bit line BL1, the second program disable voltage 2Vin is applied to the second bit line BL2, and the first program disable voltage 1Vin is applied to the third bit line BL3 and the fourth bit line BL4.

[0120] Since the memory cell connected to the first bit line BL1 is the program initial cell MCi, a program allowance voltage Val is applied to the first bit line BL1 in order to quickly raise the threshold voltage of the program initial cell MCi. The program allowance voltage Val can be the lowest voltage among the voltages set to be applied to the bit line during program operation.

[0121] Since the memory cell connected to the second bit line BL2 is the program-adjacent cell MCa, a second program-block voltage 2Vin is applied to the second bit line BL2 to raise the threshold voltage of the program-adjacent cell MCa later than the program-initial cell MCi. The second program-block voltage 2Vin can be set higher than the program-allowable voltage Val and equal to or lower than the first program-block voltage 1Vin.

[0122] Since the memory cell connected to the third bit line BL3 is the program-completed cell MCc and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, a first program-block voltage of 1Vin is applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the program-completed cell MCc and the unselected memory cell Unsel_MC from becoming any higher. The first program-block voltage of 1Vin can be the highest voltage among the voltages set to be applied to the bit lines during program operation.

[0123] A second program voltage of 2Vpgm can be applied to the selected word line Sel_WL. The second program voltage of 2Vpgm can be set to be a step voltage higher than the first program voltage of 1Vpgm. The second program voltage of 2Vpgm can be set to be applied to the selected word line Sel_WL from the third time T3' to the fifth time T5'.

[0124] The first program disable voltage 1Vin is also applied to the third and fourth bit lines BL3 and BL4 during the third time T3' to the fifth time T5'.

[0125] The second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a shorter period than the time the second program voltage 2Vpgm or the first program-blocking voltage 1Vin is applied. In step S106 of the operation described with reference to Figure 10, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for the duration of the first adjustment time CT1. That is, if the number of incomplete cells Nf detected in the verification operation is less than the reference number Nr, the time for which the second program-blocking voltage 2Vin is applied to the second bit line BL2 can be defined as the first adjustment time CT1. In other words, a number of incomplete cells Nf being less than the reference number Nr means that there are many programmed cells. To put it another way, a number of incomplete cells Nf being less than the reference number Nr means that there are fewer cells for which the threshold voltage must be increased. Therefore, the control circuit (170 in Figure 1) can control the page buffer group (140 in Figure 1) such that the second program prohibition voltage 2Vin is applied to the second bit line BL2 for a longer period than the program allowance voltage Val.

[0126] The first adjustment time CT1 is the time from the third time T3' to the fourth time T4'. Since the fourth time T4' is earlier than the fifth time T5', the first adjustment time CT1 is shorter than the time from the third time T3' to the fifth time T5'. The first adjustment time CT1 is changeable between the third time T3' and the fifth time T5'. Between the fourth and fifth times T4'-T5', the program allowable voltage Val can be applied to the second bit line BL2.

[0127] Referring to Figures 6, 10, and 11b, we assume that the memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and the memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0128] At the first time T1' when the program loop of the selected page begins, a first program voltage of 1Vpgm is applied to the selected word line Sel_WL, a program allow voltage Val is applied to the first to third bit lines BL1 to BL3, and a first program disable voltage of 1Vin is applied to the fourth bit line BL4. A pass voltage may be applied to the unselected word lines, a ground voltage may be applied to the source lines, and a turn-on voltage may be applied to the drain and source selection lines.

[0129] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltage of the selected memory cells can be increased by the first program voltage of 1 Vpgm.

[0130] After a first program voltage of 1 Vpgm is applied for the first to second time intervals T1'-T2', a verification operation of the memory cells contained in the selected page is performed. The verification operation can be performed in the manner described with reference to Figure 8.

[0131] Based on the verification results, as explained with reference to Figure 6, we assume that the memory cell connected to the first bit line BL1 is the program initial cell MCi, the memory cell connected to the second bit line BL2 is the program adjacent cell MCa, and the memory cell connected to the third bit line BL3 is the program completed cell MCc.

[0132] Depending on the results of the verification operation, when the next program loop is started, at the third time T3', the program allow voltage Val is applied to the first bit line BL1, the second program disable voltage 2Vin is applied to the second bit line BL2, and the first program disable voltage 1Vin is applied to the third bit line BL3 and the fourth bit line BL4.

[0133] Since the memory cell connected to the first bit line BL1 is the program initial cell MCi, a program allowance voltage Val is applied to the first bit line BL1 in order to quickly raise the threshold voltage of the program initial cell MCi. The program allowance voltage Val can be the lowest voltage among the voltages set to be applied to the bit line during program operation.

[0134] Since the memory cell connected to the second bit line BL2 is the program-adjacent cell MCa, a second program-block voltage 2Vin is applied to the second bit line BL2 to raise the threshold voltage of the program-adjacent cell MCa later than the program-initial cell MCi. The second program-block voltage 2Vin can be set higher than the program-allowable voltage Val and equal to or lower than the first program-block voltage 1Vin.

[0135] Since the memory cell connected to the third bit line BL3 is the program-completed cell MCc and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, a first program-block voltage of 1Vin is applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the program-completed cell MCc and the unselected memory cell Unsel_MC from becoming any higher. The first program-block voltage of 1Vin can be the highest voltage among the voltages set to be applied to the bit lines during program operation.

[0136] A second program voltage of 2Vpgm can be applied to the selected word line Sel_WL. The second program voltage of 2Vpgm can be set to be a step voltage higher than the first program voltage of 1Vpgm. The second program voltage of 2Vpgm can be set to be applied to the selected word line Sel_WL from the third time T3' to the fifth time T5'.

[0137] The first program disable voltage 1Vin is also applied to the third and fourth bit lines BL3 and BL4 during the third time T3' to the fifth time T5'.

[0138] The second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a shorter time than the time the second program voltage 2Vpgm or the first program-blocking voltage 1Vin is applied. In step S107 of the operation described with reference to Figure 10, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a second adjustment time CT2 which is shorter than the first adjustment time CT1. In other words, if the number of incomplete cells Nf detected in the verification operation is greater than the reference number Nr, the time for which the second program-blocking voltage 2Vin is applied to the second bit line BL2 can be defined as the second adjustment time CT2. That is, if the number of incomplete cells Nf is greater than the reference number Nr, it means that fewer cells have been passed. In other words, if the number of incomplete cells Nf is greater than the reference number Nr, it means that there are more cells for which the threshold voltage must be increased. Therefore, the control circuit (170 in Figure 1) can control the page buffer group (140 in Figure 1) such that the second program prohibition voltage 2Vin is applied to the second bit line BL2 for a shorter duration than the program allowance voltage Val.

[0139] The second adjustment time CT2 is the time from the third time T3' to the fourth time T4''. Since the fourth time T4'' is earlier than the fifth time T5', the second adjustment time CT2 is shorter than the time from the third time T3' to the fifth time T5'. The second adjustment time CT2 is changeable between the third time T3' and the fifth time T5'. Between the fourth and fifth times T4''-T5', a program allowable voltage Val can be applied to the second bit line BL2.

[0140] Referring to Figures 6, 10, and 11c, as explained with reference to Figure 11b, if the number of incomplete cells Nf is greater than the reference number Nr, the time during which voltage is applied to the second bit line BL2 can be shortened to between the third time T3' and the fourth time T4''. In this case, the level of the second program-block voltage 2Vin applied to the second bit line BL2 can be adjusted to a lower level (2Vin'). In other words, the time and level of the voltage applied to the second bit line BL2 can be adjusted simultaneously. For example, the second program-block voltage 2Vin' explained with reference to Figure 11c can be lower than the second program-block voltage 2Vin explained with reference to Figure 11b, and higher than 0V, and can be applied to the second bit line BL2 between the third time T3' and the fifth time T5'.

[0141] Referring to Figures 6, 10, and 12a, we assume that the memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and the memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0142] At the first time T1' when the program loop of the selected page begins, a first program voltage of 1Vpgm is applied to the selected word line Sel_WL, a program allow voltage Val is applied to the first to third bit lines BL1 to BL3, and a first program disable voltage of 1Vin is applied to the fourth bit line BL4. A pass voltage may be applied to the unselected word lines, a ground voltage may be applied to the source lines, and a turn-on voltage may be applied to the drain and source selection lines.

[0143] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltage of the selected memory cells can be increased by the first program voltage of 1 Vpgm.

[0144] After a first program voltage of 1 Vpgm is applied for the first to second time intervals T1'-T2', a verification operation of the memory cells contained in the selected page is performed. The verification operation can be performed in the manner described with reference to Figure 8.

[0145] Based on the verification results, as explained with reference to Figure 6, we assume that the memory cell connected to the first bit line BL1 is the program initial cell MCi, the memory cell connected to the second bit line BL2 is the program adjacent cell MCa, and the memory cell connected to the third bit line BL3 is the program completed cell MCc.

[0146] Depending on the results of the verification operation, when the next program loop is started, at the third time T3', the program allowable voltage Val is applied to the first bit line BL1, the program allowable voltage Val is applied to the second bit line BL2, and the first program prohibition voltage 1Vin is applied to the third bit line BL3 and the fourth bit line BL4.

[0147] Since the memory cell connected to the first bit line BL1 is the program initial cell MCi, a program allowance voltage Val is applied to the first bit line BL1 during the third to fifth time periods T3'-T5' in order to quickly raise the threshold voltage of the program initial cell MCi. The program allowance voltage Val can be the lowest voltage among the voltages set to be applied to the bit line during program operation.

[0148] Since the memory cell connected to the second bit line BL2 is the program-adjacent cell MCa, a second program-block voltage 2Vin is applied to the second bit line BL2 after the program-allowable voltage Val is applied, in order to raise the threshold voltage of the program-adjacent cell MCa later than the program-initial cell MCi. The second program-block voltage 2Vin can be set higher than the program-allowable voltage Val and equal to or lower than the first program-block voltage 1Vin.

[0149] Since the memory cell connected to the third bit line BL3 is the program-completed cell MCc and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, a first program-block voltage of 1Vin is applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the program-completed cell MCc and the unselected memory cell Unsel_MC from becoming any higher. The first program-block voltage of 1Vin can be the highest voltage among the voltages set to be applied to the bit lines during program operation.

[0150] A second program voltage of 2Vpgm can be applied to the selected word line Sel_WL. The second program voltage of 2Vpgm can be set to be a step voltage higher than the first program voltage of 1Vpgm. The second program voltage of 2Vpgm can be set to be applied to the selected word line Sel_WL from the third time T3' to the fifth time T5'.

[0151] The first program disable voltage 1Vin is also applied to the third and fourth bit lines BL3 and BL4 during the third time T3' to the fifth time T5'.

[0152] The second program-blocking voltage 2Vin applied to the second bit line BL2 can be applied to the second bit line BL2 for a shorter period than the time the second program voltage 2Vpgm or the first program-blocking voltage 1Vin is applied. In step S106 of the operation described with reference to Figure 10, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for the duration of the first adjustment time CT1. That is, if the number of incomplete cells Nf detected in the verification operation is less than the reference number Nr, the time for which the second program-blocking voltage 2Vin is applied to the second bit line BL2 can be defined as the first adjustment time CT1. In other words, a number of incomplete cells Nf being less than the reference number Nr means that there are many programmed cells. To put it another way, a number of incomplete cells Nf being less than the reference number Nr means that there are fewer cells for which the threshold voltage must be increased. Therefore, the control circuit (170 in Figure 1) can control the page buffer group (140 in Figure 1) such that the second program prohibition voltage 2Vin is applied to the second bit line BL2 for a longer period than the program allowance voltage Val.

[0153] The first adjustment time CT1 is the time from the fourth time T4'' to the fifth time T5'. Since the fourth time T4'' is earlier than the fifth time T5', the first adjustment time CT1 is shorter than the time from the third time T3' to the fifth time T5'. The first adjustment time CT1 can be changed between the third time T3' and the fifth time T5'.

[0154] Referring to Figures 6, 10, and 12b, we assume that the memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and the memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0155] At the first time T1' when the program loop of the selected page begins, a first program voltage of 1Vpgm is applied to the selected word line Sel_WL, a program allow voltage Val is applied to the first to third bit lines BL1 to BL3, and a first program disable voltage of 1Vin is applied to the fourth bit line BL4. A pass voltage may be applied to the unselected word lines, a ground voltage may be applied to the source lines, and a turn-on voltage may be applied to the drain and source selection lines.

[0156] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltage of the selected memory cells can be increased by the first program voltage of 1 Vpgm.

[0157] After a first program voltage of 1 Vpgm is applied for the first to second time intervals T1'-T2', a verification operation of the memory cells contained in the selected page is performed. The verification operation can be performed in the manner described with reference to Figure 8.

[0158] Based on the verification results, as explained with reference to Figure 6, we assume that the memory cell connected to the first bit line BL1 is the program initial cell MCi, the memory cell connected to the second bit line BL2 is the program adjacent cell MCa, and the memory cell connected to the third bit line BL3 is the program completed cell MCc.

[0159] Depending on the results of the verification operation, when the next program loop is started, at the third time T3', the program allowable voltage Val is applied to the first bit line BL1, the program allowable voltage Val is applied to the second bit line BL2, and the first program prohibition voltage 1Vin is applied to the third bit line BL3 and the fourth bit line BL4.

[0160] Since the memory cell connected to the first bit line BL1 is the program initial cell MCi, a program allowance voltage Val is applied to the first bit line BL1 in order to quickly raise the threshold voltage of the program initial cell MCi. The program allowance voltage Val can be the lowest voltage among the voltages set to be applied to the bit line during program operation.

[0161] Since the memory cell connected to the second bit line BL2 is the program-adjacent cell MCa, a second program-block voltage 2Vin is applied to the second bit line BL2 after the program-allowable voltage Val is applied, in order to raise the threshold voltage of the program-adjacent cell MCa later than the program-initial cell MCi. The second program-block voltage 2Vin can be set higher than the program-allowable voltage Val and equal to or lower than the first program-block voltage 1Vin.

[0162] Since the memory cell connected to the third bit line BL3 is the program-completed cell MCc and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, a first program-block voltage of 1Vin is applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the program-completed cell MCc and the unselected memory cell Unsel_MC from becoming any higher. The first program-block voltage of 1Vin can be the highest voltage among the voltages set to be applied to the bit lines during program operation.

[0163] A second program voltage of 2Vpgm can be applied to the selected word line Sel_WL. The second program voltage of 2Vpgm can be set to be a step voltage higher than the first program voltage of 1Vpgm. The second program voltage of 2Vpgm can be set to be applied to the selected word line Sel_WL from the third time T3' to the fifth time T5'.

[0164] The first program disable voltage 1Vin is also applied to the third and fourth bit lines BL3 and BL4 during the third time T3' to the fifth time T5'.

[0165] The second program-blocking voltage 2Vin applied to the second bit line BL2 can be applied to the second bit line BL2 for a shorter period than the time the second program voltage 2Vpgm or the first program-blocking voltage 1Vin is applied. In step S107 of the operation described with reference to Figure 10, the second program-blocking voltage 2Vin can be applied to the second bit line BL2 for a second adjustment time CT2 that is shorter than the first adjustment time CT1. That is, if the number of incomplete cells Nf detected in the verification operation is greater than the reference number Nr, the time for which the second program-blocking voltage 2Vin is applied to the second bit line BL2 can be defined as the second adjustment time CT2. In other words, if the number of incomplete cells Nf is greater than the reference number Nr, it means that the number of programmed cells is smaller. To put it another way, if the number of incomplete cells Nf is greater than the reference number Nr, it means that there are many cells for which the threshold voltage must be increased. Therefore, the control circuit (170 in Figure 1) can control the page buffer group (140 in Figure 1) such that the second program prohibition voltage 2Vin is applied to the second bit line BL2 for a shorter duration than the program allowance voltage Val.

[0166] The second adjustment time CT2 is the time from the fourth time T4' to the fifth time T5'. Since the fourth time T4' is earlier than the fifth time T5', the second adjustment time CT2 is shorter than the time from the third time T3' to the fifth time T5'. The second adjustment time CT2 can be changed between the third time T3' and the fifth time T5'.

[0167] Referring to Figures 6, 10, and 12c, as explained with reference to Figure 12b, if the number of incomplete cells Nf is greater than the reference number Nr, the time during which voltage is applied to the second bit line BL2 can be shortened to between the fourth time T4' and the fifth time T5', i.e., to the second adjustment time CT2. In this embodiment, the level of the second program-blocking voltage 2Vin applied to the second bit line BL2 can be adjusted to a lower level (2Vin'). In other words, the time and level of the voltage applied to the second bit line BL2 can be adjusted simultaneously. For example, the second program-blocking voltage 2Vin' explained with reference to Figure 12c can have a level lower than the second program-blocking voltage 2Vin explained with reference to Figure 12b, and higher than 0V, and can be applied to the second bit line BL2 between the fourth time T4' and the fifth time T5'.

[0168] Figures 13a to 13d illustrate the continuously increasing threshold voltage of a memory cell during program operation according to the present invention.

[0169] Referring to Figure 13a, since the program operation is performed on a memory cell in an erased state, the threshold voltage of the memory cell can be lower than the pre-target voltage Vp at the beginning of the program operation. In the verification operation described with reference to Figure 5, a pre-verification operation and a target verification operation can be performed. Whether the program operation performed on the selected page is a pass or a fail is determined by the result of the target verification operation. As shown in Figure 13a, at the beginning of the program operation, the threshold voltage of the memory cell is lower than the target voltage Vt, so the result of the verification operation can be a fail.

[0170] Since the verification result is a fail, the voltage applied to the bit line connected to the selected memory cell can be set for the next program loop. As shown in Figure 13a, if the threshold voltage of the selected memory cell is lower than the pre-target voltage Vp, the program allowable voltage can be applied to the bit line connected to the selected memory cell.

[0171] Referring to Figure 13b, when the threshold voltage of a memory cell increases due to the program voltage, the selected page may include memory cells with a threshold voltage higher than the target voltage Vt, memory cells with a threshold voltage between the pre-target voltage Vp and the target voltage Vt, and memory cells with a threshold voltage lower than the pre-target voltage Vp. The reason why memory cells programmed by the same program voltage have different threshold voltages is that the electrical characteristics of the memory cells are different from each other. That is, since the memory cells are programmed at different speeds, programmed memory cells cannot have the same threshold voltage. Therefore, the threshold voltages of memory cells corresponding to the same program state can be distributed within the range set for the same program state. As shown in Figure 13b, if the number of memory cells that fail the verification operation is greater than the number of memory cells that pass the verification operation, the number of incomplete cells Nf can be greater than the reference number Nr.

[0172] In this case, in the next program loop, the program allowable voltage can be applied to the bit lines of program initial cells where the threshold voltage is lower than the pre-target voltage Vp, the second program prohibition voltage and the program allowable voltage can be applied at different times to the bit lines of program adjacent cells where the threshold voltage is between the pre-target voltage Vp and the target voltage Vt, and the first program prohibition voltage can be applied to the bit lines of program completion cells where the threshold voltage is higher than the target voltage Vt.

[0173] As shown in Figure 13b, if the number of incomplete cells Nf is greater than the reference number Nr, the second program disable voltage can be applied to the bit line for a second time (CT2 in Figure 11b or Figure 12b).

[0174] Referring to Figure 13c, if the threshold voltage of the memory cells is further increased by the program voltage, the number of memory cells that pass the verification operation can be greater than the number of memory cells that fail, so the number of incomplete cells Nf can be less than the reference number Nr.

[0175] In this case, in the next program loop, the program allowable voltage can be applied to the bit lines of program initial cells where the threshold voltage is lower than the pre-target voltage Vp, the second program prohibition voltage and the program allowable voltage can be applied at different times to the bit lines of program adjacent cells where the threshold voltage is between the pre-target voltage Vp and the target voltage Vt, and the first program prohibition voltage can be applied to the bit lines of program completion cells where the threshold voltage is higher than the target voltage Vt.

[0176] As shown in Figure 13c, if the number of incomplete cells Nf is less than the reference number Nr, the second program disable voltage can be applied to the bit line for a first time (CT1 in Figure 11a or Figure 12a).

[0177] Referring to Figure 13d, if the threshold voltage of the selected memory cell included in the selected page becomes higher than the target voltage Vt, the verification operation can be passed and the program operation of the selected page can be terminated.

[0178] Figure 14 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present invention is applied.

[0179] Referring to Figure 14, the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0180] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 can be configured to control program, read, or erase operations of the memory device 3200, or to control background operations. The controller 3100 is configured to provide an interface between the memory device 3200 and the host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0181] The controller 3100 can communicate with an external device via the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device via at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0182] The memory device 3200 may include memory cells and may be configured similarly to the memory device 100 shown in Figure 1. For example, the memory device 3200 may include memory cells, peripheral circuits configured to program the memory cells, and a control circuit configured to control the peripheral circuits in response to commands. During programming, the peripheral circuits may be configured to perform a verification operation on a selected memory cell according to a target voltage and a pre-target voltage lower than the target voltage. The control circuit may control the peripheral circuits to adjust the voltage applied to the bit lines connected to the memory cells according to the results of the verification operation. The control circuit may control the peripheral circuits to adjust the time the voltage is applied to the bit lines according to the number of incomplete cells detected during the verification operation.

[0183] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, personal computer memory card international association), CompactFlash® card (CF), SmartMedia card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), or general-purpose flash memory (UFS).

[0184] Figure 15 is a diagram illustrating an SSD (Solid State Drive) system to which a memory device according to an embodiment of the present invention is applied.

[0185] Referring to Figure 15, the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 via a signal connector 4001 and receives power input via a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221-422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0186] The controller 4210 can control multiple memory devices 4221-422n in response to signals received from the host 4100. Exemplary, the signals can be based on the interfaces of the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0187] Multiple memory devices 4221-422n may include cells capable of storing data. Each of the multiple memory devices 4221-422n may be configured similarly to memory device 100 shown in Figure 1. For example, each of the multiple memory devices 4221-422n may include a memory cell, peripheral circuits configured to program the memory cell, and a control circuit configured to control the peripheral circuit in response to commands. During programming, the peripheral circuit may be configured to perform a verification operation on a selected memory cell according to a target voltage and a pre-target voltage lower than the target voltage. The control circuit may control the peripheral circuit to adjust the voltage applied to the bit line connected to the memory cell according to the result of the verification operation. The control circuit may control the peripheral circuit to adjust the time the voltage is applied to the bit line according to the number of incomplete cells detected during the verification operation.

[0188] The auxiliary power supply unit 4230 is connected to the host 4100 via the power connector 4002. The auxiliary power supply unit 4230 can receive power supply voltage input from the host 4100 and be charged. The auxiliary power supply unit 4230 can provide power supply voltage to the SSD 4200 if the power supply from the host 4100 is not smooth. Exemplarily, the auxiliary power supply unit 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply unit 4230 may be located on the main board and provide auxiliary power to the SSD 4200.

[0189] The buffer memory 4240 operates as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from multiple flash memories 4221-422n, or it can temporarily store metadata (e.g., mapping tables) of the memory devices 4221-422n. The buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or non-volatile memory such as FRAM®, ReRAM, STT-MRAM, or PRAM. [Explanation of Symbols]

[0190] 100 memory devices 110 memory cell array 120 Voltage generation unit 130 Low Decoder 140-page buffer group 150-column decoder 160 Input / Output Circuits 170 Control circuits 180 Peripheral Circuits Vp Pre-Target Voltage Vt Target Voltage Nf Number of incomplete cells Nr Standard number MCi program initial cell MCa Program Adjacent Cell MCc Program Complete Cell

Claims

1. Memory cells and; A peripheral circuit configured to execute the programmed operation of the memory cell, verify the memory cell according to a target voltage and a pre-target voltage lower than the target voltage, and apply a voltage to the bit line connected to the memory cell; Includes a control circuit configured to control the aforementioned peripheral circuits, The aforementioned control circuit is Depending on the verification results of the memory cell, the memory cell is determined to be a program initial cell, a program adjacent cell, or a program completion cell. The timing at which the bit line voltage is applied to the bit lines connected to the program initial cell, the program adjacent cell, and the program completion cell is controlled and adjusted. A memory device that controls the peripheral circuit to adjust the timing of the bit line voltage applied to the bit line connected to the program adjacent cell, among the bit line voltages, according to the number of at least one of the program initial cell, the program adjacent cell, and the program completion cell.

2. The aforementioned peripheral circuitry is The memory device according to claim 1, wherein the voltage applied to the bit line in accordance with the control of the control circuit is configured to selectively output a program-allowable voltage, a second program-prohibited voltage, and a first program-prohibited voltage.

3. The memory device according to claim 2, wherein the second program prohibition voltage is higher than the program allowance voltage and lower than the first program prohibition voltage.

4. The memory device according to claim 2, wherein the second program prohibition voltage is higher than the program allowance voltage and is the same as the first program prohibition voltage.

5. The aforementioned control circuit is While a program voltage is applied to the word line connected to the memory cell, The program allowable voltage is applied to the first bit line connected to the program initial cell among the bit lines. Of the bit lines, at least one of the second program prohibition voltage and the program allowance voltage is selectively applied to the second bit line connected to the program adjacent cell. The first program disable voltage is applied to the third bit line connected to the program completion cell among the bit lines. The memory device according to claim 2, which controls the aforementioned peripheral circuit.

6. The aforementioned peripheral circuitry is The memory device according to claim 5, configured to apply the second program prohibition voltage to the second bit line for a first time, and then apply the program allowance voltage to the second bit line for a second time.

7. The aforementioned peripheral circuitry is During the first time, the program allow voltage is applied to the first bit line, and the first program disable voltage is applied to the third bit line. During the second time, the program allow voltage is applied to the first bit line and the first program disable voltage is applied to the third bit line. The memory device according to claim 6, which controls the aforementioned peripheral circuit.

8. The aforementioned peripheral circuitry is The memory device according to claim 5, configured to apply the program-allowing voltage to the second bit line for a first time, and then apply the second program-prohibiting voltage to the second bit line for a second time.

9. The aforementioned control circuit is The number of incomplete cells, which is the sum of the number of initial cells in the program and the number of adjacent cells in the program, is compared with the reference number. The memory device according to claim 5, wherein the peripheral circuit is controlled to adjust the time for which the second program prohibition voltage is applied to the second bit line according to the result of the comparison.

10. The aforementioned control circuit is If the number of incomplete cells exceeds the standard number, The memory device according to claim 9, wherein the peripheral circuit is controlled such that the time for which the second program prohibition voltage is applied to the second bit line is shortened.

11. The aforementioned control circuit is If the number of incomplete cells exceeds the standard number, The memory device according to claim 9, wherein the peripheral circuit is controlled to increase the time for which the second program disable voltage is applied to the second bit line.

12. The aforementioned control circuit is If the number of incomplete cells is less than the standard number, The memory device according to claim 9, wherein the peripheral circuit is controlled to increase the time for which the second program disable voltage is applied to the second bit line.

13. The aforementioned control circuit is If the number of incomplete cells is less than the standard number, The memory device according to claim 9, wherein the peripheral circuit is controlled such that the time for which the second program prohibition voltage is applied to the second bit line is shortened.

14. The aforementioned control circuit is The memory device according to claim 9, which controls the peripheral circuit to adjust the level of the second program disable voltage applied to the second bit line according to the result of the comparison.

15. During program operation, the memory cell is divided into a program initial cell, a program adjacent cell, or a program completion cell according to the verification result of the memory cell; The steps include: applying a program allow voltage to a first bit line corresponding to the initial program cell; selectively applying a second program prohibition voltage and the program allowance voltage to a second bit line corresponding to the adjacent program cell; and applying a first program prohibition voltage to a third bit line corresponding to the completed program cell; The step includes applying a program voltage to a word line connected to the memory cell, A method for operating a memory device in which the application time of the second program prohibition voltage applied to the second bit line is adjusted according to the number of program initial cells and program adjacent cells.

16. While the first program disable voltage is applied to the third bit line, The operation method of the memory device according to claim 15, wherein the second program prohibition voltage and the program allowance voltage are sequentially applied to the second bit line.

17. The operation method of a memory device according to claim 16, wherein the second program prohibition voltage is applied to the second bit line, and then the program allowance voltage is applied to the second bit line.

18. The operation method of a memory device according to claim 16, wherein the second program prohibition voltage is applied to the second bit line after the program allow voltage has been applied to the second bit line.

19. The method for operating a memory device according to claim 15, wherein the second program prohibition voltage is set higher than the program allowance voltage and lower than the first program prohibition voltage.

20. The method for operating a memory device according to claim 15, wherein the second program prohibition voltage is set to be higher than the program allowance voltage and the same as the first program prohibition voltage.

21. The time during which the second program disable voltage is applied to the second bit line is: The number of the initial program cell and the adjacent program cell are compared with a reference number. A method for operating a memory device according to claim 15, which is adjusted according to the results of the comparison.

22. If the number of the program's initial cell and the program's adjacent cells is greater than the standard number, The method for operating a memory device according to claim 21, wherein the time for which the second program prohibition voltage is applied to the second bit line is shortened.

23. If the number of the program's initial cell and the program's adjacent cells is less than the standard number, The operation method of the memory device according to claim 21, wherein the time for which the second program prohibition voltage is applied to the second bit line is increased.

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