Indication device

Abstract

To provide a display device that can improve yield. [Solution] According to the embodiment, the display device includes a display area including a plurality of subpixels, a partition wall surrounding each of the plurality of subpixels, a plurality of display elements each arranged on the plurality of subpixels and including an organic layer that emits light in response to the application of a voltage, and a plurality of sealing layers formed of an inorganic insulating material that cover each of the plurality of display elements. The partition wall is divided by a slit extending in a first direction and includes a first segment and a second segment aligned in a second direction intersecting the first direction, and a first connecting portion that connects the first segment and the second segment across the slit. Furthermore, two adjacent sealing layers among the plurality of sealing layers overlap at least a portion of the first connecting portion in a plan view.

Description

Technical Field

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[0005] ,

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Generally, according to the embodiment, the display device comprises a display area including a plurality of subpixels, a partition wall surrounding each of the plurality of subpixels, a plurality of display elements each of the plurality of subpixels, each of which is arranged on the plurality of subpixels and includes an organic layer that emits light in response to the application of a voltage, and a plurality of sealing layers formed of an inorganic insulating material that cover each of the plurality of display elements. The partition wall is divided by a slit extending in a first direction and includes a first segment and a second segment aligned in a second direction intersecting the first direction, and a first connecting portion that crosses the slit and connects the first segment and the second segment. Furthermore, two adjacent sealing layers among the plurality of sealing layers overlap at least a portion of the first connecting portion in a plan view. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view showing some elements of the display device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall and sealing layer according to the first embodiment. [Figure 6A] Figure 6A is a schematic cross-sectional view of the display device along line AA in Figure 5. [Figure 6B] Figure 6B is a schematic cross-sectional view of the display device along line BB in Figure 5. [Figure 6C] Figure 6C is a schematic cross-sectional view of the display device along the CC line in Figure 5. [Figure 7A] Figure 7A is a schematic cross-sectional view showing a modified example of the first embodiment. [Figure 7B]FIG. 7B is another schematic cross-sectional view showing a modification of the first embodiment. [Figure 7C] FIG. 7C is yet another schematic cross-sectional view showing a modification of the first embodiment. [Figure 8] FIG. 8 is a flowchart showing an example of a method for manufacturing a display device according to the first embodiment. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a process following FIG. 9A. [Figure 9C] [[ID=I5]]FIG. 9C is a schematic cross-sectional view showing a process following FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a process following FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing a process following FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing a process following FIG. 9E. [Figure 9G] FIG. 9G is a schematic cross-sectional view showing a process following FIG. 9F. [Figure 10] FIG. 10 is a schematic plan view of a partition wall and a sealing layer according to the second embodiment. < OOOOO87> [Figure 11A] FIG. 11A is a schematic cross-sectional view of a display device taken along line A-A in FIG. 10. [Figure 11B] FIG. 11B is a schematic cross-sectional view of a display device taken along line B-B in FIG. 10. [Figure 11C] FIG. 11C is a schematic cross-sectional view of a display device taken along line C-C in FIG. 10. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a first modification of the second embodiment. [Figure 12B] FIG. 12B is another schematic cross-sectional view showing the first modification. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing a second modification of the second embodiment. [Figure 13B] FIG. 13B is another schematic cross-sectional view showing the second modification. [Figure 13C] Figure 13C is yet another schematic cross-sectional view showing a second modified example. [Figure 14] Figure 14 is a schematic plan view of the display device according to the third embodiment. [Figure 15] Figure 15 is a schematic plan view showing an example of a configuration applicable to the dummy pixel region. [Figure 16A] Figure 16A is a schematic cross-sectional view of the display device along line AA in Figure 15. [Figure 16B] Figure 16B is a schematic cross-sectional view of the display device along line BB in Figure 15. [Figure 16C] Figure 16C is a schematic cross-sectional view of the display device along the CC line in Figure 15. [Modes for carrying out the invention]

[0007] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0008] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis as the Y direction, and the direction along the Z axis as the Z direction. The Z direction is the normal direction of the plane containing the X and Y directions. Viewing various elements parallel to the Z direction is called a plan view.

[0009] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0011] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to circular, and may be other shapes such as rectangles, squares, or ellipses.

[0012] The display area DA comprises a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0013] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0014] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0015] The display area DA is arranged with multiple scan lines G that supply scan signals to the pixel circuits 1 of each sub-pixel SP, multiple signal lines S that supply video signals to the pixel circuits 1 of each sub-pixel SP, and multiple power lines PL. In Figure 1, the scan lines G and power lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not the only example.

[0016] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the Y direction. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the X direction.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0020] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel apertures AP1, AP2, and AP3 are all rectangular. The areas of pixel apertures AP1 and AP2 are each larger than the area of ​​pixel aperture AP3. Pixel aperture AP2 extends longer in the Y direction than both pixel apertures AP1 and AP3. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0021] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0022] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] A conductive partition wall 6 is positioned above the rib layer 5. The partition wall 6 separates the display elements DE1, DE2, and DE3, and also serves as wiring to supply a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps the rib layer 5 overall and has a similar planar shape to the rib layer 5. The partition wall 6 surrounds the sub-pixels SP1, SP2, and SP3.

[0024] The partition wall 6 has multiple slits SL extending in the Y direction (first direction). The slits SL do not overlap with the lower electrodes LE1, LE2, and LE3. In the example in Figure 2, the sub-pixels SP1, SP2, and SP3 that constitute one pixel PX are arranged between the two slits SL in the X direction (second direction). Furthermore, the partition wall 6 has a connecting section CT that connects the parts separated by the slits SL (segments described later). Note that the arrangement of the slits SL and the connecting section CT is not limited to the example in Figure 2.

[0025] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are each placed on top of the organic insulating layer 12. The rib layer 5 is placed on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are all covered by the rib layer 5.

[0027] The partition wall 6 includes a conductive lower portion 61 positioned on the rib layer 5 and an upper portion 62 positioned on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. In other words, the partition wall 6 is overhanging in that both ends of the upper portion 62 protrude beyond the sides of the lower portion 61.

[0028] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is formed thinner than the axial layer 64 and is located between the axial layer 64 and the rib layer 5. Both ends of the bottom layer 63 protrude from both sides of the axial layer 64.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0030] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0031] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0032] Sub-pixels SP1, SP2, and SP3 are surrounded by sealing layers SE11, SE12, and SE13, respectively, which cover the stacked films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 surrounding sub-pixel SP3.

[0033] In the example shown in Figure 3, the sealing layers SE11 and SE12 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP2. Also, the sealing layers SE11 and SE13 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP3. This example is not limited to this; the sealing layers SE11, SE12, and SE13 may be spaced apart above the partition 6.

[0034] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0035] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0036] In the example shown in Figure 3, a touch panel electrode TP for detecting user touch operations is placed on top of the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material and has a shape similar to the partition wall 6 in a plan view.

[0037] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0038] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0039] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0040] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0041] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0042] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0043] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0044] The upper part 62 of the partition wall 6 includes, for example, a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. In this case, the metallic material of the lower layer can be titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. The conductive oxide of the upper layer can be ITO or IZO. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0045] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line S through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0046] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0047] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0048] Figure 4 is a schematic plan view showing some elements of the display device DSP. The partition wall 6 is divided into multiple segments SG by multiple slits SL, as also shown in Figure 2. Note that in Figure 4, the slits SL and segments SG are schematically shown. For example, if slits SL are located on both sides of the pixel PX in the X direction, as shown in Figure 2, more slits SL are formed in the display area DA.

[0049] At least some of the multiple segments SG are connected by connecting sections CT that cross the slits SL, as shown in Figure 2. On the other hand, some of the multiple slits SL may not have connecting sections CT.

[0050] Each segment SG has a first end Ea and a second end Eb in the direction of extension of the slit SL (Y direction in this embodiment). The first end Ea is connected to a power supply line PW provided in the peripheral region SA. The power supply line PW is connected to a terminal section T. A common voltage is applied to each segment SG from the terminal section T via the power supply line PW. In the example in Figure 4, the second end Eb of each segment SG is separated by the slit SL and is not connected by a conductive member such as the power supply line PW.

[0051] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall 6 and sealing layers SE11, SE12, and SE13 according to this embodiment. In this figure, a portion of the two segments SG1 and SG2 (first segment and second segment) separated by the slit SL is shown. Also, the sealing layer SE11 is given a diagonal line pattern. In the following description, the portion of segment SG1 that extends in the Y direction adjacent to the slit SL will be called partition wall 6A, and the portion of segment SG2 that extends in the Y direction adjacent to the slit SL will be called partition wall 6B.

[0052] Segments SG1 and SG2 are connected by multiple connection points CTs. In the example in Figure 5, connection points CTs are provided at positions aligned with the partition wall 6 between sub-pixels SP1 and SP3 in the X direction. However, the positions of the connection points CTs are not limited to this example.

[0053] The sealing layer SE11 overlaps with one sub-pixel SP1 (display element DE1). The sealing layer SE13 overlaps with one sub-pixel SP3 (display element DE3). The sealing layer SE12 is formed continuously over multiple sub-pixels SP2 (display elements DE2) aligned in the Y direction, for example.

[0054] The sealing layers SE11 and SE12 are aligned in the X direction via the slit SL. The sealing layers SE12 and SE13 are also aligned in the X direction via the slit SL. The sealing layers SE11 and SE13 are aligned in the Y direction without the slit SL.

[0055] The sealing layer SE11 has ends E1a and E1b in the X direction and ends E1c and E1d in the Y direction. The sealing layer SE12 has ends E2a and E2b in the X direction. The sealing layer SE13 has ends E3a and E3b in the X direction and ends E3c and E3d in the Y direction. For example, ends E1a, E1b, E2a, E2b, E3a, and E3b are straight lines parallel to the Y direction. Also, ends E1c, E1d, E3c, and E3d are straight lines parallel to the X direction.

[0056] In the example in Figure 5, ends E1c and E3d overlap. Also, ends E1d and E3c overlap. This example is not limited to this; ends E1c and E3d may be spaced apart. Similarly, ends E1d and E3c may be spaced apart.

[0057] The sealing layer SE11 has two protrusions PT1 that project from end E1a in a direction parallel to the X direction (towards the sealing layer SE12). These protrusions PT1 are located at the corner formed by ends E1a and E1c, and at the corner formed by ends E1a and E1d, respectively.

[0058] Furthermore, the sealing layer SE13 has two protrusions PT3 that project from end E3a in a direction parallel to the X direction (towards the sealing layer SE12). These protrusions PT3 are located at the corner formed by ends E3a and E3c, and at the corner formed by ends E3a and E3d, respectively.

[0059] In this embodiment, adjacent sealing layers SE11 and SE13 overlap with at least a portion of a single connection portion CT. Specifically, the protrusion PT1 of sealing layer SE11 overlaps with a portion of the connection portion CT, and the protrusion PT3 of sealing layer SE13 adjacent to sealing layer SE11 overlaps with a portion of the connection portion CT. In the example in Figure 5, the protrusions PT1 and PT3 also overlap with a portion of the slit SL.

[0060] Figure 6A is a schematic cross-sectional view of the DSP display device along line AA in Figure 5. The partition walls 6A and 6B, separated by the slit SL, are overhanging, similar to the partition wall 6 shown in Figure 3. In the slit SL, there is no opening in the rib layer 5. That is, the slit SL overlaps with the rib layer 5 overall.

[0061] In the cross-section of Figure 6A, the sealing layer SE11 covers the partition wall 6A. The end E1a of the sealing layer SE11 is located in the slit SL. The sealing layer SE12 covers the partition wall 6B. The end E2b of the sealing layer SE12 is located, for example, in the slit SL and is spaced apart from the end E1a. In other examples, the end E1a may be located above the partition wall 6A. Also, the end E2b may be located above the partition wall 6B.

[0062] Figure 6B is a schematic cross-sectional view of the display device DSP along line BB in Figure 5. The sealing layer SE13 covers the partition wall 6A. End E3a of the sealing layer SE13 is located in the slit SL and is spaced apart from end E2b of the sealing layer SE12. In another example, end E3a may be located above the partition wall 6A.

[0063] Figure 6C is a schematic cross-sectional view of the display device DSP along the CC line in Figure 5. The connecting section CT includes a lower section 61 (bottom layer 63 and axial layer 64) and an upper section 62, similar to the partition walls 6A and 6B. The cross-sectional shape of the connecting section CT along the Y direction is an overhang shape, similar to that of the partition walls 6A and 6B.

[0064] The protrusion PT1 covers one side of the connection part CT in the Y direction. The protrusion PT3 covers the other side of the connection part CT in the Y direction. In the example in Figure 6C, one end of the protrusion PT1 is located above the slit SL, and the other end is located above the connection part CT. Similarly, one end of the protrusion PT3 is located above the slit SL, and the other end is located above the connection part CT.

[0065] As shown in Figure 6C, the protrusions PT1 and PT3 may overlap above the connection CT. Alternatively, the protrusions PT1 and PT3 may be spaced apart in the Y direction above the connection CT.

[0066] In the examples shown in Figures 6A to 6C, gaps GP1 are formed below the sealing layer SE11, gaps GP2 below the sealing layer SE12, and gaps GP3 below the sealing layer SE13, except for the parts that overlap with the display elements DE1, DE2, and DE3. Specifically, gaps GP1 are formed between the upper part 62 of partition wall 6A and the sealing layer SE11, between the rib layer 5 in the slit SL and the sealing layer SE11, between the upper part 62 of the connection part CT and the protrusion PT1, and between the rib layer 5 and the protrusion PT1 in the slit SL. Gap GP2 is formed between the upper part 62 of partition wall 6B and the sealing layer SE12, and between the rib layer 5 in the slit SL and the sealing layer SE12. Gap GP3 is formed between the upper part 62 of partition wall 6A and the sealing layer SE13, between the rib layer 5 in the slit SL and the sealing layer SE13, and between the upper part 62 of the connection part CT and the protrusion PT3.

[0067] The gaps GP1, GP2, and GP3 correspond to the spaces where the laminated films FL1, FL2, and FL3, which were initially formed during the manufacturing process of the DSP display device, have disappeared due to various etching processes. These gaps GP1, GP2, and GP3 may be voids, or at least a portion of them may be filled with the resin layer RS1 (see Figure 3).

[0068] Figures 7A to 7C are schematic cross-sectional views showing modified examples of this embodiment. Figure 7A corresponds to a cross-section along line AA in Figure 5, Figure 7B corresponds to a cross-section along line BB in Figure 5, and Figure 7C corresponds to a cross-section along line CC in Figure 5.

[0069] In Figures 7A to 7C, the laminated films FL1, FL2, and FL3 are positioned in the locations corresponding to the gaps GP1, GP2, and GP3 in Figures 6A to 6C, respectively. Alternatively, the laminated films FL1, FL2, and FL3 may be positioned to fill a portion of the locations corresponding to the gaps GP1, GP2, and GP3 in Figures 6A to 6C.

[0070] Next, we will describe an example of a manufacturing method for a display device DSP. Figure 8 is a flowchart showing an example of a method for manufacturing a display device DSP. Figures 9A to 9G are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 9A to 9G, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0071] In the manufacturing of the display device DSP, a circuit layer 11 is first formed on top of the substrate 10 (step PR1 in Figure 8). Furthermore, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in Figure 8).

[0072] After step PR2, as shown in Figure 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in Figure 8). Furthermore, a rib layer 5 is formed to cover the lower electrodes LE1, LE2, and LE3 (step PR4 in Figure 8). At this point, the rib layer 5 does not have pixel apertures AP1, AP2, and AP3. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0073] After the formation of the rib layer 5, a partition wall 6 is formed on top of the rib layer 5, as shown in Figure 9B (step PR5 in Figure 8). For example, in the formation of the partition wall 6, layers of material for the bottom layer 63, axial layer 64, and upper layer 62 are formed over the entire mother substrate MB. Furthermore, a resist in the shape of the partition wall 6 is placed on top of these layers. By etching each layer using this resist as a mask, a partition wall 6 can be formed that has openings at each sub-pixel SP1, SP2, SP3 and includes multiple segments SG separated by slits SL.

[0074] Next, as shown in Figure 9C, pixel apertures AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in Figure 8). Note that the pixel apertures AP1, AP2, and AP3 may be formed in front of the partition wall 6.

[0075] After process PR6, a process for forming the display element DE1 is carried out (process PR7 in Figure 8). In forming the display element DE1, first, as shown in Figure 9D, a laminated film FL1 and a sealing layer SE11 are formed over the entire substrate. As shown in Figure 3, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1.

[0076] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can also be formed, for example, by CVD. The multilayer film FL1 is divided by overhanging partitions 6. The sealing layer SE11 continuously covers each divided portion of the multilayer film FL1 and the partitions 6.

[0077] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 9D, the resist RT1 is placed on top of the sealing layer SE11. The resist RT1 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0078] Subsequently, an etching process is performed using resist RT1 as a mask. As a result, as shown in Figure 9E, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist RT1 are removed. This forms the display element DE1 on the sub-pixel SP1.

[0079] The etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the resist RT1 is removed (exfoliated).

[0080] In the etching process, the laminated film FL1 near the edge of the sealing layer SE11 may be removed, forming the gap GP1 described above. The gap GP1 may also be formed by various etching processes performed after the etching process. Furthermore, at least a portion of the laminated film FL1 may remain in the gap GP1.

[0081] After step PR7, a process for forming the display element DE2 is carried out (step PR8 in Figure 8). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire substrate. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0082] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can also be formed, for example, by CVD. By patterning such a multilayer film FL2 and sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 9F.

[0083] In the example shown in Figure 9F, the laminated film FL2 near the edge of the sealing layer SE12 is removed, forming the gap GP2 described above. The gap GP2 may also be formed by various etching processes performed after the etching step. Furthermore, at least a portion of the laminated film FL2 may remain in the gap GP2.

[0084] After step PR8, a process for forming the display element DE3 is carried out (step PR9 in Figure 8). The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire substrate. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0085] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. By patterning such a multilayer film FL3 and sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 9G.

[0086] In the example shown in Figure 9G, the laminated film FL3 near the edge of the sealing layer SE13 is removed, forming the gap GP3 described above. The laminated film FL3 may remain in at least a portion of the gap GP3.

[0087] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0088] After step PR9, a resin layer RS1 is formed, for example, by an inkjet method (step PR10 in Figure 8). Furthermore, a sealing layer SE2 is formed, for example, by CVD (step PR11 in Figure 8).

[0089] After step PR11, the touch panel electrode TP is formed on the sealing layer SE2 (step PR12 in Figure 8). Subsequently, a resin layer RS2 covering the touch panel electrode TP and the sealing layer SE2 is formed, for example, by an inkjet method (step PR13 in Figure 8). The display device DSP is completed by a manufacturing method including at least the above steps.

[0090] Here, we will explain some of the effects of the DSP display device according to this embodiment. Electronic devices equipped with a display device (DSP) may also include optical sensors, such as illuminance sensors, to detect ambient light. When such optical sensors are located on the back side of the display device (DSP), the display device (DSP) needs to be light-transmitting.

[0091] However, the lower electrodes LE1, LE2, and LE3 all include the aforementioned reflective layer. Furthermore, the partition wall 6, which is at least partially made of a metallic material, has light-shielding properties. Therefore, when the lower electrodes LE1, LE2, LE3 and the partition wall 6 are arranged without gaps in the display area DA, most of the light incident on the display surface of the display device DSP can be reflected or shielded without being transmitted to the back side.

[0092] In contrast, when a slit SL is provided in the partition wall 6 as in this embodiment, a portion of the light incident on the display surface is transmitted through the slit SL to the back side of the display device DSP. This improves the light transmittance of the display device DSP. In this embodiment, as shown in Figures 6A and 6B, a region is formed in the slit SL that does not overlap with the sealing layers SE11, SE12, and SE13. Further improvement in transmittance can be expected in such a region.

[0093] Furthermore, electronic devices equipped with a display device DSP may also have an antenna for near-field communication (NFC). This antenna is positioned, for example, opposite the back of the display device DSP and communicates wirelessly with other electronic devices through the display device DSP. During wireless communication, the magnetic field formed by the antenna generates eddy currents in the partition wall 6. These eddy currents form a magnetic field that cancels out the magnetic field, thus attenuating the signal strength of the wireless communication. Therefore, when wireless communication is performed via the display device DSP, the communication sensitivity may decrease.

[0094] The eddy currents mentioned above can be reduced by dividing the partition wall 6. In other words, as explained above in the description of Figure 4, by providing a slit SL in which no connecting CT is located, large eddy currents are less likely to occur in the partition wall 6, and a decrease in communication sensitivity can be suppressed.

[0095] Thus, according to this embodiment, it is possible to provide a display device DSP that is compatible with optical sensors and antennas for wireless communication. Furthermore, as will be explained below, according to this embodiment, the yield of the display device DSP can be improved.

[0096] As shown in Figure 7C, the connecting portion CT has overhangs on both sides. When a connecting portion CT with this shape is covered with various resists during the manufacturing of a display device DSP, there is a possibility that air bubbles may be incorporated into the resist. In this case, when the resist is dried under reduced pressure, these air bubbles may burst, potentially exposing areas that should be covered by the resist. In contrast, in this embodiment, both sides of the connecting portion CT are covered by protrusions PT1 and PT3, respectively. Therefore, it is possible to suppress the incorporation of air bubbles into the resist formed after the protrusions PT1 and PT3.

[0097] The sealing layer SE11, formed from an inorganic insulating material, is particularly prone to cracking at its corners. If the substrate shape at the corners of the sealing layer SE11 is unstable, the occurrence of these cracks can become more pronounced. Such cracks also contribute to the incorporation of air bubbles into the resist placed on top of the sealing layer SE11. In this embodiment, a protrusion PT1 is formed at the corner of the sealing layer SE11 on the slit SL side. Furthermore, the protrusion PT1 overlaps the connection portion CT. This stabilizes the substrate shape at the corners of the sealing layer SE11, thereby suppressing the occurrence of cracks. A similar effect occurs with the sealing layer SE13 having a protrusion PT3.

[0098] When the resin layer RS1 is formed using the inkjet method described above, droplets of uncured resin ejected from the nozzle adhere to the sealing layers SE11, SE12, SE13 and the rib layer 5 in the slit SL, wetting and spreading over the area where the resin layer RS1 is to be formed. If the connecting portion CT is not covered by the protrusions PT1 and PT3, the spreading of the droplets may be hindered by the overhanging sides of the connecting portion CT. In contrast, if both sides of the connecting portion CT are covered by the protrusions PT1 and PT3, as in this embodiment, the droplets spread well, thereby suppressing defects in the shape of the resin layer RS1.

[0099] In addition to the above, various other desirable effects can be obtained from this embodiment.

[0100] [Second Embodiment] A second embodiment will now be described. Configurations not specifically mentioned can be those the same as in the first embodiment.

[0101] Figure 10 is a schematic plan view of the partition wall 6 and sealing layers SE11, SE12, and SE13 according to this embodiment. This embodiment differs from the first embodiment in the shape of the sealing layers SE11, SE12, and SE13.

[0102] In other words, in the example shown in Figure 10, the sealing layer SE11 does not have the protrusion PT1 shown in Figure 5. Also, the sealing layer SE13 does not have the protrusion PT3 shown in Figure 5. On the other hand, the sealing layer SE12 has multiple protrusions PT2 that project from the end E2b in a direction parallel to the X direction.

[0103] In the example shown in Figure 10, the end E1a of the sealing layer SE11 and the end E3a of the sealing layer SE13 are misaligned in the X direction. Specifically, end E1a is located near partition wall 6B, and end E3a is located near partition wall 6A. As a result, most of the slit SL between subpixels SP1 and SP2 overlaps with the sealing layer SE11. On the other hand, the sealing layer SE13 hardly overlaps with the slit SL.

[0104] Each protrusion PT2 is positioned to align with the sealing layer SE13 in the X direction. As a result, most of the slit SL between the subpixels SP2 and SP3 overlaps with the protrusion PT2.

[0105] In this embodiment, the sealing layers SE11 and SE12 overlap with the connection portion CT, respectively. Specifically, the ends E1a, E1c, and E1d of the sealing layer SE11 overlap with the connection portion CT, respectively. Also, both ends of the protrusion PT2 in the Y direction overlap with the connection portion CT, respectively.

[0106] Figure 11A is a schematic cross-sectional view of the display device DSP along line AA in Figure 10. The sealing layer SE11 covers the partition wall 6A. End E1a of the sealing layer SE11 is located in the slit SL. The sealing layer SE12 covers the partition wall 6B. End E2b of the sealing layer SE12 is located, for example, in the slit SL and is spaced apart from end E1a. In another example, end E2b may be located above the partition wall 6B.

[0107] Figure 11B is a schematic cross-sectional view of the display device DSP along line BB in Figure 10. The sealing layer SE13 covers the partition wall 6A. The end E3a of the sealing layer SE13 is located in the slit SL. In another example, the end E3a may be located above the partition wall 6A. The protrusion PT2 of the sealing layer SE12 is located above the rib layer 5 in the slit SL and is spaced apart from the end E3a.

[0108] Figure 11C is a schematic cross-sectional view of the display device DSP along the CC line in Figure 10. The sealing layer SE11 covers one side of the connection part CT in the Y direction. The protrusion PT2 covers the other side of the connection part CT in the Y direction. In the example in Figure 11C, the end E1c of the sealing layer SE11 is located above the slit SL. Also, the end of the protrusion PT2 is located above the slit SL. As shown in Figure 11C, the end E1c and the protrusion PT2 may overlap above the connection part CT. In another example, the end E1c and the protrusion PT2 may be spaced apart in the Y direction above the connection part CT.

[0109] In the examples shown in Figures 11A to 11C, a gap GP1 is formed below the sealing layer SE11, a gap GP2 is formed below the sealing layer SE12, and a gap GP3 is formed below the sealing layer SE13, except for the parts that overlap with the display elements DE1, DE2, and DE3. Specifically, gap GP1 is formed between the upper part 62 of partition wall 6A and the sealing layer SE11, and between the rib layer 5 in the slit SL and the sealing layer SE11. Gap GP2 is formed between the upper part 62 of partition wall 6B and the sealing layer SE12, and between the rib layer 5 in the slit SL and the protrusion PT2. Gap GP3 is formed between the upper part 62 of partition wall 6A and the sealing layer SE13, and between the rib layer 5 in the slit SL and the sealing layer SE13.

[0110] Figures 12A and 12B are schematic cross-sectional views showing a first modified example of this embodiment. Figure 12A corresponds to a cross-section along line AA in Figure 10, and Figure 12B corresponds to a cross-section along line BB in Figure 10.

[0111] The configuration in Figure 12A differs from that in Figure 11A in that the end E2b of the sealing layer SE12 overlaps with the end E1a of the sealing layer SE11. End E2b is located above end E1a in the Z direction.

[0112] Furthermore, the configuration in Figure 12B differs from that in Figure 11B in that the end portion E3a of the sealing layer SE13 overlaps with the protrusion PT2 of the sealing layer SE12. The end portion E3a is located above the protrusion PT2 in the Z direction.

[0113] Figures 13A to 13C are schematic cross-sectional views showing a second modified example of this embodiment. Figure 13A corresponds to a cross-section along line AA in Figure 10, Figure 13B corresponds to a cross-section along line BB in Figure 10, and Figure 13C corresponds to a cross-section along line CC in Figure 10.

[0114] In Figures 13A to 13C, the laminated films FL1, FL2, and FL3 are positioned in the locations corresponding to the gaps GP1, GP2, and GP3 in Figures 11A to 11C, respectively. The laminated films FL1, FL2, and FL3 may also be positioned to fill a portion of the locations corresponding to the gaps GP1, GP2, and GP3 in Figures 11A to 11C. Furthermore, in the configuration of the first modified example shown in Figures 12A and 12B, the laminated films FL1, FL2, and FL3 may also be positioned in the locations corresponding to the gaps GP1, GP2, and GP3, respectively.

[0115] The configuration of this embodiment also provides the same effects as the first embodiment. Furthermore, when forming small protrusions PT1 and PT3 as in the first embodiment, there are limitations to the processing accuracy depending on the size of the sealing layers SE11, SE12, and SE13. In contrast, in this embodiment, the connecting portion CT is covered with a rectangular sealing layer SE11 and a protrusion PT2 with a width approximately the same as the spacing between the connecting portions CT. With such a configuration, the influence of processing accuracy is reduced, and sealing layers SE11, SE12, and SE13 with a stable shape can be formed.

[0116] [Third Embodiment] A third embodiment will now be described. Configurations not specifically mentioned can be those similar to those in the embodiments described above.

[0117] Figure 14 is a schematic plan view of the display device DSP according to this embodiment. Similar to that shown in Figure 1, the display device DSP has an insulating substrate 10, a display area DA for displaying an image, and a peripheral area SA surrounding the display area DA. Furthermore, the peripheral area SA has a dummy pixel area DMY surrounding the display area DA.

[0118] Figure 14 shows a magnified view of a portion of the dummy pixel region DMY. Multiple dummy pixels DPX are arranged within the dummy pixel region DMY. For example, dummy pixel DPX includes dummy sub-pixels DP1, DP2, and DP3. Dummy sub-pixels DP1, DP2, and DP3 have a structure similar to the sub-pixels SP1, SP2, and SP3 arranged in the display region DA, respectively.

[0119] Specifically, dummy sub-pixel DP1 comprises a lower electrode LE1, an organic layer OR1, and an upper electrode UE1. Dummy sub-pixel DP2 comprises a lower electrode LE2, an organic layer OR2, and an upper electrode UE2. Dummy sub-pixel DP3 comprises a lower electrode LE3, an organic layer OR3, and an upper electrode UE3.

[0120] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy sub-pixels DP1, DP2, and DP3. Alternatively, the pixel apertures AP1, AP2, and AP3 may be omitted in each of the dummy sub-pixels DP1, DP2, and DP3. As a result, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, preventing the flow of current that would cause them to emit light.

[0121] A portion of partition wall 6 is located in the dummy pixel region DMY, enclosing each of the multiple dummy pixels DPX. More specifically, partition wall 6 encloses each of the dummy sub-pixels DP1, DP2, and DP3. The shape and layout of the openings of partition wall 6 in each of the dummy sub-pixels DP1, DP2, and DP3 are the same as the shape and layout of the openings of partition wall 6 in each of the sub-pixels SP1, SP2, and SP3.

[0122] A portion of the slit SL disclosed in each of the embodiments described above is located in the dummy pixel region DMY. A connection portion CT (second connection portion) is also provided in the dummy pixel region DMY.

[0123] Figure 15 is a schematic plan view showing a specific example of a configuration applicable to the dummy pixel region DMY. The dummy pixel region DMY has a dummy sealing layer DSE1 overlapping the dummy sub-pixel DP1, a dummy sealing layer DSE2 overlapping the dummy sub-pixel DP2, and a dummy sealing layer DSE3 overlapping the dummy sub-pixel DP3. In Figure 15, the dummy sealing layers DSE1 and DSE3 are given a diagonal pattern. The dummy sealing layers DSE1, DSE2, and DSE3 are formed of the same inorganic insulating material as the sealing layers SE11, SE12, and SE13.

[0124] The partition 6 and dummy sealing layers DSE1, DSE2, and DSE3 in the dummy pixel region DMY can be configured in the same way as the partition 6 and sealing layers SE11, SE12, and SE13 shown in Figures 5 and 10. As an example, Figure 15 shows a case where the partition 6 and dummy sealing layers DSE1, DSE2, and DSE3 have the same configuration as the partition 6 and sealing layers SE11, SE12, and SE13 shown in Figure 5.

[0125] Specifically, as shown in Figure 15, a portion of segments SG1 and SG2, separated by the slit SL, is located in the dummy pixel region DMY. In the dummy pixel region DMY, segments SG1 and SG2 are connected by multiple connection parts CT. Dummy sealing layer DSE1 has ends E1a and E1b in the X direction and ends E1c and E1d in the Y direction. Dummy sealing layer DSE2 has ends E2a and E2b in the X direction. Dummy sealing layer DSE3 has ends E3a and E3b in the X direction and ends E3c and E3d in the Y direction. Dummy sealing layer DSE1 also has two protrusions PT1. Dummy sealing layer DSE3 has two protrusions PT3. Dummy sealing layer DSE2 is formed continuously over multiple dummy sub-pixels DP2 arranged in the Y direction, for example.

[0126] In the example shown in Figure 15, adjacent dummy sealing layers DSE1 and DSE3 each overlap with at least a portion of a single connection section CT. Specifically, the protrusion PT1 of dummy sealing layer DSE1 overlaps with a portion of the connection section CT, and the protrusion PT3 of dummy sealing layer DSE3, which is adjacent to DSE1, overlaps with a portion of the connection section CT. Protrusions PT1 and PT3 also overlap with a portion of the slit SL.

[0127] Figure 16A is a schematic cross-sectional view of the display device DSP along line AA in Figure 15. In the cross-section of Figure 16A, the dummy sealing layer DSE1 covers the partition wall 6A. End E1a of the dummy sealing layer DSE1 is located at the slit SL. The dummy sealing layer DSE2 covers the partition wall 6B. End E2b of the dummy sealing layer DSE2 is located, for example, at the slit SL and is spaced apart from end E1a. In other examples, end E1a may be located above partition wall 6A. Also, end E2b may be located above partition wall 6B.

[0128] Figure 16B is a schematic cross-sectional view of the display device DSP along line BB in Figure 15. End E3a of the dummy sealing layer DSE3 is located in the slit SL and is spaced apart from and opposite to end E2b of the dummy sealing layer DSE2. In another example, end E3a may be located above partition wall 6A.

[0129] Figure 16C is a schematic cross-sectional view of the display device DSP along the CC line in Figure 15. The protrusion PT1 covers one side of the connection part CT in the Y direction. The protrusion PT3 covers the other side of the connection part CT in the Y direction. In the example in Figure 16C, one end of the protrusion PT1 is located above the slit SL, and the other end is located above the connection part CT. Similarly, one end of the protrusion PT3 is located above the slit SL, and the other end is located above the connection part CT.

[0130] As shown in Figure 16C, the protrusions PT1 and PT3 may overlap above the connection CT. Alternatively, the protrusions PT1 and PT3 may be spaced apart in the Y direction above the connection CT.

[0131] In the examples shown in Figures 16A to 16C, gaps GP1 are formed between the upper part 62 of partition wall 6A and the dummy sealing layer DSE1, between the rib layer 5 in slit SL and the dummy sealing layer DSE1, between the upper part 62 of connection part CT and the protrusion PT1, and between the rib layer 5 and the protrusion PT1 in slit SL. Gaps GP2 are also formed between the upper part 62 of partition wall 6B and the dummy sealing layer DSE2, and between the rib layer 5 in slit SL and the dummy sealing layer DSE2. Furthermore, gaps GP3 are formed between the upper part 62 of partition wall 6A and the dummy sealing layer DSE3, between the rib layer 5 in slit SL and the dummy sealing layer DSE3, and between the upper part 62 of connection part CT and the protrusion PT3. As another example, a laminated film FL1 may be placed in at least a portion of gap GP1, a laminated film FL2 may be placed in at least a portion of gap GP2, and a laminated film FL3 may be placed in at least a portion of gap GP3.

[0132] In Figures 16A and 16B, the dummy sub-pixels DP1, DP2, and DP3 do not have pixel apertures AP1, AP2, and AP3. As a result, rib layers 5 are interposed between the lower electrode LE1 and the laminated film FL1, between the lower electrode LE2 and the laminated film FL2, and between the lower electrode LE3 and the laminated film FL3. As another example, the dummy sub-pixels DP1, DP2, and DP3 may have pixel apertures AP1, AP2, and AP3.

[0133] When the dummy pixel region DMY has the configuration described above, the same effects as in the first embodiment can be obtained for the dummy pixel region DMY as well. Furthermore, when the partition wall 6 and dummy sealing layers DSE1, DSE2, DSE3 of the dummy pixel region DMY are configured in the same way as the partition wall 6 and sealing layers SE11, SE12, SE13 disclosed in the second embodiment, the same effects as in the second embodiment can be obtained for the dummy pixel region DMY as well.

[0134] In each of the embodiments described above, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a different shape from the partition wall disclosed in each embodiment, the laterally protruding portion corresponds to the "upper part," and the recessed portion below that portion corresponds to the "lower part."

[0135] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices disclosed in each embodiment also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0136] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0137] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0138] DSP...Display device, DA...Display area, SA...Peripheral area, DMY...Dummy pixel area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, DPX...Dummy pixel, DP1, DP2, DP3...Dummy sub-pixel, LE1, LE2, LE3...Lower electrode, OR1, OR2, OR3...Organic layer, UE1, UE2, UE3...Upper electrode, SE11, SE12, SE13...Sealing layer, DSE1, DSE2, DSE3...Dummy sealing layer, RS1, RS2...Resin layer, SL...Slit, CT...Connection part, 5...Rib layer, 6...Partition wall, 61...Lower part, 62...Upper part, 63...Bottom layer, 64...Axial layer.

Claims

1. A display area containing multiple subpixels, It includes a conductive lower part and an upper part having an end protruding from the side surface of the lower part, and a partition wall surrounding each of the plurality of subpixels, Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, Equipped with, The aforementioned partition wall is Divided by a slit extending in a first direction, the first segment and the second segment are aligned in a second direction intersecting the first direction, A first connecting portion that crosses the slit and connects the first segment and the second segment, Includes, Of the plurality of sealing layers, two adjacent sealing layers overlap with at least a portion of the first connection portion in a plan view. Display device.

2. The two sealing layers overlap with at least a portion of the slit in a plan view. The display device according to claim 1.

3. A gap is formed beneath the two sealing layers in the slit. The display device according to claim 1.

4. The two sealing layers overlap above the first connection portion. The display device according to claim 1.

5. The plurality of sealing layers include a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer and the second sealing layer are aligned in the second direction via the slit, The first sealing layer and the third sealing layer are aligned in the first direction, The first sealing layer and the third sealing layer each overlap with at least a portion of the first connection portion in a plan view. The display device according to claim 1.

6. The first sealing layer has a first protrusion that protrudes in a direction parallel to the second direction, The third sealing layer has a second protrusion that protrudes in a direction parallel to the second direction, The first protrusion and the second protrusion each overlap with at least a part of the first connecting portion in a plan view. The display device according to claim 5.

7. A gap is formed between the first connecting portion and the first protrusion located above the first connecting portion. The display device according to claim 6.

8. A gap is formed between the first connecting portion and the second protrusion located above the first connecting portion. The display device according to claim 7.

9. The first protrusion overlaps with a part of the slit in a plan view. The display device according to claim 6.

10. The second protrusion overlaps with a part of the slit in a plan view. The display device according to claim 9.

11. The first protrusion and the second protrusion overlap above the first connecting portion. The display device according to claim 6.

12. The plurality of sealing layers include a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer and the second sealing layer are aligned in the second direction via the slit, The first sealing layer and the third sealing layer are aligned in the first direction, The first sealing layer and the second sealing layer each overlap with at least a portion of the first connection portion in a plan view. The display device according to claim 1.

13. In the first direction, the end of the first sealing layer overlaps with at least a portion of the first connecting portion in a plan view. The display device according to claim 12.

14. A gap is formed between the first connecting portion and the end of the first sealing layer located above the first connecting portion. The display device according to claim 13.

15. The second sealing layer has a protrusion that projects in a direction parallel to the second direction, The protrusion overlaps with at least a part of the first connecting portion in a plan view. The display device according to claim 13.

16. A gap is formed between the first connecting portion and the protrusion located above the first connecting portion. The display device according to claim 15.

17. The display area further comprises a dummy pixel area that includes multiple dummy subpixels and is located outside the display area, A portion of the partition wall is located in the dummy pixel region and surrounds each of the plurality of dummy subpixels. The display device according to claim 1.

18. A portion of the slit is located in the dummy pixel region, The partition wall further includes a second connecting portion that connects the first segment and the second segment in the dummy pixel region. The display device according to claim 17.

19. The plurality of sealing layers further include a dummy sealing layer that overlaps in a plan view with at least one of the plurality of dummy subpixels and at least a portion of the second connection portion. The display device according to claim 18.

20. The system further comprises a resin layer covering the plurality of sealing layers. The display device according to any one of claims 1 to 19.

Images